ADSP-21161NCCA-100 - Analog Devices

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC Processor

ADSP-21161N

Rev. B

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SUMMARY

High performance 32-Bit DSP—applications in audio, medi-

cal, military, wireless communications, graphics, imaging,

motor-control, and telephony

Super Harvard Architecture—four independent buses for

dual data fetch, instruction fetch, and nonintrusive zero-

overhead I/O

Code compatible with all other sharc family DSPs

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point computation units,

each with a multiplier, ALU, shifter, and register file

Serial ports offer I

S support via 8 programmable and simul-

taneous receive or transmit pins, which support up to 16

transmit or 16 receive channels of audio

Integrated peripherals—integrated I/O processor, 1m bit on-

chip dual-ported SRAM, SDRAM controller, glueless multi-

processing features, and I/O ports (serial, link, external

bus, SPI, and JTAG)

ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit

floating-point formats

100 MHz/110 MHz core instruction rate

Single-cycle instruction execution, including SIMD opera-

tions in both computational units

Up to 660 MFLOPs peak and 440 MFLOPs sustained

performance

225-ball 17 mm × 17 mm CSP_BGA package

Figure 1. ADSP-21161N Functional Block Diagram

ALU

MULT

DATA

FILE

(PEY)

16 u40-BIT

BARREL

SHIFTER

BARREL

SHIFTER

ALU

DATA

FILE

(PEX)

16 u40-BIT

TIMER

INSTRUCTION

CACHE

32 u48-BIT

DAG1

8u4u32 PROGRAM

SEQUENCER

PM ADDRESS BUS

DM ADDRESS BUS

BUS

CONNECT

(PX)

PM DATA BUS

DM DATA BUS

CORE PROCESSOR

SPI PORTS (1)

SERIAL PORTS (4)

LINK PORTS (2)

DMA

CONTROLLER

IOP

REGISTERS

(MEMORY MAPPED)

CONTROL,

STATUS, &

DATA BUFFERS

I/O PROCESSOR

TWO INDEPENDENT

DUAL-PORTED BLOCKS

ADDR DATA DATA

DATA

ADDR

ADDR DATA ADDR

PROCESSOR PORT I/O PORT

BLOCK0

BLOCK1

DUAL-PORTED SRAM

HOST PORT

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

DATA BUS

MUX

EXTERNAL PORT

JTAG TEST

AND EMULATION

GPIO

FLAGS

SDRAM

CONTROLLER

IOA

IOD

DAG2

8u4u32

MULT

Rev. B | Page 2 of 60 | November 2009

ADSP-21161N

TABLE OF CONTENTS

Summary ............................................................... 1

Revision History ...................................................... 2

General Description ................................................. 3

ADSP-21161N Family Core Architecture .................... 3

ADSP-21161N Memory and I/O Interface Features ....... 5

Development Tools ............................................... 9

Additional Information ........................................ 11

Pin Function Descriptions ....................................... 12

Boot Modes ....................................................... 17

Specifications ........................................................ 18

Operating Conditions .......................................... 18

Electrical Characteristics ....................................... 19

Package Information ............................................ 20

Absolute Maximum Ratings ................................... 20

ESD Caution ...................................................... 20

Timing Specifications ........................................... 20

Power Dissipation ............................................... 21

Output Drive Currents ......................................... 55

Test Conditions .................................................. 55

Environmental Conditions .................................... 56

225-Ball CSP_BGA Ball Configurations ....................... 57

Outline Dimensions ................................................ 59

Surface-Mount Design .......................................... 59

Ordering Guide ..................................................... 59

REVISION HISTORY

11/09—Rev. A to Rev. B.

Corrected all outstanding document errata.

Added 110 MHz products. See the following sections.

Benchmarks ........................................................... 3

Operating Conditions ............................................. 18

Electrical Characteristics .......................................... 19

Timing Specifications ............................................. 20

Ordering Guide ..................................................... 59

This revision contains a change in package nomenclature from

MiniBGA (or MBGA) to chip-scale package, ball grid array (or

CSP_BGA). This change in no way affects or changes fit, form,

or function of the actual product. See Ordering Guide .... 59

ADSP-21161N

Rev. B | Page 3 of 60 | November 2009

GENERAL DESCRIPTION

The ADSP-21161N SHARC

DSP is a low cost derivative of the

ADSP-21160 featuring Analog Devices Super Harvard Archi-

tecture. Easing portability, the ADSP-21161N is source code

compatible with the ADSP-21160 and with first generation

ADSP-2106x SHARC processors in SISD (Single-Instruction,

Single-Data) mode. Like other SHARC DSPs, the ADSP-

21161N is a 32-bit processor that is optimized for high perfor-

mance DSP applications. The ADSP-21161N includes a 100

MHz or 110 MHz core, a dual-ported on-chip SRAM, an inte-

grated I/O processor with multiprocessing support, and

multiple internal buses to eliminate I/O bottlenecks.

As was first offered in the ADSP-21160, the ADSP-21161N

offers a single-instruction multiple-data (SIMD) architecture.

Using two computational units (ADSP-2106x SHARC proces-

sors have one), the ADSP-21161N can double cycle

performance versus the ADSP-2106x on a range of DSP

algorithms.

Fabricated in a state of the art, high speed, low power CMOS

process, the ADSP-21161N has a 10 ns or 9 ns instruction cycle

time. With its SIMD computational hardware running at 110

MHz, the ADSP-21161N can perform 660 million math opera-

tions per second. Table 1 shows performance benchmarks for

the ADSP-21161N.

These benchmarks provide single-channel extrapolations of

measured dual-channel processing performance. For more

information on benchmarking and optimizing DSP code, for

both single and dual-channel processing, see the Analog Devices

Inc. website.

The ADSP-21161N continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features. These

features include a 1M bit dual ported SRAM memory, host pro-

cessor interface, I/O processor that supports 14 DMA channels,

four serial ports, two link ports, SDRAM controller, SPI inter-

face, external parallel bus, and glueless multiprocessing.

The block diagram of the ADSP-21161N on Page 1 illustrates

the following architectural features:

• Two processing elements, each made up of an ALU, multi-

plier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core every core proces-

sor cycle

•Interval timer

•On-Chip SRAM (1M bit)

• SDRAM controller for glueless interface to SDRAMs

• External port that supports:

• Interfacing to off-chip memory peripherals

• Glueless multiprocessing support for six

ADSP-21161N SHARCs

• Host port read/write of IOP registers

• DMA controller

• Four serial ports

•Two link ports

• SPI compatible interface

• JTAG test access port

• 12 general-purpose I/O pins

Figure 2 shows a typical single-processor system. A multipro-

cessing system appears in Figure 5 on Page 8.

ADSP-21161N FAMILY CORE ARCHITECTURE

The ADSP-21161N includes the following architectural features

of the ADSP-2116x family core. The ADSP-21161N is code

compatible at the assembly level with the ADSP-21160,

ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L.

SIMD Computational Engine

The ADSP-21161N contains two computational processing ele-

ments that operate as a single-instruction multiple-data (SIMD)

engine. The processing elements are referred to as PEX and

PEY, and each contains an ALU, multiplier, shifter, and register

file. PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the

bandwidth between memory and the processing elements.

Table 1. Benchmarks

Benchmark Algorithm

100 MHz

Instruction

Rate

110 MHz

Instruction

Rate

1024 Point Complex FFT

(Radix 4, with Reversal)

92 μs 83.6 μs

FIR Filter (Per Tap) 5 ns 4.5 ns

IIR Filter (Per Biquad) 20 ns 18.18 ns

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1] 45 ns 40.9 ns

[4 × 4] × [4 × 1] 80 ns 72.72 ns

Divide (y/x) 60 ns 54.54 ns

Inverse Square Root 40 ns 36.36 ns

DMA Transfers 800M bytes/s 880M bytes/s

Rev. B | Page 4 of 60 | November 2009

ADSP-21161N

When using the DAGs to transfer data in SIMD mode, two data

values are transferred with each access of memory or the regis-

ter file.

SIMD is supported only for internal memory accesses and is not

supported for off-chip accesses.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform single-cycle

instructions. The three units within each processing element are

arranged in parallel, maximizing computational throughput.

Single multifunction instructions execute parallel ALU and

multiplier operations. In SIMD mode, the parallel ALU and

multiplier operations occur in both processing elements. These

computation units support IEEE 32-bit single-precision float-

ing-point, 40-bit extended precision floating-point, and 32-bit

fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

architecture, allow unconstrained data flow between computa-

tion units and internal memory. The registers in PEX are

referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21161N features an enhanced Harvard architecture

in which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With the ADSP-21161N’s separate program and

data memory buses and on-chip instruction cache, the proces-

sor can simultaneously fetch four operands (two over each data

bus) and an instruction (from the cache), all in a single cycle.

Figure 2. System Diagram

DMA DEVICE

(OPTIONAL)

DATA

CLKOUT

DMAR2-1

DMAG2-1

ADDR

DATA

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

CLOCK CLKIN

XTAL

IRQ2-0

2CLK_CFG1-0

EBOOT

LBOOT

FLAG11-0

TIMEXP

CLKDBL

RESET JTAG

SBTS

ADSP-21161N

BMS

LINK

DEVICES

(2 MAX)

(OPTIONAL)

LXCLK

LXACK

LXDAT7-0

SCLK0

D0B

D0A

FS0

SERIAL

DEVICE

(OPTIONAL)

CSBOOT

EPROM

(OPTIONAL)

ADDR

MEMORY

AND

PERIPHERALS

(OPTIONAL)

DATA

RAS

ACK

BR6-1

RPBA

ID2-0

HBG

HBR

SDWE

MS3-0

DATA47-16

DATA

ADDR

ACK

ADDR23-0

DATA

CONTROL

ADDRESS

BRST

SDRAM

(OPTIONAL)

SCLK1

D1B

D1A

FS1

SERIAL

DEVICE

(OPTIONAL)

SCLK2

D2B

D2A

FS2

SERIAL

DEVICE

(OPTIONAL)

SCLK3

D3B

D3A

FS3

SERIAL

DEVICE

(OPTIONAL)

SPICLK

MISO

MOSI

SPIDS

SPI

COMPATIBLE

DEVICE

(HOSTORSLAVE)

(OPTIONAL)

DATA

CAS

RAS

DQM

ADDR

A10

CKE

CLK

DQM

CAS

REDY

SDCKE

SDA10

SDCLK1-0

RSTOUT

ADSP-21161N

Rev. B | Page 5 of 60 | November 2009

Instruction Cache

The ADSP-21161N includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache enables full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators With Hardware Circular Buffers

The ADSP-21161N’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the ADSP-21161N con-

tain sufficient registers to allow the creation of up to 32 circular

buffers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wrap-around, reduce

overhead, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21161N can conditionally execute a multiply, an add,

and a subtract in both processing elements, while branching, all

in a single instruction.

ADSP-21161N MEMORY AND I/O INTERFACE

FEATURES

The ADSP-21161N adds the following architectural features to

the ADSP-2116x family core.

Dual-Ported On-Chip Memory

The ADSP-21161N contains one megabit of on-chip SRAM,

organized as two blocks of 0.5M bits (Figure 3). Each block can

be configured for different combinations of code and data stor-

age. Each memory block is dual-ported for single-cycle,

independent accesses by the core processor and I/O processor.

The dual-ported memory in combination with three separate

on-chip buses allow two data transfers from the core and one

from the I/O processor, in a single cycle. On the ADSP-21161N,

the memory can be configured as a maximum of 32K words of

32-bit data, 64K words of 16-bit data, 21K words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to one megabit. All of the memory can be accessed as

16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the amount

of data that may be stored on-chip. Conversion between the

32-bit floating-point and 16-bit floating-point formats is done

in a single instruction. While each memory block can store

combinations of code and data, accesses are most efficient when

one block stores data using the DM bus for transfers, and the

other block stores instructions and data using the PM bus for

transfers. Using the DM bus and PM bus, with one dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

Off-Chip Memory and Peripherals Interface

The ADSP-21161N’s external port provides the processor’s

interface to off-chip memory and peripherals. The 62.7-M word

off-chip address space (254.7-M word if all SDRAM) is included

in the ADSP-21161N’s unified address space. The separate on-

chip buses—for PM addresses, PM data, DM addresses, DM

data, I/O addresses, and I/O data—are multiplexed at the exter-

nal port to create an external system bus with a single 24-bit

address bus and a single 32-bit data bus. Every access to external

memory is based on an address that fetches a 32-bit word.

When fetching an instruction from external memory, two 32-bit

data locations are being accessed for packed instructions.

Unused link port lines can also be used as additional data lines

DATA15–DATA0, allowing single-cycle execution of instruc-

tions from external memory, at up to 110 MHz. Figure 4 shows

the alignment of various accesses to external memory.

The external port supports asynchronous, synchronous, and

synchronous burst accesses. Synchronous burst SRAM can be

interfaced gluelessly. The ADSP-21161N also can interface glue-

lessly to SDRAM. Addressing of external memory devices is

facilitated by on-chip decoding of high-order address lines to

generate memory bank select signals. The ADSP-21161N pro-

vides programmable memory wait states and external memory

acknowledge controls to allow interfacing to memory and

peripherals with variable access, hold, and disable time

requirements.

SDRAM Interface

The SDRAM interface enables the ADSP-21161N to transfer

data to and from synchronous DRAM (SDRAM) at the core

clock frequency or at one-half the core clock frequency. The

synchronous approach, coupled with the core clock frequency,

supports data transfer at a high throughput—up to 440M

bytes/s for 32-bit transfers and up to 660M bytes/s for 48-bit

transfers.

The SDRAM interface provides a glueless interface with stan-

dard SDRAMs—16Mb, 64Mb, 128Mb, and 256Mb— and

includes options to support additional buffers between the

ADSP-21161N and SDRAM. The SDRAM interface is

extremely flexible and provides capability for connecting

SDRAMs to any one of the ADSP-21161N’s four external mem-

ory banks, with up to all four banks mapped to SDRAM.

Systems with several SDRAM devices connected in parallel may

require buffering to meet overall system timing requirements.

The ADSP-21161N supports pipelining of the address and con-

trol signals to enable such buffering between itself and multiple

SDRAM devices.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21161N

processor to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

Rev. B | Page 6 of 60 | November 2009

ADSP-21161N

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor’s JTAG interface ensures that

the emulator will not affect target system loading or timing.

For complete information on SHARC Analog Devices DSP

Tools product line of JTAG emulator operation, see the appro-

priate Emulator Hardware User’s Guide. For detailed infor-

mation on the interfacing of Analog Devices JTAG emulators

with Analog Devices DSP products with JTAG emulation ports,

please refer to Engineer to Engineer Note EE-68: Analog Devices

JTAG Emulation Technical Reference. Both of these documents

can be found on the Analog Devices website.

DMA Controller

The ADSP-21161N’s on-chip DMA controller enables zero-

overhead data transfers without processor intervention. The

DMA controller operates independently and invisibly to the

processor core, allowing DMA operations to occur while the

core is simultaneously executing its program instructions. DMA

transfers can occur between the ADSP-21161N’s internal mem-

ory and external memory, external peripherals, or a host

processor. DMA transfers can also occur between the ADSP-

21161N’s internal memory and its serial ports, link ports, or the

SPI-compatible (Serial Peripheral Interface) port. External bus

packing and unpacking of 32-, 48-, or 64-bit words in internal

memory is performed during DMA transfers from either 8-,

16-, or 32-bit wide external memory. Fourteen channels of

DMA are available on the ADSP-21161N—two are shared

between the SPI interface and the link ports, eight via the serial

ports, and four via the processor’s external port (for host pro-

cessor, other ADSP-21161Ns, memory, or I/O transfers).

Programs can be downloaded to the ADSP-21161N using DMA

transfers. Asynchronous off-chip peripherals can control two

DMA channels using DMA Request/Grant lines (DMAR2–1,

DMAG2–1). Other DMA features include interrupt generation

upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

Figure 3. Memory Map

0x000A 0000

0x000A7FFF(BLK1)

0x0002 8000

0x0002 9FFF (BLK 1)

0x0005 0000

0x0005 3FFF (BLK 1)

0x0010 0000

0x0011 FFFF

0x0004 0000

0x0004 3FFF (BLK 0)

0x00080000

0X00087FFF (BLK 0)

0x0012 0000

0x0013FFFF

0x0014 0000

0x0015 FFFF

0x0016 0000

0x0017 FFFF

0x001A 0000

0x001B FFFF

0x0000 0000

0x0001 FFFF

0x0002 0000

0x0002 1FFF (BLK 0)

0x0020 0000

BANK 1

MS0

BANK 2

MS1

BANK 3

MS2

MS3

IOP REGISTERS

LONG WORD ADDRESSING

SHORT WORD ADDRESSING

NORMAL WORD ADDRESSING

ADDRESS

BANK 0

0x03FF FFFF (SDRAM)

0x00FF FFFF (NON-SDRAM)

0x0400 0000

0x07FF FFFF (SDRAM)

0x04FF FFFF (NON-SDRAM)

0x0800 0000

0x0BFF FFFF (SDRAM)

0x08FF FFFF (NON-SDRAM)

0x0C00 0000

0x0FFF FFFF (SDRAM)

0x0CFF FFFF (NON-SDRAM)

NOTE: BANK SIZESARE FIXED

0x00180000

0x0019 FFFF

INTERNAL

MEMORY

SPACE

MULTIPROCESSOR

MEMORY

SPACE

ADDRESS

IOP REGISTERSOF ADSP-21161N

WITH ID = 001

IOP REGISTERSOF ADSP-21161N

WITH ID = 010

IOP REGISTERSOF ADSP-21161N

WITH ID = 011

IOP REGISTERSOF ADSP-21161N

WITH ID = 100

IOP REGISTERSOF ADSP-21161N

WITH ID = 101

IOP REGISTERSOF ADSP-21161N

WITH ID = 110

RESERVED

0x001C 0000

0x001F FFFF

EXTERNAL MEMORY SPACE

ADSP-21161N

Rev. B | Page 7 of 60 | November 2009

Multiprocessing

The ADSP-21161N offers powerful features tailored to

multiprocessing DSP systems. The external port and link ports

provide integrated glueless multiprocessing support.

The external port supports a unified address space (see Figure 3)

that enables direct interprocessor accesses of each ADSP-

21161N’s internal memory-mapped (I/O processor) registers.

All other internal memory can be indirectly accessed via DMA

transfers initiated via the programming of the IOP DMA

parameter and control registers. Distributed bus arbitration

logic is included on-chip for simple, glueless connection of sys-

tems containing up to six ADSP-21161Ns and a host processor

(Figure 5). Master processor change over incurs only one cycle

of overhead. Bus arbitration is selectable as either fixed or rotat-

ing priority. Bus lock enables indivisible read-modify-write

sequences for semaphores. A vector interrupt is provided for

interprocessor commands. Using an instruction rate of 110

MHz, maximum throughput for interprocessor data transfer is

440M bytes/s over the external port.

Two link ports provide a second method of multiprocessing

communications. Each link port can support communications

to another ADSP-21161N. The ADSP-21161N, running at

110 MHz, has a maximum throughput for interprocessor com-

munications over the links of 220M bytes/s. The link ports and

cluster multiprocessing can be used concurrently or

independently.

Link Ports

The ADSP-21161N features two 8-bit link ports that provide

additional I/O capabilities. With the capability of running at

110 MHz, each link port can support 110M bytes/s. Link port

I/O is especially useful for point-to-point interprocessor com-

munication in multiprocessing systems. The link ports can

operate independently and simultaneously, with a maximum

data throughput of 220M bytes/s. Link port data is packed into

48- or 32-bit words and can be directly read by the core proces-

sor or DMA-transferred to on-chip memory. Each link port has

its own double-buffered input and output registers.

Clock/acknowledge handshaking controls link port transfers.

Transfers are programmable as either transmit or receive.

Serial Ports

The ADSP-21161N features four synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. Each serial port is made up of

two data lines, a clock and frame sync. The data lines can be

programmed to either transmit or receive.

The serial ports operate at up to half the clock rate of the core,

providing each with a maximum data rate of 50M bit/s. The

serial data pins are programmable as either a transmitter or

receiver, providing greater flexibility for serial communications.

Serial port data can be automatically transferred to and from

on-chip memory via a dedicated DMA. Each of the serial ports

features a Time Division Multiplex (TDM) multichannel mode,

where two serial ports are TDM transmitters and two serial

ports are TDM receivers (SPORT0 Rx paired with SPORT2 Tx,

SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports

also support the I

S protocol (an industry standard interface

commonly used by audio codecs, ADCs and DACs), with two

data pins, allowing four I

S channels (using two I

S stereo

devices) per serial port, with a maximum of up to 16 I

S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For I

S mode, data-word lengths are selectable between

8 bits and 32 bits. Serial ports offer selectable synchronization

and transmit modes as well as optional μ-law or A-law com-

panding. Serial port clocks and frame syncs can be internally or

externally generated.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard syn-

chronous serial link, enabling the ADSP-21161N SPI-

compatible port to communicate with other SPI-compatible

devices. SPI is a 4-wire interface consisting of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The ADSP-21161N SPI-com-

patible peripheral implementation also features programmable

baud rate and clock phase/polarities. The ADSP-21161N SPI-

compatible port uses open drain drivers to support a multimas-

ter configuration and to avoid data contention.

Host Processor Interface

The ADSP-21161N host interface enables easy connection to

standard 8-bit, 16-bit, or 32-bit microprocessor buses with little

additional hardware required. The host interface is accessed

through the ADSP-21161N’s external port. Four channels of

DMA are available for the host interface; code and data transfers

are accomplished with low software overhead. The host proces-

sor requests the ADSP-21161N’s external bus with the host bus

request (HBR), host bus grant (HBG), and chip select (CS) sig-

nals. The host can directly read and write the internal IOP

registers of the ADSP-21161N, and can access the DMA channel

Figure 4. External Data Alignment Options

DAT A1 5–0

15 870

L1DATA7–0

DATA15-8

L0DATA7–0

DATA7–0

16-BI T PACKED DMA DATA

16-BI T PACKED INSTRUC-

TION EXECUTION

FLOAT OR FIXED, D31– D0 ,

32-BIT PA CKED

32-BIT PA CKED INSTRUC-

TION

EX TRA DA TA LI NE SDATA15–0 AR E ONLY ACCE SSIBLE IF LINK PORTS

ARE D ISABLED. ENAB LE THESE ADDITIONAL DATA L INKSBY SELECT-

ING IP AC

–

1IN

YSC

48-BIT INSTRUCTION FETCH

(NO PACKING)

47 40 393231242316

DATA 4 7–1 6

8-BIT PACKED DMA D ATA

8-BIT PACKED INSTRUCTION

EXECUTION

PROM

BO O T

NOTE:

Rev. B | Page 8 of 60 | November 2009

ADSP-21161N

setup and message registers. DMA setup via a host would allow

it to access any internal memory address via DMA transfers.

Vector interrupt support provides efficient execution of host

commands.

The host processor interface can be used in either multiproces-

sor or single processor SHARC systems. For multiprocessor

systems, host access to the SHARC requires address pins

ADDR17, ADDR18, ADDR19, and ADDR20 to be driven low.

It is not enough to tie these pins to ground through a resistor

Figure 5. Shared Memory Multiprocessing System

ACK

ADDR

DATA

GLOBAL

MEMORY

AND

PERIPHERALS

(OPTIONAL)

CONTROL

ADSP-21161N #1

ADDR23-0

CONTROL

ADSP-21161N #3

ID2-0

RESET

CLKIN

ADSP-21161N #4

CLOCK

ADDR

DATA

SDRAM

(OPTIONAL)

ADDR

DATA

BOOT

EPROM

(OPTIONAL)

ID2-0

RESET

CLKIN

CONTROL

ADDRESS

DATA

CONTROL

ADDRESS

DATA

CONTROL

ADSP-21161N #2

ID2-0

RESET

CLKIN

ADDR

DATA

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

RAS

CAS

DQM

CLK

A10

CKE

DATA47-16

SDWE

RAS

CAS

DQM

SDCLK1-0

SDA10

SDCKE

BR6-2

MS3-0

SBTS

ACK

BR1

REDY

HBG

HBR

BMS

ADDR23-0

RESET

DATA47-16

ADDR23-0

DATA47-16

ADSP-21161N

Rev. B | Page 9 of 60 | November 2009

(for example 10k ohm). These pins must be driven low with a

strong enough drive strength (10–50 ohms) to overcome the

SHARC keeper latches present on these pins. If the drive

strength provided is not strong enough, data access failures can

occur.

For single processor SHARC systems using this host access fea-

ture, address pins ADDR17, ADDR18, ADDR19, and ADDR20

may be tied low (for example through a 10k ohm resistor),

driven low by a buffer/driver, or left floating. Any of these

options is sufficient.

General-Purpose I/O Ports

The ADSP-21161N also contains 12 programmable, general

purpose I/O pins that can function as either input or output. As

output, these pins can signal peripheral devices; as input, these

pins can provide the test for conditional branching.

Program Booting

The internal memory of the ADSP-21161N can be booted at

system power-up from either an 8-bit EPROM, a host processor,

the SPI interface, or through one of the link ports. Selection of

the boot source is controlled by the Boot Memory Select (BMS),

EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.

8-, 16-, or 32-bit host processors can also be used for booting.

Phase-Locked Loop and Crystal Double Enable

The ADSP-21161N uses an on-chip phase-locked loop (PLL) to

generate the internal clock for the core. The CLK_CFG1–0 pins

are used to select ratios of 2:1, 3:1, and 4:1. In addition to the

PLL ratios, the CLKDBL pin can be used for more clock ratio

options. The (1×/2× CLKIN) rate set by the CLKDBL

pin determines the rate of the PLL input clock and the rate at

which the external port operates. With the combination of

CLK_CFG1–0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1

between the core and CLKIN are supported. See also Figure 12

on Page 21.

Power Supplies

The ADSP-21161N has separate power supply connections for

the analog (AV

/AGND), internal (V

DDINT

), and external

DDEXT

) power supplies. The internal and analog supplies must

meet the 1.8 V requirement. The external supply must meet the

3.3 V requirement. All external supply pins must be connected

to the same supply.

Note that the analog supply (AV

) powers the ADSP-21161N’s

clock generator PLL. To produce a stable clock, provide an

external circuit to filter the power input to the AV

pin. Place

the filter as close as possible to the pin. The AV

filter circuit

shown in Figure 6 must be added for each ADSP-21161N in the

multiprocessor system. To prevent noise coupling, use a wide

trace for the analog ground (AGND) signal and install a decou-

pling capacitor as close as possible to the pin.

DEVELOPMENT TOOLS

The ADSP-21161N is supported with a complete set of software

and hardware development tools, including Analog Devices

emulators and VisualDSP++

development environment. The

same emulator hardware that supports other SHARC DSPs, also

fully emulates the ADSP-21161N.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy-to-use assembler that is based on an algebraic

syntax; an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ run-time library that includes DSP and mathemat-

ical functions. Two key points for these tools are:

• Compiled ADSP-21161N C/C++ code efficiency—The

compiler has been developed for efficient translation of

C/C++ code to ADSP-21161N assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

• ADSP-2106x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-2106x applications to the ADSP-21161N.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the syntax highlighting in the

VisualDSP++ editor. This capability permits:

• Controlling how the development tools process inputs and

generate outputs.

• Maintaining a one-to-one correspondence with the tool’s

command line switches.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test

access port of the ADSP-21161N processor to monitor and con-

trol the target board processor during emulation. The emulator

Figure 6. Analog Power (AV

) Filter Circuit

10 ⍀

VDDINT

0.1␮F0.01␮F

AGND

AVDD

Rev. B | Page 10 of 60 | November 2009

ADSP-21161N

provides full-speed emulation, allowing inspection and modifi-

cation of memory, registers, and processor stacks. Nonintrusive

in-circuit emulation is assured by the use of the processor’s

JTAG interface—the emulator does not affect target system

loading or timing.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC PC plug-in cards. Third party

software tools include DSP libraries, real-time operating sys-

tems, and block diagram design tools.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices DSP Tools family of emulators are tools

that every DSP developer needs to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG DSP. The emulator

uses the TAP to access the internal features of the DSP, allowing

the developer to load code, set breakpoints, observe variables,

observe memory, and examine registers. The DSP must be

halted to send data and commands, but once an operation has

been completed by the emulator, the DSP system is set running

at full speed with no impact on system timing.

To use these emulators, the target’s design must include the

interface between an Analog Devices JTAG DSP and the emula-

tion header on a custom DSP target board.

Target Board Header

The emulator interface to an Analog Devices JTAG DSP is a

14-pin header, as shown in Figure 7. The customer must supply

this header on the target board in order to communicate with

the emulator. The interface consists of a standard dual row

0.025" square post header, set on 0.1" ×0.1" spacing, with a min-

imum post length of 0.235". Pin 3 is the key position used to

prevent the pod from being inserted backwards. This pin must

be clipped on the target board.

Also, the clearance (length, width, and height) around the

header must be considered. Leave a clearance of at least 0.15"

and 0.10" around the length and width of the header, and

reserve a height clearance to attach and detach the pod

connector.

As shown in Figure 7, there are two sets of signals on the header.

There are the standard JTAG signals TMS, TCK, TDI, TDO,

TRST, and EMU used for emulation purposes (via an emulator).

There are also secondary JTAG signals BTMS, BTCK, BTDI,

and BTRST that are optionally used for board-level (boundary

scan) testing.

When the emulator is not connected to this header, place jump-

ers across BTMS, BTCK, BTRST, and BTDI as shown in

Figure 8. This holds the JTAG signals in the correct state to

allow the DSP to run free. Remove all the jumpers when con-

necting the emulator to the JTAG header.

Figure 8. JTAG Target Board Connector with No

Local Boundary Scan

Figure 7. JTAG Target Board Connector for JTAG Equipped Analog Devices

DSP (Jumpers in Place)

TOP VIEW

1314

11 12

910

EMU

GND

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

TOP VIEW

1314

11 12

910

GND

TMS

TCK

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTDI

GND

BTRST TRST

EMU

ADSP-21161N

Rev. B | Page 11 of 60 | November 2009

JTAG Emulator Pod Connector

Figure 9 details the dimensions of the JTAG pod connector at

the 14-pin target end. Figure 10 displays the keep-out area for a

target board header. The keep-out area enables the pod connec-

tor to properly seat onto the target board header. This board

area should contain no components (chips, resistors, capacitors,

etc.). The dimensions are referenced to the center of the 0.025"

square post pin.

Design-for-Emulation Circuit Information

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68”. This document is updated regularly

to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-21161N architecture and functionality. For detailed

information on the ADSP-2116x Family core architecture and

instruction set, refer to the ADSP-21161 SHARC DSP Hardware

Reference and the ADSP-21160 SHARC DSP Instruction Set

Reference.

Figure 9. JTAG Pod Connector Dimensions

Figure 10. JTAG Pod Connector Keep-Out Area

0.64"

0.88"

0.24"

0.10"

0.1 5"

Rev. B | Page 12 of 60 | November 2009

ADSP-21161N

PIN FUNCTION DESCRIPTIONS

ADSP-21161N pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-

tified as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST).Tie or pull unused inputs to

DDEXT

or GND, except for the following:

• ADDR23–0, DATA47–0, BRST, CLKOUT (Note: These

pins have a logic-level hold circuit enabled on the

ADSP-21161N DSP with ID2–0 = 00x.)

•PA

, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)

(Note: These pins have a pull-up enabled on the

ADSP-21161N DSP with ID2–0 = 00x.)

• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See

Link Port Buffer Control Register Bit definitions in the

ADSP-21161N SHARC DSP Hardware Reference.)

• DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,

TMS,TRST, TDI (Note: These pins have a pull-up.)

The following symbols appear in the Type column of Table 2:

A = Asynchronous, G = Ground, I = Input, O = Output,

P = Power Supply, S = Synchronous, (A/D) = Active Drive,

(O/D) = Open Drain, and T = Three-State (when SBTS is

asserted or when the ADSP-21161N is a bus slave).

Unlike previous SHARC processors, the ADSP-21161N con-

tains internal series resistance equivalent to 50 Ω on all

input/output drivers except the CLKIN and XTAL pins.

Therefore, for traces longer than six inches, external series resis-

tors on control, data, clock, or frame sync pins are not required

to dampen reflections from transmission line effects for point-

to-point connections. However, for more complex networks

such as a star configuration, series termination is still

recommended.

Table 2. Pin Function Descriptions

Pin Type Function

ADDR23–0 I/O/T External Bus Address. The ADSP-21161N outputs addresses for external memory and peripherals on these

pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other

ADSP-21161Ns while all other internal memory resources can be accessed indirectly via DMA control (that

is, accessing IOP DMA parameter registers). The ADSP-21161N inputs addresses when a host processor or

multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0 pins

maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with

ID2–0=00x.

DATA47–16 I/O/T External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these pins. Pull-up

resistors on unused data pins are not necessary. A keeper latch on the DSP’s DATA47–16 pins maintains the

input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2–0=00x.

Note: DATA15–8 pins (multiplexed with L1DAT7–0) can also be used to extend the data bus if the link ports are

disabled and will not be used. In addition, DATA7–0 pins (multiplexed with L0DAT7–0) can also be used to extend

the data bus if the link ports are not used. This enables execution of 48-bit instructions from external SBSRAM

(system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half

the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1–0= 0x1)

to enable this full instruction Width/No-packing Mode of operation.

MS3–0 I/O/T Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of

external memory. Memory bank sizes are fixed to 16 M words for non-SDRAM and 64M words for SDRAM.

The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs

transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the

other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. In a

multiprocessor system, the MSx signals are tracked by slave SHARCs.

RD I/O/T Memory Read Strobe. RD is asserted whenever ADSP-21161N reads a word from external memory or from

the IOP registers of other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert RD

for reading from a word of the ADSP-21161N IOP register memory. In a multiprocessing system, RD is driven

by the bus master. RD has a 20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

WR I/O/T Memory Write Low Strobe. WR is asserted when ADSP-21161N writes a word to external memory or IOP

registers of other ADSP-21161Ns. External devices must assert WR for writing to ADSP-21161N IOP registers.

In a multiprocessing system, the bus master drives WR. WR has a 20 kΩ internal pull-up resistor that is enabled

for DSPs with ID2–0=00x.

ADSP-21161N

Rev. B | Page 13 of 60 | November 2009

BRST I/O/T Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data associated with consecutive

addresses is being read or written. A slave device samples the initial address and increments an internal

address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-

21161N in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol.

BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for

the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the DSP’s

BRST pin maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N

with ID2–0=00x.

ACK I/O/S Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an external memory

access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an

external memory access. The ADSP-21161N deasserts ACK as an output to add wait states to a synchronous

access of its IOP registers. ACK has a 20 kΩ internal pull-up resistor that is enabled during reset or on DSPs

with ID2–0=00x.

SBTS I/S Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address,

data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21161N attempts to

access external memory while SBTS is asserted, the processor will halt and the memory access will not be

completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21161N

deadlock.

CAS I/O/T SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,

defines the operation for the SDRAM to perform.

RAS I/O/T SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines

the operation for the SDRAM to perform.

SDWE I/O/T SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the

operation for the SDRAM to perform.

DQM O/T SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command

and during SDRAM power-up initialization.

SDCLK0 I/O/S/T SDRAM Clock Output 0. Clock for SDRAM devices.

SDCLK1 O/S/T SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices,

handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or

both SDCLKx pins can be three-stated.

SDCKE I/O/T SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with the

SDRAM device.

SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-SDRAM accesses or host

accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

IRQ2–0 I/A Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-triggered

or level-sensitive.

FLAG11–0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a

condition. As an output, it can be used to signal external peripherals.

TIMEXP O Timer Expired. Asserted for four core clock cycles when the timer is enabled and TCOUNT decrements to zero.

HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21161N’s external

bus. When HBR is asserted in a multiprocessing system, the ADSP-21161N that is bus master will relinquish

the bus and assert HBG. To relinquish the bus, the ADSP-21161N places the address, data, select, and strobe

lines in a high impedance state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multipro-

cessing system.

HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of

the external bus. HBG is asserted (held low) by the ADSP-21161N until HBR is released. In a multiprocessing

system, HBG is output by the ADSP-21161N bus master and is monitored by all others.

After HBR is asserted, and before HBG is given, HBG will float for 1 t

(1 CLKIN cycle). To avoid erroneous

grants, HBG should be pulled up with a 20kΩ to 50kΩ external resistor.

CS I/A Chip Select. Asserted by host processor to select the ADSP-21161N.

REDY O (O/D) Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to a host access of its

IOP registers when CS and HBR inputs are asserted.

Table 2. Pin Function Descriptions (Continued)

Pin Type Function

Rev. B | Page 14 of 60 | November 2009

ADSP-21161N

DMAR1 I/A DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has

a 20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

DMAR2 I/A DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has

a 20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

DMAG1 O/T DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the requested DMA starts on the

next cycle. Driven by bus master only. DMAG1 has a 20 kΩ internal pull-up resistor that is enabled for DSPs

with ID2–0=00x.

DMAG2 O/T DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the requested DMA starts on the

next cycle. Driven by bus master only. DMAG2 has a 20 kΩ internal pull-up resistor that is enabled for DSPs

with ID2–0=00x.

BR6–1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for bus mastership. An

ADSP-21161N only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all

others. In a multiprocessor system with less than six ADSP-21161Ns, the unused BRx pins should be pulled

high; the processor's own BRx line must not be pulled high or low because it is an output.

BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is current bus master

of the shared external bus. The ADSP-21161N drives BMSTR high only while it is the bus master. In a single-

processor system (ID=000), the processor drives this pin high. This pin is used for debugging purposes.

ID2–0 I Multiprocessing ID. Determines which multiprocessing bus request (BR6–BR1) is used by ADSP-21161N.

ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on. Use ID=000 or ID=001 in single-

processor systems. These lines are a system configuration selection that should be hardwired or only changed

at reset.

RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus

arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration

selection that must be set to the same value on every ADSP-21161N. If the value of RPBA is changed during

system operation, it must be changed in the same CLKIN cycle on every ADSP-21161N.

PA I/O/T Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt background DMA

transfers and gain access to the external bus. PA is connected to all ADSP-21161Ns in the system. If access

priority is not required in a system, the PA pin should be left unconnected. PA has a 20 kΩ internal pull-up

resistor that is enabled for DSPs with ID2–0=00x.

DxA I/O Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor.

Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to

receive serial data.

DxB I/O Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor.

Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to

receive serial data.

SCLKx I/O Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal pull-up resistor. This

signal can be either internally or externally generated.

FSx I/O Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data.

This signal is either generated internally or externally. It can be active high or low or an early or a late frame

sync, in reference to the shifting of serial data.

SPICLK I/O Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is

transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit trans-

mitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word.

Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift

out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge

of the clock and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data

are programmable into the SPICTL control register and define the transfer format. SPICLK has a 50 kΩ internal

pull-up resistor.

Table 2. Pin Function Descriptions (Continued)

Pin Type Function

ADSP-21161N

Rev. B | Page 15 of 60 | November 2009

SPIDS ISerial Peripheral Interface Slave Device Select. An active low signal used to enable slave devices. This input

signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster

mode SPIDS signal can be asserted to a master device to signal that an error has occurred, as some other

device is also trying to be the master device. If asserted low when the device is in master mode, it is considered

a multimaster error. For a single-master, multiple-slave configuration where FLAG3–0 are used, this pin must

be tied or pulled high to V

DDEXT

on the master device. For ADSP-21161N to ADSP-21161N SPI interaction, any

of the master ADSP-21161N’s FLAG3–0 pins can be used to drive the SPIDS signal on the ADSP-21161N SPI

slave device.

MOSI I/O (o/d) SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin becomes a data transmit

(output) pin, transmitting output data. If the ADSP-21161N is configured as a slave, the MOSI pin becomes a

data receive (input) pin, receiving input data. In an ADSP-21161N SPI interconnection, the data is shifted out

from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal

pull-up resistor.

MISO I/O (o/d) SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin becomes a data receive

(input) pin, receiving input data. If the ADSP-21161N is configured as a slave, the MISO pin becomes a data

transmit (output) pin, transmitting output data. In an ADSP-21161N SPI interconnection, the data is shifted

out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has an

internal pull-up resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.

Note: Only one slave is allowed to transmit data at any given time.

LxDAT7–0

[DATA15–0]

I/O

[I/O/T]

Link Port Data (Link Ports 0–1).

For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data

pin; or a 20 kΩ internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.

For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 kΩ internal pull-down resistor that is enabled

or disabled by the LxPDRDE bit of the LCTL register.

Note: L1DAT7–0 are multiplexed with the DATA15–8 pins L0DAT7–0 are multiplexed with the DATA7–0 pins. If link

ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at

up to the full clock rate from external memory. See DATA47–16 for more information.

LxCLK I/O Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 kΩ resistor that is enabled or

disabled by the LxPDRDE bit of the LCTL register.

LxACK I/O Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down 50 kΩ resistor that is

enabled or disabled by the LxPDRDE bit of the LCTL register.

EBOOT I EPROM Boot Select. For a description of how this pin operates, see the table in the BMS pin description. This

signal is a system configuration selection that should be hardwired.

LBOOT I Link Boot. For a description of how this pin operates, see the table in the BMS pin description. This signal is

a system configuration selection that should be hardwired.

BMS I/O/T Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins (see Table 4).

This input is a system configuration selection that should be hardwired. For Host and PROM boot, DMA

channel 10 (EPB0) is used. For Link boot and SPI boot, DMA channel 8 is used.

Three-state only in EPROM boot mode (when BMS is an output).

CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input. It configures the ADSP-

21161N to use either its internal clock generator or an external clock source. Connecting the necessary

components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN

while leaving XTAL unconnected configures the ADSP-21161N to use the external clock source such as an

external clock oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The instruction

cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the CLK_CFG1–0 pins.

CLKIN may not be halted, changed, or operated below the specified frequency.

XTAL O Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-21161N’s internal clock

oscillator or to disable it to use an external clock source. See CLKIN.

CLK_CFG1-0 I Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal to n × PLLICLK where

n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs. These pins can also be used in combination

with the CLKDBL pin to generate additional core clock rates of 6 ×CLKIN and 8 ×CLKIN (see the Clock Rate

Ratios table in the CLKDBL description).

Table 2. Pin Function Descriptions (Continued)

Pin Type Function

Rev. B | Page 16 of 60 | November 2009

ADSP-21161N

CLKDBL ICrystal Double Mode Enable. This pin is used to enable the 2× clock double circuitry, where CLKOUT can

be configured as either 1× or 2× the rate of CLKIN. This CLKIN double circuit is primarily intended to be used

for an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock

generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to

a maximum of 27.5 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 55 MHz

input into the PLL. The 2× clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is

connected to V

DDEXT

for 1× clock mode. For example, this enables the use of a 27.5 MHz crystal to enable 110

MHz core clock rates and a 55 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0.

This pin can also be used to generate different clock rate ratios for external clock oscillators as well. The

possible clock rate ratio options (up to 110 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal

input) are shown in Table 3 on Page 17. An 8:1 ratio enables the use of a 12.5 MHz crystal to generate a 100

MHz core (instruction clock) rate and a 25 MHz CLKOUT (external port) clock rate. See also Figure 12 on

Page 21. Note: When using an external crystal, the maximum crystal frequency cannot exceed 27.5 MHz. For all

other external clock sources, the maximum CLKIN frequency is 55 MHz.

CLKOUT O/T Local Clock Out. CLKOUT is 1× or 2× and is driven at either 1× or 2× the frequency of CLKIN frequency by the

current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the

ADSP-21161N is not the bus master or when the host controls the bus (HBG asserted). A keeper latch on the

DSP’s CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on the ADSP-

21161N with ID2–0=00x.

If CLKDBL enabled, CLKOUT=2 × CLKIN

If CLKDBL disabled, CLKOUT=1 × CLKIN

Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1

CLKIN or 2

CLKIN.

Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.

RESET I/A Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the program memory

location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up.

RSTOUT

OReset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in reset. It is deasserted

4080 cycles after RESET is deasserted indicating that the PLL is stable and locked.

TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan.

TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor.

TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up

resistor.

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held

low for proper operation of the ADSP-21161N. TRST has a 20 kΩ internal pull-up resistor.

EMU O (O/D) Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools product line of JTAG

emulators target board connector only. EMU has a 50 kΩ internal pull-up resistor.

DDINT

PCore Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).

DDEXT

PI/O Power Supply. Nominally +3.3 V dc. (13 pins).

AVDD P Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock generator). This pin

has the same specifications as V

DDINT

, except that added filtering circuitry is required. For more information,

see Power Supplies on Page 9.

AGND G Analog Power Supply Return.

GND G Power Supply Return. (26 pins).

NC Do Not Connect. Reserved pins that must be left open and unconnected. (4 pins).

RSTOUT exists only for silicon revisions 1.2 and greater.

Table 2. Pin Function Descriptions (Continued)

Pin Type Function

ADSP-21161N

Rev. B | Page 17 of 60 | November 2009

BOOT MODES

Table 3. Clock Rate Ratios

CLKDBL CLK_CFG1 CLK_CFG0 Core:CLKIN CLKIN:CLKOUT

10 0 2:1 1:1

10 1 3:1 1:1

11 0 4:1 1:1

00 0 4:1 1:2

00 1 6:1 1:2

01 0 8:1 1:2

Table 4. Boot Mode Selection

EBOOT LBOOT BMS Booting Mode

1 0 Output EPROM (Connect BMS to EPROM chip select.)

0 0 1 (Input) Host Processor

0 1 0 (Input) Serial Boot via SPI

0 1 1 (Input) Link Port

0 0 0 (Input) No Booting. Processor executes from external memory.

11x (Input)Reserved

Rev. B | Page 18 of 60 | November 2009

ADSP-21161N

SPECIFICATIONS

OPERATING CONDITIONS

Parameter

Specifications subject to change without notice.

Description Test Conditions

100 MHz 110 MHz

UnitMinMax MinMax

DDINT

Internal (Core) Supply Voltage 1.71 1.89 1.71 1.89 V

Analog (PLL) Supply Voltage 1.71 1.89 1.71 1.89 V

DDEXT

External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V

High Level Input Voltage

Applies to input and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, DMAR1, DMAR2, BR6–1, ID2–0,

RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE,

CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI.

@ V

DDEXT

= Max 2.0 V

DDEXT

+0.5 2.0 V

DDEXT

+0.5 V

Low Level Input Voltage

@ V

DDEXT

= Min –0.5 +0.8 –0.5 +0.8 V

CASE

Case Operating Temperature

See Thermal Characteristics on Page 56 for information on thermal specifications.

–40+105 –40+125 °C

ADSP-21161N

Rev. B | Page 19 of 60 | November 2009

ELECTRICAL CHARACTERISTICS

Parameter Description Test Conditions Min Max Unit

High Level Output Voltage

@ V

DDEXT

= Min, I

= –2.0 mA

2.4 V

Low Level Output Voltage

@ V

DDEXT

= Min, I

= 4.0 mA

0.4 V

High Level Input Current

@ V

DDEXT

= Max, V

= V

DDEXT

Max 10 μA

Low Level Input Current

@ V

DDEXT

= Max, V

= 0 V 10 μA

IHC

CLKIN High Level Input Current

@ V

DDEXT

= Max, V

= V

DDEXT

Max 35 μA

ILC

CLKIN Low Level Input Current

@ V

DDEXT

= Max, V

= 0 V 35 μA

IKH

Keeper High Load Current

@ V

DDEXT

= Max, V

= 2.0 V –250 –100 μA

IKL

Keeper Low Load Current

@ V

DDEXT

= Max, V

= 0.8 V 50 200 μA

IKH-OD

Keeper High Overdrive Current

@ V

DDEXT

= Max –300 μA

IKL-OD

Keeper Low Overdrive Current

@ V

DDEXT

= Max 300 μA

ILPU

Low Level Input Current Pull-Up

@ V

DDEXT

= Max, V

= 0 V 350 μA

OZH

Three-State Leakage Current

10,

@ V

DDEXT

= Max, V

= V

DDEXT

Max 10 μA

OZL

Three-State Leakage Current

9, 12, 13

@ V

DDEXT

= Max, V

= 0 V 10 μA

OZLPU1

Three-State Leakage Current Pull-Up1

@ V

DDEXT

= Max, V

= 0 V 500 μA

OZLPU2

Three-State Leakage Current Pull-Up2

@ V

DDEXT

= Max, V

= 0 V 350 μA

OZHPD1

Three-State Leakage Current Pull-Down1

@ V

DDEXT

= Max, V

= V

DDEXT

Max 350 μA

OZHPD2

Three-State Leakage Current Pull-Down2

@ V

DDEXT

= Max, V

= V

DDEXT

Max 500 μA

DD-INPEAK

Supply Current (Internal)

14, 15

CCLK

= 9.0 ns, V

DDINT

= Max

CCLK

= 10.0 ns, V

DDINT

= Max

965

900

DD-INHIGH

Supply Current (Internal)

15, 16

CCLK

= 9.0 ns, V

DDINT

= Max

CCLK

= 10.0 ns, V

DDINT

= Max

700

650

DD-INLOW

Supply Current (Internal)

15, 17

CCLK

= 9.0 ns, V

DDINT

= Max

CCLK

= 10.0 ns, V

DDINT

= Max

535

500

DD-IDLE

Supply Current (Idle)

15, 18

CCLK

= 9.0 ns, V

DDINT

= Max

CCLK

= 10.0 ns, V

DDINT

= Max

425

400

Supply Current (Analog)

@ AV

= Max 10 mA

Input Capacitance

20, 21

= 1 MHz, T

CASE

= 25°C, V

= 1.8 V 4.7 pF

Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,

BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,

TDO, CLKOUT, TIMEXP, RSTOUT.

See Output Drive Currents on Page 55 for typical drive current capabilities.

Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,

SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.

Applies to input pins with 20 kΩ internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.

Applies to CLKIN only.

Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.

Current required to switch from kept high to low or from kept low to high.

Characterized, but not tested.

Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,

BRST.

Applies to three-statable pins with 20 kΩ pull-ups: RD, WR, DMAG1, DMAG2, PA.

Applies to three-statable pins with 50 kΩ internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.

Applies to three-statable pins with 50 kΩ internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use I

OZHPD2

for Rev. 1.2 and higher.

Applies to three-statable pins with 20 kΩ internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).

The test program used to measure I

DDINPEAK

represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 21.

Current numbers are for V

DDINT

and AVDD supplies combined.

DDINHIGH

is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 21.

DDINLOW

is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 21.

Idle denotes ADSP-21161N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 21.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

Rev. B | Page 20 of 60 | November 2009

ADSP-21161N

PACKAGE INFORMATION

The information presented in Figure 11 provides details about

how to read the package brand and relate it to specific product

features.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 6 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

ESD CAUTION

TIMING SPECIFICATIONS

The ADSP-21161N’s internal clock switches at higher frequen-

cies than the system input clock (CLKIN). To generate the

internal clock, the DSP uses an internal phase-locked loop

(PLL). This PLL-based clocking minimizes the skew between

the system clock (CLKIN) signal and the DSP’s internal clock

(the clock source for the external port logic and I/O pads).

The ADSP-21161N’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, link ports, serial ports, and external port (as required for

read/write strobes in asynchronous access mode). During reset,

program the ratio between the DSP’s internal clock frequency

and external (CLKIN) clock frequency with the CLK_CFG1–0

and CLKDBL pins. Even though the internal clock is the clock

source for the external port, it behaves as described in the Clock

Rate Ratio chart in Table 3 on Page 17. To determine switching

frequencies for the serial and link ports, divide down the inter-

nal clock, using the programmable divider control of each port

(DIVx for the serial ports and LxCLKD for the link ports).

Note the following definitions of various clock periods that are a

function of CLKIN and the appropriate ratio control (Table 7).

Figure 12 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and

8:1 with external oscillator or crystal. It also shows support for

CLKOUT-to-CLKIN ratios of 1:1 and 2:1.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times.

See Figure 41 on Page 55 under Test Conditions for voltage ref-

erence levels.

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given circum-

stance. Use switching characteristics to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Figure 11. Typical Package Brand

Table 5. Package Brand Information

Brand Key Field Description

ADSP-21161N Model Number

tTemperature Range

pp Package Type

z RoHS Compliance Option

vvvvv.x Assembly Lot Code

n.n Silicon Revision

# RoHS Compliance Designation

yyww Date Code

Table 6. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V

DDINT

) –0.3 V to +2.2 V

Analog (PLL) Supply Voltage (A

VDD

) –0.3 V to +2.2 V

External (I/O) Supply Voltage (V

DDEXT

) –0.3 V to +4.6 V

Input Voltage –0.5 V to V

DDEXT

+ 0.5 V

Output Voltage Swing –0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance 200 pF

Storage Temperature Range –65°C to +150°C

vvvvvv.x n.n

#yyww country_of_origin

ADSP-21161N

tppZ-cc

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

ADSP-21161N

Rev. B | Page 21 of 60 | November 2009

POWER DISSIPATION

Total power dissipation has two components: one due to inter-

nal circuitry and one due to the switching of external output

drivers.

Internal power dissipation depends on the instruction execution

sequence and the data operands involved. Using the current

specifications (I

DDINPEAK

, I

DDINHIGH

, I

DDINLOW

, I

DDIDLE

) from the

Electrical Characteristics on Page 19 and the current-versus-

operation information in Table 8, the programmer can estimate

the ADSP-21161N’s internal power supply (V

DDINT

) input cur-

rent for a specific application, according to the following

formula:

% Peak × I

INPEAK

% High × I

INHIGH

% Low × I

INLOW

+ % Peak × I

IDLE

= I

DDINT

Figure 12. Core Clock and System Clock Relationship to CLKIN

Table 7. CLKOUT and CCLK Clock Generation Operation

Timing Requirements Description

Calculation

CLKIN Input Clock 1/t

CLKOUT External Port System Clock 1/t

CKOP

PLLICLK PLL Input Clock 1/t

PLLIN

CCLK Core Clock 1/t

CCLK

CLKIN Clock Period 1/CLKIN

CCLK

(Processor) Core Clock Period 1/CCLK

LCLK

Link Port Clock Period (t

CCLK

) × LR

SCLK

Serial Port Clock Period (t

CCLK

) × SR

SDK

SDRAM Clock Period (t

CCLK

) × SDCKR

SPICLK

SPI Clock Period (t

CCLK

) × SPIR

where:

LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)

SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)

SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)

LCLK = Link Port Clock

SCLK = Serial Port Clock

SDK = SDRAM Clock

SPICLK = SPI Clock

CLOCK DOUBLER

x1, x2

RATIOS

x2, x3,x4

PLL

ASYNCHRONOUSEP

HOST

SRAM

SYNCHRONOUSEP

MULTIPROCESSING

SBSRAM

HARDWARE

INTERRUPT

I/O FLAG

TIMER

PLLICLK

(4.2–50MHz)

CLKDBL CLKOUT CLK_CFG1–0

CLKIN

(CRYSTAL OSCILLATOR

4.2–55 MHz)

XTAL

(QUARTZ CRYSTAL

27.5 MHz MAX)

CORE

I/O PROCESSOR

SPI

x1/8MAX

SERIAL PORTS

x1/2 MAX

SDRAM

x1, x1/2

LINK PORTS

x1, x1/2, x1/3,x1/4

CCLK

(33.3–110MHz)

Rev. B | Page 22 of 60 | November 2009

ADSP-21161N

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• The number of output pins that switch during each cycle

(O)

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

• Their voltage swing (V

)

and is calculated by:

The load capacitance should include the processor package

capacitance (C

). The switching frequency includes driving the

load high and then back low. At a maximum rate of 1/t

address and data pins can drive high and low, while writing to a

SDRAM memory.

Example: Estimate P

EXT

with the following assumptions:

• A system with one bank of external memory (32 bit)

•Two 1M ⴛ 16 SDRAM chips are used, each with a load of

10 pF (ignoring trace capacitance)

• External Data Memory writes can occur every cycle at a

rate of 1/t

with 50% of the pins switching

• The bus cycle time is 55 MHz

• The external SDRAM clock rate is 110 MHz

• Ignoring SDRAM refresh cycles

• Addresses are incremental and on the same page

The P

EXT

equation is calculated for each class of pins that can

drive, as shown in Table 9.

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

Where:

EXT

is from Table 9.

INT

is I

DDINT

× 1.8 V, using the calculation I

DDINT

listed in Power

Dissipation on Page 21.

PLL

is AI

× 1.8 V, using the value for AI

listed in the Electri-

cal Characteristics on Page 19.

Note that the conditions causing a worst-case P

EXT

are different

from those causing a worst-case P

INT

. Maximum P

INT

cannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

Table 8. Operation Types Versus Input Current

Operation Peak Activity

DDINPEAK

)High Activity

DDINHIGH

)Low Activity

DDINLOW

)

Instruction Type Multifunction Multifunction Single Function

Instruction Fetch Cache Internal Memory Internal Memory

Core Memory Access

2 per t

cycle (DM×64 and PM×64) 1 per t

cycle (DM×64) None

Internal Memory DMA 1 per 2 t

CCLK

cycles 1 per 2 t

CCLK

cycles N/A

External Memory DMA 1 per external port cycle (×32) 1 per external port cycle (×32) N/A

Data bit pattern for core

memory access and DMA

Worst case Random N/A

The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.

These assume a 2:1 core clock ratio. For more information on ratios and clocks (t

and t

CCLK

), see the timing ratio definitions on Page 20.

PEXT OC×VDD

×f×=

PTOTAL PEXT PINT PPLL

++=

Table 9. External Power Calculations—110 MHz Instruction Rate

Pin Type Number of Pins % Switching ⴛ C ⴛ f ⴛ V

DD2

= P

EXT

Address 11 20 24.7 pF 55 MHz 10.9 V = 0.033 W

MSx 4 0 24.7 pF N/A 10.9 V = 0.000 W

SDWE 1 0 24.7 pF N/A 10.9 V = 0.000 W

Data 32 50 14.7 pF 55 MHz 10.9 V = 0.141 W

SDCLK0 1 100 24.7 pF 110 MHz 10.9 V = 0.030 W

EXT

= 0.204 W

ADSP-21161N

Rev. B | Page 23 of 60 | November 2009

Power-Up Sequencing — Silicon Revision 1.2 and Greater

The timing requirements for DSP startup are given in Table 10.

During the power-up sequence of the DSP, differences in the

ramp-up rates and activation time between the two supplies can

cause current to flow in the I/O ESD protection circuitry. To

prevent damage to the ESD diode protection circuitry, Analog

Devices recommends including a bootstrap Schottky diode.

The bootstrap Schottky diode is connected between the 1.8 V

and 3.3 V power supplies as shown in Figure 13. It protects the

ADSP-21161N from partially powering the 3.3 V supply.

Including a Schottky diode will shorten the delay between

the supply ramps and thus prevent damage to the ESD diode

protection circuitry. With this technique, if the 1.8 V rail rises

ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail

along with the 1.8 V rail.

Figure 13. Dual Voltage Schottky Diode

3.3V I/O

VOLTAGE

REGULATOR

1.8VCORE

VOLTAGE

REGULATOR

VDDEXT

VDDINT

ADSP-21161N

DC INPUT

SOURCE

Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

RESET Low Before V

DDINT

DDEXT

on 0 ns

IVDDEVDD

DDINT

on Before V

DDEXT

–50 +200 ms

CLKVDD

CLKIN Valid After V

DDINT

DDEXT

Valid

0200ms

CLKRST

CLKIN Valid Before RESET Deasserted

10 μs

PLLRST

PLL Control Setup Before RESET Deasserted

20 μs

WRST

Subsequent RESET Low Pulsewidth

Switching Requirements

CORERST

DSP core reset deasserted after RESET deasserted 4080t

CK3, 5

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4080 cycle count depends on t

SRST

specification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in

4081 cycles maximum.

Figure 14. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)

RESET

RSTOUT

CLKDBL

CLK_CFG1-0

CLKIN

tRSTVDD

VDDEXT

VDDINT

tPLLRST

tCLKRST

tCLKVDD

tIVDDEVDD

tCORERST

Rev. B | Page 24 of 60 | November 2009

ADSP-21161N

Clock Input

In systems that use multiprocessing or SBSRAM, CLKDBL can-

not be enabled nor can the systems use an external crystal as the

CLKIN source.

Do not use CLKOUT as the clock source for the SBSRAM

device. Using an external crystal in conjunction with CLKDBL

to generate a CLKOUT frequency is not supported. Negative

hold times can result from the potential skew between CLKIN

and CLKOUT.

Table 11. Clock Input

Parameter

100 MHz 110 MHz

Unit

Min Max Min Max

Timing Requirements

CLKIN Period

20 238 18 238 ns

CKL

CLKIN Width Low

7.5 119 7 119 ns

CKH

CLKIN Width High

7.5 119 7 119 ns

CKRF

CLKIN Rise/Fall (0.4 V–2.0 V) 3 3 ns

CCLK

CCLK Period 10 30 9 30 ns

Switching Characteristics

DCKOO

CLKOUT Delay After CLKIN 0 2 0 2 ns

CKOP

CLKOUT Period t

–1 t

+1 t

–1 t

+1 ns

CKWH

CLKOUT Width High t

CKOP

/2–2 t

CKOP

/2+2 t

CKOP

/2–2 t

CKOP

/2+2 ns

CKWL

CLKOUT Width Low t

CKOP

/2–2 t

CKOP

/2+2 t

CKOP

/2–2 t

CKOP

/2+2 ns

CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired t

CCLK

Figure 15. Clock Input

CLKIN

tCKH

tCK

tCKL

CLKOUT

tDCKOO1tCKOP1

tCKWL1

tCKWH1

CLKOUT

NOTES:

1. WHEN CLKDBL ISDISABLED, ANY SPECIFICATION TO CLKIN

APPLIESTO THE RISING EDGE, ONLY.

2. WHEN CLKDBL ISENABLED, ANY SPECIFICATION TO CLKIN

APPLIESTO THE RISING OR FALLING EDGE.

tDCKOO2

tCKOP2

tDCKOO2

tCKWH2tCKWL2

ADSP-21161N

Rev. B | Page 25 of 60 | November 2009

Clock Signals

The ADSP-21161N can use an external clock or a crystal. See

CLKIN pin description. The programmer can configure the

ADSP-21161N to use its internal clock generator by connecting

the necessary components to CLKIN and XTAL. Figure 16

shows the component connections used for a crystal operating

in fundamental mode.

Reset

Figure 16. 100 MHz Operation (Fundamental Mode Crystal)

Table 12. Reset

Parameter Min Max Unit

Timing Requirements

WRST

RESET Pulsewidth Low

Applies after the power-up sequence is complete.

SRST

RESET Setup Before CLKIN High

Only required if multiple ADSP-21161Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21161Ns

communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.

8.5 ns

Figure 17. Reset

CLKIN XTAL

27pF

SUGGESTED COMPONENTSFOR 100MHz OPERATION:

ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE)

ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE)

C1 = 27pF

C2 = 27pF

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS25MHz

CRYSTAL GENERATESA 100MHz CCLK AND A 50MHz EP CLOCK

WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.

RESET

CLKIN

tWRSTtSRST

Rev. B | Page 26 of 60 | November 2009

ADSP-21161N

Interrupts

Timer

Table 13. Interrupts

Parameter Min Max Unit

Timing Requirements

SIR

IRQ2–0 Setup Before CLKIN

6ns

HIR

IRQ2–0 Hold After CLKIN

0ns

IPW

IRQ2–0 Pulsewidth

CKOP

+ 2 ns

Only required for IRQx recognition in the following cycle.

Applies only if t

SIR

and t

HIR

requirements are not met.

Figure 18. Interrupts

CLKIN

tIPW

tSIR

tHIR

IRQ2–0

Table 14. Timer

Parameter Min Max Unit

Switching Characteristic

DTEX

CCLK to TIMEXP 1 7 ns

Figure 19. Timer

CCLK

TIMEXP

tDTEX

ADSP-21161N

Rev. B | Page 27 of 60 | November 2009

Flags

Table 15. Flags

100 MHz 110 MHz

Parameter Min Max Min Max Unit

Timing Requirement

SFI

FLAG11–0

Setup Before CLKIN

44ns

HFI

FLAG11–0

Hold After CLKIN

11ns

DWRFI

FLAG11–0

Delay After RD/WR Low

12 9 ns

HFIWR

FLAG11–0

Hold After RD/WR Deasserted

00ns

Switching Characteristics

DFO

FLAG11–0

OUT

Delay After CLKIN 9 9 ns

HFO

FLAG11–0

OUT

Hold After CLKIN 1 1 ns

DFOE

CLKIN to FLAG11–0

OUT

Enable 1 1 ns

DFOD

CLKIN to FLAG11–0

OUT

Disable 5 5 ns

Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.

Figure 20. Flags

CLKIN

FLAG11–0OUT

FLAG OUTPUT

CLKIN

FLAG INPUT

FLAG11–0IN

tDFO

tHFO

tDFO tDFOD

tDFOE

tSFI tHFI

tHFIWR

tDWRFI

⌹⌬ ⑁⌹

Rev. B | Page 28 of 60 | November 2009

ADSP-21161N

Memory Read — Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN except for ACK pin requirements listed in footnote 4 of

Table 16. These specifications apply when the ADSP-21161N is

the bus master accessing external memory space in asynchro-

nous access mode.

Table 16. Memory Read — Bus Master

100 MHz 110 MHz

Parameter Min Max Min Max Unit

Timing Requirements

DAD

Address, Selects Delay to

Data Valid

1, 2

CKOP

–0.25t

CCLK

–8.5+W t

CKOP

–0.25t

CCLK

–6.75+W ns

DRLD

RD Low to Data Valid

0.75t

CKOP

–11+W 0.75t

CKOP

–11+W ns

HDA

Data Hold from Address,

Selects

00ns

SDS

Data Setup to RD High88ns

HDRH

Data Hold from RD High

11ns

DAAK

ACK Delay from Address,

Selects

2, 4

CKOP

–0.5t

CCLK

–12+W t

CKOP

–0.5t

CCLK

–12+W ns

DSAK

ACK Delay from RD Low

CKOP

–0.75t

CCLK

–11+W t

CKOP

–0.75t

CCLK

–11+W ns

SAKC

ACK Setup to CLKIN

0.5t

CCLK

+3 0.5t

CCLK

+3 ns

HAKC

ACK Hold After CLKIN 1 1 ns

Switching Characteristics

DRHA

Address Selects Hold

After RD High

0.25t

CCLK

–1+H 0.25t

CCLK

–1+H ns

DARL

Address Selects to RD

Low

0.25t

CCLK

–3 0.25t

CCLK

–3 ns

RD Pulsewidth t

CKOP

–0.5t

CCLK

–1+W t

CKOP

–0.5t

CCLK

–1+W ns

RWR

RD High to WR, RD,

DMAGx Low

0.5t

CCLK

–1+HI 0.5t

CCLK

–1+HI ns

W = (number of wait states specified in WAIT register) × t

CKOP

HI = t

CKOP

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t

CKOP

(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

Data Delay/Setup: User must meet t

DAD

, t

DRLD

, or t

SDS.

The falling edge of MSx, BMS is referenced.

Data Hold: User must meet t

HDA

or t

HDRH

in asynchronous access mode. See Example System Hold Time Calculation on Page 55 for the calculation of hold times given capacitive

and dc loads.

For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,

ACK must be driven low (deasserted) by t

DAAK

, t

DSAK

, or t

SAKC

. For the second and subsequent cycles of an asynchronous external memory access, the t

SAKC

and t

HAKC

must be

met for both assertion and deassertion of ACK signal.

ADSP-21161N

Rev. B | Page 29 of 60 | November 2009

Figure 21. Memory Read — Bus Master

ACK

DATA

tDARL tRW

tDAD

tDAAK

tHDRH

tHDA

tRWR

tDRLD

tDRHA

tDSAK

tSDS

tSAKC tHAKC

CLKIN

ADDRESS

MSx,BMS

WR,DMAG

Rev. B | Page 30 of 60 | November 2009

ADSP-21161N

Memory Write — Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN except for ACK pin requirements listed in footnote 1 of

Table 17. These specifications apply when the ADSP-21161N is

the bus master accessing external memory space in asynchro-

nous access mode.

Table 17. Memory Write — Bus Master

Parameter Min Max Unit

Timing Requirements

DAAK

ACK Delay from Address, Selects

1, 2

CKOP

–0.5t

CCLK

–12+W ns

DSAK

ACK Delay from WR Low

CKOP

–0.75t

CCLK

–11+W ns

SAKC

ACK Setup to CLKIN

0.5t

CCLK

+3 ns

HAKC

ACK Hold After CLKIN

1ns

Switching Characteristics

DAWH

Address, Selects to WR Deasserted

CKOP

–0.25t

CCLK

–3+W ns

DAWL

Address, Selects to WR Low

0.25t

CCLK

–3 ns

WR Pulsewidth t

CKOP

–0.5t

CCLK

–1+W ns

DDWH

Data Setup Before WR High t

CKOP

–0.25t

CCLK

–13.5+W ns

DWHA

Address Hold After WR Deasserted 0.25t

CCLK

–1+H ns

DWHD

Data Hold After WR Deasserted 0.25t

CCLK

–1+H ns

DATRWH

Data Disable After WR Deasserted

0.25t

CCLK

– 2+H 0.25t

CCLK

+2.5+H ns

WWR

WR High to WR, RD, DMAGx Low 0.5t

CCLK

–1.25+HI ns

DDWR

Data Disable Before WR or RD Low 0.25t

CCLK

–3+I ns

WDE

WR Low to Data Enabled –0.25t

CCLK

–1 ns

W = (number of wait states specified in WAIT register) × t

CKOP

H = t

CKOP

(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t

CKOP

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t

CKOP

(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,

ACK must be driven low (deasserted) by t

DAAK

, t

DSAK

, or t

SAKC

. For the second and subsequent cycles of an asynchronous external memory access, the t

SAKC

and t

HAKC

must be

met for both assertion and deassertion of ACK signal.

The falling edge of MSx, BMS is referenced.

See Example System Hold Time Calculation on Page 55 for calculation of hold times given capacitive and dc loads.

ADSP-21161N

Rev. B | Page 31 of 60 | November 2009

Figure 22. Memory Write — Bus Master

tDATRWH

ACK

DATA

tDAWL tWW

tDAAK

tWWR

tWDE

tDDWR

tDWHA

tDAWH

tDSAK

tDDWH

tDWHD

tSAKC tHAKC

CLKIN

ADDRESS

MSx,BMS

RD,DMAG

Rev. B | Page 32 of 60 | November 2009

ADSP-21161N

Synchronous Read/Write — Bus Master

Use these specifications for interfacing to external memory sys-

tems that require CLKIN, relative to timing or for accessing a

slave ADSP-21161N (in multiprocessor memory space). When

accessing a slave ADSP-21161N, these switching characteristics

must meet the slave's timing requirements for synchronous

read/writes (see Synchronous Read/Write — Bus Slave on

Page 33). The slave ADSP-21161N must also meet these (bus

master) timing requirements for data and acknowledge setup

and hold times.

Table 18. Synchronous Read/Write — Bus Master

Parameter Min Max Unit

Timing Requirements

SSDATI

Data Setup Before CLKIN 5.5 ns

HSDATI

Data Hold After CLKIN 1 ns

SACKC

ACK Setup Before CLKIN 0.5t

CCLK

+3 ns

HACKC

ACK Hold After CLKIN 1 ns

Switching Characteristics

DADDO

Address, MSx, BMS, BRST, Delay After CLKIN 10 ns

HADDO

Address, MSx, BMS, BRST, Hold After CLKIN 1.5 ns

DRDO

RD High Delay After CLKIN 0.25t

CCLK

–1 0.25t

CCLK

+9 ns

DWRO

WR High Delay After CLKIN 0.25t

CCLK

–1 0.25t

CCLK

+9 ns

DRWL

RD/WR Low Delay After CLKIN 0.25t

CCLK

–1 0.25t

CCLK

+9 ns

DDATO

Data Delay After CLKIN 12.5 ns

HDATO

Data Hold After CLKIN 1.5 ns

Figure 23. Synchronous Read/Write — Bus Master

CLKIN

ACK

(IN)

DATA (OUT)

DATA

(IN)

WRITE CYCLE

READ CYCLE

tHSDATI

tSSDATI

tDRDO

tDWRO

tHDATO

tDDATO

tSACKC tHACKC

tHADDO

tDADDO

ADDRESS

MSx,BRST

tDRWL

ADSP-21161N

Rev. B | Page 33 of 60 | November 2009

Synchronous Read/Write — Bus Slave

Use these specifications for ADSP-21161N bus master accesses

of a slave’s IOP registers in multiprocessor memory space. The

bus master must meet these (bus slave) timing requirements.

Table 19. Synchronous Read/Write — Bus Slave

Parameter Min Max Unit

Timing Requirements

SADDI

Address, BRST Setup Before CLKIN 5 ns

HADDI

Address, BRST Hold After CLKIN 1 ns

SRWI

RD/WR Setup Before CLKIN 5 ns

HRWI

RD/WR Hold After CLKIN 1 ns

SSDATI

Data Setup Before CLKIN 5.5 ns

HSDATI

Data Hold After CLKIN 1 ns

Switching Characteristics

DDATO

Data Delay After CLKIN 12.5 ns

HDATO

Data Hold After CLKIN 1.5 ns

DACKC

ACK Delay After CLKIN 10 ns

HACKO

ACK Hold After CLKIN 1.5 ns

Figure 24. Synchronous Read/Write — Bus Slave

CLKIN

ADDRESS

ACK

DATA

(OUT)

WRITE ACCESS

DATA

(IN)

READ ACCESS

tSADDI tHADDI

tDACKC tHACKO

tHRWI

tSRWI

tDDATO tHDATO

tSRWI tHRWI

tHSDATI

tSSDATI

Rev. B | Page 34 of 60 | November 2009

ADSP-21161N

Host Bus Request

Use these specifications for asynchronous host bus requests of

an ADSP-21161N (HBR, HBG).

Table 20. Host Bus Request

100 MHz 110 MHz

Parameter Min Max Min Max Unit

Timing Requirements

HBGRCSV

HBG Low to RD/WR/CS Valid 19 19 ns

SHBRI

HBR Setup Before CLKIN

66ns

HHBRI

HBR Hold After CLKIN

11ns

SHBGI

HBG Setup Before CLKIN 6 6 ns

HHBGI

HBG Hold After CLKIN 1 1 ns

Switching Characteristics

DHBGO

HBG Delay After CLKIN 7 7 ns

HHBGO

HBG Hold After CLKIN 1.5 1.5 ns

DRDYCS

REDY (O/D) or (A/D) Low from CS and HBR Low

10 10 ns

TRDYHG

REDY (O/D) Disable or REDY (A/D) High from HBG

CKOP

+ 14 t

CKOP

+ 12 ns

ARDYTR

REDY (A/D) Disable from CS or HBR High

11 11 ns

Only required for recognition in the current cycle.

(O/D) = open drain, (A/D) = active drive.

ADSP-21161N

Rev. B | Page 35 of 60 | November 2009

Figure 25. Host Bus Request

RE D Y

(O/D)

RE D Y

(A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

tDRDYCS

tHBGRCSV

tTRDYHG

tARDYTR

tSHBGI tHHBGI

CLKIN

(OUT )HBG

tHHBRI

tSHBRI

tHHBGO

tDHBGO

HBR

(IN)

HBG

HBR

(OUT )HBG

Rev. B | Page 36 of 60 | November 2009

ADSP-21161N

Multiprocessor Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-21161Ns (BRx).

Table 21. Multiprocessor Bus Request

Parameter Min Max Unit

Timing Requirements

SBRI

BRx, Setup Before CLKIN High 9 ns

HBRI

BRx, Hold After CLKIN High 0.5 ns

SPAI

PA Setup Before CLKIN High 9 ns

HPAI

PA Hold After CLKIN High 1 ns

SRPBAI

RPBA Setup Before CLKIN High 6 ns

HRPBAI

RPBA Hold After CLKIN High 2 ns

Switching Characteristics

DBRO

BRx Delay After CLKIN High 8 ns

HBRO

BRx Hold After CLKIN High 1.0 ns

DPASO

PA Delay After CLKIN High, Slave 8 ns

TRPAS

PA Disable After CLKIN High, Slave 1.5 ns

DPAMO

PA Delay After CLKIN High, Master 0.25t

CCLK

+9 ns

PATR

PA Disable Before CLKIN High, Master 0.25t

CCLK

–5 ns

Figure 26. Multiprocessor Bus Request

tHBRI

RP BA

O/D = OP EN DRAIN

tHR P B AI

tSRPBAI

tSBRI

CLKIN

PA (OUT)

(SLA V E)

tDBRO

tHBRO

tDP A SOtTRPAS

PA (OUT)

(MASTER)

tDPAMO tPATR

PA (IN)

(O/D)

tHPAI

tSPAI

BRx (OUT)

BRx (IN)

ADSP-21161N

Rev. B | Page 37 of 60 | November 2009

Asynchronous Read/Write — Host to ADSP-21161N

Use these specifications for asynchronous host processor

accesses of an ADSP-21161N, after the host has asserted CS and

HBR (low). After HBG is returned by the ADSP-21161N, the

host can drive the RD and WR pins to access the

ADSP-21161N’s IOP registers. HBR and HBG are assumed low

for this timing. Although the DSP will recognize HBR asserted

before reset, a HBG will not be returned by the DSP until after

reset is deasserted and the DSP completes bus synchronization.

Note: Host internal memory access is not supported.

Table 22. Read Cycle

Parameter Min Max Unit

Timing Requirements

SADRDL

Address Setup and CS Low Before RD Low 0 ns

HADRDH

Address Hold and CS Hold Low After RD 2ns

WRWH

RD/WR High Width 3.5 ns

DRDHRDY

RD High Delay After REDY (O/D) Disable 0 ns

DRDHRDY

RD High Delay After REDY (A/D) Disable 0 ns

Switching Characteristics

SDATRDY

Data Valid Before REDY Disable from Low 2 ns

DRDYRDL

REDY (O/D) or (A/D) Low Delay After RD Low 10 ns

RDYPRD

REDY (O/D) or (A/D) Low Pulsewidth for Read 1.5t

CCLK

HDARWH

Data Disable After RD High 26ns

Table 23. Write Cycle

Parameter Min Max Unit

Timing Requirements

SCSWRL

CS Low Setup Before WR Low 0 ns

HCSWRH

CS Low Hold After WR High 0 ns

SADWRH

Address Setup Before WR High 6 ns

HADWRH

Address Hold After WR High 2 ns

WWRL

WR Low Width t

CCLK

+1 ns

WRWH

RD/WR High Width 3.5 ns

DWRHRDY

WR High Delay After REDY (O/D) or (A/D) Disable 0 ns

SDATWH

Data Setup Before WR High 5 ns

HDATWH

Data Hold After WR High 4 ns

Switching Characteristics

DRDYWRL

REDY (O/D) or (A/D) Low Delay After WR/CS Low

11 ns

RDYPWR

REDY (O/D) or (A/D) Low Pulsewidth for Write

12 ns

Only when slave write FIFO is full.

Rev. B | Page 38 of 60 | November 2009

ADSP-21161N

Figure 27. Asynchronous Read/Write — Host to ADSP-21161N

REDY (O/D)

READ CYCLE

DATA (OUT)

RED Y (A / D )

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

REDY (O/D)

WRIT E CY CLE

DA T A ( I N )

ADDRESS

REDY (A/D)

tDRDYRDL

tHDARWH

tRD YPRD

tDRDHRDY

tSDATRDY

tSDATWH tHDATWH

tDRDYWRL

tHADWRH

tRDYPW R tDWRHRDY

tSADWRH

tSCSWRL tHCSWRH

tHADRDH

tWRWH

tWWRL tWRWH

tSADRDL

ADDRESS/CS

ADSP-21161N

Rev. B | Page 39 of 60 | November 2009

Three-State Timing — Bus Master, Bus Slave

These specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. This timing is applicable to bus master transi-

tion cycles (BTC) and host transition cycles (HTC) as well as the

SBTS pin.

During reset, the DSP will not respond to SBTS, HBR, and MMS

accesses. Although the DSP will recognize HBR asserted before

reset, a HBG will not be returned by the DSP until after reset is

deasserted and the DSP completes bus synchronization.

Table 24. Three-State Timing — Bus Master, Bus Slave

Parameter Min Max Unit

Timing Requirements

STSCK

SBTS Setup Before CLKIN 6 ns

HTSCK

SBTS Hold After CLKIN 2 ns

Switching Characteristics

MIENA

Address/Select Enable After CLKIN High 1.5 9 ns

MIENS

Strobes Enable After CLKIN High

−1.5 +9 ns

MIENHG

HBG Enable After CLKIN 1.5 9 ns

MITRA

Address/Select Disable After CLKIN High 0.5t

CKOP

–20 0.5t

CKOP

–15 ns

MITRS

Strobes Disable After CLKIN High t

CKOP

– 0.25t

CCLK

−17 t

CKOP

– 0.25t

CCLK

−12.5 ns

MITRHG

HBG Disable After CLKIN

0.5t

CKOP

+N×t

CCLK

–20 0.5t

CKOP

+N×t

CCLK

–15 ns

DATEN

Data Enable After CLKIN

1.5 10 ns

DATTR

Data Disable After CLKIN

1.5 6 ns

ACKEN

ACK Enable After CLKIN High 1.5 9 ns

ACKTR

ACK Disable After CLKIN High 0.2 5 ns

CDCEN

CLKOUT Enable After CLKIN

0.5t

CKOP

+N×t

CCLK

0.5t

CKOP

+N×t

CCLK

+5 ns

CDCTR

CLKOUT Disable After CLKIN t

CKOP

−5 t

CKOP

ATRHBG

Address/Select Disable Before HBG Low

1.5t

CKOP

–6 1.5t

CKOP

+2 ns

STRHBG

RD/WR/DMAGx Disable Before HBG Low

CKOP

+ 0.25t

CCLK

−4t

CKOP

+ 0.25t

CCLK

+3 ns

BTRHBG

BMS Disable Before HBG Low

0.5t

CKOP

–4 0.5t

CKOP

+2 ns

MENHBG

Memory Interface Enable After HBG High

CKOP

–5 t

CKOP

+5 ns

Strobes = RD, WR, DMAGx.

Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively.

In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.

Rev. B | Page 40 of 60 | November 2009

ADSP-21161N

Figure 28. Three-State Timing — Bus Master, Bus Slave

CLKIN

ACK

MEMORY

INTERFACE

CLKOUT

tCDCTR

DATA

MEMORY

INTERFACE

tMITRA, tMITRS,tMITRHG

tHTSCK

tCDCEN

tMIENA, tMIENS,tMIENHG

CLKIN

tATRHBG, tSTRHBG, tBTRHBG

tSTSCK

tDATEN

tACKEN

tDATTR

tACKTR

tMENHBG

SBTS

HBG

MEMORY INTERFACE = ADDRESS,RD,WR,MSx,DMAGx,BMS (IN EPROM MODE)

ADSP-21161N

Rev. B | Page 41 of 60 | November 2009

DMA Handshake

These specifications describe the three DMA handshake modes.

In all three modes DMAR is used to initiate transfers. For hand-

shake mode, DMAG controls the latching or enabling of data

externally. For external handshake mode, the data transfer is

controlled by the ADDR23–0, RD, WR, MS3–0, ACK, and

DMAG signals. For Paced Master mode, the data transfer is

controlled by ADDR23–0, RD, WR, MS3–0, and ACK (not

DMAG). For Paced Master mode, the Memory Read-Bus Mas-

ter, Memory Write-Bus Master, and Synchronous Read/Write-

Bus Master timing specifications for ADDR23–0, RD, WR,

MS3–0, DATA47–16, and ACK also apply.

Table 25. DMA Handshake

100 MHz 110 MHz

Parameter Min Max Min Max Unit

Timing Requirements

SDRC

DMARx Setup Before CLKIN

3.5 3.5 ns

WDR

DMARx Width Low

(Nonsynchronous)

CCLK

+4.5 t

CCLK

+4.5 ns

SDATDGL

Data Setup After DMAGx Low

CKOP

–0.5t

CCLK

–7 t

CKOP

–0.5t

CCLK

–7 ns

HDATIDG

Data Hold After DMAGx High 2 2 ns

DATDRH

Data Valid After DMARx High

CKOP

+3 t

CKOP

+3 ns

DMARLL

DMARx Low Edge to Low Edge

CKOP

DMARH

DMARx Width High

CCLK

+4.5 t

CCLK

+4.5 ns

Switching Characteristics

DDGL

DMAGx Low Delay After CLKIN 0.25t

CCLK

+1 0.25t

CCLK

+9 0.25t

CCLK

+1 0.25t

CCLK

+9 ns

WDGH

DMAGx High Width 0.5t

CCLK

–1+HI 0.5t

CCLK

–1+HI ns

WDGL

DMAGx Low Width t

CKOP

–0.5t

CCLK

–1 t

CKOP

–0.5t

CCLK

–1 ns

HDGC

DMAGx High Delay After CLKIN t

CKOP

–0.25t

CCLK

+1.0 t

CKOP

–0.25t

CCLK

+9 t

CKOP

– 0.25t

CCLK

+1.0 t

CKOP

–0.25t

CCLK

+9 ns

VDATDGH

Data Valid Before DMAGx High

CKOP

–0.25t

CCLK

–8 t

CKOP

–0.25t

CCLK

+5 t

CKOP

– 0.25t

CCLK

–8 t

CKOP

–0.25t

CCLK

+5 ns

DATRDGH

Data Disable After DMAGx High

0.25t

CCLK

–3 0.25t

CCLK

+4 0.25t

CCLK

–3 0.25t

CCLK

+4 ns

DGWRL

WRx Low Before DMAGx Low –1.5 +2 –1.5 +2 ns

DGWRH

DMAGx Low Before WRx High t

CKOP

–0.5t

CCLK

–2+W t

CKOP

–0.5t

CCLK

–2+W ns

DGWRR

WRx High Before DMAGx High

–1.5 +2 –1.5 +2 ns

DGRDL

RDx Low Before DMAGx Low –1.5 +2 –1.5 +2 ns

DRDGH

RDx Low Before DMAGx High t

CKOP

–0.5t

CCLK

–2+W t

CKOP

–0.5t

CCLK

–2+W ns

DGRDR

RDx High Before DMAGx High

–1.5 +2 –1.5 +2 ns

DGWR

DMAGx High to WRx, RDx Low 0.5t

CCLK

–2+HI 0.5t

CCLK

–2+HI ns

DADGH

Address/Select Valid to DMAGx High 15 13 ns

DDGHA

Address/Select Hold After DMAGx

High

11ns

W = (number of wait states specified in WAIT register) × t

CKOP

HI = t

CKOP

(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

Only required for recognition in the current cycle.

Maximum throughput (@ 110 MHz) using DMARx/DMAGx handshaking equals t

WDR

+ t

DMARH

= (t

CCLK

+4.5) + (t

CCLK

+4.5)=27 ns (37 MHz). This throughput limit applies

to non-synchronous access mode only.

SDATDGL

is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can

be driven t

DATDRH

after DMARx is brought high.

Use t

DMARLL

if DMARx transitions synchronous with CLKIN. Otherwise, use t

WDR

and t

DMARH

VDATDGH

is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t

VDATDGH

CKOP

–0.25t

CCLK

–8+(n×t

CKOP

) where

n equals the number of extra cycles that the access is prolonged.

See Example System Hold Time Calculation on Page 55 for calculation of hold times given capacitive and dc loads.

This parameter applies for synchronous access mode only.

Rev. B | Page 42 of 60 | November 2009

ADSP-21161N

Figure 29. DMA Handshake

CLKIN

tSDRC

DATA

tWDR

tSDRC

tDMARH

tDMARLL

tHDGC

tWDGH

tDDGL

tVDATDGH

tDATDRH

tDATRDGH

tHDATIDG

tDGWRL tDGWRH tDGWRR

tDGRDL

tDRDGH

tDGRDR

tSDATDGL

(EXTERNAL DEVICE TO EXTERNAL MEMORY)

(EXTERNAL MEMORY TO EXTERNAL DEVICE)

TRANSFERSBETWEEN ADSP-21161N

INTERNAL MEMORY AND EXTERNAL DEVICE

TRANSFERSBETWEEN EXTERNAL DEVICE AND

EXTERNAL MEMORY1(EXTERNAL HANDSHAKE MODE)

tDDGHA

ADDRESS

MSx

tDADGH

tWDGL

(FROM EXTERNAL DRIVE TO ADSP-21161N)

(FROM ADSP-2116x TO EXTERNAL DRIVE)

tDGWR

DMARx

DMAGx

1MEMORY READ BUSMASTER, MEMORY WRITE BUSMASTER, OR SYNCHRONOUSREAD/WRITE BUSMASTER

TIMING SPECIFICATIONSFOR ADDR23–0, RD,WR,MS3-0 AND ACK ALSOAPPLYHERE.

ADSP-21161N

Rev. B | Page 43 of 60 | November 2009

SDRAM Interface — Bus Master

Use these specifications for ADSP-21161N bus master accesses

of SDRAM:

SDRAM Interface — Bus Slave

These timing requirements allow a bus slave to sample the bus

master’s SDRAM command and detect when a refresh occurs:

Table 26. SDRAM Interface — Bus Master

Parameter

100 MHz 110 MHz

UnitMin Max Min Max

Timing Requirements

SDSDK

Data Setup Before SDCLK 2.0 2.0 ns

HDSDK

Data Hold After SDCLK 2.3 2.3 ns

Switching Characteristics

DSDK1

First SDCLK Rise Delay After CLKIN

0.75t

CCLK

+ 1.5 0.75t

CCLK

+ 8.0 0.75t

CCLK

+ 1.5 0.75t

CCLK

+ 8.0 ns

SDK

SDCLK Period t

CCLK

2 × t

CCLK

2 × t

CCLK

SDKH

SDCLK Width High 4 3 ns

SDKL

SDCLK Width Low 4 3 ns

DCADSDK

Command, Address, Data, Delay After SDCLK

0.25t

CCLK

+2.5 0.25t

CCLK

+2.5 ns

HCADSDK

Command, Address, Data, Hold After SDCLK

2.0 2.0 ns

SDTRSDK

Data Three-State After SDCLK

0.5t

CCLK

+ 2.0 0.5t

CCLK

+ 2.0 ns

SDENSDK

Data Enable After SDCLK

0.75t

CCLK

0.75t

CCLK

SDCTR

Command Three-State After CLKIN 0.5t

CCLK

–1.5 0.5t

CCLK

+ 6.0 0.5t

CCLK

–1.5 0.5t

CCLK

+ 6.0 ns

SDCEN

Command Enable After CLKIN 2 5 2 5 ns

SDSDKTR

SDCLK Three-State After CLKIN 0 3 0 3 ns

SDSDKEN

SDCLK Enable After CLKIN 1 4 1 4 ns

SDATR

Address Three-State After CLKIN −0.25 t

CCLK

−5−0.25t

CCLK

−0.25 t

CCLK

−5−0.25t

CCLK

SDAEN

Address Enable After CLKIN −0.4 +7.2 −0.4 +7.2 ns

For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the t

DSDK1

and t

SSDKC1

values, depending upon the SDCKR

value and the core clock to CLKIN ratio.

Subtract t

CCLK

from result if value is greater than or equal to t

CCLK

Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE.

SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.

Valid when DSP transitions to SDRAM master from SDRAM slave.

Table 27. SDRAM Interface — Bus Slave

Parameter Min Max Unit

Timing Requirements

SSDKC1

First SDCLK Rise after CLKOUT

1, 2, 3

SDCK × t

CCLK

−0.5t

CCLK

− 0.5 SDCKR × t

CCLK

−0.25t

CCLK

+ 2.0 ns

SCSDK

Command Setup before SDCLK

2ns

HCSDK

Command Hold after SDCLK

1ns

For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the t

DSDK1

and t

SSDKC1

values, depending upon the

SDCKR value and the Core clock to CLKOUT ratio.

SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.

Subtract t

CCLK

from result if value is greater than or equal to t

CCLK

Command = SDCKE, RAS, CAS, and SDWE.

Rev. B | Page 44 of 60 | November 2009

ADSP-21161N

Figure 30. SDRAM Interface

CLKIN

SDCLK

DATA(IN)

DATA(OUT)

CMND1ADDR

(OUT)

CMND1(OUT)

ADDR

(OUT)

CLKOUT

SDCLK (IN)

CMND2(IN)

tSDK

tDSDK1 tSDKH

tSDKL

tSDSDK

tHDSDK

tDCADSDK

tSDENSDK

tSDTRSDK

tHCADSDK

tDCADSDK

tHCADSDK

tSDCEN tSDCTR

tSDATR

tSDAEN

tSSDKC1

tSCSDK

tHCSDK

CLKIN

tSDSDKEN tSDSDKTR

SDCLK

1COMMAND = SDCKE, MSx,RAS,CAS,SDWE,DQM,ANDSDA10.

2COMMAND = SDCKE, RAS,CAS, AND SDWE.

ADSP-21161N

Rev. B | Page 45 of 60 | November 2009

Link Ports

Calculation of link receiver data setup and hold relative to link

clock is required to determine the maximum allowable skew

that can be introduced in the transmission path between

LDATA and LCLK. Setup skew is the maximum delay that can

be introduced in LDATA relative to LCLK,

(setup skew = t

LCLKTWH

min – t

DLDCH

– t

SLDCL

). Hold skew is the

maximum delay that can be introduced in LCLK relative to

LDATA, (hold skew = t

LCLKTWL

min – t

HLDCH

– t

HLDCL

). Calcula-

tions made directly from speed specifications will result in

unrealistically small skew times because they include multiple

tester guardbands. The setup and hold skew times shown below

are calculated to include only one tester guardband.

ADSP-21161N Setup Skew = 1.5 ns max

ADSP-21161N Hold Skew = 1.5 ns max

Note that there is a two-cycle effect latency between the link

port enable instruction and the DSP enabling the link port.

Table 28. Link Ports — Receive

Parameter Min Max Unit

Timing Requirements

SLDCL

Data Setup Before LCLK Low 1 ns

HLDCL

Data Hold After LCLK Low 3.5 ns

LCLKIW

LCLK Period t

LCLK

LCLKRWL

LCLK Width Low 4.0 ns

LCLKRWH

LCLK Width High 4.0 ns

Switching Characteristics

DLALC

LACK Low Delay After LCLK High

812ns

LACK goes low with t

DLALC

relative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.

Figure 31. Link Ports—Receive

LCLK

LDAT7-0

LACK (OUT)

RECEIVE

tSLDCL tHLDCL

tDLALC

tLCLKRWL

tLCLKIW

tLCLKRW H

Rev. B | Page 46 of 60 | November 2009

ADSP-21161N

Table 29. Link Ports — Transmit

Parameter Min Max Unit

Timing Requirements

SLACH

LACK Setup Before LCLK High 8 ns

HLACH

LACK Hold After LCLK High –2 ns

Switching Characteristics

DLDCH

Data Delay After LCLK High 3 ns

HLDCH

Data Hold After LCLK High 0 ns

LCLKTWL

LCLK Width Low 0.5t

LCLK

–1.0 0.5t

LCLK

+1.0 ns

LCLKTWH

LCLK Width High 0.5t

LCLK

–1.0 0.5t

LCLK

+1.0 ns

DLACLK

LCLK Low Delay After LACK High 0.5t

LCLK

+3 3t

LCLK

+11 ns

Figure 32. Link Ports—Transmit

LCLK

LDAT7-0

LACK (IN)

THE tSLACH REQUIREMENT APPLIESTO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

TRANSMIT

LAST NIBBLE/BYTE

TRANSMITTED

FIRST NIBBLE/BYTE

TRANSMITTED

LCLK INACTIVE

(HIGH)

OUT

tDLDCH

tHLDCH

tLCLKTWH tLCLKTWL

tSLACH tHLACH tDLACLK

ADSP-21161N

Rev. B | Page 47 of 60 | November 2009

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 30. Serial Ports — External Clock

Parameter Min Max Unit

Timing Requirements

SFSE

Transmit/Receive FS Setup Before Transmit/Receive SCLK

3.5 ns

HFSE

Transmit/Receive FS Hold After Transmit/Receive SCLK

2ns

SDRE

Receive Data Setup Before Receive SCLK

1.5 ns

HDRE

Receive Data Hold After Receive SCLK

4ns

SCLKW

SCLKx Width 7 ns

SCLK

SCLKx Period 2t

CCLK

Referenced to sample edge.

Table 31. Serial Ports — Internal Clock

Parameter Min Max Unit

Timing Requirements

SFSI

FS Setup Time Before SCLK (Transmit/Receive Mode)

8ns

HFSI

FS Hold After SCLK (Transmit/Receive Mode)

0.5t

CCLK

+1 ns

SDRI

Receive Data Setup Before SCLK

4ns

HDRI

Receive Data Hold After SCLK

3ns

Referenced to sample edge.

Table 32. Serial Ports — External Clock

Parameter

100 MHz 110 MHz

UnitMin Max Min Max

Switching Characteristics

DFSE

FS Delay After SCLK (Internally Generated FS)

1, 2, 3

13 13 ns

HOFSE

FS Hold After SCLK (Internally Generated FS)

1, 2 , 3

32.75ns

DDTE

Transmit Data Delay After SCLK

1, 2

16 16 ns

HDTE

Transmit Data Hold After SCLK

1, 2

00ns

Referenced to drive edge.

SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.

Table 33. Serial Ports — Internal Clock

Parameter Min Max Unit

Switching Characteristics

DFSI

FS Delay After SCLK (Internally Generated FS)

1, 2, 3

4.5 ns

HOFSI

FS Hold After SCLK (Internally Generated FS)

1, 2, 3

–1.5 ns

DDTI

Transmit Data Delay After SCLK

1, 2

7.5 ns

HDTI

Transmit Data Hold After SCLK

1, 2

0ns

SCLKIW

SCLK Width

0.5t

SCLK

–2.5 0.5t

SCLK

+2 ns

Referenced to drive edge.

SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.

Rev. B | Page 48 of 60 | November 2009

ADSP-21161N

Table 34. Serial Ports —– Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK

1, 2

4ns

DDTTE

Data Disable from External Transmit SCLK

10 ns

DDTIN

Data Enable from Internal Transmit SCLK

0ns

DDTTI

Data Disable from Internal Transmit SCLK

3ns

Referenced to drive edge.

SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

Table 35. Serial Ports — External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS with

MCE = 1, MFD = 0

13 ns

DDTENFS

Data Enable from Late FS or MCE = 1, MFD = 0

0.5 ns

MCE = 1, Transmit FS enable and Transmit FS valid follow t

DDTLFSE

and t

DDTENFS

ADSP-21161N

Rev. B | Page 49 of 60 | November 2009

Figure 33. Serial Ports

DRIVE EDGE

SCLK (INT)

DRIVE EDGE

SCLK

DRIVE EDGE DRIVE EDGE

SCLK

SCLK (EXT)

tDDTTE

tDDTEN

tDDTTI

tDDTIN

DXA/DXB

SCLK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE— EXTERNAL CLOCK

SCLK

DRIVE EDGE SAMPLE EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED ASTHE ACTIVE SAMPLING EDGE.

tSDRI tHDRI

tSFSItHFSI

tDFSI

tHOFSI

tSCLKIW

tSDRE tHDRE

tSFSEtHFSE

tDFSE

tSCLKW

tHOFSE

DXA/DXBDXA/DXB

tDDTI

SCLK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — INTERNAL CLOCK

tSFSItHFSI

tDFSI

tHOFSI

tSCLKIW

DXA/DXB

tHDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED ASTHE ACTIVE SAMPLING EDGE.

tDDTE

SCLK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

tSFSEtHFSE

tDFSE

tHOFSE

tSCLKW

DXA/DXB

tHDTE

Rev. B | Page 50 of 60 | November 2009

ADSP-21161N

Figure 34. Serial Ports — External Late Frame Sync

DRIVE SAMPLE DRIVE

SCLK

DXA/DXB

DRIVE SAMPLE DRIVE

LATE EXTERNAL TRANSMIT FS

EXTERNAL RECEIVE FSWITH MCE = 1, MFD = 0

1ST BIT 2ND BIT

SCLK

1ST BIT 2ND BIT

tHOFSE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

tHOFSE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

DXA/DXB

ADSP-21161N

Rev. B | Page 51 of 60 | November 2009

SPI Interface Specifications

Table 36. SPI Interface Protocol — Master Switching and Timing

100 MHz 110 MHz

UnitParameter Min Max Min Max

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0.5t

CCLK

+10 0.5t

CCLK

+10 ns

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid 0.5t

CCLK

+1 0.5t

CCLK

+1 ns

Switching Characteristics

SPICLKM

Serial Clock Cycle 8t

CCLK

–4 ns

SPICHM

Serial Clock High Period 4t

CCLK

–4 4t

CCLK

–4 ns

SPICLM

Serial Clock Low Period 4t

CCLK

–4 4t

CCLK

–4 ns

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time) 3 3 ns

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0 0 ns

SDSCIM_0

FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for

CPHASE = 0

CCLK

SDSCIM_1

FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for

CPHASE = 1

CCLK

HDSM

Last SPICLK Edge to FLAG3–0 High t

CCLK

–3 t

CCLK

–3 ns

SPITDM

Sequential Transfer Delay 2t

CCLK

Figure 35. SPI Interface Protocol — Master Switching and Timing

LSB

VALID

MSB

VALID

tSSPIDM

tHSPIDM

tHDSPIDM

LSBMSB

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

FLAG3-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

tSPICHM tSPICLM

tSPICLM

tSPICLKM

tSPICHM

tHDSMtSPITDM

tHDSPIDM

LSB

VALID

LSBMSB

MSB

VALID

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

tSSPIDM

CPHASE=1

CPHASE=0

tSDSCIM

tSSPIDM

Rev. B | Page 52 of 60 | November 2009

ADSP-21161N

Table 37. SPI Interface Protocol — Slave Switching and Timing

Parameter Min Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle 8t

CCLK

SPICHS

Serial Clock High Period 4t

CCLK

–4 ns

SPICLS

Serial Clock Low Period 4t

CCLK

–4 ns

SDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0 3.5t

CCLK

+8 ns

CPHASE = 1 1.5t

CCLK

+8 ns

HDS

Last SPICLK Edge to SPIDS Not Asserted

CPHASE = 0 0 ns

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0 ns

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid t

CCLK

+1 ns

SDPPW

SPIDS Deassertion Pulsewidth (CPHASE = 0) t

CCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active 2 0.5t

CCLK

+5.5 ns

DSDHI

SPIDS Deassertion to Data High Impedance 1.5 0.5t

CCLK

+5.5 ns

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time) 0.75t

CCLK

+3 ns

HDSPIDS1

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0.25t

CCLK

+3 ns

HDLSBS1

SPICLK Edge to Last Bit Out Not Valid

(Data Out Hold Time) for LSB 0.5t

SPICLK

+4.5t

CCLK

DSOV2

SPIDS Assertion to Data Out Valid (CPHASE = 0) 1.5t

CCLK

+7 ns

When CPHASE = 0 and baud rate is greater than 1, t

HDLSBS

affects the length of the last bit transmitted.

Applies to the first deassertion of SPIDS only.

ADSP-21161N

Rev. B | Page 53 of 60 | November 2009

Figure 36. SPI Interface Protocol — Slave Switching and Timing

tHSPIDS

tDDSPIDS

tDSDHI

LSBMSB

MSBVALID

tDSOE

tDDSPIDS

tHDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

SPIDS

(INPUT)

SPICLK

(CP = 0)

(INPUT)

SPICLK

(CP = 1)

(INPUT)

tSDSCO

tSPICHStSPICLS

tSPICLS

tSPICLKS

tHDS

tSPICHS

tSSPIDStHSPIDS

tDSDHI

LSBVALID

MSB

MSBVALID

tDSOE

tDDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

LSBVALID

LSB

CPHASE=1

CPHASE=0

tSDPPW

tDSOV

tHDSPIDS

tHDLSBS

Rev. B | Page 54 of 60 | November 2009

ADSP-21161N

JTAG Test Access Port and Emulation

Table 38. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period t

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS

System Inputs Setup Before TCK Low

2ns

HSYS

System Inputs Hold After TCK Low

15 ns

TRSTW

TRST Pulsewidth 4t

Switching Characteristics

DTDO

TDO Delay from TCK Low 13 ns

DSYS

System Outputs Delay After TCK Low

30 ns

System Inputs = DATA47–16, ADDR23–0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2–1, CLK_CFG1–0, CLKDBL, CS, HBR, SBTS, ID2–0, IRQ2–0, RESET,

BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6–1, PA, MS3–0, FLAG11–0.

System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, DATA47–16, SDWE, ACK, HBG, RAS, CAS, SDCLK1–0, SDCKE,

BRST, RD, WR, BR6–1, PA, MS3–0, ADDR23–0, FLAG11–0, DMAG2–1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR, RSTOUT.

Figure 37. JTAG Test Access Port and Emulation

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYStHSYS

tDSYS

ADSP-21161N

Rev. B | Page 55 of 60 | November 2009

OUTPUT DRIVE CURRENTS

Figure 38 shows typical I-V characteristics for the output driv-

ers of the ADSP-21161N. The curves represent the current drive

capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The DSP is tested for output enable, disable, and hold time.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving. The output enable time t

ENA

is the interval from

the point when a reference signal reaches a high or low voltage

level to the point when the output has reached a specified high

or low trip point, as shown in the Output Enable/Disable dia-

gram (Figure 39). If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to start

driving.

Output Disable Time

Output pins are considered to be disabled when they stop driv-

ing, go into a high-impedance state, and start to decay from

their output high or low voltage. The time for the voltage on the

bus to decay by ΔV is dependent on the capacitive load, C

and

the load current, I

. This decay time can be approximated by the

following equation:

DECAY

= (C

ΔV)/I

The output disable time t

DIS

is the difference between t

MEASURED

and t

DECAY

as shown in Figure 39. The time t

MEASURED

is the inter-

val from when the reference signal switches to when the output

voltage decays ΔV from the measured output high or output low

voltage. t

DECAY

is calculated with test loads C

and I

, and with

ΔV equal to 0.5 V.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t

DECAY

using the equation given above. Choose ΔV

to be the difference between the ADSP-21161N’s output voltage

and the input threshold for the device requiring the hold time. A

typical ΔV will be 0.4 V. C

is the total bus capacitance (per data

line), and I

is the total leakage or three-state current (per data

line). The hold time will be t

DECAY

plus the minimum disable

time (i.e., t

DATRWH

for the write cycle).

Figure 38. Typical Drive Currents

SWEEP (VDDEXT) VOLTAGE – V

–10

–40

03.50.5 1.0 1.5 2.0 2.5 3.0

–20

–30

–50

–60

LOAD(V

DDEXT

)CURRENT–mA

VDDEXT =3.47V, –40°C

VDDEXT =3.3V, +25°C

VDDEXT =3.13V, +105°C

VDDEXT =3.47V, –40°C

VDDEXT =3.3V, +25°C

–80

Figure 39. Output Enable/Disable

Figure 40. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

Figure 41. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

REFERENCE

SIGNAL

tDIS

OUTPUT STARTSDRIVING

VOH (MEASURED) – ⌬V

VOL (MEASURED) + ⌬V

tMEASURED

VOH

(MEASURED)

VOL

(MEASURED)

2.0V

1.0V

VOH

(MEASURED)

VOL

(MEASURED)

HIGH IMPEDANCE STATE.

TESTCONDITIONSCAUSETHIS

VOLTAGE TO BE APPROXIMATELY 1.5V.

OUTPUT STOPSDRIVING

tENA

tDECAY

1.5V

30pF

OUTPUT

50⍀

INPUT

OUTPUT

1.5V 1.5V

Rev. B | Page 56 of 60 | November 2009

ADSP-21161N

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 40 on Page 55). Figure 42 shows

graphically how output delays and holds vary with load capaci-

tance. (Note that this graph or derating does not apply to output

disable delays; see Output Disable Time on Page 55.) The graphs

of Figure 42, Figure 43, and Figure 44 may not be linear outside

the ranges shown for Typical Output Delay vs. Load Capaci-

tance and Typical Output Rise Time (20% – 80%, V = Min) vs.

Load Capacitance.

ENVIRONMENTAL CONDITIONS

The thermal characteristics in which the DSP is operating influ-

ence performance.

Thermal Characteristics

The ADSP-21161N is packaged in a 225-ball chip scale package

ball grid array (CSP_BGA). The ADSP-21161N is specified for a

case temperature (T

CASE

). To ensure that the T

CASE

data sheet

specification is not exceeded, a heatsink and/or an air flow

source may be used. Use the center block of ground pins

(CSP_BGA balls: F6-10, G6-10, H6-10, J6-10, K6-10) to provide

thermal pathways to the printed circuit board’s ground plane. A

heatsink should be attached to the ground plane (as close as pos-

sible to the thermal pathways) with a thermal adhesive.

where:

•T

CASE

= Case temperature (measured on top surface

of package)

•PD = Power dissipation in W (this value depends upon the

specific application; a method for calculating PD is shown

under Power Dissipation).

•

= Value from Table 39.

•θ

= 8.0°C/W

Figure 42. Typical Output Delay or Hold vs. Load Capacitance (at Max Case

Temperature)

Figure 43. Typical Output Rise/Fall Time (20% – 80%, V

DDEXT

= Max)

Figure 44. Typical Output Rise/Fall Time (20% – 80%, V

DDEXT

= Min)

LOAD CAPACITANCE – pF

–5

021030 60 90 120 150 180

NOMINAL

Y=0.0835X - 2.42

OUTPUTDELAYORHOLD–ns

LOAD CAPACITANCE – pF

16.0

8.0

0 20020 40 60 80 100 120 140 160 180

14.0

12.0

4.0

2.0

10.0

6.0 FALL TIME

RISETIME

Y = 0.0743X+1.5613

RISEANDFALLTIMES–ns

(0.694VTO2.77V,20%TO80%)

Y = 0.0414X + 2.0128

LOAD CAPACITANCE – pF

16.0

8.0

0020020 40 60 80 100 120 140 160 180

14.0

12.0

4.0

2.0

10.0

6.0 FALL TIME

RISETIME

Y=0.0773X+1.4399

RISEANDFALLTIMES–ns

(0.694VTO2.77V,20%TO80%)

Y = 0.0417X + 1.8674

Table 39. Airflow Over Package Versus θ

Airflow (Linear Ft./Min.) 0 200 400

(°C/W)θ

JC1

= 6.8°C/W.

17.9 15.2 13.7

TCASE TAMB PD θCA

×()+=

ADSP-21161N

Rev. B | Page 57 of 60 | November 2009

225-BALL CSP_BGA BALL CONFIGURATIONS

Table 40. 225-Ball CSP_BGA Ball Assignments

Ball Name Ball Number Ball Name Ball Number Ball Name Ball Number Ball Name Ball Number

NC A01 TRST B01 TMS C01 TDO D01

BMSTR A02 TDI B02 EMU C02 TCK D02

BMS A03 RPBA B03 GND C03 FLAG11 D03

SPIDS A04 MOSI B04 SPICLK C04 MISO D04

EBOOT A05 FS0 B05 D0B C05 SCLK0 D05

LBOOT A06 SCLK1 B06 D1A C06 D1B D06

SCLK2 A07 D2B B07 D2A C07 FS1 D07

D3B A08 D3A B08 FS2 C08 V

DDINT

D08

L0DAT4 A09 L0DAT7 B09 FS3 C09 SCLK3 D09

L0ACK A10 L0CLK B10 L0DAT6 C10 L0DAT5 D10

L0DAT2 A11 L0DAT1 B11 L1DAT7 C11 L0DAT3 D11

L1DAT6 A12 L1DAT4 B12 L1DAT3 C12 L1DAT5 D12

L1CLK A13 L1ACK B13 L1DAT1 C13 DATA42 D13

L1DAT2 A14 L1DAT0 B14 DATA45 C14 DATA46 D14

NC A15 RSTOUT

B15 DATA47 C15 DATA44 D15

FLAG10 E01 FLAG5 F01 FLAG1 G01 FLAG0 H01

RESET E02 FLAG7 F02 FLAG2 G02 IRQ0 H02

FLAG8 E03 FLAG9 F03 FLAG4 G03 V

DDINT

H03

D0A E04 FLAG6 F04 FLAG3 G04 IRQ1 H04

DDEXT

E05 V

DDINT

F05 V

DDEXT

G05 V

DDINT

H05

DDINT

E06 GND F06 GND G06 GND H06

DDEXT

E07 GND F07 GND G07 GND H07

DDINT

E08 GND F08 GND G08 GND H08

DDEXT

E09 GND F09 GND G09 GND H09

DDINT

E10 GND F10 GND G10 GND H10

DDEXT

E11 V

DDINT

F11 V

DDEXT

G11 V

DDINT

H11

L0DAT0 E12 DATA37 F12 DATA34 G12 DATA29 H12

DATA39 E13 DATA40 F13 DATA35 G13 DATA28 H13

DATA43 E14 DATA38 F14 DATA33 G14 DATA30 H14

DATA41 E15 DATA36 F15 DATA32 G15 DATA31 H15

IRQ2 J01 TIMEXP K01 ADDR19 L01 ADDR16 M01

ID1 J02 ADDR22 K02 ADDR17 L02 ADDR12 M02

ID2 J03 ADDR20 K03 ADDR21 L03 ADDR18 M03

ID0 J04 ADDR23 K04 ADDR2 L04 ADDR6 M04

DDEXT

J05 V

DDINT

K05 V

DDEXT

L05 ADDR0 M05

GND J06 GND K06 V

DDINT

L06 MS1 M06

GND J07 GND K07 V

DDEXT

L07 BR6 M07

GND J08 GND K08 V

DDINT

L08 V

DDEXT

M08

GND J09 GND K09 V

DDEXT

L09 WR M09

GND J10 GND K10 V

DDINT

L10 SDA10 M10

DDEXT

J11 V

DDINT

K11 V

DDEXT

L11 RAS M11

DATA26 J12 DATA22 K12 CAS L12 ACK M12

DATA24 J13 DATA19 K13 DATA20 L13 DATA17 M13

DATA25 J14 DATA21 K14 DATA16 L14 DMAG2 M14

DATA27 J15 DATA23 K15 DATA18 L15 DMAG1 M15

Rev. B | Page 58 of 60 | November 2009

ADSP-21161N

ADDR14 N01 ADDR13 P01 NC R01

ADDR15 N02 ADDR9 P02 ADDR11 R02

ADDR10 N03 ADDR8 P03 ADDR7 R03

ADDR5 N04 ADDR4 P04 ADDR3 R04

ADDR1 N05 MS2 P05 MS3 R05

MS0 N06 SBTS P06 PA R06

BR5 N07 BR4 P07 BR3 R07

BR2 N08 BR1 P08 RD R08

BRST N09 SDCLK1 P09 CLKOUT R09

SDCKE N10 SDCLK0 P10 HBR R10

CS N11 REDY P11 HBG R11

CLK_CFG1 N12 CLKIN P12 CLKDBL R12

CLK_CFG0 N13 DQM P13 XTAL R13

AVDD N14 AGND P14 SDWE R14

DMAR1 N15 DMAR2 P15 NC R15

RSTOUT exists only for silicon revisions 1.2 and greater. Leave this ball unconnected for silicon revisions 0.3, 1.0, and 1.1.

Figure 45. 225-Ball CSP_BGA Ball Assignments (Bottom View, Summary)

Table 40. 225-Ball CSP_BGA Ball Assignments (Continued)

Ball Name Ball Number Ball Name Ball Number Ball Name Ball Number Ball Name Ball Number

VDDINT

VDDEXT

GND*

AGND

AVDD

SIGNAL

*USE THE CENTER BLOCK OF GROUND PINSTO PROVIDE THERMAL

PATHWAYSTO YOUR PRINTED CIRCUIT BOARD GROUND PLANE

KEY:

1214

15 13

ADSP-21161N

Rev. B | Page 59 of 60 | November 2009

OUTLINE DIMENSIONS

The ADSP-21161N comes in a 17 mm × 17 mm, 225-ball

CSP_BGA package with 15 rows of balls.

SURFACE-MOUNT DESIGN

Table 41 is provided as an aid to PCB design. For industry stan-

dard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

ORDERING GUIDE

Figure 46. 225-Ball CSP_BGA (BC-225-1)

*COMPLIANT TO JEDEC STANDARDS MO-192-AAF-2

WITH THE EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.

0.50

REF

17.20

17.00 SQ

16.80

BALL DIAMETER

COPLANARITY

0.20

1.00

BSC

14.00

BSC SQ

DETAIL A

A1 BALL

CORNER

A1 BALL

CORNER

DETAIL A

BOTTOM VIEW

TOP VIEW

SEATING

PLANE

0.70

0.60

0.50

0.54

0.50

0.30

*1.31

1.21

1.10

*1.85

1.71

1.40

15 14 13 12 11 10 987654321

Table 41. BGA Data for Use with Surface-Mount Design

Package Ball Attach Type Solder Mask Opening Ball Pad Size

225-Ball CSP_BGA (BC-225-1) Solder Mask Defined 0.40 mm diameter 0.53 mm diameter

Model Temperature Range

Referenced temperature is case temperature.

Instruction Rate

On-Chip

SRAM

Package

Description

Package

Option

ADSP-21161NKCA-100 0°C to 85°C 100 MHz 1M bit 225-Ball CSP_BGA BC-225-1

ADSP-21161NCCA-100 –40°C to +105°C 100 MHz 1M bit 225-Ball CSP_BGA BC-225-1

ADSP-21161NKCAZ100

Z indicates RoHS compliant package.

0°C to 85°C 100 MHz 1M bit 225-Ball CSP_BGA BC-225-1

ADSP-21161NCCAZ100

–40°C to +105°C 100 MHz 1M bit 225-Ball CSP_BGA BC-225-1

ADSP-21161NYCAZ110

–40°C to +125°C 110 MHz 1M bit 225-Ball CSP_BGA BC-225-1

Rev. B | Page 60 of 60 | November 2009

ADSP-21161N

registered trademarks are the property of their respective owners.

D02935-0-11/09 (B)