LTC7003 Fast 60V Protected High Side NMOS Static Switch Driver FEATURES DESCRIPTION Wide Operating VIN: 3.5V to 60V n 1 Pull-Down, 2.2 Pull-Up for Fast Turn-On and Turn-Off Times with 35ns Propagation Delays n Internal Charge Pump for 100% Duty Cycle n Short-Circuit Protected n Adjustable Current Trip Threshold n Current Monitor Output n Automatic Restart Timer n Open-Drain Fault Flag n Adjustable Turn-On Slew Rate n Gate Driver Supply from 3.5V to 15V n Adjustable V Undervoltage and Overvoltage IN Lockouts n Adjustable Driver Supply V CC Undervoltage Lockout n Low Shutdown Current: 1A n CMOS Compatible Input n Thermally Enhanced, High Voltage Capable 16-Lead MSOP Package The LTC(R)7003 is a fast high side N-channel MOSFET gate driver that operates from input voltages up to 60V. It contains an internal charge pump that fully enhances an external N-channel MOSFET switch, allowing it to remain on indefinitely. n Its powerful driver can easily drive large gate capacitances with very short transition times, making it well suited for both high frequency switching applications or static switch applications that require a fast turn-on and/or turn-off time. When an internal comparator senses that the switch current has exceeded a preset level, a fault flag is asserted and the switch is turned off after a period of time set by an external timing capacitor. After a cooldown period, the LTC7003 automatically retries. The LTC7003 is available in the thermally-enhanced 16-lead MSOP package. All registered trademarks and trademarks are the property of their respective owners. APPLICATIONS Static Switch Driver Load and Supply Switch Driver n Electronic Valve Driver n High Frequency High Side Gate Driver n n TYPICAL APPLICATION High Side Switch with 100% Duty Cycle and Overcurrent Protection VIN 3.5V TO 60V VIN RUN OFF ON SNS+ LTC7003 INP SNS- VCC TGUP TGDN 100k 1F 1nF FAULT TIMER VCCUV OVLO BST TS GND 7003 TA01a 100 0.007 Turn-On Transient Waveform VINP 2V/DIV VLOAD 20V/DIV 0.1F LOAD 3.5V TO 60V 3A CONTINOUS MAX PINS NOT USED IN THIS CIRCUIT: IMON ISET VIN = 60V 20ns/DIV 7003 TA01b Rev. B Document Feedback For more information www.analog.com 1 LTC7003 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 3 Order Information........................................... 3 Pin Configuration........................................... 3 Electrical Characteristics.................................. 4 Typical Performance Characteristics.................... 6 Pin Functions................................................ 8 Block Diagram............................................... 9 Timing Diagram............................................ 10 Operation................................................... 10 Overcurrent Protection............................................ 10 Current Monitor....................................................... 10 VCC Power................................................................ 10 Internal Charge Pump.............................................. 11 Start-Up and Shutdown........................................... 11 Protection Circuitry.................................................. 11 2 Applications Information................................. 12 Input Stage.............................................................. 12 Output Stage............................................................ 12 SNS+ and SNS- Pins................................................ 12 ISET Pin.................................................................... 13 Fault Timer and Fault Flag........................................ 13 Cooldown Period and Restart.................................. 14 Fast Turn-Off Mode.................................................. 15 High Side Current Monitor Output........................... 15 RUN Pin and External Input Overvoltage/ Undervoltage Lockout.............................................. 15 Bootstrapped Supply (BST-TS)................................ 16 VCC Undervoltage Comparator................................. 17 MOSFET Selection................................................... 18 Limiting Inrush Current During Turn-On.................. 18 Optional Schottky Diode Usage on TS..................... 19 Reverse Current Protection...................................... 19 Design Example....................................................... 19 PC Board Layout Considerations.............................20 Typical Applications....................................... 21 Package Description...................................... 24 Revision History........................................... 25 Typical Application........................................ 26 Related Parts............................................... 26 Rev. B For more information www.analog.com LTC7003 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltages VIN........................................................... -0.3V to 65V BST-TS......................................................-0.3V to 15V VCC...........................................................-0.3V to 15V BST Voltage............................................. -0.3V to 80V TS Voltage...................................................... -6V to 65V RUN, SNS+ and SNS- Voltages ................... -0.3V to 65V SNS+ - SNS- Continuous........................................... -0.3V to +0.3V <1msec..........................................-100mA to +100mA INP Voltage..................................................... -6V to 15V Driver Outputs TGUP, TGDN................................. (Note 7) TIMER, FAULT, Voltages................................-0.3V to 15V VCCUV, ISET, IMON, OVLO Voltages.................. -0.3V to 6V Operating Junction Temperature Range (Notes 2, 3, 4) LTC7003E, LTC7003I........................... -40C to 125C LTC7003H............................................ -40C to 150C LTC7003MP......................................... -55C to 150C Storage Temperature Range.................... -65C to 150C Lead Temperature (Soldering, 10 sec) MSOP Package................................................... 300C PIN CONFIGURATION LTC7003 TOP VIEW RUN 1 VIN 2 VCC 3 VCCUV 4 FAULT 5 TIMER 6 INP 7 OVLO 8 17 GND 16 15 14 13 12 11 10 9 SNS+ SNS- BST TS TGUP TGDN IMON ISET MSE PACKAGE 16-LEAD PLASTIC MSOP (NOTE 6) TJMAX = 150C, JA = 45C/W, JC = 10C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7003EMSE#PBF LTC7003EMSE#TRPBF 7003 16-Lead Plastic MSOP -40C to 125C LTC7003IMSE#PBF LTC7003IMSE#TRPBF 7003 16-Lead Plastic MSOP -40C to 125C LTC7003HMSE#PBF LTC7003HMSE#TRPBF 7003 16-Lead Plastic MSOP -40C to 150C LTC7003MPMSE#PBF LTC7003MPMSE#TRPBF 7003 16-Lead Plastic MSOP -55C to 150C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev. B For more information www.analog.com 3 LTC7003 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN=VSNS+=10V, VCC=VBST=10V, VTS=GND=0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supplies VIN Input Voltage Operating Range TS Operating Voltage Range 3.5 60 V 0 60 V 3.5 60 V 85 60 3 A A A A SNS+/- Input Voltage Range Independent of VIN Total Supply Current (Note 8) ON or Sleep, Charge Pump Regulating ON Mode, Charge Pump Overdriven Sleep Mode, Charge Pump Overdriven Shutdown Mode CVCC=1F VRUN=2V, VBST = Open, VTS = VSNS = 12V VINP=4V, VRUN = 2V, VBST-TS = 13V VINP=0.4V, VRUN = 2V, VBST-TS = 13V VRUN=0V VIN DC Supply Current, Charge Pump Overdriven (Note 5) ON Mode Sleep Mode Shutdown Mode CVCC=1F, VBST-TS = 13V, VINP=4V, VRUN = 2V VINP=0.4V, VRUN = 2V VRUN=0V 35 25 1 A A A SNS+ Current VINP=4V, VRUN = 2V VINP=0.4V, VRUN = 2V VRUN=0V 21 12 0 A A A SNS- Current VINP=4V, VRUN = 2V VINP=0.4V, VRUN = 2V VRUN = 0V VCC LDO Output Voltage CVCC=1F, VIN = 12V 10 V VCC LDO Dropout Voltage (VIN-VCC) VIN = 6V, IVCC = -1mA 0.2 V VCC UVLO VCC Undervoltage Lockout VCCUV = OPEN, VIN=VCC VCC Rising VCC Falling Hysteresis VCCUV = 0V, VIN=VCC VCC Rising VCC Falling Hysteresis VCCUV = 1.5V, VIN=VCC VCC Rising VCC Falling Hysteresis 250 60 37 1 l l l 2 4 0 0 6.5 A A A l l 6.5 5.8 7.0 6.4 600 7.5 6.9 V V mV l l 3.1 2.8 3.5 3.2 300 3.7 3.4 V V mV 9.7 9.1 10.5 9.9 600 10.9 10.3 V V mV 14 14 14 Bootstrapped Supply (BST-TS) VBST-TS VTG Above VTS with VINP=3.5V (DC) VIN=VCC=VTS=7V, IBST=0A VIN=VCC=VTS=10V, IBST=0A VTS=60V, IBST=0A l l 9 10 10 11 12 12 Charge Pump Output Current VTS=20V, VBST-TS=10V l -15 -30 A BST-TS Floating UVLO BST-TS Rising BST-TS Falling 3.1 2.8 V V V V V Output Gate Driver (TG) TG Pull-Up Resistance VIN=VBST=12V l l 2.2 7 1 4 TG Pull-Down Resistance VIN=VBST=12V tr Output Rise Time 10% to 90%, CL=1nF 10% to 90%, CL=10nF 13 90 ns ns tf Output Fall Time 10% to 90%, CL=1nF 10% to 90%, CL=10nF 13 40 ns ns tPLH tPHL Input to Output Propagation Delay VINP Rising, CL=1nF VINP Falling, CL=1nF 4 l l 35 35 70 70 ns ns Rev. B For more information www.analog.com LTC7003 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN=VSNS+=10V, VCC=VBST=10V, VTS=GND=0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS Input Threshold Voltages VINP Rising VINP Falling Hysteresis Input Pull-Down Resistance VINP=1V RUN and OVLO Pin Threshold Voltages Rising Falling Hysteresis RUN and OVLO Leakage Current VRUN = 1.3V, VOVLO = 1.3V MIN TYP MAX UNITS 1.7 1.3 2 1.6 400 2.2 1.8 1.16 1.05 1.21 1.10 110 1.26 1.15 V V mV -100 0 100 nA 1.25 1.3 1.35 V 75 100 125 mV -115 -100 -80 A 2.0 2.5 3.0 A Operation VIH VIL l l 1 TIMER Threshold Voltage VTIMER Rising to VFAULT Going Low TIMER Early Warning Voltage VFAULT Going Low to (TG-TS) Going Low l V V mV M TIMER Pin Fault Pull-Up Current VTIMER=1.0V, ISET=OPEN TIMER Pin Pull-Down Current VTIMER=0.6V ISET=OPEN VSNS=0mV FAULT Output Low Voltage IFAULT=1mA l 0.2 0.5 V FAULT Leakage Current VFAULT=5V l -100 0 100 nA VTH Current Sense Threshold Voltage VSNS = (VSNS+ - VSNS-) ISET=OPEN VISET=1.2V VISET=0V l 22 54 15 30 60 20 36 64 24 mV mV mV D Retry Duty Cycle VSNS = 200mV CTIMER = 1nF l 0.06 0.1 % ISET and VCCUV Pull-Up Current VISET=1.0V, VCCUV = 1.0V IMON Output Voltage VSNS=60mV, VTIMER=0V, VINP = 3.5V VSNS=30mV, VTIMER=0V, VINP = 3.5V VSNS=0mV, VTIMER=0V, VINP = 3.5V Over-Current to TG Low Propagation Delay VSNS Step 10mV to 50mV, ISET=OPEN, VTIMER=VCC, VINP = 3.5V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7003 is tested under pulsed load conditions such that TJTA. The LTC7003E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7003I is guaranteed over the -40C to 125C operating junction temperature range, the LTC7003H is guaranteed over the -40C to 150C operating junction temperature range and the LTC7003MP is tested and guaranteed over the -55C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. l l -11.3 -10 -8.7 A 1.12 0.52 1.2 0.6 0 1.28 0.68 0.1 V V V 70 ns Note 3: The junction temperature (TJ, in C) is calculated from the ambient temperature (TA, in C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD * JA), where JA is 45C/W. Note 4: This IC includes over temperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: For application concerned with pin creepage and clearance distances at high voltages, the MSE16(12) variation package should be used. See Applications Information. Note 7: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only; otherwise permanent damage may occur. Note 8: Total supply current is the sum of the current into the VIN, SNS+, SNS- and TS pins. Rev. B For more information www.analog.com 5 LTC7003 TYPICAL PERFORMANCE CHARACTERISTICS Driver On Resistance vs VBST-TS Voltage VSNS+ = VSNS- = VTS 2.5 VCCUV = 0V 2.0 12 10 4 1.5 14 TGUP TGDN 5 RDSON () 3 8 6 1.0 2 0.5 1 2 0 0 0 0 4 8 12 VTS (V) 16 20 15 VCC = 4V 6 11 5.0 12 15 7 5 3 -20 -40 IBST (A) -60 -80 -25.0 15 30 VTS (V) 7003 G04 RUN and OVLO Threshold Voltages vs Temperature 8.0 7003 G03 40 30 20 45 ISET = 0V ISET = OPEN 0 -50 60 0 ISET = 1.2V ISET = 1.5V 50 100 TEMPERATURE (C) Driver On Resistance vs Temperature 4 VCCUV = OPEN VBST-TS = 12V TGUP TGDN 3 1.15 1.10 RISING FALLING 0 50 100 TEMPERATURE (C) 150 7.0 RESISTANCE () VCCUV LOCKOUT (V) THRESHOLD VOLTAGE (V) 7.5 6.5 6.0 2 1 5.5 5.0 -50 RISING FALLING 0 50 100 TEMPERATURE (C) 7003 G07 6 150 7003 G06 7003 G05 1.20 1.05 -50 20 50 VCCUV Lockout vs Temperature 1.25 15 60 10 25C 150C 0 10 VTS (V) 70 -15.0 -45.0 5 VTH vs Temperature -35.0 0 0 80 VCC = 7V VBST-TS = 10V 1 IBST = 0A 7003 G02 -5.0 IBST (A) 9 -1 9 VBST-TS (V) Charge Pump Output Current vs VTS VTS = 4V VTS = 6V VTS = 8V VTS = 10V VTS = 12V 13 VBST-VTS (V) 3 7003 G01 Charge Pump Load Regulation VCC = 4V VCC = 5V VCC = 6V VCC = 7V VCC 8V 4 CURRENT SENSE THRESHOLD VOLTAGE (mV) CURRENT (mA) 6 VIN = 5V VIN = 12V Charge Pump No-Load Output Voltage vs VTS VBST - V TS (V) 3.0 Total Supply Current vs VTS TA = 25C, unless otherwise noted. 150 7003 G08 0 -50 0 50 100 TEMPERATURE (C) 150 7003 G09 Rev. B For more information www.analog.com LTC7003 TYPICAL PERFORMANCE CHARACTERISTICS SNS+ Supply Current vs Temperature VIN Supply Current vs Temperature 35 30 VIN = 10V 6.0 VIN = VSNS+ = VSNS- = 10V 20 25 CURRENT (A) CURRENT (A) 30 SNS- Supply Current vs Temperature 20 15 10 5 0 -50 0 50 100 TEMPERATURE (C) 10 0 SHUTDOWN SLEEP ON SHUTDOWN SLEEP ON 0 50 100 TEMPERATURE (C) -2.0 -50 150 7003 G10 SHUTDOWN, SLEEP ON 0 50 100 TEMPERATURE (C) 7003 G11 VIN = 10V 150 7003 G12 SNS+ FAULT Threshold vs Temperature Input Threshold Voltage vs Temperature 3.0 2.0 0 -10 -50 150 VIN = VSNS+ = VSNS- = 10V 4.0 CURRENT (A) 40 TA = 25C, unless otherwise noted. Overcurrent to TGDN=LOW Delay Time vs Temperature 3.4 22 3.3 21 CTIMER = 1nF 2.0 1.5 1.0 0.5 0 -50 RISING FALLING 0 50 100 TEMPERATURE (C) TIME (s) THRESHOLD VOLTAGE (V) THRESHOLD VOLTAGE (V) 2.5 3.2 3.1 19 3.0 -50 150 RISING FALLING 0 50 100 TEMPERATURE (C) 7003 G13 -9.0 0.065 150 3.5 PULL-UP CURRENT (A) THRESHOLD VOLTAGE (V) DUTY CYCLE (%) 150 VISET = 1.0V VVCCUV = 1.0V 0.070 50 100 TEMPERATURE (C) 50 100 TEMPERATURE (C) ISET and VCCUV Pull-Up Current vs Temperature 4.0 0.075 0 0 7003 G15 VBST-TS Floating UVLO Voltage vs Temperature CTIMER = 1nF 0.060 -50 18 -50 150 7003 G15 Retry Duty Cycle vs Temperature 0.080 20 3.0 2.5 2.0 -50 RISING FALLING 0 50 100 TEMPERATURE (C) 7003 G16 150 7003 G17 -9.5 -10.0 -10.5 -11.0 -50 0 50 100 TEMPERATURE (C) 150 7003 G18 Rev. B For more information www.analog.com 7 LTC7003 PIN FUNCTIONS RUN (Pin 1): Run Control Input. A voltage on this pin above 1.21V enables normal operation. Forcing this pin below 0.7V shuts down the LTC7003, reducing quiescent current to approximately 1A. Optionally connect to the input supply through a resistive divider to set the undervoltage lockout. VIN (Pin 2): Main Supply Pin. A bypass capacitor with a minimum value of 0.1F should be tied between this pin and GND. VCC (Pin 3): Output of internal LDO and power supply for gate drivers and internal circuitry. Decouple this pin to GND with a minimum 1.0F low ESR ceramic capacitor. Do not use the VCC pin for any other purpose. VCC can be overdriven from an external high efficiency source for high frequency switching applications that require higher power delivered to the external MOSFET. Do not connect VCC to a voltage greater than VIN. VCCUV (Pin 4): VCC Supply Undervoltage Lockout. A resistor on this pin sets the reference for the Gate Drive undervoltage lockout. The voltage on this pin in the range of 0.4V to 1.5V is multiplied by 7 to be the undervoltage lockout for the Gate Drive (VCC pin). Short to ground to set the minimum gate drive UVLO of 3.5V. Leave open to set gate drive UVLO to 7.0V FAULT (Pin 5): Open Drain Fault Output. This pin pulls low after the voltage on the TIMER pin has reached the fault threshold of 1.3V. It indicates the pass transistor is about to turn off due to an overcurrent condition. The typical pull-down impedance is 200. The FAULT pin does not go to a high-impedance state until the overcurrent condition and the TIMER cooldown period expire. If the TIMER pin is pulled above 3.5V, the TIMER function is disabled. In this state this pin pulls low when the VTGUP-TS signal is driven high. TIMER (Pin 6): Fault Timer Input. A timing capacitor, CT, from the TIMER pin to GND sets the times for fault warning, fault turn off and retry periods (see Applications Information). When the TIMER pin is connected to a voltage higher than 3.5V, an overcurrent condition will immediately pull the TGUP pin to TS. TGDN will not go high again until the fault condition is reset by the INP pin going low and then back high. 8 INP (Pin 7): Input Signal. CMOS compatible input reference to GND that sets the state of TGDN and TGUP pins (see Applications Information). INP has an internal 1M pull-down to GND to keep TGDN pulled to TS during startup transients. OVLO (Pin 8): Overvoltage Lockout Input. Connect to the input supply through a resistor divider to set the overvoltage lockout level. A voltage on this pin above 1.21V causes TGDN to be pulled to TS. Normal operation resumes when the voltage on this pin decreases below 1.11V. Triggering an OVLO causes a fault condition. OVLO should be tied to GND when not used. ISET (Pin 9): Current Trip Threshold Set. A resistor on this pin to GND sets the peak current threshold. The voltage on this pin (internally clamped between 0.4V and 1.5V) is divided by 20 to be the current comparator reference. Short to GND for minimum peak current (20mV VTH). Leave open for an accurate peak current (30mV VTH). IMON (Pin 10): Current Monitor. The voltage on this pin with respect to GND represents the voltage across the sense resistor multiplied by 20. The range on this pin is 0V to 1.5V. TGDN (Pin 11): High Current Gate Driver Pull-Down. This pin pulls down to TS. For the fastest turn-off, tie this pin directly to the gate of the external high side MOSFET. TGUP (Pin 12): High Current Gate Driver Pull-Up. This pin pulls up to BST. Tie this pin to TGDN for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the in-rush current during turn-on. See Applications Information. TS (Pin 13): Top (High Side) source connection or GND if used in ground referenced applications. BST (Pin 14): High Side Bootstrapped Supply. An external capacitor with a minimum value of 0.1F should be tied between this pin and TS. Voltage swing on this pin is 12V to (VIN+12V). Rev. B For more information www.analog.com LTC7003 PIN FUNCTIONS SNS- (Pin 15), SNS+ (Pin 16): Current Sense Comparator Input. Place a sense resistor in series with the drain of the external MOSFET to set the peak current. The SNS- pin should be connected to the sense resistor using a minimum 100 resistor. Use a Kelvin connection from the SNS+ pin to the sense resistor. The current comparator trip threshold voltage, VTH is the ISET voltage divided by 20. The trip threshold is internally clamped to a minimum of 20mV and a maximum of 75mV. If ISET is open or greater than 2.0V, VTH is set internally to 30mV. GND (Exposed Pad Pin 17): Ground. The exposed pad must be soldered to the PCB for rated electrical and thermal performance. BLOCK DIAGRAM 3.5V TO 60V 2 9 VIN 10 IMON ISET 2.3V 1.0V 3 - + 100k 10A /20 VCC CVCC SNS+ 16 + 20x - SNS- 15 20mV TO 75mV + - 9R RSNS RFLT VCC D1 (OPTIONAL) BST 14 R PCH TGUP 12 LEVEL SHIFT UP CHARGE PUMP CB TGDN M1 11 NCH TS 13 SNS+ 2.3V VCCUV 3.2V + - LEVEL SHIFT DOWN + - 10A 4 RUN 1 1.21V OVLO 8 INP 7 1M + - LOAD FAULT 5 200 2.3V 102.5A/5A LOGIC TIMER + - 6 + - 3.5V 1.4V 1.3V 0.4V CT 2.5A 7003 BD Rev. B For more information www.analog.com 9 LTC7003 TIMING DIAGRAM INPUT RISE/FALL TIME < 10ns INPUT (INP) VIH VIL 90% 10% OUTPUT (TG-TS) tPLH tr tPHL tf 7003 TD OPERATION (Refer to Block Diagram) The LTC7003 is designed to receive a ground-referenced, low voltage digital input signal, INP and quickly drive and protect a high side N-channel power MOSFET whose drain can be up to 60V above ground. The LTC7003 is capable of driving a 1nF load using a 12V bootstrapped supply voltage (VBST -V TS) with 35ns of propagation delay and fast rise/fall times. The high gate drive voltage reduces external power losses associated with external MOSFET on-resistance. The strong drivers not only provide fast turn on and off times but hold the TGUP and TGDN to TS voltages in the desired state in the presence of high slew rate transients which can occur driving inductive loads at high voltages. Overcurrent Protection The LTC7003 protects a high side N-channel MOSFET from an overcurrent condition by monitoring the voltage across an external sense resistor placed in series with the drain of an external MOSFET and forcing the external MOSFET to turn off by pulling TGDN to TS when the voltage across the sense resistor, VSNS, exceeds the current comparator threshold voltage, V TH, after a period of time set by the timing capacitor, CT. When an overcurrent condition is detected with ISET open, V TH is internally programmed to a low value of 30mV minimizing the external conduction loss associated with current sensing by allowing the use of lower value sense resistors. A resistor placed between ISET and ground allows V TH to be programmed from 20mV to 75mV. 10 An adjustable fault and overcurrent timer is enabled by placing a capacitor, C T from the TIMER pin to ground and allows the load to continue functioning during brief overcurrent transient events while protecting the MOSFET from long periods of high currents. An external fault flag is available which can warn of an impending MOSFET turn off. A fast turn-off mode where TGDN is immediately pulled to TS due to an overcurrent is available by connecting the TIMER pin to VCC. Current Monitor The LTC7003 provides an output voltage referenced to ground on the IMON pin that reflects the current flowing through the external sense resistor connected between SNS+ and SNS- while TGUP is high. The voltage on IMON is the voltage difference between the SNS+ and SNS- pins multiplied by 20x and referenced to ground with a range of 0V to 1.5V. The IMON output voltage has an output impedance of 100k and is pulled to ground with a 100k resistor when INP is low. VCC Power Power for the MOSFET driver and internal circuitry is derived from the VCC pin. The VCC pin voltage is generated from an internal P-channel LDO connected to VIN. VCC can also be overdriven from a high efficiency external source for high frequency switching applications that require higher power delivered to external MOSFET. VCC should never be driven higher than VIN or permanent damage to the LTC7003 could occur. Rev. B For more information www.analog.com LTC7003 OPERATION (Refer to Block Diagram) Internal Charge Pump The LTC7003 contains an internal charge pump that enables the MOSFET gate drive to have 100% duty cycle. The charge pump regulates the BST-TS voltage to 12V reducing external power losses associated with external MOSFET on-resistance. The charge pump uses the higher voltage of TS or VCC as the source for the charge. Start-Up and Shutdown If the voltage on the RUN pin is less than 0.7V, the LTC7003 enters a shutdown mode in which all internal circuitry is disabled, reducing the DC supply current to approximately 1A. When the voltage on the RUN pin exceeds 0.7V, the internal LDO connected to VIN is enabled and regulates VCC to 10V. At VIN voltages less than 10V, the LDO will operate in drop-out and VCC will follow VIN. When the voltage on the RUN pin exceeds 1.21V, the input circuitry is enabled allowing TGUP and TGDN to be driven high with respect to TS. Protection Circuitry When using the LTC7003, care must be taken not to exceed any of the ratings specified in the Absolute Maximum Ratings section. As an added safeguard, the LTC7003 incorporates an overtemperature shutdown feature. If the junction temperature reaches approximately 180C, the LTC7003 will enter thermal shutdown mode and TGDN will be pulled to TS. After the part has cooled below 160C, TGDN will be allowed to go back high. The overtemperature level is not production tested. The LTC7003 is guaranteed to start a temperatures below 150C. The LTC7003 additionally implements protection features which prohibit TGUP being pulled to BST when VIN, VCC or (VBST -V TS) are not within proper operating ranges. By using a resistive divider from VIN to ground, the RUN and OVLO pins can serve as a precise input supply overvoltage/undervoltage lockouts. TGDN is pulled to TS when either RUN falls below 1.11V or OVLO rises above 1.21V, which can be configured to limit switching to a specific range on input supply voltages. Furthermore, if VIN falls below 3.5V, an internal undervoltage detector pulls TGDN to TS. VCC contains an undervoltage lockout feature that will pull TGDN to TS and is configured by the VCCUV pin. If VCCUV is open, TGDN is pulled to TS until VCC is greater than 7.0V. By using a resistor from VCCUV to ground, the rising undervoltage lockout on VCC can be adjusted from 3.5V to 10.5V. An additional internal undervoltage lockout is included that will pull TGDN to TS when the floating voltage from BST to TS is less than 3.1V (typical). Rev. B For more information www.analog.com 11 LTC7003 APPLICATIONS INFORMATION Input Stage LTC7003 The LTC7003 employs CMOS compatible input thresholds that allow a low voltage digital signal connected to INP to drive standard power MOSFETs. The LTC7003 contains an internal voltage regulator which biases the input buffer connected to INP allowing the input thresholds (VIH=2.0V, VIL=1.6V) to be independent of variations in VCC. The 400mV hysteresis between VIH and VIL eliminates false triggering due to noise events. However, care should be taken to keep INP from any noise pickup, especially in high frequency, high voltage applications. INP also contains an internal 1M pull-down resistor to ground, keeping TGDN pulled to TS during startup and other unknown transient events. During shutdown (VRUN<0.7V) the internal 1M pull-down resistor is disabled and INP becomes high impedance. INP has an Absolute Maximum of -6V to +15V which allows the signal driving INP to have voltage excursions outside the normal power supply and ground range. It is not uncommon for signals routed with long PCB traces and driven with fast rise/fall times to inductively ring to voltages higher than power supply or lower than ground. Output Stage A simplified version of the LTC7003 output stage is shown in Figure1. The pull-down device is an N-channel MOSFET with a typical 1 RDS(ON) and the pull-up device is a P-channel MOSFET with a typical 2.2 RDS(ON). The pull-up and pull-down pins have been separated to allow the turn-on transient to be controlled while maintaining a fast turn-off. The LTC7003 powerful output stage (1 pull-down and 2.2 pull-up) minimizes transition losses when driving external MOSFETs and keeps the MOSFET in the state commanded by INP even if high voltage and high frequency transients couple from the power MOSFET back to the driving circuitry. The large gate drive voltage on TGUP and TGDN reduces conduction losses in the external MOSFET because RDS(ON) is inversely proportional to its gate overdrive (VGS-VTH). 12 BST 12V + AV = 1 - + - CHARGE PUMP VCC 2.2 TGUP TGDN 30A 1 INP HIGH SPEED 60V LEVEL SHIFTER TS 7003 F01 Figure1. Simplified Output Stage SNS+ and SNS- Pins SNS+ and SNS- are the inputs to the high side current comparator and current monitor. The common mode operational voltage range for these pins is 3.5V to 60V independent of any other voltages. SNS+ also provides power to the current comparator and current monitor and draws approximately 21A when not shut down and INP is high. SNS- draws a bias current of approximately 4A when not shut down and INP is high. When SNS+ is less than 3.2V typical (3.5V maximum), a fault condition occurs and the adjustable fault timer is enabled with the same behavior as an overcurrent fault. Normally the SNS pins are connected to the drain side of the external MOSFET. However, the SNS pins can be connected to the source side of the external MOSFET as long as the source voltage rises above 3.5V before the Fault Timer expires. See Fault Timer and Fault Flag section. A filter resistor, RFLT should be placed in series with the SNS- pin as shown in Figure2. Note that the SNS- pin takes 4A of bias current which will affect the current sense and current monitoring functions. RFLT should be at least 2000x larger than RSNS (minimum 100) to provide robustness during short-circuit events. The current injected in to the SNS+ and SNS- pins, during a short circuit event, depends on the voltage on POWER, RSNS, external MOSFET RDSON, timer capacitor value and the value of RFLT. Rev. B For more information www.analog.com LTC7003 APPLICATIONS INFORMATION POWER SNS+ LTC7003 CFLT SNS- INP = LO, 0A INP = HI, 4A RSNS RFLT M1 TGUP TGDN TS 7003 F02 LOAD Figure2. Sense Pins Filtering ISET Pin The current comparator has an adjustable threshold voltage, VTH, of 20mV to 75mV and is set by placing a resistor to ground on the ISET pin. The ISET pin is biased with an internal 10A current source. Floating ISET enables the current comparator to have an accurate 30mV threshold voltage which allows for lower value sense resistors and reduces the external power dissipation. By placing a 40k to 150k resistor between ISET and ground, the sense threshold voltage can be programmed to values between 20mV and 75mV. The value of resistor for a particular sense threshold voltage can be selected using Figure3 or the following equation: RISET = VTH 0.5A Where 20mV< VTH < 75mV. CURRENT SENSE THRESHOLD VTH (mV) 80 70 Fault Timer and Fault Flag The LTC7003 includes an adjustable fault timer. Connecting a capacitor from the TIMER pin to ground sets the delay period before the external MOSFET is turned off during an overcurrent fault condition. The same capacitor also sets the cooldown period before the external MOSFET is allowed to turn back on. Once a fault condition is detected, a 100A current charges the TIMER pin. When the voltage on the TIMER pin reaches 1.3V, the FAULT pin pulls low to indicate the detection of a fault condition and provide warning of an impending power loss. After the TIMER voltage crosses the 1.4V threshold, TGDN is immediately pulled to TS turning off the external MOSFET. The ontime of the external MOSFET, TOVER_CURRENT, during an overcurrent event is given by the following equation: TOVER _CURRENT = 1.4V * CTIMER + 1.5sec 100A The warning time, TWARNING, generated by an overcurrent event is given by the following equation: TWARNING = 0.1V * CTIMER + 1.5sec 100A If the overcurrent fault condition disappears before TIMER has reached 1.4V, TIMER is discharged by a 2.5A current. If TIMER had reached 1.3V (FAULT has gone low) and the overcurrent fault condition disappears, TIMER is discharged with a 2.5A current and FAULT will be reset when TIMER reaches 0.4V. The on-time and warning times are shown graphically in Figure4. VTMR (V) 60 1.4 50 1.3 40 30 20 10 0 0 30 60 90 120 150 180 210 240 ISET RESISTOR TO GROUND (k) 7003 F03 TIME TFAULT TWARNING 13ms/F 1ms/F TOVER_CURRENT 7003 F04 14ms/F Figure3. RISET Selection Figure4. Fault Timer Trip Points Rev. B For more information www.analog.com 13 LTC7003 APPLICATIONS INFORMATION Cooldown Period and Restart As soon as TIMER reaches 1.4V, TGDN is pulled to TS in an overcurrent fault condition and the TIMER pin starts discharging with a 2.5A current. When TIMER reaches 0.4V, TIMER charges with a 2.5A current. When TIMER reaches 1.4V, it starts discharging again with a 2.5A current. This pattern repeats 32 times to form a long cooldown timer period (TCOOL_DOWN) before retry (Figure5). If INP is cycled low, TGDN will be pulled to TS and TIMER will be pulled low with an internal 100k resistor. If INP is cycled low during the cooldown period, the timer counter will be reset. If INP then goes high, TGUP will pulled to BST and the fault timer will be reactivated with the TIMER voltage starting from it's current value. The retry duty cycle in percent is to a first order independent of CT and is defined by: D= 100 * TOVER _CURRENT TOVER _CURRENT + TCOOL _DOWN To defeat the automatic retry, place a 100k resistor in parallel with the TIMER capacitor. Note that the time to turn off from an overcurrent fault will be increased by 7% and the FAULT pin will remain low indicating a fault has occurred. To get the LTC7003 to retry and to clear the fault flag the INP signal needs to cycle low then back high. Typical turn-off times and cooldown periods for some standard value timer capacitors are shown Table1: Table1. Fault Time for Typical Capacitors At the end of the cooldown period (when TIMER drops below 0.4V for the 32nd time), the LTC7003 retries, pulling TGUP to BST and turning on the external MOSFET. The FAULT pin will then go to a high impedance state. The total cooldown timer period is given by: CTIMER TOVER_CURRENT 63 * 1.0V * CTIMER 2.5A TCOOL _DOWN = TCOOL_DOWN Retry Duty Cycle (nF) (s) (s) % <0.1 ~3 0.0005 ~0.6 1 16 0.025 0.06 10 142 0.250 0.06 100 1402 2.500 0.06 >30mV <30mV VSNS 1.40V 1.30V TIMER 0.4V 1ST 2ND 31ST 32ND FAULT V(TG-TS) (TGUP SHORTED TO TGDN) 7003 F05 INP COOLDOWN PERIOD (TCOOL_DOWN) Figure5. Auto Retry Cool-Down Timer Cycle 14 Rev. B For more information www.analog.com LTC7003 APPLICATIONS INFORMATION >30mV >30mV <30mV VSNS 1.40V 1.30V TIMER 0.4V 1ST 1ST 31ST 32ND FAULT V(TG-TS) (TGUP SHORTED TO TGDN) 7003 F06 INP Figure6. Auto Retry with INP Cycling Low Fast Turn-Off Mode If the TIMER pin is connected to VCC or any other supply greater than 3.5V (abs max 15V), an overcurrent event will immediately pull TGDN to TS and the LTC7003 will remain there until the INP signal has cycled low and then back high. In fast turn-off mode, the typical delay from a VSNS overcurrent step to TG going low is around 70ns, so very fast short-circuit events can be detected. Also, when the TIMER pin is connected to a voltage greater than 3.5V, the FAULT signal is redefined to be the inverse state of the high side pull-up (VTGUP-VTS). The FAULT signal can be used in this application as low-voltage digital information that has been level shifted down from the high side MOSFET. An application for this could include using this signal to wait until VTGUP-VTS has gone low before turning on a redundant power MOSFET. High Side Current Monitor Output The LTC7003 contains a high side current monitor output. The high side differential voltage sensed across the SNS+ and SNS- pins (VSNS) is multiplied by 20 and ground referenced on the IMON pin which makes it suitable for monitoring and regulating the MOSFET current. The working range of IMON is 0V to 1.5V as VSNS varies from 0mV to 75mV. The IMON pin is a voltage output whose nominal output impedance is 100k and should not be resistively loaded. The current monitor output is only available after the INP signal has been high for 150sec (typical), otherwise the IMON pin is pulled to ground. A block diagram of the IMON circuit is shown in Figure7. The gm of the transimpedance amplifier tracks the 100k internal resistor to ground which makes variations over process minimal. LTC7003 SNS+ SNS- + - gm = 200A/V INP IMON 100k 7003 F07 Figure7. IMON Block diagram RUN Pin and External Input Overvoltage/Undervoltage Lockout The RUN pin has two different threshold voltage levels. Pulling RUN below 0.7V puts the LTC7003 into a low quiescent current shutdown mode (IQ ~ 1A). When the RUN pin is greater than 1.21V, the part is enabled. Figure8 shows examples of configurations for driving the RUN pin from logic. Rev. B For more information www.analog.com 15 LTC7003 APPLICATIONS INFORMATION The RUN and OVLO pins can alternatively be configured as precise undervoltage (UVLO) and overvoltage (OVLO) lockouts on the VIN supply with a resistive divider from VIN to ground. A simple resistive divider can be used as shown in Figure9 to meet specific VIN voltage requirements. When RUN is less that 1.11V or OVLO is greater than 1.21V, TGDN will be pulled to TS and the external MOSFET will be turned off. The approximate delay time for the OVLO pin to turn on or turn off the external MOSFET is 2.5sec. The approximate delay time for the RUN pin falling lower than 1.11V to turn off the external MOSFET is 3.5sec. VIN SUPPLY R1 LTC7003 LTC7003 RUN RUN M2 7003 F08 VIN RUN LTC7003 7003 F09 Figure9. Adjustable UV and OV Lockout The current that flows through the R3-R4-R5 divider will directly add to the shutdown, sleep and active current of the LTC7003, and care should be taken to minimize the impact of this current on the overall current used by the application circuit. Resistor values in the megaohm range may be required to keep the impact of the quiescent shutdown and sleep currents low. To pick resistor values, the sum total of R3+R4+R5 (RTOTAL) should be chosen first based on the allowable DC current that can be drawn from VIN. The individual values of R3, R4 and R5 can then be calculated from the following equations: R5 = RTOTAL * 16 For applications that do not need a precise external OVLO the OVLO pin is required to be tied directly to ground. The RUN pin in this type of application can be used as an external UVLO using the above equations with R5=0. Similarly, for applications that do not require a precise UVLO, the RUN pin can be tied to VIN. In this configuration, the UVLO threshold is limited by the internal VIN UVLO thresholds as shown in the Electrical Characteristics table. The resistor values for the OVLO can be computed using the above equations with R3=0. If the VIN(MAX) relationship for the OVLO pin cannot be satisfied, an external 5V Zener diode should also be placed from OVLO to ground in addition to any lockout setting resistors. OVLO R5 R3 = RTOTAL - R5 - R4 R5 VIN(MAX) * < 6V R3+R4+R5 R3 D5 1.21V - R5 Rising VIN UVLO Threshold Be aware that the OVLO pin cannot be allowed to exceed its absolute maximum rating of 6V. To keep the voltage on the OVLO pin from exceeding 6V, the following relationship should be satisfied: Figure8. RUN Pin Interface to Logic R4 R4 = RTOTAL * 1.21V Rising VIN OVLO Threshold Bootstrapped Supply (BST-TS) An external bootstrapped capacitor, CB, connected between BST and TS supplies the gate drive voltage for the MOSFET driver. The LTC7003 keeps the BST-TS supply charged with an internal charge pump, allowing for duty cycles up to 100%. When the high side external MOSFET is to be turned on, the driver places the CB voltage across the gate-source of the MOSFET. This enhances the high side MOSFET and turns it on. The source of the MOSFET, TS, rises to VIN and the BST pin follows. With the high side MOSFET on, the BST voltage is above the input supply; VBST=VIN+12V. The boost capacitor, CB, supplies the charge to turn on the external MOSFET and needs to have at least 10 times the charge to turn on the external MOSFET fully. The charge to turn on the external MOSFET Rev. B For more information www.analog.com LTC7003 APPLICATIONS INFORMATION is referred to gate charge, QG, and is typically specified in the external MOSFET data sheet. Gate charge can range from 5nC to hundreds of nCs and is influenced by the gate drive level and the type of external MOSFET used. For most applications, a capacitor value of 0.1F for CB will be sufficient. However, the following relationship for CB should be maintained: CB > The internal charge pump that charges the BST-TS supply outputs approximately 30A to the BST pin. If the time to charge the external bootstrapped capacitor, CB from initial power-up with the internal charge pump is not sufficient for the application, a low reverse leakage external silicon diode, D1, with a reverse voltage rating greater than VIN connected between VCC and BST should be used as shown in Figure10. An external silicon diode between VCC and BST should be used if the following relationship cannot be met: BST diode required if C * 12V power-up to INP going high < B 40ms 30A VCC D1 BST TS 7003 F10 Figure10. External BST Diode Another reason to use an external silicon diode between VCC and BST is if the external MOSFET is switched at a frequency so high that the BST-TS supply collapses. An external silicon diode between VCC and BST should be used if the following relationship cannot be met: *BAS416, Nexperia *BAQ34, Vishay Semiconductors *CMOD6001, Central Semiconductor The VCC pin provides the power for the MOSFET gate drivers and internal circuitry. The LTC7003 features an internal P-channel low dropout regulator (LDO) that can supply power at VCC from the VIN supply pin or VCC can be driven from an external power supply. If the internal P-channel LDO is used to power VCC, it must have a minimum 1.0F low ESR ceramic capacitor to ensure stability and should not be connected to any other circuitry other than optionally biasing some pins on the LTC7003 (FAULT, INP or TIMER). If the internal P-channel LDO is used to power VCC and an external silicon diode is used between VCC and BST, care must be taken not to switch an external MOSFET at too high a frequency that can collapse the internal LDO. The internal LDO can only supply 1mA with a 200mV drop-out. In order to keep the internal LDO supply from collapsing when an external silicon diode is used from VCC to BST, the following relationship should be maintained: Maximum switching frequency with internal LDO< CB BST diode required if switching frequency > *BAS116 Series, Multiple Vendors VCC Generation External MOSFET QG 1V LTC7003 Some example silicon diodes with low leakage include: 30A 500Hz 2 * MOSFET QG A Schottky diode should not be used between VCC and BST, as the reverse leakage of the Schottky diode at hot will be more current than the charge pump can overcome. 1mA 20kHz 2 * MOSFET QG For higher gate charge applications, an external silicon diode between VCC and BST should be used and VCC can be driven from a high efficiency external supply. VCC should never be driven higher than VIN or permanent damage to the LTC7003 could occur. VCC Undervoltage Comparator The LTC7003 contains an adjustable undervoltage lockout (UVLO) on the VCC voltage that pulls TGDN to TS and can be easily programmed using a resistor (RVCCUV) between the VCCUV pin and ground. The voltage generated on VCCUV by RVCCUV and the internal 10A current source set the VCC UVLO. The rising VCC UVLO is internally limited within Rev. B For more information www.analog.com 17 LTC7003 APPLICATIONS INFORMATION the range of 3.5V and 10.5V. If VCCUV is open the rising VCC UVLO is set internally to 7.0V. The typical value of resistor for a particular rising VCC UVLO can be selected using Figure11 or the following equation: RVCCUV = Rising VCC UVLO 70A Limiting Inrush Current During Turn-On Where 3.5V < Rising VCC UVLO < 10.5V. 11 10 9 VCC UVLO (V) 8 7 6 5 4 3 2 RISING VCC UVLO FALLING VCC UVLO 1 0 0 damage to the MOSFET. The overcurrent trip point (RSNS and RISET) of the LTC7003 and TIMER capacitor should be chosen to stay within the SOA region of the MOSFET selected for the application. 30 60 90 120 150 180 210 240 VCCUV RESISTOR TO GROUND (k) 7003 F11 Figure11. VCCUV Resistor Selection MOSFET Selection The most important parameters in high voltage applications for MOSFET selection are the breakdown voltage BVDSS, on-resistance RDS(ON) and the safe operating area, SOA. The MOSFET, when off, will see the full input range of the input power supply plus any additional ringing than can occur when driving inductive loads. Driving large capacitive loads such as complex electrical systems with large bypass capacitors should be powered using the circuit shown in Figure12. The pull-up gate drive to the power MOSFET from TGUP is passed through an RC delay network, RG and CG, which greatly reduces the turn-on ramp rate of the MOSFET. Since the MOSFET source voltage follows the gate voltage, the load is powered smoothly from ground. This dramatically reduces the inrush current from the source supply and reduces the transient ramp rate of the load allowing for slower activation of sensitive electrical loads. The turn-off of the MOSFET is not affected by the RC delay network as the pull-down for the MOSFET gate is directly from the TGDN pin. Note that the voltage rating on capacitor CG needs to be the same or higher than the external MOSFET and CLOAD. Adding CG to the gate of the external MOSFET can cause high frequency oscillation. A low power, low ohmic value resistor (10) should be placed in series with CG to dampen the oscillations as shown in Figure12 whenever CG is used in an application. Alternatively, the low ohmic value resistor can be placed in series with the gate of the external MOSFET. LTC7003 SNS- External conduction losses are minimized when using low RDS(ON) MOSFETs. Since many high voltage MOSFETs have higher threshold voltages (typical VTH5V) and RDS(ON) is directly related to the (VGS-VTH) of the MOSFET, the LTC7003 maximum gate drive of greater than 10V makes it an ideal solution to minimize external conduction losses associated with external high voltage MOSFETs. SOA is specified in Typical Characteristic curves in power N-channel MOSFET data sheets. The SOA curves show the relationship between the voltages and current allowed in a timed operation of a power MOSFET without causing 18 VIN SNS+ TGUP TGDN BST TS 7003 F12 RSNS RFLT RG 100k CB 1F 10 CG 0.047F CLOAD 100F LOAD Figure12. Powering Large Capacitive Loads Rev. B For more information www.analog.com LTC7003 APPLICATIONS INFORMATION The values for RG and CG to limit the inrush current can be calculated from the below equation: IIN_RUSH 0.7 * 12V * CLOAD RG * CG For the values shown in Figure12 the inrush current will be: IIN_RUSH 0.7 * 12V * 100F 180mA 100k * 0.047F Reverse Current Protection To protect the load from discharging back into VIN when the external MOSFET is off and the VIN voltage drops below the load voltage, two external N-channel MOSFETs should be used and must be configured in a back-to-back arrangement as shown in Figure 14. Dual N-channel packages such as the following devices are good choices for space saving designs: * FDS3890, Fairchild/ON Semiconductor Correspondingly, the ramp rate at the load for the circuit in Figure12 is approximately: VLOAD 0.7 * 12V 2V/ ms T R * C G G * IRF7380PbF, Infineon/IR * SQJB80EP, Vishay/Siliconix LTC7003 When CG is added to the circuit in Figure12, the value of the bootstrap capacitor, CB, must be increased to be able to supply the charge to both to MOSFET gate and capacitor CG. The relationship for CB that needs to be maintained when CG is used is given by: CB > MOSFET QG + 10 * CG 1V VIN SNS+ RSNS RFLT TGUP M1A TGDN L1 TS 7003 F13 TGUP RFLT RSNS M1A TGDN INP TS 7003 F14 M1B Figure14. Protecting Load from Voltage Drops on VIN When turning off a power MOSFET that is connected to an inductive load (inductor, long wire or complex load), the TS pin can be pulled below ground until the current in the inductive load has completely discharged. The TS pin is tolerant of voltages down to -6V, however, an optional Schottky diode with a voltage rating at least as high as the load voltage should be connected between TS and ground to prevent discharging the load through the TS pin of the LTC7003. See Figure13. SNS- SNS- LOAD Optional Schottky Diode Usage on TS LTC7003 VIN SNS+ LOAD D2 Figure13. Optional Schottky Diode Usage Design Example As a design example, consider a fast power supply switch with the following specifications: VIN=VLOAD=4V to 60V, ILOAD=3A, Insertion Loss < 0.5W at room temp with maximum load, output rise time with a 1F load is 1V/s (1A inrush current) and a shorted load should immediately turn off the MOSFET. The first item to select is the N-channel MOSFET. The Si7812DN is selected because it has sufficient breakdown voltage (BVDSS_MIN=75V), sufficient continuous current rating for a 3A load (ID_MAX=5.7A) and the on-resistance is low enough (RDS(ON)_MAX=46m) to be able to meet the power loss specification. Examining the MOSFET data sheet, the VGS vs RDS(ON) typical performance curve shows a sharp increase in RDS(ON) as the MOSFET VGS gets below 5.0V. Since the default VCC UVLO is 7.0V, the VCCUV pin can be left open. The OVLO pin is connected to ground since there is no specification for Overvoltage Lockout. Rev. B For more information www.analog.com 19 LTC7003 APPLICATIONS INFORMATION The value of the current sense resistor, RSNS is calculated next. With ISET open, the LTC7003 has a fixed current sense threshold, VTH, of 30mV typical and 22mV minimum. To provide a minimum 3A load current, the minimum specified VTH=22mV should be used for the RSNS calculation below: RSNS = 22mV = 7.3m 3A The closest standard value is 7m. The power dissipation of RSNS is 63mW so choose a power rating of greater than 0.25W to provide adequate margin. The next item to check is to make sure the insertion loss specification is satisfied. The insertion loss is given by: PLOSS = ILOAD2 * RDS(ON)(MAX) +RSNS ( ) Which meets the design specification of less than 0.5W. The fast output slew rate specification of 1V/s into a 1F load can be met by placing a resistor, RG, in series with the TGUP pin to the MOSFET gate, as well as connecting TGDN and a capacitor, CG, to ground on the MOSFET gate. The values of RG and TG can be calculated from the following expression: RG * CG 0.7 * 12V = 8.4s 1V / s CG needs to have a voltage rating as high as the BVDSS of the MOSFET. A good choice for CG is the AVX 06031C471KAT2A which has a value of 470pF and a voltage rating of 100V. RG is then calculated to be 17.8k. VIN 4V TO 60V 100nF will be used. To meet the short-circuit specification, the TIMER pin should be connected to VCC to enable immediate turn-off (approximately 70ns) of the MOSFET in the case of an overcurrent condition. If an overcurrent condition turns off the MOSFET, it will not turn back on until the INP pin has cycled low then back high. The complete circuit is shown in Figure15. 1. Solder the exposed pad on the backside of the LTC7003 packages directly to the ground plane of the board. 2. Kelvin connect the SNS+ pin to the current sense resistor. 3. Limit the resistance of the TS trace, by making it short and wide. 4.CB needs to be close to chip. 5. Always include an option in the PC board layout to place a resistor in series with the gate of any external MOSFET. High frequency oscillations are design dependent and having the option to add a series dampening resistor can save a design iteration of the PC board. Turn-On Transient SNS+ VIN VCC 1F QG 24nC + 10 * CG = + 10 * 470pF 1V 1V 0.33nF CB > PC Board Layout Considerations = 3A 2 * (0.046 + 0.007) = 0.48W The bootstrap capacitor CB can be calculated from the gate charge as specified in the MOSFET data sheet and CG as follows: SNS- TIMER FAULT ISET INP LTC7003 17.8k BST 0.1F GND VINP 5V/DIV VIN = 60V Si7812DN VLOAD 30V/DIV 10 IMON VCCUV OVLO TGUP TGDN 0.007 100 470pF 100V TS LOAD 4V TO 60V 1F 3A CONTINUOUS MODE 7003 F15 IDMOSFET 1A/DIV 50s/DIV 7003 F15b Figure15. Design Example 20 Rev. B For more information www.analog.com LTC7003 TYPICAL APPLICATIONS Source Side Current Sense VIN 3.5V to 60V VIN RUN OFF ON TGUP TGDN INP ISET IMON BST 100k SNS- VCC 0.1F 1nF 100 0.02 10nF 1F TIMER VCCUV OVLO NOTE: WITH THE SENSE RESISTOR ON THE SOURCE SIDE OF THE EXTERNAL MOSFET, THE LOAD NEEDS TO RISE HIGHER THAN 3.5V WITHIN 140SEC OF INP GOING HIGH OR A FAULT WILL BE INDICATED AND THE LTC7003 WILL RETRY. SNS+ FAULT 1F TS LTC7003 SI7852ADP GND LOAD 3.5V to 60V 1A CONTINOUS MAX 7003 TA02 Protected Redundant Supply Switchover with Shoot Through Protection 0.002 MAIN POWER 7V TO 60V 2x BSC057N08NS3G 2x BSC057N08NS3G LOAD 0.0015 10F 10F 100 100 10 100 SNS+ VIN RUN SNS- TGDN TGUP TS 100 LTC7003 FAULT 100k 1F GND NOTE: THE BACKUP PATH WILL LATCH-OFF WITH AN OVERCURRENT FAULT. LTC7003 1F VCC TIMER OVLO SNS+ VIN RUN BST INP 6.98k 0.1F TGDN SNS- 0.1F BST 200k 4.99k TGUP TS 0.1F FAULT VCCUV IMON ISET 10 0.1F 1nF 0.1F VBACKUP 10F 7V TO 60V VCC INP TIMER OVLO 1nF GND VCCUV IMON ISET 7003 TA03 VLOAD vs Main Power Voltage 70 VMAIN Falling Through 33V VBACKUP = 60V VTG-TS MAIN 10V/DIV VLOAD (V) 60 VMAIN Rising Through 36V RLOAD = 50 VTG-TS MAIN 10V/DIV VTG-TS BACKUP 10V/DIV VTG-TS BACKUP 10V/DIV VLOAD 20V/DIV VLOAD 20V/DIV RLOAD = 50 50 40 40s/DIV 30 0 10 20 30 40 50 MAIN POWER (V) 60 7003 TA03c 10s/DIV 7003 TA03d 70 7003 TA03b Rev. B For more information www.analog.com 21 LTC7003 TYPICAL APPLICATIONS High Side Switch with Input Overvoltage and Overcurrent Protection VIN 3.5V TO 48V (60V TOLERANT) SNS+ VIN RUN OVLO 464k 12.1k 1F FAULT 100k 1nF LTC7003 VCC OFF ON INP BSC047N08NS3 0.1F TS TIMER GND 0.005 100 SNS- TGUP TGDN BST ISET IMON VCCUV LOAD 3.5V TO 48V 10A CONTINUOUS MAX 150k 7003 TA04a High Side Switch with Overcurrent Protection and Fault Latchoff VIN 3.5V TO 60V 100k 1F RTIMER 10nF SNS+ VIN RUN VCC FAULT TIMER LTC7003 SNS- TGUP TGDN 100 BSC047N08NS3 BST 0.1F ISET IMON OFF ON 0.04 INP GND TS OVLO VCCUV LOAD 3.5V TO 60V 0.5A CONTINUOUS 7003 TA05a RTIMER = OPEN 12/100ms LOAD PULSE RLOAD 10k/DIV RLOAD 10k/DIV VLOAD 10V/DIV VLOAD 10V/DIV ILOAD 1A/DIV ILOAD 1A/DIV VTIMER 1A/DIV VTIMER 1V/DIV 100ms/DIV VIN = 12V VINP = 4V 22 RTIMER = 100k 12/100mS LOAD PULSE 7003 TA05b 100ms/DIV 7003 TA05c VIN = 12V VINP = 4V Rev. B For more information www.analog.com LTC7003 TYPICAL APPLICATIONS Average Current Trip VIN 3.5V TO 60V 3.3V VINP D Q Response to 1.2A Load Step SNS+ VIN RUN INP RB LTC7003 FAULT 0.06 249 SNS- TGUP TGDN ILOAD 1A/DIV VIMON 1V/DIV SI7852ADP BST 100k 0.1F VCC VCCUV TIMER OVLO 1F TS IMON ISET GND VIN = 12V VAMPOUT 2V/DIV LOAD 3.5V TO 60V <1A AVERAGE VLOAD 10V/DIV 250ms/DIV 150k 7003 TA06b 500k AMPOUT 3.3V 8 5 1 LTC1541 + - + - 7 1F + - 2 400k 3 0.1F 6 1.2V 7003 TA06a 4 High Side Switch with Auto-Retry, Inrush Control and OVLO VIN 7V TO 30V (60V TOLERANT) 47F + 1F 294k 1F 100k RUN VIN SNS+ VCC SNS- VCCUV TGUP TGDN FAULT LTC7003 OVLO OFF ON 12.1k BST INP 0.003 100 220k 10 GND VINP 5V/DIV VLOAD 10V/DIV 4.7F IMON ISET BAS30 VIN = 24V IPB020N10N5 0.47F TS TIMER 100nF Turn-On Response LOAD 15mF 7V TO 30V ILOAD 1A/DIV 100ms/DIV 7003 TA07b 7003 TA07 Rev. B For more information www.analog.com 23 LTC7003 PACKAGE DESCRIPTION MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 0.102 (.112 .004) 5.10 (.201) MIN 2.845 0.102 (.112 .004) 0.889 0.127 (.035 .005) 8 1 1.651 0.102 (.065 .004) 1.651 0.102 3.20 - 3.45 (.065 .004) (.126 - .136) 0.305 0.038 (.0120 .0015) TYP 16 0.50 (.0197) BSC 4.039 0.102 (.159 .004) (NOTE 3) RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 0.12 REF DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE 0.280 0.076 (.011 .003) REF 16151413121110 9 DETAIL "A" 0 - 6 TYP 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 -0.27 (.007 - .011) TYP 1234567 8 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 24 0.86 (.034) REF 0.1016 0.0508 (.004 .002) MSOP (MSE16) 0213 REV F Rev. B For more information www.analog.com LTC7003 REVISION HISTORY REV DATE DESCRIPTION A 09/18 Added 100 resistor to Typical Application. 1 Added Total Supply Current with Charge Pump Regulating section to Electrical Characteristics table. 4 Removed the temperature dot from the TIMER Pin Pull-Down Current specification. 5 Updated SNS+ and SNS- in Pin Functions. 9 Added RFLT. B 09/20 PAGE NUMBER 18, 19, 20, 21, 22, 23, 26 Change parameter INP = 3V (DC) to VINP = 3.5V (DC). Change condition VIN = VTS = 60V, IBST = 0A to VTS = 60V, IBST = 0A. 4 Add mV in units columns where indicated (two places). 5 Update title to graph 7003 G01. 6 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 25 LTC7003 TYPICAL APPLICATION VIN 40V TO 60V 590k Protected Motor Driver SNS+ VIN RUN 6.04k OVLO 12.1k 1nF LTC7003 SNS- TGUP TGDN TIMER 100k 86.6k 0.004 BSC076N06NS3 LOAD 40V TO 60V 8A CONTINUOUS MAX TS ISET 0.1F BST VCCUV BAS116L PWM -20kHz INP IMON 100 VS-12CWQ06FN VCC 100k GND FAULT M 48V, 500W MOTOR 1F 7003 TA08 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC7000/LTC7000-1 Fast 150V Protected High Side NMOS Static Switch Driver LTC7001 Fast 150V High Side NMOS Static Switch Driver LTC7004 Fast 60V High Side NMOS Static Switch Driver LTC4440/LTC4440-5/ High Speed, High Voltage High Side Gate Driver LTC4440A-5 LTC7138 High Efficiency, 150V 250mA/400mA Synchronous Step-Down Regulator LTC7103 105V, 2.3A Low EMI Synchronous Step-Down Regulator LTC7801 150V Low IQ, Synchronous Step-Down DC/DC Controller LT1910 Protected High Side MOSFET Driver LTC1255 Dual 24V High Side MOSFET Driver LTC4367 LTC4364 100V Overvoltage, Undervoltage and Reverse Supply Protection Controller 100V Overvoltage, Undervoltage and Reverse Supply Protection Controller with Bidirectional Circuit Breaker Surge Stopper with Ideal Diode LTC7860 LTC4231 High Efficiency Switching Surge Stopper Micropower Hot Swap Controller LTC3895 150V Low IQ, Synchronous Step-Down DC/DC Controller Low Quiescent Current Surge Stopper LTC4368 LTC4380 LTC3639 26 High Efficiency, 150V 100mA Synchronous Step-Down Regulator 3.5V to 150V Operation, Short Circuit Protected, Delta VSNS = 30mV, IQ = 35A, Turn-On (CL = 1 nF) = 35ns, Internal Charge Pump 3.5V to 150V Operation, IQ=35A, Turn-On (CL=1nF)=35ns, Internal ChargePump 3.5V to 60V Operation, IQ = 27A, Turn-On (CL =1 nF) = 35ns, Internal Charge Pump Up to 100V Supply Voltage, 8V VCC 15V, 2.4A Peak Pull-Up/1.5 Peak Pull-Down Integrated Power MOSFETs, 4V VIN 150V, 0.8V VOUT VIN, IQ=12A, MSOP-16 (12) 4.4V VIN 105V, 1V VOUT VIN, IQ=2A Fixed Frequency 200kHz to 2MHz, 5mm x 6mm QFN 4V VIN 140V, 150V abs max, 0.8V VOUT 60V, IQ=40A ,PLL Fixed Frequency 320kHz to 2.25MHz 8V to 48V Operation, VSNS=65mV, IQ=110A, Turn-On (CL=1nF)=220s, Internal Charge Pump 9V to 24V Operation, VSNS=100mV, IQ=600A, Turn-On (CL=1nF)=100s, Internal Charge Pump Wide Operating Range: 2.5V to 60V, Protection Range: -40V to 100V, No TVS Required for Most Applications Wide Operating Range: 2.5V to 60V, Protection Range: -40V to 100V, No TVS Required for Most Applications 4V to 80V Operation, VSNS=50mV, IQ=425A, Turn-On (CL=1nF)=500s, Internal Charge Pump 4V to 60V Operation, VSNS=95mV, IQ=370A, PMOS Driver 2.7V to 36V Operation, VSNS=50mV, IQ=4A, Turn-On (CL=1nF)=1ms, Internal Charge Pump PLL Fixed Frequency 50kHz to 900kHz, 4V VIN 140V, 0.8VVOUT60V, IQ=40A 4V to 80V Operation, VSNS=50mV, IQ=8A, Turn-On=5ms, Internal Charge Pump Integrated Power MOSFETs, 4V VIN 150V, 0.8VVOUTVIN, IQ=12A, MSOP-16(12) Rev. B 09/20 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2017-2020