LP2998
December 15, 2009
DDR-I and DDR-II Termination Regulator
General Description
The LP2998 linear regulator is designed to meet JEDEC
SSTL-2 and JEDEC SSTL-18 specifications for termination of
DDR1-SDRAM and DDR-II memory. The device contains a
high-speed operational amplifier to provide excellent re-
sponse to load transients. The output stage prevents shoot
through while delivering 1.5A continuous current as required
for DDR1-SDRAM termination, and 0.5A continuous current
as required for DDR-II termination. The LP2998 also incor-
porates a VSENSE pin to provide superior load regulation and
a VREF output as a reference for the chipset and DIMMs.
An additional feature found on the LP2998 is an active low
shutdown (SD) pin that provides Suspend To RAM (STR)
functionality. When SD is pulled low, the VTT output will tri-
state providing a high impedance output, while VREF remains
active. A power savings advantage can be obtained in this
mode through lower quiescent current.
Features
Source and sink current
Low output voltage offset
No external resistors required
Linear topology
Suspend to Ram (STR) functionality
Low external component count
Thermal Shutdown
Available in SO-8, PSOP-8 packages
Applications
DDR-I and DDR-II Termination Voltage
SSTL-18 Termination
SSTL-2 and SSTL-3 Termination
HSTL Termination
Typical Application Circuit
30026918
© 2009 National Semiconductor Corporation 300269 www.national.com
LP2998 DDR-I and DDR-II Termination Regulator
Connection Diagrams
30026903
Top View
PSOP-8 Layout
30026904
Top View
SO-8 Layout
Pin Descriptions
SO-8 Pin or PSOP-8 Pin Name Function
1 GND Ground.
2 SD Shutdown.
3 VSENSE Feedback pin for regulating VTT.
4 VREF Buffered internal reference voltage of VDDQ /2.
5 VDDQ Input for internal reference equal to VDDQ/2.
6 AVIN Analog input pin.
7 PVIN Power input pin.
8 VTT Output voltage for connection to termination resistors.
EP Exposed pad thermal connection. Connect to soft Ground (PSOP-8 only).
Ordering Information
Order Number Package Type NSC Package Drawing Supplied As
LP2998MA SO-8 M08A 95 Units per Rail
LP2998MAX SO-8 M08A 2500 Units Tape and Reel
LP2998MAE SO-8 M08A 250 Units Tape and Reel
LP2998MR PSOP-8 MRA08A 95 Units per Rail
LP2998MRX PSOP-8 MRA08A 2500 Units Tape and Reel
LP2998MRE PSOP-8 MRA08A 250 Units Tape and Reel
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LP2998
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN, AVIN, VDDQ to GND
No pin should exceed AVIN −0.3V to +6V
Storage Temp. Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature (Soldering, 10 sec) 260°C
SO-8 Thermal Resistance (θJA)151°C/W
PSOP-8 Thermal Resistance (θJA)43°C/W
Minimum ESD Rating (Note 2) 1kV
Operating Range
Junction Temp. Range (Note 3) -40°C to +125°C
AVIN to GND 2.2V to 5.5V
Electrical Characteristics Specifications with standard typeface are for TJ = 25°C and limits in boldface type
apply over the full Operating Temperature Range (TJ = -40°C to +125°C) (Note 4). Unless otherwise specified,
VIN = AVIN = PVIN = 2.5V.
Symbol Parameter Conditions Min Typ Max Units
VREF
VREF Voltage (DDR I) VIN = VDDQ = 2.3V 1.135 1.158 1.185 V
VIN = VDDQ = 2.5V 1.235 1.258 1.285 V
VIN = VDDQ = 2.7V 1.335 1.358 1.385 V
VREF Voltage (DDR II) PVIN = VDDQ = 1.7V 0.837 0.860 0.887 V
PVIN = VDDQ = 1.8V 0.887 0.910 0.937 V
PVIN = VDDQ = 1.9V 0.936 0.959 0.986 V
ZVREF VREF Output Impedance IREF = -30 to +30 µA 2.5 k
VTT
VTT Output Voltage (DDR I) (Note 7)
IOUT = 0A
VIN = VDDQ = 2.3V 1.120 1.159 1.190 V
VIN = VDDQ = 2.5V 1.210 1.259 1.290 V
VIN = VDDQ = 2.7V 1.320 1.359 1.390 V
IOUT = +/- 1.5A
VIN = VDDQ = 2.3V 1.125 1.159 1.190 V
VIN = VDDQ = 2.5V 1.225 1.259 1.290 V
VIN = VDDQ = 2.7V 1.325 1.359 1.390 V
VTT Output Voltage (DDR II) (Note 7)
IOUT = 0A, AVIN = 2.5V
PVIN = VDDQ = 1.7V 0.822 0.856 0.887 V
PVIN = VDDQ = 1.8V 0.874 0.908 0.939 V
PVIN = VDDQ = 1.9V 0.923 0.957 0.988 V
IOUT = +/- 0.5A, AVIN = 2.5V
PVIN = VDDQ = 1.7V 0.820 0.856 0.890 V
PVIN = VDDQ = 1.8V 0.870 0.908 0.940 V
PVIN = VDDQ = 1.9V 0.920 0.957 0.990 V
VOSVtt
VTT Output Voltage Offset (VREF – VTT) for DDR I (Note 7) IOUT = 0A -30 030 mV
IOUT = -1.5A -30 030 mV
IOUT = +1.5A -30 030 mV
VTT Output Voltage Offset (VREF – VTT) for DDR II (Note 7)
IOUT = 0A -30 030 mV
IOUT = -0.5A -30 030 mV
IOUT = +0.5A -30 030 mV
IQQuiescent Current (Note 5) IOUT = 0A 320 500 µA
ZVDDQ VDDQ Input Impedance 100 k
ISD Quiescent current in shutdown (Note 5) SD = 0V 115 150 µA
IQ_SD Shutdown leakage current SD = 0V 2 5µA
VIH Minimum Shutdown High Level 1.9 V
VIL Maximum Shutdown Low Level 0.8 V
Iv VTT leakage current in shutdown SD = 0V
VTT = 1.25V
1 10 µA
ISENSE VSENSE Input current 13 nA
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LP2998
Symbol Parameter Conditions Min Typ Max Units
TSD Thermal Shutdown (Note 6) 165 °C
TSD_HYS Thermal Shutdown Hysteresis 10 °C
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin.
Note 3: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θJA = 151.2° C/W
junction to ambient with no heat sink.
Note 4: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality
Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).
Note 5: Quiescent current is defined as the current flow into AVIN.
Note 6: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA,
and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal
shutdown.
Note 7: VTT load regulation is tested by using a 10 ms current pulse and measuring VTT.
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LP2998
Typical Performance Characteristics Unless otherwise specified VIN = AVIN = PVIN = 2.5V
Iq vs AVIN in SD
30026920
Iq vs AVIN
30026921
VIH and VIL
30026922
VREF vs VDDQ
30026924
VTT vs VDDQ
30026926
ISD vs AVIN over Temperature
30026927
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LP2998
Iq vs AVIN over Temperature
30026928
Maximum Sourcing Current vs AVIN
(VDDQ = 1.8V, PVIN = 1.8V)
30026935
Maximum Sinking Current vs AVIN
(VDDQ = 1.8V)
30026936
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 1.8V)
30026931
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 2.5V)
30026932
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 3.3V)
30026933
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LP2998
Maximum Sinking Current vs AVIN
(VDDQ = 2.5V)
30026934
Maximum Sourcing Current vs AVIN
(VDDQ = 1.8V, PVIN = 3.3V)
30026937
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LP2998
Block Diagram
30026905
Description
The LP2998 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-18. The
output, VTT is capable of sinking and sourcing current while
regulating the output voltage equal to VDDQ / 2. The output
stage has been designed to maintain excellent load regulation
while preventing shoot through. The LP2998 also incorpo-
rates two distinct power rails that separates the analog cir-
cuitry from the power output stage. This allows a split rail
approach to be utilized to decrease internal power dissipation.
It also permits the LP2998 to provide a termination solution
for the next generation of DDR-SDRAM memory (DDRII). The
LP2998 can also be used to provide a termination voltage for
other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termination.
This involves one RS series resistor from the chipset to the
memory and one RT termination resistor. Typical values for
RS and RT are 25 Ohms, although these can be changed to
scale the current requirements from the LP2998. This imple-
mentation can be seen below in .
30026906
FIGURE 1. SSTL-Termination Scheme
Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2998. AVIN
is used to supply all the internal control circuitry. PVIN, how-
ever, is used exclusively to provide the rail voltage for the
output stage used to create VTT. These pins have the capa-
bility to work off separate supplies, under the condition that
AVIN is always greater than or equal to PVIN. For SSTL-18
applications, it is recommended to connect PVIN to the 1.8V
rail used for the memory core and AVIN to a rail within its
operating range of 2.2V to 5.5V (typically a 2.5V supply). PVIN
should always be used with either a 1.8V or 2.5V rail. This
prevents the thermal limit from tripping because of excessive
internal power dissipation. If the junction temperature ex-
ceeds the thermal shutdown threshold, the part will enter a
shutdown state identical to the manual shutdown where VTT
is tri-stated and VREF remains active. A lower rail, such as
1.5V can be used but it will reduce the maximum output cur-
rent. Therefore it is not recommended for most termination
schemes.
VDDQ
VDDQ is the input used to create the internal reference volt-
age for regulating VTT. The reference voltage is generated
from a resistor divider of two internal 50k resistors. This
guarantees that VTT will precisely track VDDQ / 2. The optimal
implementation of VDDQ is as a remote sense. This can be
achieved by connecting VDDQ directly to the 1.8V rail at the
DIMM instead of PVIN. This ensures that the reference volt-
age precisely tracks the DDR memory rails without a large
voltage drop from the power lines. For SSTL-18 applications,
VDDQ will be a 1.8V signal, which will create a 0.9V termina-
tion voltage at VTT (See Electrical Characteristics Table for
exact values of VTT over temperature).
VSENSE
The purpose of the sense pin is to provide improved remote
load regulation. In most motherboard applications, the termi-
nation resistors will connect to VTT in a long plane. If the output
voltage was regulated only at the output of the LP2998, then
the long trace will cause a significant IR drop resulting in a
termination voltage lower at one end of the bus than the other.
The VSENSE pin can be used to improve this performance by
connecting it to the middle of the bus. This will provide a better
distribution across the entire termination bus. If remote load
regulation is not used, then the VSENSE pin must still be con-
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LP2998
nected to VTT. Care should be taken when a long VSENSE trace
is implemented in close proximity to the memory. Noise pick-
up in the VSENSE trace can cause problems with precise
regulation of VTT. A small 0.1uF ceramic capacitor placed next
to the VSENSE pin can help filter any high frequency signals
and prevent errors.
SHUTDOWN
The LP2998 contains an active low shutdown pin that can be
used for suspend to RAM functionality. In this condition, the
VTT output will tri-state while the VREF output remains active
providing a constant reference signal for the memory and
chipset. During shutdown, VTT should not be exposed to volt-
ages that exceed PVIN. With the shutdown pin asserted low
the quiescent current of the LP2998 will drop. However, VD-
DQ will always maintain its constant impedance of 100k for
generating the internal reference. Therefore, to calculate the
total power loss in shutdown, both currents need to be con-
sidered. For more information refer to the Thermal Dissipation
section. The shutdown pin also has an internal pull-up current.
Therefore, to turn the part on, the shutdown pin can either be
connected to AVIN or left open.
VREF
VREF provides the buffered output of the internal reference
voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory.
Since the inputs typically have an extremely high impedance,
there should be little current drawn from VREF. For improved
performance, an output bypass capacitor can be placed,
close to the pin, to help with noise. A ceramic capacitor in the
range of 0.1 µF to 0.01 µF is recommended. This output re-
mains active during the shutdown state and thermal shutdown
events for the suspend to RAM functionality.
VTT
VTT is the regulated output that is used to terminate the bus
resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ / 2. The LP2998 is
designed to handle continuous currents of up to +/- 1.5A with
excellent load regulation. If a transient is expected to last
above the maximum continuous current rating for a significant
amount of time, then the bulk output capacitor should be sized
large enough to prevent an excessive voltage drop. If the
LP2998 is to operate in elevated temperatures for long dura-
tions, care should be taken to ensure that the maximum
operating junction temperature is not exceeded. Proper ther-
mal de-rating should always be used (Please refer to the
Thermal Dissipation section). If the junction temperature ex-
ceeds the thermal shutdown threshold, VTT will tri-state until
the part returns below the temperature hysteresis trip-point.
Component Selections
INPUT CAPACITOR
The LP2998 does not require a capacitor for input stability,
but it is recommended for improved performance during large
load transients to prevent the input rail from dropping. The
input capacitor should be located as close as possible to the
PVIN pin. Several recommendations exist and is dependent
on the application required. A typical value recommended for
AL electrolytic capacitors is 22 µF. Ceramic capacitors can
also be used. A value in the range of 10 µF with X5R or better
would be an ideal choice. The input capacitance can be re-
duced if the LP2998 is placed close to the bulk capacitance
from the output of the 1.8V DC-DC converter. For the AVIN
pin, a small 0.1uF ceramic capacitor is sufficient to prevent
excessive noise from coupling into the device.
OUTPUT CAPACITOR
The LP2998 has been designed to be insensitive of output
capacitor size or ESR (Equivalent Series Resistance). This
allows the flexibility to use any capacitor desired. The choice
for output capacitor will be determined solely on the applica-
tion and the requirements for load transient response of VTT.
As a general recommendation the output capacitor should be
sized above 100 µF with a low ESR for SSTL applications with
DDR-SDRAM. The value of ESR should be determined by the
maximum current spikes expected and the extent at which the
output voltage is allowed to droop. Several capacitor options
are available on the market and a few of these are highlighted
below:
AL - It should be noted that many aluminum electrolytics only
specify impedance at a frequency of 120 Hz, which indicates
they have poor high frequency performance. Only aluminum
electrolytics that have an impedance specified at a higher fre-
quency (100 kHz) should be used for the LP2998. To improve
the ESR several AL electrolytics can be combined in parallel
for an overall reduction. An important note to be aware of is
the extent at which the ESR will change over temperature.
Aluminum electrolytic capacitors tend to have rapidly increas-
ing ESR at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capaci-
tance, in the range of 10 to 100 µF. They also have excellent
AC performance for bypassing noise because of very low
ESR (typically less than 10 m). However, some dielectric
types do not have good capacitance characteristics as a func-
tion of voltage and temperature. Because of the typically low
value of capacitance, it is recommended to use ceramic ca-
pacitors in parallel with another capacitor such as an alu-
minum electrolytic. A dielectric of X5R or better is recom-
mended for all ceramic capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP
are available from several manufacturers. These offer a large
capacitance while maintaining a low ESR. These are the best
solution when size and performance are critical, although
their cost is typically higher than any other capacitor type.
Thermal Dissipation
Since the LP2998 is a linear regulator, any current flow from
VTT will result in internal power dissipation and heat genera-
tion. To prevent damaging the part by exceeding the maxi-
mum allowable operating junction temperature, care should
be taken to derate the part based on the maximum expected
ambient temperature and power dissipation. The maximum
allowable internal temperature rise (TRmax) can be calculated
given the maximum ambient temperature (TAmax) of the ap-
plication and the maximum allowable junction temperature
(TJmax).
TRmax = TJmax − TAmax
From this equation, the maximum power dissipation (PDmax)
of the part can be calculated:
PDmax = TRmax / θJA
The θJA of the LP2998 will depend on several variables: the
package used; the thickness of copper; the number of vias
and the airflow. For instance, the θJA of the SO-8 is 163°C/W
with the package mounted to a standard 8x4 2-layer board
with 1oz. copper, no airflow, and 0.5W dissipation at room
temperature. This value can be reduced to 151.2°C/W by
changing to a 3x4 board with 2 oz. copper that is the JEDEC
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LP2998
standard. Figure 2 shows how the θJA varies with airflow for
the two boards mentioned.
30026907
FIGURE 2. θJA vs Airflow (SO-8)
Additional improvements can be made by the judicious use of
vias to connect the part and dissipate heat to an internal
ground plane. Using larger traces and more copper on the top
side of the board can also help. With careful layout, it is pos-
sible to reduce the θJA further than the nominal values shown
in Figure 2
Optimizing the θJA and placing the LP2998 in a section of a
board exposed to lower ambient temperature allows the part
to operate with higher power dissipation. The internal power
dissipation can be calculated by summing the three main
sources of loss: output current at VTT, either sinking or sourc-
ing, and quiescent currents at AVIN and VDDQ. During the
active state (when shutdown is not held low) the total internal
power dissipation can be calculated from the following equa-
tions:
PD = PAVIN + PVDDQ + PVTT
Where,
PAVIN = IAVIN * VAVIN
PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
To calculate the maximum power dissipation at VTT, both the
sinking and sourcing current conditions need to be examined.
Although only one equation will add into the total, VTT cannot
source and sink current simultaneously.
PVTT = VVTT x ILOAD (Sinking) or
PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing)
The power dissipation of the LP2998 can also be calculated
during the shutdown state. During this condition the output
VTT will tri-state. Therefore, that term in the power equation
will disappear as it cannot sink or source any current (leakage
is negligible). The only losses during shutdown will be the re-
duced quiescent current at AVIN and the constant impedance
that is seen at the VDDQ pin.
PD = PAVIN + PVDDQ
PAVIN = IAVIN x VAVIN
PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
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LP2998
Typical Application Circuits
Several different application circuits have been shown in Fig-
ure 3 through Figure 12 to illustrate some of the options that
are possible in configuring the LP2998. Graphs of the indi-
vidual circuit performance can be found in the Typical Perfor-
mance Characteristics section of the datasheet. These
curves illustrate how the maximum output current is affected
by changes in AVIN and PVIN.
SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL-2
termination scheme it is recommended to connect all the input
rails to the 2.5V rail. This provides an optimal trade-off be-
tween power dissipation and component count and selection.
An example of this circuit can be seen in Figure 3.
30026910
FIGURE 3. Recommended SSTL-2 Implementation
If power dissipation or efficiency is a major concern then the
LP2998 has the ability to operate on split power rails (see
Figure 4). The output stage (PVIN) can be operated on a lower
rail such as 1.8V and the analog circuitry (AVIN) can be con-
nected to a higher rail such as 2.5V, 3.3V or 5V. This allows
the internal power dissipation to be lowered when sourcing
current from VTT. The disadvantage of this circuit is that the
maximum continuous current is reduced because of the lower
rail voltage, although it is adequate for all motherboard
SSTL-2 applications. Increasing the output capacitance can
also help if periods of large load transients will be encoun-
tered.
30026911
FIGURE 4. Lower Power Dissipation SSTL-2 Implementation
The third option for SSTL-2 applications in the situation that
a 1.8V rail is not available and it is not desirable to use 2.5V,
is to connect the LP2998 power rail to 3.3V (see Figure 5). In
this situation AVIN will be limited to operation on the 3.3V or
5V rail as PVIN can never exceed AVIN. This configuration
has the ability to provide the maximum continuous output cur-
rent at the downside of higher thermal dissipation. Care
should be taken to prevent the LP2998 from experiencing
large current levels which cause the device to exceed the
maximum operating junction temperature. Because of this
risk it is not recommended to supply the output stage with a
voltage higher than a nominal 3.3V rail.
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LP2998
30026912
FIGURE 5. SSTL-2 Implementation With Higher Voltage Rails
DDR-II APPLICATIONS
With the separate VDDQ pin and an internal resistor divider
it is possible to use the LP2998 in applications utilizing DDR-
II memory. Figure 6 and Figure 7 show several implementa-
tions of recommended circuits with output curves displayed
in the Typical Performance Characteristics. Figure 6 shows
the recommended circuit configuration for DDR-II applica-
tions. The output stage is connected to the 1.8V rail and the
AVIN pin can be connected to either a 2.5, 3.3V or 5.5V rail.
30026913
FIGURE 6. Recommended DDR-II Termination
If it is not desirable to use the 1.8V rail it is possible to connect
the output stage to a 3.3V rail. Care should be taken to not
exceed the maximum operating junction temperature as the
thermal dissipation increases with lower VTT output voltages.
For this reason it is not recommended to power PVIN with a
rail higher than the nominal 3.3V. The advantage of this con-
figuration is that it has the ability to source and sink a higher
maximum continuous current.
30026914
FIGURE 7. DDR-II Termination With Higher Voltage Rails
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LP2998
LEVEL SHIFTING
If standards other than SSTL-2 are required, such as SSTL-3,
it may be necessary to use a different scaling factor than 0.5
times VDDQ for regulating the output voltage. Several options
are available to scale the output to any voltage required. One
method is to level shift the output by using feedback resistors
from VTT to the VSENSE pin. This has been illustrated in Figure
8 and Figure 9. Figure 8 shows how to use two resistors to
level shift VTT above the internal reference voltage of VDDQ/
2. To calculate the exact voltage at VTT the following equation
can be used.
VTT = VDDQ/2 (1 + R1/R2)
30026915
FIGURE 8. Increasing VTT by Level Shifting
Conversely, the R2 resistor can be placed between VSENSE
and VDDQ to shift the VTT output lower than the internal refer-
ence voltage of VDDQ/2. The equation relating to VTT and
the resistors can be used as shown:
VTT = VDDQ/2 (1 - R1/R2)
30026916
FIGURE 9. Decreasing VTT by Level Shifting
HSTL APPLICATIONS
The LP2998 can be easily adapted for HSTL applications by
connecting VDDQ to the 1.5V rail. This will produce a VTT and
VREF voltage of approximately 0.75V for the termination re-
sistors. AVIN and PVIN should be connected to a 2.5V rail for
optimal performance.
30026917
FIGURE 10. HSTL Application
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LP2998
QDR APPLICATIONS
Quad data rate (QDR) applications utilize multiple channels
for improved memory performance. However, this increase in
bus lines increases the current levels required for termination.
The recommended approach in terminating multiple channels
is to use a dedicated LP2998 for each channel. This simplifies
layout and reduces the internal power dissipation for each
regulator. Separate VREF signals can be used for each DIMM
bank from the corresponding regulator with the chipset refer-
ence provided by a local resistor divider or one of the LP2998
signals. Because VREF and VTT are expected to track and the
part to part variations are minor, there should be little differ-
ence between the reference signals of each LP2998.
OUTPUT CAPACITOR SELECTION
For applications utilizing the LP2998 to terminate SSTL-2 I/O
signals the typical application circuit shown in Figure 11 can
be implemented.
30026918
FIGURE 11. Typical SSTL-2 Application Circuit
This circuit permits termination in a minimum amount of board
space and component count. Capacitor selection can be var-
ied depending on the number of lines terminated and the
maximum load transient. However, with motherboards and
other applications where VTT is distributed across a long
plane, it is recommended to use multiple bulk capacitors in
addition to high frequency decoupling. Figure 12 depicts an
example circuit where 2 bulk output capacitors could be situ-
ated at both ends of the VTT plane for optimal placement.
Large aluminum electrolytic capacitors are typically used for
their low ESR and low cost.
30026919
FIGURE 12. Typical SSTL-2 Application Circuit for Motherboards
In most PC applications, an extensive amount of decoupling
is required because of the long interconnects encountered
with the DDR-SDRAM DIMMs mounted on modules. As a re-
sult, bulk aluminum electrolytic capacitors in the range of
1000uF are typically used.
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LP2998
PCB Layout Considerations
1. The input capacitor for the power rail should be placed
as close as possible to the PVIN pin.
2. VSENSE should be connected to the VTT termination bus
at the point where regulation is required. For
motherboard applications an ideal location would be at
the center of the termination bus.
3. VDDQ can be connected remotely to the VDDQ rail input at
either the DIMM or the Chipset. This provides the most
accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side
copper should be used to dissipate heat from the
package. Numerous vias from the ground connection to
the internal ground plane will help. Additionally these can
be located underneath the package if manufacturing
standards permit.
5. Care should be taken when routing the VSENSE trace to
avoid noise pickup from switching I/O signals. A 0.1uF
ceramic capacitor located close to the SENSE can also be
used to filter any unwanted high frequency signal. This
can be an issue especially if long SENSE traces are used.
6. VREF should be bypassed with a 0.01 µF or 0.1 µF
ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the
VREF pin.
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LP2998
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Small Outline Package (M8)
NS Package Number M08A
8-Lead PSOP Package (PSOP-8)
NS Package Number MRA08A
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LP2998
Notes
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LP2998
Notes
LP2998 DDR-I and DDR-II Termination Regulator
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