©2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1
RFD16N05, RFD16N05SM
16A, 50V, 0.047 Ohm, N-Channel Power
MOSFETs
The RFD16N05 and RFD16N05SM N-channel power
MOSFETs are manufactured using the MegaFET process.
This pro cess , wh ich us es feature siz es a pproac hing t hose o f
LSI integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. Th ey were designed
for use in applications such as switching regulators,
s wit ching c on v erters, moto r driv ers , and relay drivers . These
transistors can be operated directly from integrated circuits.
Formerly developmental type TA09771.
Features
• 16A, 50V
•r
DS(ON) = 0.047Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
•175
oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-251AA JEDEC TO-252AA
Ordering Information
PART NUMBER PACKAGE BRAND
RFD16N05 TO-251AA D16N05
RFD16N05SM TO-252AA D16N05
NOTE: When ordering, use the entire part number . Add the suf fix 9A to
obtain the TO-25 2AA variant in th e tape and reel, i .e., RFD16N 05SM9A. G
D
S
SOURCE
DRAIN (FLANGE) GATE
DRAIN GATE
SOURCE
DRAIN (FLANGE)
Data Sheet November 2003
©2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD16N05, RFD16N05SM, UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 50 V
Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 50 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pul s e d D rai n C u r re n t (No te 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 16
Refer to Peak Current Curve A
Gate to Sou rc e Volta g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V GS ±20 V
Pulsed Aval a nche Ra tin g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Refer to Figure 5
Power Dis sipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate abov e 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
0.48 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
P ackage Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: St resses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 50 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA2-4V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 1 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V,
TC = 150oC--25µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 16A, VGS = 10V (Figure 9) - - 0.047 Ω
Turn-On Time t(ON) VDD = 25V, ID = 8A, RL = 3.125Ω,
VGS = 10V, RGS = 25Ω
(Figure 13)
- - 65 ns
Turn-On Delay Time td(ON) -14- ns
Rise Time tr-30- ns
Turn-Off Delay Time td(OFF) -55- ns
Fall Ti me tf-30- ns
Turn-Off Time t(OFF) - - 125 ns
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 40V, ID ≈ 16A,
RL = 2.5Ω
Ig(REF) = 0.8mA
(Figure 13)
- - 80 nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - - 45 nC
Threshold Gate Charge Q(TH) VGS = 0V to 2V - - 2.2 nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12) - 900 - pF
Output Capacitance COSS - 325 - pF
Reverse Transfer Capacitance CRSS - 100 - pF
Thermal Resistance Junction to Case RθJC - - 2.083 oC/W
Thermal Resistance Junction to Ambient RθJA TO-251 and TO-252 - - 100 oC/W
Sour ce to Drain Diode Specificatio ns
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 16A - - 1.5 V
Diode Reverse Recovery Time trr ISD = 16A, dISD/dt = 100A/µs - - 125 ns
NOTES:
2. Pulse test: pulse width ≤ 250µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
RFD16N05, RFD16N05SM
©2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE
TENPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRE NT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
8
4
025 50 75 100 125 150
12
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
16
175
20
t, RECTANGULAR PULSE DURATION (s)
10-3 10-2 10-1 100
0.01
0.1
1
10-5 101
10-4
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
PDM
t1t2
0.01
0.02
0.05
0.1
0.2
0.5
SINGLE PULSE
VDS, DRAIN TO SOURCE VOLTAGE (V)
10 100
1
100
10
1
ID, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
100µs
10ms
1ms
DC
100ms
VDSS(MAX) = 50V
TC = 25oC
SINGLE PULSE
TJ = MAX RATED
t, PULSE WIDTH (s)
10
10-5 10-4 10-3 10-2 10-1 100101
100
IDM, PEAK CURRENT (A)
200
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 20V
VGS = 10V
TC = 25oC
RFD16N05, RFD16N05SM
©2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPE RATURE
FIGURE 10. NO RMALIZED GATE THRESHOLD V OLTAGE vs
JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
0.1 110
10
0.01
100
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AV ALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
0
10
20
01234
30
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 4.5V
VGS = 5V
VGS = 7V
40
50
VGS = 8V
VGS = 10V
VGS = 20V
VGS = 6V
PULSE DURATION = 80µs
TC = 25oC
DUTY CYCLE = 0.5% MAX
0468102
0
10
20
30
IDS(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
40
50
175oC
-55oC
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
0
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
200
2.5 PULSE DURATION = 80µs
VGS = 10V, ID = 16A
ON RESISTANCE
DUTY CYCLE = 0.5% MAX
-80 -40 0 40 80 120 160
0
0.5
1.0
2.0
NORMALIZED GATE
THRESHOLD VO LTAGE
TJ, JUNCTION TEMPERAT URE (oC) 200
1.5
VGS = VDS, ID = 250µA2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
200
ID = 250µA
RFD16N05, RFD16N05SM
©2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZE D SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY W AVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
1600
1200
400
00 5 10 15 20 25
C, CAPACITANCE (pF)
800
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
CRSS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
25
12.5
0
20IGREF()
IGACT()
-------------------------t, TIME (ms) 80IGREF()
IGACT()
----------------------
10
5
2.5
0
VDS, DRAIN TO SOURCE V O LTAGE (V)
VGS, GATE TO SOURCE VO LTAGE (V)
50
7.5
37.5
VDD = BVDSS
VDD = BVDSS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
RL = 3.125Ω
IG(REF) = 0.8mA
VGS = 10V
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RFD16N05, RFD16N05SM
©2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
IG(REF)
0
0
RFD16N05, RFD16N05SM
©2003 Fairchild Semiconductor Corporation RFD16N05, RFD16N05SM Rev. B1
PSPICE Electrical Model
.SUBCKT RFD16N05 2 1 3 ; rev 10/31/94
CA 12 8 1.788e-10
CB 15 14 1.875e-10
CIN 6 8 8.33e-10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 64.89
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.56e-9
LSOURCE 3 7 4.13e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 0.4e-3
RGATE 9 20 3.0
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 21.5e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.82
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/94,7))}
.MODEL DBDMOD D (IS = 2.5e-13 RS = 7.1e-3 TRS1 = 3.04e-3 TRS2 = -10e-6 CJO = 1.12e-9 TT = 5.6e-8)
.MODEL DBKMOD D (RS = 2.51e-1 TRS1 = -6.57e-4 TRS2 = 1.66e-6)
.MODEL DPLCAPMOD D (CJO = 6.1e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (V TO = 3.96 KP = 16.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -7.19e-7)
.MODEL RDSMOD RES (T C1 = 5.45e-3 TC2 = 1.66e-5)
.MODEL RSCLMOD RES (T C1 = 1.25e-3 TC2 = 17e-6)
.MODEL RVTOMOD RES (TC1 = -5.15e-3 TC2 = -4.83e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.25 V OFF= -3.25)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.25 V OFF= -5.25)
.MODEL S2AMOD VS WITCH (RO N = 1e-5 ROFF = 0.1 VON = 0.56 VOFF= 5.56)
.MODEL S2BMOD VS WITCH (RO N = 1e-5 ROFF = 0.1 VON = 5.56 VOFF= 0.56)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPI CE Sub-Circuit for the Power MOSFET Feat uring Global
Te mpe rature Options; written by William J. Hepp and C. Frank Wheatle y.
EVTO
+
13
CA CB
EGS EDS
RIN CIN
MOS1
MOS2
DBREAK
EBREAK
DBODY
LDRAIN
DRAIN
RSOURCE LSOURCE
SOURCE
RBREAK
RVTO
VBAT
IT
VTO
DPLCAP
6
10 5
16
21
8
14
73
17 18
19
2
+
+
+
RDRAIN
ESCL
RSCL1
RSCL2 51
50
+
S1A S2A
S2BS1B
12 15
13
814
13
6
8
+
-
5
8
-
-
18
8
RGATE
GATE
LGATE
209
1
ESG +
-6
811 +
-
17
18
5
51
RFD16N05, RFD16N05SM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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SILENT SWITCHER
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Across the board. Around the world.™
The Power Franchise™
Programmable Active Droop™
