STD5NE10
N - CHANNEL 100V - 0.32 Ω - 5A TO-251/TO-252
STripFET POWER MOSFET
■TYPICAL RDS(on) = 0.32 Ω
■EXCEPTIONAL dv/dt CAPABILITY
■AV ALANCHE TES TED
■100% AVALANCHE TESTED
■AP PLICA TION ORIENT ED
CHARACTERIZATION
■ADD SUFFIX "T4" FOR ORDERING IN TAPE
& RE EL
DESCRIP TION
This Power MOSFET is the latest development of
STMicroelectronics unique "Single Feature
Size" strip-based process. The resulting transi-
stor shows extremely high packing density for low
on-resistance, rugged avalanche characteristics
and less critical alignment steps therefore a re-
markable manufacturing reproducibility.
APPLIC A TION S
■MOTOR CON TROL (DISK DRIVES, etc.)
■DC-DC & DC-AC CONV ERTE RS
■SY NCHRONO U S REC TIFICATION
®
INTERNAL SCHEMATIC DIAGRAM
May 1999
3
2
1
IPAK
TO-251
(Suffix "-1")
13
DPAK
TO-252
(Suffix "T4")
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 100 V
VDGR Drain- gate Voltage (RGS = 20 kΩ)100V
V
GS Gate-source Voltage ± 20 V
IDDrain Current (continuous) at Tc = 25 oC5A
I
D
Drain Current (continuous) at Tc = 100 oC3.5A
I
DM(•) Drain Current (pulsed) 20 A
Ptot Total Dissipation at Tc = 25 oC25W
Derating Factor 0.17 W/oC
dv/dt(1) Peak Diode Recovery voltage slope 0.6 V/ns
Tstg Storage Temperature -65 to 175 oC
TjMax. Operating Junction Temperature 175 oC
(•) Pulse widt h lim ited by safe operating area (1) ISD ≤ 5A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, T j ≤ TJMAX
TYPE VDSS RDS(on) ID
STD5NE10 100 V < 0.4 Ω5 A
1/9
THERMAL DATA
Rthj-case
Rthj-amb
Rthc-sink
Tl
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Thermal Resistance Case-sink Typ
Maximum Lead Temperature For Soldering Purpose
6
100
1.5
275
oC/W
oC/W
oC/W
oC
AVALANCHE CHARACTE RIST ICS
Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T j max) 5A
E
AS Single Pulse Avalanche Energy
(starting T j = 25 oC, ID = IAR, VDD = 30V) 25 mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless other wise specified)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source
Breakdown Voltage ID = 250 µA VGS = 0 100 V
IDSS Zero Gate Voltage
Drain Current (VGS = 0) VDS = Max Rating
VDS = Max Rating Tc = 125 oC1
10 µA
µA
IGSS Gate-body Leakage
Current (VDS = 0) VGS = ± 20 V ± 100 nA
ON (∗)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA234V
R
DS(on) Static Drain-source On
Resistance VGS = 10V ID = 2.5 A 0.32 0.4 Ω
ID(on) On State Drain Current VDS > ID(on) x RDS(on)max
VGS = 10 V 5A
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs ( ∗) Forward
Transconductance VDS > ID(on) x RDS(on)max ID = 2.5 A 2.5 S
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25 V f = 1 MHz VGS = 0 305
45
21
pF
pF
pF
STD5NE10
2/9
ELECTRICAL CHARACTERISTICS (continued)
SWI TCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on)
trTurn-on Delay Time
Rise Time VDD = 50 V ID = 3.5 A
RG = 4.7 Ω VGS = 10 V
(Resistive Load, see fig. 3)
6.5
15 ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 80 V ID = 5 A VGS = 10 V 14
6
4
18 nC
nC
nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(off)
tfTurn-off Delay Time
Fall Time VDD = 50 V ID = 3.5 A
RG = 4.7 Ω VGS = 10 V
(Resistive Load, see fig. 3)
25
7ns
ns
tr(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
VDD = 80 V ID = 7 A
RG = 4.7 Ω VGS = 10 V
(Inductive Load, see fig. 5)
7
8
16
ns
ns
ns
SOURCE DRA IN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD
ISDM(•)Source-drain Current
Source-drain Current
(pulsed)
5
20 A
A
VSD ( ∗) Forward On Voltage ISD = 8 A VGS = 0 1.5 V
trr
Qrr
IRRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
ISD = 5 A di/dt = 100 A/µs
VDD = 50 V Tj = 150 oC
(see test circuit, fig. 5)
75
210
5.5
ns
nC
A
(∗) Pul sed: Pulse durati on = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area for Thermal Impedance
STD5NE10
3/9
Output Characteristics
Transconductance
Gate Charge vs Gate-source Voltage
Transfer Characteristics
Static Drain-source On Resistance
Capacitance Variations
STD5NE10
4/9
Normalized Gate Threshold Volt age vs
Temperature
Source-drain Diode Forward Characteristics
Normalized On Resistance vs T em perature
STD5NE10
5/9
Fig. 1: Unc lamped Inductive Load Tes t Circuit
Fig. 3: Switching Times Test Circuits For
Resis tive Load
Fig. 2: Unclamped Inductive Waveform
Fig. 4 : Gate Charge tes t Circuit
Fig. 5 : Test Circuit For Inductive Load Switching
And Diode Recovery Times
STD5NE10
6/9
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031
B2 5.2 5.4 0.204 0.212
B3 0.85 0.033
B5 0.3 0.012
B6 0.95 0.037
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370
L1 0.8 1.2 0.031 0.047
L2 0.8 1 0.031 0.039
A
C2
C
A3
H
A1
DL
L2
L1
1 3
= =
B3
B
B6
B2
E
G
= =
= =
B5
2
TO-2 51 (I PA K) ME CH ANI CAL DAT A
0068771-E
STD5NE10
7/9
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035
B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397
L2 0.8 0.031
L4 0.6 1 0.023 0.039
==
D
L2
L4
1 3
==
B
E
==
B2
G
2
A
C2
C
H
A1
DETAIL "A"
A2
DETAIL "A"
TO-252 (DP AK ) ME CHA NICAL DAT A
0068772-B
STD5NE10
8/9
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
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STD5NE10
9/9
