© 2000 Fairchild Semiconductor Corporation DS012466 www.fairchildsemi.com
May 1995
Revised September 2000
74LCX257 Low Voltage Quad 2-Input Multi plexer with 5V Tolerant Inputs and Outputs
74LCX257
Low Voltage Quad 2-Input Multiplexer
with 5V Tolerant Inputs and Outputs
General Description
The LCX257 is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a Common Data Select input. The four outputs
present the selected data in true (non inverted ) form. The
outputs may be switched to a high impedance state by
placing a logic HIGH on the common Output Enable (OE)
input, allo w ing th e ou tpu ts to i nt erf ace d i rec tly with bus-ori-
ented systems.
The 74LCX257 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
■5V tolerant inputs and outputs
■2.3V–3. 6V VCC specifications provided
■6.0 ns tPD max (VCC = 3.3V, In → Zn), 10 µA ICC max
■Power down high impedance inputs and outputs
■Supports live insertion/withdrawal (Note 1)
■Implements patented noise/EMI reduction circuitry
■Latch-up per for man c e exce eds 500 mA
■ESD performa nce :
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC throug h a pull- up resist or: the min imum value or the
resisto r is det ermin ed by the current-so urc ing capability of th e driver.
Ordering Code:
Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74LCX257M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74LCX257SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX257MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
S Common Data Select Input
OE 3-STATE Output Enab le Input
I0a–I0d Data Inputs from Source 0
I1a–I1d Data Inputs from Source 1
Za–Zd3-STATE Multiplexer Outputs