STM8S105xx Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, IC Interrupt management Nested interrupt controller with 32 interrupts * * Up to 37 external interrupts on 6 vectors LQFP48 7x7 LQFP44 10x10 UFQFPN32 5x5 LQFP32 7x7 insertion and flexible synchronization Core 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline * * Extended instruction set Memories Medium-density Flash/EEPROM: Program memory up to 32 Kbytes; data retention 20 years at 55C after 10 kcycles - Data memory up to 1 Kbytes true data EEPROM; endurance 300 kcycles Clock, reset and supply management 2.95 V to 5.5 V operating voltage * 8-bit basic timer with 8-bit prescaler * Auto wake-up timer * Window and independent watchdog timers Communications interfaces UART with clock output for synchronous operation, Smartcard, IrDA, LIN * * SPI interface up to 8 Mbit/s * I C interface up to 400 Kbit/s 2 Analog-to-digital converter (ADC) 10-bit, 1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog * I/Os Up to 38 I/Os on a 48-pin package including 16 high sink outputs * RAM: Up to 2 Kbytes * clock control, 4 master clock sources: * Flexible Low power crystal resonator oscillator - External clock input - Internal, user-trimmable 16 MHz RC - Internal low power 128 kHz RC * Clock security system with clock monitor management: * Power Low - power modes (wait, active-halt, halt) - Switch-off peripheral clocks individually active, low consumption power-on * Permanently and power-down reset June 2012 * control timer: 16-bit, 4 CAPCOM * Advanced channels, 3 complementary outputs, dead-time SDIP32 400 ml Features * Timers 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) * robust I/O design, immune against current * Highly injection Development support Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging * Unique ID 96-bit unique key for each device * Table 1: Device summary Reference Part number STM8S105xx STM8S105K4, STM8S105K6, STM8S105S4, DocID14771 Rev 12 STM8S105S6, STM8S105C4, STM8S105C6 1/124 www.st.com Contents STM8S105xx Contents 1 2 3 4 Introduction ..............................................................................................................8 Description ...............................................................................................................9 Block diagram ........................................................................................................10 Product overview ...................................................................................................11 4.1 Central processing unit STM8 .....................................................................................11 4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11 4.3 Interrupt controller .......................................................................................................12 4.4 Flash program and data EEPROM memory ................................................................12 4.5 Clock controller ............................................................................................................13 4.6 Power management ....................................................................................................14 4.7 Watchdog timers ..........................................................................................................15 4.8 Auto wakeup counter ...................................................................................................15 4.9 Beeper ........................................................................................................................15 4.10 TIM1 - 16-bit advanced control timer .........................................................................16 4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................16 4.12 TIM4 - 8-bit basic timer ..............................................................................................16 4.13 Analog-to-digital converter (ADC1) ............................................................................17 4.14 Communication interfaces .........................................................................................17 4.14.1 UART2 ...............................................................................................17 4.14.2 SPI .....................................................................................................18 4.14.3 IC ......................................................................................................19 5 Pinout and pin description ...................................................................................20 5.1 STM8S105 pinouts and pin description .......................................................................21 5.1.1 Alternate function remapping ...............................................................27 6 Memory and register map .....................................................................................29 6.1 Memory map 6.2 Register map 6.2.1 6.2.2 6.2.3 ................................................................................................................29 ...............................................................................................................30 I/O port hardware register map ............................................................30 General hardware register map ...........................................................33 CPU/SWIM/debug module/interrupt controller registers ......................44 7 Interrupt vector mapping ......................................................................................47 8 Option bytes ...........................................................................................................49 9 Unique ID ................................................................................................................54 10 Electrical characteristics ....................................................................................55 10.1 Parameter conditions .................................................................................................55 10.1.1 Minimum and maximum values .........................................................55 10.1.2 Typical values .....................................................................................55 2/124 DocID14771 Rev 12 STM8S105xx Contents 10.1.3 Typical curves ....................................................................................55 10.1.4 Typical current consumption ..............................................................55 10.1.5 Loading capacitor ...............................................................................56 10.1.6 Pin input voltage .................................................................................56 10.2 Absolute maximum ratings ........................................................................................56 10.3 Operating conditions ..................................................................................................58 10.3.1 VCAP external capacitor ....................................................................61 10.3.2 Supply current characteristics ............................................................61 10.3.3 External clock sources and timing characteristics .............................73 10.3.4 Internal clock sources and timing characteristics ...............................75 10.3.5 Memory characteristics ......................................................................78 10.3.6 I/O port pin characteristics .................................................................79 10.3.7 Typical output level curves .................................................................83 10.3.8 Reset pin characteristics ....................................................................88 10.3.9 SPI serial peripheral interface ............................................................91 2 10.3.10 I C interface characteristics .............................................................94 10.3.11 10-bit ADC characteristics ................................................................96 10.3.12 EMC characteristics .........................................................................99 11 Package information ..........................................................................................103 11.1 48-pin LQFP package mechanical data ...................................................................103 11.2 44-pin LQFP package mechanical data ...................................................................105 11.3 32-pin LQFP package mechanical data ...................................................................106 11.4 32-lead UFQFPN package mechanical data ...........................................................108 11.5 SDIP32 package mechanical data ...........................................................................109 12 Thermal characteristics ....................................................................................111 12.1 Reference document ...............................................................................................112 12.2 Selecting the product temperature range ................................................................112 13 Ordering information .........................................................................................113 13.1 STM8S105 FASTROM microcontroller option list ...................................................113 14 STM8 development tools ..................................................................................118 14.1 Emulation and in-circuit debugging tools .................................................................118 14.2 Software tools ..........................................................................................................118 14.2.1 STM8 toolset ....................................................................................119 14.2.2 C and assembly toolchains ..............................................................119 14.3 Programming tools ..................................................................................................119 15 Revision history .................................................................................................120 DocID14771 Rev 12 3/124 List of tables STM8S105xx List of tables Table 1. Device summary .........................................................................................................................1 Table 2. STM8S105xx access line features .............................................................................................9 Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14 Table 4. TIM timer features ...................................................................................................................16 Table 5. Legend/abbreviations for pinout tables ...................................................................................20 Table 6. Pin description for STM8S105 microcontrollers .......................................................................24 Table 7. Flash, Data EEPROM and RAM boundary addresses ..........................................................105 Table 8. I/O port hardware register map ..............................................................................................108 Table 9. General hardware register map ................................................................................................33 Table 10. CPU/SWIM/debug module/interrupt controller registers ......................................................109 Table 11. Interrupt mapping ....................................................................................................................47 Table 12. Option bytes ..........................................................................................................................54 Table 13. Option byte description ...........................................................................................................50 Table 14. Description of alternate function remapping bits [7:0] of OPT2 ..............................................52 Table 15. Unique ID registers (96 bits) ...................................................................................................54 Table 16. Voltage characteristics ...........................................................................................................56 Table 17. Current characteristics ...........................................................................................................57 Table 18. Thermal characteristics ..........................................................................................................58 Table 19. General operating conditions .................................................................................................59 Table 20. Operating conditions at power-up/power-down ......................................................................60 Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................61 Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................73 Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................64 Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................65 Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................65 Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................66 Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................67 Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................68 Table 29. Wakeup times .........................................................................................................................68 Table 30. Total current consumption and timing in forced reset state ..................................................102 Table 31. Peripheral current consumption .............................................................................................69 Table 32. HSE user external clock characteristics .................................................................................73 Table 33. HSE oscillator characteristics .................................................................................................74 Table 34. HSI oscillator characteristics ..................................................................................................75 Table 35. LSI oscillator characteristics ...................................................................................................77 Table 36. RAM and hardware registers ..................................................................................................78 Table 37. Flash program memory/data EEPROM memory ....................................................................78 Table 38. I/O static characteristics .........................................................................................................79 Table 39. Output driving current (standard ports) ..................................................................................82 Table 40. Output driving current (true open drain ports) ........................................................................82 Table 41. Output driving current (high sink ports) ..................................................................................83 Table 42. NRST pin characteristics ........................................................................................................88 Table 43. SPI characteristics ..................................................................................................................91 2 Table 44. I C characteristics ..................................................................................................................94 Table 45. ADC characteristics ................................................................................................................96 Table 46. ADC accuracy with RAIN < 10 k , VDDA= 5 V .......................................................................97 Table 47. ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V ............................................................98 4/124 DocID14771 Rev 12 STM8S105xx List of tables Table 48. EMS data ..............................................................................................................................100 Table 49. EMI data ...............................................................................................................................101 Table 50. ESD absolute maximum ratings ...........................................................................................102 Table 51. Electrical sensitivities ...........................................................................................................102 Table 52. 48-pin low profile quad flat package mechanical data .........................................................103 Table 53. 44-pin low profile quad flat package mechanical data .........................................................105 Table 54. 32-pin low profile quad flat package mechanical data .........................................................120 Table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data ...........................108 Table 56. 32-lead shrink plastic DIP (400 ml) package mechanical data ............................................109 (1) Table 57. Thermal characteristics ....................................................................................................111 Table 58. Document revision history ...................................................................................................120 DocID14771 Rev 12 5/124 List of figures STM8S105xx List of figures Figure 1. STM8S105xx access line block diagram ................................................................................10 Figure 2. Flash memory organisation ....................................................................................................13 Figure 3. LQFP 48-pin pinout .................................................................................................................21 Figure 4. LQFP 44-pin pinout .................................................................................................................22 Figure 5. LQFP/UFQFPN 32-pin pinout ................................................................................................23 Figure 6. SDIP 32-pin pinout ..................................................................................................................24 Figure 7. Memory map ...........................................................................................................................29 Figure 8. Supply current measurement conditions ................................................................................55 Figure 9. Pin loading conditions .............................................................................................................56 Figure 10. Pin input voltage ...................................................................................................................56 Figure 11. fCPUmax versus VDD ..............................................................................................................60 Figure 12. External capacitor CEXT .......................................................................................................61 Figure 13. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................70 Figure 14. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................71 Figure 15. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................71 Figure 16. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................72 Figure 17. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................72 Figure 18. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................73 Figure 19. HSE external clocksource .....................................................................................................74 Figure 20. HSE oscillator circuit diagram ...............................................................................................75 Figure 21. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................76 Figure 22. Typical HSI accuracy vs VDD @ 4 temperatures ..................................................................77 Figure 23. Typical LSI accuracy vs VDD @ 4 temperatures ...................................................................78 Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................81 Figure 25. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................81 Figure 26. Typical pull-up current vs VDD @ 4 temperatures .................................................................82 Figure 27. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................84 Figure 28. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................84 Figure 29. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................85 Figure 30. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................85 Figure 31. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................86 Figure 32. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................86 Figure 33. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................87 Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................87 Figure 35. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................88 Figure 36. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................88 Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................89 Figure 38. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................90 Figure 39. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................90 Figure 40. Recommended reset pin protection ......................................................................................91 Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................93 (1) Figure 42. SPI timing diagram - slave mode and CPHA = 1 .............................................................93 (1) Figure 43. SPI timing diagram - master mode ...................................................................................94 2 (1) Figure 44. Typical application with I C bus and timing diagram .......................................................95 Figure 45. ADC accuracy characteristics ...............................................................................................99 Figure 46. Typical application with ADC ................................................................................................99 Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................103 6/124 DocID14771 Rev 12 STM8S105xx List of figures Figure 48. 44-pin low profile quad flat package ...................................................................................105 Figure 49. 32-pin low profile quad flat package (7 x 7) ........................................................................106 Figure 50. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ..........................................108 Figure 51. 32-lead shrink plastic DIP (400 ml) package ......................................................................109 Figure 52. STM8S105xx access line ordering information scheme .....................................................113 DocID14771 Rev 12 7/124 Introduction 1 STM8S105xx Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). * information on programming, erasing and protection of the internal Flash memory * For please refer to the STM8S Flash programming manual (PM0051). information on the debug and SWIM (single wire interface module) refer to the STM8 * For SWIM communication protocol and debug module user manual (UM0470). information on the STM8 core, please refer to the STM8 CPU programming manual * For (PM0044). 8/124 DocID14771 Rev 12 STM8S105xx 2 Description Description The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program memory, plus integrated true data EEPROM. They are referred to as medium-density devices in the STM8S microcontroller family reference manual (RM0016). All devices of the STM8S105xx access line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity. The system cost is reduced thanks to an integrated true data EEPROM for up to 300 kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. Device performance is ensured by a 16 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system. Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. Full documentation is offered with a wide choice of development tools. Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply. Table 2: STM8S105xx access line features Device STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4 Pin count 48 48 44 44 32 32 Maximum number of GPIOs 38 38 34 34 25 25 Ext. Interrupt pins 35 35 31 31 23 23 Timer CAPCOM channels 9 9 8 8 8 8 Timer complementary outputs 3 3 3 3 3 3 A/D Converter channels 10 10 9 9 7 7 High sink I/Os 16 16 15 15 12 12 Medium density Flash Program memory (bytes) 32K 16K 32K 16K 32K 16K Data EEPROM (bytes) 1024 1024 1024 1024 1024 1024 RAM (bytes) 2K 2K 2K 2K 2K 2K Peripheral set 2 Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I C, UART, Window WDG, Independent WDG, ADC DocID14771 Rev 12 9/124 Block diagram 3 STM8S105xx Block diagram Figure 1: STM8S105xx access line block diagram Reset block XTAL 1-16 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Debug/SWIM Up to 32 Kbytes program Flash Master/slave autosynchro LIN master SPI emul. UART2 1 Kbytes data EEPROM 400 Kbit/s 8 Mbit/s Up to 10 channels 1/2/4 kHz beep 10/124 2 I C SPI Address and data bus Single wire debug interf. Up to 2 Kbytes RAM Boot ROM 16-bit advanced control timer (TIM1) Up to 4 CAPCOM channels +3 complementary outputs 16-bit general purpose timers (TIM2, TIM3) Up to 5 CAPCOM channels 8-bit basic timer (TIM4) ADC1 Beeper AWU timer DocID14771 Rev 12 STM8S105xx 4 Product overview Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers Harvard architecture * * 3-stage pipeline * 32-bit wide program memory bus - single cycle fetching for most instructions Y 16-bit index registers - enabling indexed addressing modes with or without offset * Xandandread-modify-write type data manipulations 8-bit accumulator * * 24-bit program counter - 16-Mbyte linear memory space * 16-bit stack pointer - access to a 64 K-level stack * 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing 20 addressing modes * indirect addressing mode for look-up tables located anywhere in the address * Indexed space * Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2-byte average instruction size * * Standard data movement and logic/arithmetic functions * 8-bit by 8-bit multiplication * 16-bit by 8-bit and 16-bit by 16-bit division * Bit manipulation * Data transfer between stack and accumulator (push/pop) with direct stack access * Data transfer using the X and Y registers or direct memory-to-memory transfers 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. DocID14771 Rev 12 11/124 Product overview STM8S105xx SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers. R/W to RAM and peripheral registers in real-time * * R/W access to all resources by stalling the CPU * Breakpoints on all program-memory instructions (software breakpoints) * Two advanced breakpoints, 23 predefined configurations 4.3 Interrupt controller * Nested interrupts with three software priority levels * 32 interrupt vectors with hardware priority * Up to 37 external interrupts on 6 vectors including TLI * Trap and reset interrupts 4.4 Flash program and data EEPROM memory * Up to 32 Kbytes of Flash program single voltage Flash memory * Up to 1 Kbytes true data EEPROM * Read while write: Writing in data memory possible while executing code in program memory * User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below. The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: Main program memory: Up to 32 Kbytes minus UBC * * User-specific boot code (UBC): Configurable up to 32 Kbytes 12/124 DocID14771 Rev 12 STM8S105xx Product overview The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2: Flash memory organisation Data EEPROM memory Data memory area ( 1 Kbyte) Option bytes UBC area Remains write protected during IAP Programmable area from 1 Kbyte (2 first pages) up to 32 Kbytes (1 page steps) Medium density Flash program memory (up to 32 Kbytes) Program memory area Write access possible for IAP Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 4.5 Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. * clock switching: Clock sources can be changed safely on the fly in run mode * Safe through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. management: To reduce power consumption, the clock controller can stop the * Clock clock to the core, individual peripherals or memory. clock sources: Four different clock sources can be used to drive the master * Master clock: - 1-16 MHz high-speed external crystal (HSE) - Up to 16 MHz high-speed user-external clock (HSE user-ext) DocID14771 Rev 12 13/124 Product overview - STM8S105xx 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) clock: After reset, the microcontroller restarts by default with an internal 2 MHz * Startup clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. security system (CSS): This feature can be enabled by software. If an HSE clock * Clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. main clock output (CCO): This outputs an external clock for use by the * Configurable application. Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Bit Peripheral Bit clock Peripheral Bit clock Peripheral Bit clock Peripheral clock PCKEN1 7 TIM1 PCKEN1 3 UART2 PCKEN2 7 Reserved PCKEN2 3 ADC PCKEN1 6 TIM3 PCKEN1 2 Reserved PCKEN2 6 Reserved PCKEN2 2 AWU PCKEN1 5 TIM2 PCKEN1 1 SPI PCKEN2 5 Reserved PCKEN2 1 Reserved PCKEN1 4 TIM4 PCKEN1 0 I C PCKEN2 4 Reserved PCKEN2 0 Reserved 4.6 2 Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. * halt mode with regulator on: In this mode, the CPU and peripheral clocks are * Active stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. halt mode with regulator off: This mode is the same as active halt with regulator * Active on, except that the main voltage regulator is powered off, so the wake up time is slower. mode: In this mode the microcontroller uses the least power. The CPU and peripheral * Halt clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. 14/124 DocID14771 Rev 12 STM8S105xx 4.7 Product overview Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 s up to 64 ms. 2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register. Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 s to 1 s. 4.8 Auto wakeup counter * Used for auto wakeup from active halt mode * Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock * LSI clock can be internally connected to TIM3 input capture channel 1 for calibration 4.9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. The beeper output port is only available through the alternate function remap option bit AFR7. DocID14771 Rev 12 15/124 Product overview 4.10 STM8S105xx TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler * independent capture/compare channels (CAPCOM) configurable as input capture, * Four output compare, PWM generation (edge and center aligned mode) and single pulse mode output * Synchronization module to control the timer with external signals * Break input to force the timer outputs into a defined state * Three complementary outputs with adjustable dead time * Encoder mode * Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.11 TIM2, TIM3 - 16-bit general purpose timers * 16-bit autoreload (AR) up-counter * 15-bit prescaler adjustable to fixed power of 2 ratios 1...32768 * Timers with 3 or 2 individually configurable capture/compare channels * PWM mode * Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 4.12 TIM4 - 8-bit basic timer * 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 * Clock source: CPU clock * Interrupt source: 1 x overflow/update Table 4: TIM timer features Timer Counter Prescaler size (bits) TIM1 16 Any integer from 1 to Up/ 65536 down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No 16/124 Counting CAPCOM Complem. Ext. Timer mode channels outputs trigger synchronization/ chaining DocID14771 Rev 12 No STM8S105xx Product overview Timer Counter Prescaler size (bits) Counting CAPCOM Complem. Ext. Timer mode channels outputs trigger synchronization/ chaining TIM4 8 Up 4.13 Any power of 2 from 1 to 128 0 0 No Analog-to-digital converter (ADC1) The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 10 multiplexed input channels and the following main features: Input voltage range: 0 to VDDA * * Conversion time: 14 clock cycles * Single and continuous and buffered continuous conversion modes * Buffer size (n x 10 bits) where n = number of input channels * Scan mode for single and continuous conversion of a sequence of channels * Analog watchdog capability with programmable upper and lower thresholds * Analog watchdog interrupt * External trigger input * Trigger from TIM1 TRGO * End of conversion (EOC) interrupt Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers. 4.14 Communication interfaces The following communication interfaces are implemented: UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, LIN2.1 master/slave capability * * SPI : Full and half-duplex, 8 Mbit/s * IC: Up to 400 Kbit/s 4.14.1 UART2 Main features One Mbit/s full duplex SCI * * SPI emulation * High precision baud rate generator * Smartcard emulation * IrDA SIR encoder decoder DocID14771 Rev 12 17/124 Product overview STM8S105xx * LIN master mode * LIN slave mode Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) * transmit and receive baud rates up to 1 Mbit/s (f /16) and capable of * Programmable following any standard baud rate regardless of the input frequency * Separate enable bits for transmitter and receiver receiver wakeup modes: * TwoAddress bit (MSB) Idle line (interrupt) * Transmission error detection with interrupt generation * Parity control CPU Synchronous communication Full duplex synchronous transfers * * SPI master operation * 8-bit data communication * Maximum speed: 1 Mbit/s at 16 MHz (f CPU/16) LIN master mode Emission: Generates 13-bit synch break frame * * Reception: Detects 11-bit break frame LIN slave mode Autonomous header handling - one single interrupt per valid message header * * Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % * Synch delimiter checking * 11-bit LIN synch break detection - break detection always active * Parity check on the LIN identifier field * LIN error management * Hot plugging support 4.14.2 SPI * Maximum speed: 8 Mbit/s (f /2) both for master and slave * Full duplex synchronous transfers * Simplex synchronous transfers on two lines with a possible bidirectional data line * Master or slave operation - selectable by hardware or software * CRC calculation * 1 byte Tx and Rx buffer * Slave/master selection input pin MASTER 18/124 DocID14771 Rev 12 STM8S105xx 4.14.3 Product overview IC master features: * IC Clock generation Start and stop generation slave features: * IC Programmable I2C address detection Stop bit detection * Generation and detection of 7-bit/10-bit addressing and general call different communication speeds: * Supports Standard speed (up to 100 kHz) - Fast speed (up to 400 kHz) DocID14771 Rev 12 19/124 Pinout and pin description 5 STM8S105xx Pinout and pin description Table 5: Legend/abbreviations for pinout tables Type I= Input, O = Output, S = Power supply Level Input CM = CMOS Output HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control configuration Reset state Input float = floating, wpu = weak pull-up Output T = True open drain, OD = Open drain, PP = Push pull Bold X (pin state after internal reset release). Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. 20/124 DocID14771 Rev 12 STM8S105xx STM8S105 pinouts and pin description NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 (HS) PA4 (HS) PA5 (HS) PA6 PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDAA PE3/TIM1_BKIN PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] Figure 3: LQFP 48-pin pinout 1 48 47 46 45 44 43 42 41 40 39 38 37 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 12 26 25 PG1 PG0 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS AIN8/PE7 AIN9/PE6 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 13 14 15 16 17 18 19 20 21 22 23 24 VDDA VSSA AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 5.1 Pinout and pin description 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). DocID14771 Rev 12 21/124 Pinout and pin description STM8S105xx PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] Figure 4: LQFP 44-pin pinout NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 31 PG1 PG0 PC7 (HS)/SPI_MISO 4 30 PC6 (HS)/SPI_MOSI VSS VCAP VDD VDDIO_1 5 29 6 28 7 27 8 26 (HS) PA4 (HS) PA5 (HS) PA6 9 25 10 24 VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS/UART2_CK AIN9/PE6 [TIM1_CH1N] AIN0/PB0 [TIM1_CH2N] AIN1/PB1 [TIM1_CH3N] AIN2/PB2 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 AIN6/PB6 [I2C_SDA] AIN5/PB5 VSSA AIN7/PB7 VDDA 11 23 12 13 14 15 16 17 18 19 20 21 22 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 22/124 DocID14771 Rev 12 STM8S105xx Pinout and pin description PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] Figure 5: LQFP/UFQFPN 32-pin pinout 32 31 30 29 28 27 26 25 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 1 24 2 23 3 22 4 21 5 20 6 19 18 7 17 8 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 VDDA VSSA [I2C_SDA] AIN5/PB5 9 10 11 12 13 14 15 16 1. (HS) high sink capability. 2. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). DocID14771 Rev 12 23/124 Pinout and pin description STM8S105xx Figure 6: SDIP 32-pin pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ADC_ETR/TIM2_CH2/(HS) PD3 [BEEP] TIM2_CH1/(HS) PD4 UART2_TX/PD5 UART2_RX/PD6 [TIM1_CH4] TLI/PD7 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 VDDA VSSA [I2C_SDA] AIN5/PB5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS PB0/AIN0 [TIM1_CH1N] PB1/AIN1 [TIM1_CH2N] PB2/AIN2 [TIM1_CH3N] PB3/AIN3 [TIM1_ETR] PB4/AIN4[ I2C_SCL] 105_ai15057 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 6: Pin description for STM8S105 microcontrollers Pin number LQFP48 Pin name Type LQFP44 LQFP32/ SDIP32 1 1 1 6 NRST I/O 2 2 2 7 PA1/ OSC IN I/O PA2/ OSC OUT I/O 3 3 8 Output floating wpu Ext. High interrupt sink UFQFPN32 3 Input Main function (after reset) Speed OD PP X X Default alternate function Reset X O1 X X Port A1 Resonator/ crystal in X X X O1 X X Port A2 Resonator/ crystal out 4 4 - - VSSIO_1 S I/O ground 5 5 4 9 VSS S Digital ground 6 6 5 10 VCAP S 1.8 V regulator capacitor 7 7 6 11 VDD S Digital power supply 8 8 7 12 VDDIO_1 S I/O power supply 24/124 DocID14771 Rev 12 Alternate function after remap [option bit] STM8S105xx Pinout and pin description Pin number LQFP48 Pin name Type LQFP44 LQFP32/ SDIP32 - - - Output floating wpu Ext. High interrupt sink UFQFPN32 9 Input PA3/ TIM2 _CH3 [TIM3 _CH1] I/O X X X Main function (after reset) Speed OD O1 X Default alternate function PP X Port A3 Timer 2 channel 3 Alternate function after remap [option bit] TIM3_ CH1 [AFR1] 10 9 - - PA4 I/O X X X HS O3 X X Port A4 11 10 - - PA5 I/O X X X HS O3 X X Port A5 12 11 - - PA6 I/O X X X HS O3 X X Port A6 - - 8 13 PF4/ AIN12 (1) I/O X X O1 X X Port F4 13 12 9 14 VDDA S Analog power supply 14 13 10 15 VSSA S Analog ground 15 14 - - PB7/ AIN7 I/O X X X O1 X X Port B7 Analog input 7 16 15 - - PB6/ AIN6 I/O X X X O1 X X Port B6 Analog input 6 17 16 11 16 PB5/ AIN5 2 [I C_ SDA] I/O X X X O1 X X Port B5 Analog input 5 2 I C_SDA [AFR6] 18 17 12 17 PB4/ AIN4 2 [I C_ SCL] I/O X X X O1 X X Port B4 Analog input 4 2 I C_SCL [AFR6] 19 18 13 18 PB3/ AIN3 [TIM1_ ETR] I/O X X X O1 X X Port B3 Analog input 3 TIM1_ ETR [AFR5] 20 19 14 19 PB2/ AIN2 [TIM1_ CH3N] I/O X X X O1 X X Port B2 Analog input 2 TIM1_ CH3N [AFR5] 21 20 15 20 PB1/ AIN1 [TIM1_ CH2N] I/O X X X O1 X X Port B1 Analog input 1 TIM1_ CH2N [AFR5] 22 21 16 21 PB0/ AIN0 [TIM1_ CH1N] I/O X X X O1 X X Port B0 Analog input 0 TIM1_ CH1N [AFR5] 23 - - - PE7/ AIN8 I/O X X X O1 X X Port E7 Analog input 8 DocID14771 Rev 12 Analog input 12 (2) 25/124 Pinout and pin description Pin number LQFP48 STM8S105xx Pin name Type LQFP44 LQFP32/ SDIP32 Input Output floating wpu Ext. High interrupt sink UFQFPN32 Main function (after reset) Speed OD Default alternate function PP (3) Analog input 9 24 22 - - PE6/ AIN9 I/O X X X O1 X X Port E6 25 23 17 22 PE5/SPI_ NSS I/O X X X O1 X X Port E5 SPI master/slave select 26 24 18 23 PC1/ TIM1_ CH1/ UART2_CK I/O X X X O3 X X Port C1 Timer 1 - PC2/ TIM1_ CH2 I/O PC3/ TIM1_ CH3 I/O PC4/ TIM1_ CH4 I/O 27 28 29 25 26 - 19 20 21 24 25 26 HS channel 1/ UART2 synchronous clock X X X HS O3 X X Port C2 Timer 1channel 2 X X X HS O3 X X Port C3 Timer 1 channel 3 X X X HS O3 X X Port C4 Timer 1 channel 4 30 27 22 27 PC5/ SPI_ SCK I/O 31 28 - - VSSIO_2 S I/O ground 32 29 - - VDDIO_2 S I/O power supply 33 30 23 28 PC6/ SPI_ MOSI I/O X X X HS O3 X X Port C6 SPI master out/slave in 34 31 24 29 PC7/ SPI_ MISO I/O X X X HS O3 X X Port C7 SPI master in/ slave out 35 32 - - PG0 I/O X X O1 X X Port G0 36 33 - - PG1 I/O X X O1 X X Port G1 37 - - - PE3/ TIM1_ BKIN I/O X X X O1 X X Port E3 38 34 - - PE2/ 2 I C_ SDA I/O X X O1 (4) T Port E2 2 I C data 39 35 - - PE1/ 2 I C_ SCL I/O X X O1 (4) T Port E1 2 I C clock 40 36 - - PE0/ CLK_ CCO I/O X O3 X 26/124 X X X X X HS HS O3 DocID14771 Rev 12 X X X Port C5 Port E0 SPI clock Timer 1 - break input Configurable clock output Alternate function after remap [option bit] STM8S105xx Pinout and pin description Pin number LQFP48 Pin name Type LQFP44 LQFP32/ SDIP32 37 25 30 Output floating wpu Ext. High interrupt sink UFQFPN32 41 Input PD0/ TIM3_ CH2 [TIM1_ BKIN] [CLK_ CCO] I/O X X X HS Main function (after reset) Speed OD O3 X Default alternate function PP X Port D0 Timer 3 channel 2 42 38 26 31 PD1/ (5) SWIM I/O X X X HS O4 X X Port D1 SWIM data interface 43 39 27 32 PD2/ TIM3_ CH1 [TIM2_ CH3] I/O X X X HS O3 X X Port D2 Timer 3 - PD3/ TIM2_ CH2 [ADC_ ETR] I/O PD4/ TIM2_ CH1 [BEEP] I/O 44 45 40 41 28 29 1 2 channel 1 X X X HS O3 X X Port D3 Timer 2 channel 2 X X X HS O3 X X Port D4 Timer 2 channel 1 46 42 30 3 PD5/ UART2_ TX I/O X X X O1 X X Port D5 UART2 data transmit 47 43 31 4 PD6/ UART2_ RX I/O X X X O1 X X Port D6 UART2 data receive 48 44 32 5 PD7/ TLI [TIM1_ CH4] I/O X X X O1 X X Port D7 Top level interrupt Alternate function after remap [option bit] TIM1_ BKIN [AFR3]/ CLK_ CCO [AFR2] TIM2_CH3 [AFR1] ADC_ ETR [AFR0] BEEP output [AFR7] TIM1_ CH4 [AFR4] (1) A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release. (2) AIN12 is not selectable in ADC scan mode or with analog watchdog. (3) In 44-pin package, AIN9 cannot be used by ADC scan mode. (4) In the open-drain output column, `T' defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented). (5) The PD1 pin is in input pull-up during the reset phase and after internal reset release. 5.1.1 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. DocID14771 Rev 12 27/124 Pinout and pin description STM8S105xx Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). 28/124 DocID14771 Rev 12 STM8S105xx Memory and register map 6 Memory and register map 6.1 Memory map Figure 7: Memory map 0x00 0000 RAM (2 Kbytes) 0x00 07FF 512 bytes stack Reserved 0x00 4000 0x00 43FF 0x00 4400 0x00 47FF 0x00 4800 0x00 487F 0x00 4900 1 Kbyte data EEPROM Reserved Option bytes Reserved 0x00 4FFF 0x00 5000 GPIO and periph. reg. 0x00 57FF 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 CPU/SWIM/debug/ITC registers 32 interrupt vectors 0x00 807F Flash program memory (16 to 32 Kbytes) 0x00 FFFF 0x01 0000 Reserved 0x02 7FFF The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. DocID14771 Rev 12 29/124 Memory and register map STM8S105xx Table 7: Flash, Data EEPROM and RAM boundary addresses Memory area Size (bytes) Start address End address Flash program memory 32K 0x00 8000 0x00 FFFF 16K 0x00 8000 0x00 BFFF RAM 2K 0x00 0000 0x00 07FF Data EEPROM 1024 0x00 4000 0x00 43FF 6.2 Register map 6.2.1 I/O port hardware register map Table 8: I/O port hardware register map Address 30/124 Block Register label Register name Reset status 0x00 5000 Port A PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX 0x00 5002 PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 Port B PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX 0x00 5007 PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 DocID14771 Rev 12 STM8S105xx Address Memory and register map Block Register label Register name Reset status 0x00 500A Port C PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xXX 0x00 500C PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F Port D PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX 0x00 5011 PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 Port E PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xXX 0x00 5016 PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 Port F PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xXX 0x00 501B PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 DocID14771 Rev 12 31/124 Memory and register map Address 32/124 Block STM8S105xx Register label Register name Reset status 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E Port G PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX 0x00 5020 PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 Port H PH_ODR Port H data output latch register 0x00 0x00 5024 PH_IDR Port H input pin value register 0xXX 0x00 5025 PH_DDR Port H data direction register 0x00 0x00 5026 PH_CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 Port I PI_ODR Port I data output latch register 0x00 0x00 5029 PI_IDR Port I input pin value register 0xXX 0x00 502A PI_DDR Port I data direction register 0x00 0x00 502B PI_CR1 Port I control register 1 0x00 0x00 502C PI_CR2 Port I control register 2 0x00 DocID14771 Rev 12 STM8S105xx 6.2.2 Memory and register map General hardware register map Table 9: General hardware register map Address Block Register label Register name Reset status 0x00 5050 to 0x00 5059 Reserved area (10 bytes) 0x00 505A Flash FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control 0xFF register 2 0x00 505D FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF 0x00 505F FLASH _IAPSR Flash in-application programming status register 0x00 5060 to 0x00 5061 Reserved area (2 bytes) 0x00 5062 Flash 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash 0x00 5065 to 0x00 509F Reserved area (59 bytes) 0x00 50A0 ITC 0x00 50A1 FLASH _PUKR 0x00 Flash program memory unprotection register 0x00 Data EEPROM unprotection register 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 FLASH _DUKR DocID14771 Rev 12 33/124 Memory and register map STM8S105xx Address Block 0x00 50A2 to 0x00 50B2 Reserved area (17 bytes) 0x00 50B3 RST 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 CLK 0x00 50C1 34/124 Register label Register name Reset status Reset status register 0xXX CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 RST_SR 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK (1) CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 0xFF 1 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 0xFF 2 0x00 50CB CLK_CANCCR 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming 0x00 register 0x00 50CD CLK_SWIMCCR SWIM clock control register CAN clock control register DocID14771 Rev 12 0x00 0x00 0bXXXX XXX0 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 50CE to 0x00 50D0 Reserved area (3 bytes) 0x00 50D1 WWDG WWDG_CR WWDG control register 0x7F 0x00 50D2 WWDG_WR WWDR window register 0x7F IWDG_KR IWDG key register 0xXX 0x00 50E1 IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register 0xFF 0x00 50D3 to 0x00 50DF Reserved area (13 bytes) 0x00 50E0 IWDG 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 AWU (2) AWU_CSR1 AWU control/ status register 1 0x00 0x00 50F1 AWU_APR AWU asynchronous prescaler 0x3F buffer register 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/ status register 0x1F SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 50F3 BEEP 0x00 50F4 to 0x00 50FF Reserved area (12 bytes) 0x00 5200 SPI DocID14771 Rev 12 35/124 Memory and register map Address STM8S105xx Register label Register name Reset status 0x00 5204 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF 0x00 5208 to Block Reserved area (8 bytes) 0x00 520F 0x00 5210 36/124 2 I C 2 0x00 2 0x00 2 0x00 2 0x00 I2C_CR1 I C control register 1 0x00 5211 I2C_CR2 I C control register 2 0x00 5212 I2C_FREQR I C frequency register 0x00 5213 I2C_OARL I C Own address register low 0x00 5214 I2C_OARH I C own address register high 0x00 0x00 5215 Reserved 0x00 5216 I2C_DR I C data register 0x00 5217 I2C_SR1 I C status register 1 0x00 5218 I2C_SR2 I C status register 2 0x00 5219 I2C_SR3 I C status register 3 0x00 521A I2C_ITR I C interrupt control register 0x00 521B I2C_CCRL I C clock control register low 0x00 521C I2C_CCRH I C clock control register high 0x00 521D I2C_TRISER I C TRISE register 2 2 0x00 2 0x00 2 0x00 2 0x00 2 0x00 2 0x00 2 0x00 2 0x02 DocID14771 Rev 12 STM8S105xx Address Memory and register map Block 0x00 521E 0x00 521F to Register label Register name I2C_PECR I C packet error checking register 0x00 UART2 status register 0xC0 2 Reset status Reserved area (17 bytes) 0x00 522F 0x00 5230 to 0x00 523F Reserved area (6 bytes) 0x00 5240 UART2 UART2_SR 0x00 5241 UART2_DR UART2 data register 0xXX 0x00 5242 UART2_BRR1 UART2 baud rate register 1 0x00 0x00 5243 UART2_BRR2 UART2 baud rate register 2 0x00 0x00 5244 UART2_CR1 UART2 control register 1 0x00 0x00 5245 UART2_CR2 UART2 control register 2 0x00 0x00 5246 UART2_CR3 UART2 control register 3 0x00 0x00 5247 UART2_CR4 UART2 control register 4 0x00 0x00 5248 UART2_CR5 UART2 control register 5 0x00 0x00 5249 UART2_CR6 UART2 control register 6 0x00 0x00 524A UART2_GTR UART2 guard time register 0x00 0x00 524B UART2_PSCR UART2 prescaler register 0x00 TIM1_CR1 TIM1 control register 1 0x00 TIM1_CR2 TIM1 control register 2 0x00 0x00 524C to 0x00 524F Reserved area (4 bytes) 0x00 5250 TIM1 0x00 5251 DocID14771 Rev 12 37/124 Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/ compare mode 0x00 register 1 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode 0x00 register 2 0x00 525A TIM1_CCMR3 TIM1 capture/ compare mode 0x00 register 3 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode 0x00 register 4 0x00 525C TIM1_CCER1 TIM1 capture/ compare enable 0x00 register 1 0x00 525D TIM1_CCER2 TIM1 capture/compare enable 0x00 register 2 38/124 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 DocID14771 Rev 12 STM8S105xx Address Memory and register map Block Register label Register name 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/ compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/ compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/ compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/ compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/ compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/ compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/ compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/ compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 0x00 5270 to 0x00 52FF Reserved area (147 bytes) 0x00 5300 TIM2 TIM2_CR1 TIM2 control register 1 DocID14771 Rev 12 Reset status 0x00 39/124 Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/ compare mode 0x00 register 1 0x00 5306 TIM2_CCMR2 TIM2 capture/ compare mode 0x00 register 2 0x00 5307 TIM2_CCMR3 TIM2 capture/ compare mode 0x00 register 3 40/124 0x00 5308 TIM2_CCER1 TIM2 capture/ compare enable 0x00 register 1 0x00 5309 TIM2_CCER2 TIM2 capture/ compare enable 0x00 register 2 0x00 530A TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00 0x00 530C TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 530F TIM2_CCR1H TIM2 capture/ compare register 1 high 0x00 0x00 5310 TIM2_CCR1L TIM2 capture/ compare register 1 low 0x00 DocID14771 Rev 12 STM8S105xx Address Memory and register map Block Register label Register name 0x00 5311 TIM2_CCR2H TIM2 capture/ compare reg. 2 0x00 high 0x00 5312 TIM2_CCR2L TIM2 capture/ compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture/ compare register 3 high 0x00 0x00 5314 TIM2_CCR3L TIM2 capture/ compare register 3 low 0x00 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3_CCMR1 TIM3 capture/ compare mode 0x00 0x00 5315 to 0x00 531F Reserved area (11 bytes) 0x00 5320 TIM3 Reset status register 1 0x00 5326 TIM3_CCMR2 TIM3 capture/ compare mode 0x00 register 2 0x00 5327 TIM3_CCER1 TIM3 capture/ compare enable 0x00 register 1 0x00 5328 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 DocID14771 Rev 12 41/124 Memory and register map Address 42/124 STM8S105xx Block Register label Register name 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 532D TIM3_CCR1H TIM3 capture/ compare register 1 high 0x00 0x00 532E TIM3_CCR1L TIM3 capture/ compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/ compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/ compare register 2 low 0x00 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 5343 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF ADC data buffer registers 0x00 0x00 5331 to 0x00 533F Reserved area (15 bytes) 0x00 5340 TIM4 0x00 5347 to 0x00 53DF Reserved area (153 bytes) 0x00 53E0 to 0x00 53F3 ADC1 ADC _DBxR DocID14771 Rev 12 Reset status 0x00 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 53F4 to 0x00 53FF Reserved area (12 bytes) 0x00 5400 ADC1 ADC _CSR ADC control/ status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable 0x00 register high 0x00 5407 ADC_TDRL ADC Schmitt trigger disable 0x00 register low 0x00 5408 ADC_HTRH ADC high threshold register high 0x03 0x00 5409 ADC_HTRL ADC high threshold register low 0xFF 0x00 540A ADC_LTRH ADC low threshold register high 0x00 0x00 540B ADC_LTRL ADC low threshold register low 0x00 0x00 540C ADC_AWSRH ADC analog watchdog status 0x00 register high 0x00 540D ADC_AWSRL ADC analog watchdog status 0x00 register low DocID14771 Rev 12 43/124 Memory and register map Address STM8S105xx Block 0x00 540E Register label Register name Reset status ADC _AWCRH ADC analog watchdog control 0x00 register high 0x00 540F ADC_AWCRL ADC analog watchdog control 0x00 register low 0x00 5410 to 0x00 57FF 6.2.3 Reserved area (1008 bytes) (1) Depends on the previous reset source. (2) Write only register. CPU/SWIM/debug module/interrupt controller registers Table 10: CPU/SWIM/debug module/interrupt controller registers 44/124 Address Block Register label Register name Reset status 0x00 7F00 CPU A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x07 0x00 7F09 SPL Stack pointer low 0xFF (1) DocID14771 Rev 12 STM8S105xx Address Memory and register map Block 0x00 7F0A Register label Register name Reset status CCR Condition code register 0x28 0x00 7F0B to Reserved area (85 bytes) 0x00 7F5F 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF SWIM control status register 0x00 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F78 to Reserved area (2 bytes) 0x00 7F79 0x00 7F80 SWIM SWIM_CSR 0x00 7F81 to Reserved area (15 bytes) 0x00 7F8F 0x00 7F90 DM DocID14771 Rev 12 45/124 Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status 0x10 register 1 0x00 7F99 DM_CSR2 DM debug module control/status 0x00 register 2 0x00 7F9A DM_ENFCTR DM enable function register 0x00 7F9B to Reserved area (5 bytes) 0x00 7F9F (1) 46/124 Accessible by debug module only DocID14771 Rev 12 0xFF STM8S105xx 7 Interrupt vector mapping Interrupt vector mapping Table 11: Interrupt mapping IRQ no. Source block Description Wakeup from halt mode Wakeup from Vector active-halt address mode RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt - - 0x00 8004 0 TLI External top level interrupt - - 0x00 8008 1 AWU Auto wake up from halt - Yes 0x00 800C 2 CLK Clock controller - - 0x00 8010 3 EXTI0 Port A external interrupts Yes Yes 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 (1) (1) 8 0x00 8028 9 Reserved - - 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIM1 TIM1 update/ overflow/ underflow/ trigger/ break - - 0x00 8034 12 TIM1 TIM1 capture/ compare - - 0x00 8038 13 TIM2 TIM update/ overflow - - 0x00 803C 14 TIM2 TIM capture/ compare - - 0x00 8040 DocID14771 Rev 12 47/124 Interrupt vector mapping STM8S105xx IRQ no. Source block Description Wakeup from halt mode Wakeup from Vector active-halt address mode 15 TIM3 Update/ overflow - - 0x00 8044 16 TIM3 Capture/ compare - - 0x00 8048 17 Reserved - - 0x00 804C 18 Reserved - - 0x00 8050 2 2 19 I C I C interrupt Yes Yes 0x00 8054 20 UART2 Tx complete - - 0x00 8058 21 UART2 Receive register DATA FULL - - 0x00 805C 22 ADC1 ADC1 end of conversion/ analog watchdog interrupt - 0x00 8060 23 TIM4 TIM update/ overflow - - 0x00 8064 24 Flash EOP/ WR_PG_DIS - - 0x00 8068 Reserved (1) 48/124 0x00 806C to 0x00 807C Except PA1 DocID14771 Rev 12 STM8S105xx 8 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below. Option bytes can also be modified `on the fly' by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 12: Option bytes Addr. Option name Option Option bits byte no. 7 6 5 4 3 2 1 0 Factory default setting 0x4800 Read-out protection (ROP) OPT0 ROP [7:0] 00h 0x4801 User boot code(UBC) OPT1 UBC [7:0] 00h NOPT1 NUBC [7:0] FFh Alternate function remapping (AFR) OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 00h NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 FFh Miscell. option OPT3 Reserved HSI TRIM LSI_ EN IWDG _HW WWDG _HW WWDG _HALT 00h NOPT3 Reserved NHSI TRIM NLSI_ EN NIWDG _HW NWWDG _HW NWW G_HALT FFh OPT4 Reserved EXT CLK CKAWU SEL PRS C1 PRS C0 00h NOPT4 Reserved NEXT CLK NCKA WUSEL NPRSC1 NPR SC0 FFh OPT5 HSECNT [7:0] 00h NOPT5 NHSECNT [7:0] FFh Reserved 00h 0x4802 0x4803 0x4804 0x4805h 0x4806 0x4807 Clock option 0x4808 0x4809 HSE clock startup 0x480A 0x480B Reserved OPT6 DocID14771 Rev 12 49/124 Option bytes Addr. Option name STM8S105xx Option Option bits byte no. 7 NOPT6 0x480C 0x480D Reserved NOPT7 0x480E 0x487E OPT7 Bootloader OPTBL NOPTBL 0x487F 6 5 4 3 2 1 0 Factory default setting Reserved FFh Reserved 00h Reserved FFh BL[7:0] 00h NBL[7:0] FFh Table 13: Option byte description Option byte no. Description OPT0 ROP[7:0] Memory readout protection (ROP) AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 to 1 defined as UBC, memory write-protected 0x02: Page 0 to 3 defined as UBC, memory write-protected 0x03: Page 0 to 4 defined as UBC, memory write-protected ... 0x3E: Pages 0 to 63 defined as UBC, memory write-protected Other values: Reserved Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details. OPT2 AFR[7:0] Refer to following table for the alternate function remapping decriptions of bits [7:2]. OPT3 HSITRIM:High speed internal clock trimming register size 0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register 50/124 DocID14771 Rev 12 STM8S105xx Option byte no. Option bytes Description LSI_EN:Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active OPT4 EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN CKAWUSEL:Auto wake-up unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 HSECNT[7:0]:HSE crystal oscillator stabilization time 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles DocID14771 Rev 12 51/124 Option bytes STM8S105xx Option byte no. Description OPT6 Reserved OPT7 Reserved OPTBL BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details. Table 14: Description of alternate function remapping bits [7:0] of OPT2 (1) Option byte no. Description OPT2 AFR7 Alternate function remapping option 7 (2) 0: AFR7 remapping option inactive: Default alternate function . 1: Port D4 alternate function = BEEP. AFR6 Alternate function remapping option 6 (2) 0: AFR6 remapping option inactive: Default alternate functions . 2 1: Port B5 alternate function = I C_SDA; port B4 alternate function 2 = I C_SCL. AFR5 Alternate function remapping option 5 (2) 0: AFR5 remapping option inactive: Default alternate functions . 1: Port B3 alternate function = TIM1_ETR; port B2 alternate function = TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0 alternate function = TIM1_CH1N. AFR4 Alternate function remapping option 4 (2) 0: AFR4 remapping option inactive: Default alternate function . 1: Port D7 alternate function = TIM1_CH4. AFR3 Alternate function remapping option 3 (2) 0: AFR3 remapping option inactive: Default alternate function . 1: Port D0 alternate function = TIM1_BKIN. AFR2 Alternate function remapping option 2 52/124 DocID14771 Rev 12 STM8S105xx Option bytes Option byte no. (1) Description (2) 0: AFR2 remapping option inactive: Default alternate function . 1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has priority over AFR3 if both are activated. AFR1 Alternate function remapping option 1 (2) 0: AFR1 remapping option inactive: Default alternate functions . 1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3. AFR0 Alternate function remapping option 0 (2) 0: AFR0 remapping option inactive: Default alternate function . 1: Port D3 alternate function = ADC_ETR. (1) Do not use more than one remapping option in the same port. (2) Refer to pinout description. DocID14771 Rev 12 53/124 Unique ID 9 STM8S105xx Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: For use as serial numbers * use as security keys to increase the code security in the program memory while using * For and combining this unique ID with software cryptograhic primitives and protocols before programming the internal memory. * To activate secure boot processes Table 15: Unique ID registers (96 bits) Address Content description 0x48CD 0x48CE 0x48CF 7 6 5 4 3 U_ID[7:0] X co-ordinate on the wafer U_ID[15:8] U_ID[23:16] 0x48D0 Y co-ordinate on the wafer 0x48D1 Wafer number U_ID[39:32] U_ID[31:24] 0x48D2 U_ID[47:40] 0x48D3 U_ID[55:48] 0x48D4 U_ID[63:56] 0x48D5 54/124 Unique ID bits Lot number U_ID[71:64] 0x48D6 U_ID[79:72] 0x48D7 U_ID[87:80] 0x48D8 U_ID[95:88] DocID14771 Rev 12 2 1 0 STM8S105xx Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Typical current consumption For typical current consumption measurements, VDD, VDDIO and VDDA are connected together in the configuration shown in the following figure. Figure 8: Supply current measurement conditions 5 V or 3.3 V A V DD V DDA V DDIO V SS VSSA VSSIO DocID14771 Rev 12 55/124 Electrical characteristics 10.1.5 STM8S105xx Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. Figure 9: Pin loading conditions STM8 PIN 50 pF 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. Figure 10: Pin input voltage STM8 PIN VIN 10.2 Absolute maximum ratings Stresses above those listed as `absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 16: Voltage characteristics 56/124 Symbol Ratings Min Max Unit VDDx - VSS Supply voltage (including VDDA and VDDIO) -0.3 6.5 V VIN Input voltage on true open drain pins (PE1, (2) PE2) VSS - 0.3 6.5 (1) DocID14771 Rev 12 STM8S105xx Symbol Electrical characteristics Ratings (2) Input voltage on any other pin |VDDx VDD| Min Max VSS - 0.3 VDD + 0.3 Variations between different power pins 50 |VSSx - VSS| Variations between all the different ground pins VESD Unit Electrostatic discharge voltage mV 50 see Absolute maximum ratings (electrical sensitivity) (1) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply (2) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected Table 17: Current characteristics (1) Symbol Ratings IVDD Total current into VDD power lines (source) IVSS IIO IIO Max. Unit (2) 60 mA Total current out of VSS ground lines (sink) (2) 60 Output current sunk by any I/O and control pin 20 Output current source by any I/Os and control pin 20 Total output current sourced (sum of all I/O and control 200 (3) pins) for devices with two VDDIO pins Total output current sourced (sum of all I/O and control 100 (3) pins) for devices with one VDDIO pin Total output current sunk (sum of all I/O and control (3) pins) for devices with two VSSIO pins 160 Total output current sunk (sum of all I/O and control (3) pins) for devices with one VSSIO pin 80 DocID14771 Rev 12 57/124 Electrical characteristics Symbol IINJ(PIN) (4) (5) STM8S105xx (1) Ratings Max. Injected current on NRST pin 4 Injected current on OSCIN pin 4 (6) Injected current on any other pin IINJ(PIN) (1) (4) Unit 4 (6) Total injected current (sum of all I/O and control pins) 20 Data based on characterization results, not tested in production. (2) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. (3) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package between the VDDIO/VSSIO pins. (4) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected (5) Negative injection disturbs the analog performance of the device. See note in I2C interface characteristics. (6) When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 18: Thermal characteristics 10.3 Symbol Ratings Value Unit TSTG Storage temperature range -65 to 150 C TJ Maximum junction temperature 150 Operating conditions The device must be used in operating conditions that respect the parameters in the table below. In addition, full account must be taken of all physical capacitor characteristics and tolerances. 58/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Table 19: General operating conditions Symbol Parameter fCPU VDD/ VDD_IO Conditions Min Max Unit Internal CPU clock frequency 0 16 MHz Standard operating voltage 2.95 5.5 V CEXT: capacitance of external capacitor 470 3300 nF 0.3 Ohm 15 nH 443 mW (1) VCAP ESR of external capacitor at 1 MHz (2) - ESL of external capacitor PD (3) Power dissipation at TA = 85 C for suffix 6or TA= 125 C for suffix 3 44 and 48-pin devices, with output on eight standard ports, two high sink ports and two open drain ports (4) simultaneously 32-pin package, with output on eight standard ports and two high sink (4) ports simultaneously TA TJ - - - 360 Ambient temperature for 6 suffix version Maximum power dissipation -40 85 Ambient temperature for 3 suffix version Maximum power dissipation -40 125 Junction temperature range 6 suffix version -40 105 3 suffix version -40 130 C (1) Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. DocID14771 Rev 12 59/124 Electrical characteristics STM8S105xx (2) This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator. (3) To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/JA (see Thermal characteristics ) with the value for TJmax given in the current table and the value for JA given in Thermal characteristics. (4) Refer to Thermal characteristics Figure 11: fCPUmax versus VDD f CPU (MHz) Functionality 16 not guaranteed in this area 12 Functionality guaranteed @TA-40 to 125 C 8 4 0 2.95 4.0 5.0 5.5 Supply voltage Table 20: Operating conditions at power-up/power-down Symbol Parameter tVDD VDD rise time rate 2.0 VDD fall time rate 2.0 Min Typ Max Unit (1) s/V (1) VDD rising 1.7 (1) tTEMP Reset releasedelay VIT+ Power-on reset threshold 2.65 2.8 2.95 VIT- Brown-out reset threshold 2.58 2.7 2.88 VHYS(BOR) Brown-out reset hysteresis (1) 60/124 Conditions 70 Guaranteed by design, not tested in production. DocID14771 Rev 12 ms V mV STM8S105xx 10.3.1 Electrical characteristics VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH. Figure 12: External capacitor CEXT ESL C ESR RLeak 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in Pin input voltage. 10.3.2.1 Total current consumption in run mode Table 21: Total current consumption with code execution in run mode at VDD = 5 V Symbol Parameter (1) Conditions IDD(RUN) Supply fCPU = fMASTER current in run = 16 MHz mode, code executed from RAM HSE crystal osc. Typ Max Unit 3.2 mA (16 MHz) HSE user ext. clock 2.6 3.2 2.5 3.2 1.6 2.2 1.3 2.0 (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = HSE user ext. clock 125 kHz (16 MHz) HSI RC osc. (16 MHz) DocID14771 Rev 12 61/124 Electrical characteristics Symbol Parameter IDD(RUN) STM8S105xx (1) Conditions Typ Max fCPU = fMASTER/128 = HSI RC osc. 15.625 kHz (16 MH3z/8) 0.75 fCPU = fMASTER LSI RC osc. 0.55 = 128 kHz (128 kHz) Supply fCPU = fMASTER current in run = 16 MHz mode, code executed fromFlash HSE crystal osc. Unit 7.7 (16 MHz) HSE user ext. clock 7.0 8.0 7.0 8.0 (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER = 2 MHz HSI RC osc. 1.5 (2) (16 MHz/8) fCPU = fMASTER/128 = HSI RC osc. 125 kHz (16 MHz) 1.35 2.0 fCPU = fMASTER/128 = HSI RC osc. 15.625 kHz (16 MHz/8) 0.75 fCPU = fMASTER LSI RC osc. 0.6 = 128 kHz (128 kHz) (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V (1) Symbol Parameter Conditions IDD(RUN) Supply current in run 62/124 fCPU = fMASTER = 16 MHz HSE crystal osc. (16 MHz) DocID14771 Rev 12 Typ Max Unit 2.8 mA STM8S105xx Electrical characteristics (1) Symbol Parameter Conditions mode, code executed from RAM Typ Max HSE user ext. clock 2.6 3.2 2.5 3.2 1.6 2.2 1.3 2.0 Unit (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 HSE user ext. clock = 125 kHz (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 fCPU = fMASTER = 128 kHz LSI RC osc. 0.55 (128 kHz) Supply fCPU = fMASTER = 16 MHz current in run mode, code executed from Flash HSE crystal osc. 7.3 (16 MHz) HSE user ext. clock 7.0 8.0 7.0 8.0 (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER = 2 MHz HSI RC osc. 1.5 (2) (16 MHz/8) fCPU = fMASTER/128 HSI RC osc. = 125 kHz (16 MHz) fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. 1.35 2.0 0.75 (16 MHz/8) DocID14771 Rev 12 63/124 Electrical characteristics STM8S105xx (1) Symbol Parameter Conditions fCPU = fMASTER = 128 kHz Typ Max LSI RC osc. Unit 0.6 (128 kHz) 10.3.2.2 (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Total current consumption in wait mode Table 23: Total current consumption in wait mode at VDD = 5 V Symbol Parameter Conditions IDD(WFI) Supply current in wait mode fCPU = fMASTER = 16 MHz (1) HSE crystal osc. Typ Max Unit 2.15 mA (16 MHz) HSE user ext. clock 1.55 2.0 (16 MHz) HSI RC osc. 1.5 (16 MHz) fCPU = fMASTER/128 = 125 kHz HSI RC osc. fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz) 0.7 (2) (16 MHz/8) fCPU = fMASTER = 128 LSI RC osc. kHz (128 kHz) 64/124 1.3 (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. DocID14771 Rev 12 0.5 1.9 STM8S105xx Electrical characteristics Table 24: Total current consumption in wait mode at VDD = 3.3 V (1) Symbol Parameter Conditions Typ Max Unit IDD(WFI) Supply current in wait mode fCPU = fMASTER = 16 HSE crystal osc. MHz (16 MHz) 1.75 mA HSE user ext. clock 1.55 2.0 (16 MHz) HSI RC osc. 1.5 1.9 (16 MHz) 10.3.2.3 fCPU = fMASTER/128 = 125 kHz HSI RC osc. fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. fCPU = fMASTER = 128 kHz LSI RC osc. 1.3 (16 MHz) 0.7 (2) (16 MHz/8) 0.5 (128 kHz) (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Total current consumption in active halt mode Table 25: Total current consumption in active halt mode at VDD = 5 V Symbol Parameter Conditions Typ (3) Main Flash mode voltage regulator (2) (MVR) IDD(AH) Supply On current in active halt mode Operating mode Clock source HSE crystal osc. Max at 85 (1) C Max at Unit 125 (1) C 1080 A (16 MHz) LSI RC osc. DocID14771 Rev 12 200 320 400 65/124 Electrical characteristics STM8S105xx Symbol Parameter Conditions Typ (3) Main Flash mode voltage regulator (2) (MVR) Max at 85 (1) C Max at Unit 125 (1) C 140 270 350 68 120 220 12 60 150 Clock source (128 kHz) Power-down mode HSE crystal osc. 1030 (16 MHz) LSI RC osc. (128 kHz) Off Operating mode LSI RC osc. (128 kHz) Power-down mode (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. Table 26: Total current consumption in active halt mode at VDD = 3.3 V Symbol Parameter Conditions Main Flash (3) voltage mode regulator (2) (MVR) IDD(AH) Supply current in active halt mode On Operating mode Typ Max Max at Unit at 85 125 (1) (1) C C Clock source HSE crystal osc. A (16 MHz) LSI RC osc. (128 kHz) 66/124 680 DocID14771 Rev 12 200 320 400 STM8S105xx Electrical characteristics Symbol Parameter Conditions Main Flash (3) voltage mode regulator (2) (MVR) Typ Max Max at Unit at 85 125 (1) (1) C C Clock source Power-down HSE crystal mode osc. 630 (16 MHz) Off Operating mode LSI RC osc. (128 kHz) 140 270 350 LSI RC osc. (128 kHz) 66 120 220 10 60 150 Power-down mode 10.3.2.4 (1) Data based on characterization results, not tested in production. (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. Total current consumption in halt mode Table 27: Total current consumption in halt mode at VDD = 5 V Symbol Parameter Conditions Typ Max at Max at Unit (1) 85 C 125 (1) C IDD(H) Supply current in halt mode Flash in operating mode, HSI clock after wakeup 62 90 150 Flash in powerdown mode, HSI clock after wakeup 6.5 25 80 (1) A Data based on characterization results, not tested in production. DocID14771 Rev 12 67/124 Electrical characteristics STM8S105xx Table 28: Total current consumption in halt mode at VDD = 3.3 V Symbol Parameter Conditions IDD(H) Supply current in halt mode Flash in operating mode, HSI 60 clock after wakeup 90 150 Flash in powerdown mode, HSI clock after wakeup 20 80 (1) 10.3.2.5 Typ Max at Max at Unit (1) 85 C 125 (1) C 4.5 A Data based on characterization results, not tested in production. Low power mode wakeup times Table 29: Wakeup times Symbol Parameter Wakeup time from tWU(WFI) fCPU = fMASTER = 16 MHz Wakeup time active MVR voltage halt mode to run regulator Flash in operating (5) mode HSI (after on Wakeup time active MVR voltage Flash in HSI halt mode to run regulator (after (4) on Wakeup time active MVR voltage halt mode to run regulator (3) power-down mode (4) Flash in operating (6) (5) mode s HSI (after off Wakeup time active MVR voltage Flash in HSI halt mode to run regulator (after (4) (6) 2 3 wakeup) mode (3) (6) 1 wakeup) (5) mode Unit 0.56 mode (3) 68/124 (4) (1) Max See (2) note 0 to 16 MHz mode (3) tWU(H) Typ wait mode to run (3) tWU(AH) Conditions (6) 48 wakeup) power-down (5) mode off mode Wakeup time from Flash in operating mode halt mode to run Flash in power-down mode (6) 50 wakeup) (5) 52 (5) DocID14771 Rev 12 54 STM8S105xx Symbol Electrical characteristics Parameter Conditions Typ (1) Unit Max (3) mode (1) Data guaranteed by design, not tested in production. (2) tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU. (3) Measured from interrupt event to interrupt vector fetch. (4) Configured by the REGAH bit in the CLK_ICKR register. (5) Configured by the AHALT bit in the FLASH_CR1 register. (6) Plus 1 LSI clock depending on synchronization. 10.3.2.6 Total current consumption and timing in forced reset state Table 30: Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ IDD(R) Supply current in reset (2) state VDD = 5 V 500 VDD = 3.3 V 400 tRESETBL Unit A Reset pin release to vector fetch 150 (1) Data guaranteed by design, not tested in production. (2) Characterized with all I/Os tied to VSS. 10.3.2.7 (1) Max s Current consumption of on-chip peripherals Subject to general operating conditions for VDD and TA. HSI internal RC/fCPU = fMASTER = 16 MHz. Table 31: Peripheral current consumption Symbol Parameter Typ. IDD(TIM1) TIM1 supply current (1) Unit 230 A IDD(TIM2) TIM2 supply current (1) DocID14771 Rev 12 115 69/124 Electrical characteristics STM8S105xx Symbol Parameter IDD(TIM3) TIM3 timer supply current (1) 90 IDD(TIM4) TIM4 timer supply current (1) 30 IDD(UART2) UART2 supply current IDD(SPI) SPI supply current IDD(I 2 (2) 2 C) IDD(ADC1) Typ. I C supply current Unit 110 (2) 45 (2) 65 (3) ADC1 supply current when converting 955 (1) Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. (2) Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production. (3) Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Not tested in production. 10.3.2.8 Current consumption curves The following figures show typical current consumption measured with code executing in RAM. Figure 13: Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz 70/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 14: Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V Figure 15: Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz DocID14771 Rev 12 71/124 Electrical characteristics STM8S105xx Figure 16: Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V 72/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 32: HSE user external clock characteristics Symbol Parameter fHSE_ext VHSEH (1) VHSEL (1) ILEAK_HSE (1) Conditions Min Max Unit User external clock source frequency 0 16 MHz OSCIN input pin high level voltage 0.7 x VDD VDD + 0.3 V V OSCIN input pin low level voltage OSCIN input leakage current VSS < VIN < VDD VSS 0.3 x VDD -1 +1 A Data based on characterization results, not tested in production. DocID14771 Rev 12 73/124 Electrical characteristics STM8S105xx Figure 19: HSE external clocksource V HSEH V HSEL External clock source fHSE OSCIN STM8 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 33: HSE oscillator characteristics Symbol Parameter Conditions fHSE External high speed Feedback resistor (1) C Typ 1 oscillator frequency RF Min Max Unit 16 MHz 220 k Recommended load 20 (2) capacitance IDD(HSE) HSE oscillator power consumption pF C = 20 pF, 6 (startup) fOSC = 16 MHz 1.6 (stabilized) (3) mA gm C = 10 pF, 6 (startup) fOSC =16 MHz 1.2 (stabilized) Oscillator 5 transconductance tSU(HSE) (1) (3) (4) Startup time VDD is stabilized C is approximately equivalent to 2 x crystal Cload. 74/124 DocID14771 Rev 12 mA/V 1 ms STM8S105xx Electrical characteristics (2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details (3) Data based on characterization results, not tested in production. (4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 20: HSE oscillator circuit diagram Rm f HSE to core Lm CO RF CL1 Cm OSCIN gm Resonator Consumption control Resonator OSCOUT CL2 STM8 HSE oscillator critical g m equation 2 2 gmcrit= (2 x x fHSE) x Rm(2Co + C) Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1= CL2 = C: Grounded external capacitance gm >> gmcrit 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI) Table 34: HSI oscillator characteristics Symbol Parameter fHSI Conditions Frequency Min Typ 16 DocID14771 Rev 12 Max Unit MHz 75/124 Electrical characteristics STM8S105xx Symbol Parameter Conditions ACCHSI Accuracy of HSI oscillator User-trimmed with CLK_HSITRIMR register for given VDD and TA (1) conditions Accuracy of HSI oscillator (factory calibrated) tsu(HSI) Min (3) Typ Max (2) 1.0 VDD = 5 V, TA = 25C -1.0 1.0 VDD = 5 V, 25 C TA 85 C -2.0 2.0 2.95 VDD 5.5 V,-40 C TA 125 C -3.0 (3) (3) (2) 1.0 170 (1) Refer to application note. (2) Guaranteed by design, not tested in production. (3) Data based on characterization results, not tested in production. DocID14771 Rev 12 (3) 250 Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temperatures 76/124 % 3.0 HSI oscillator wakeup time including calibration IDD(HSI) HSI oscillator power consumption Unit s A STM8S105xx Electrical characteristics Figure 22: Typical HSI accuracy vs VDD @ 4 temperatures Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 35: LSI oscillator characteristics Symbol Parameter Min Typ Max Unit fLSI Frequency 110 128 146 kHz tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator power consumption (1) (1) 7 5 s A Guaranteeed by design, not tested in production. DocID14771 Rev 12 77/124 Electrical characteristics STM8S105xx Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures 10.3.5 Memory characteristics RAM and hardware registers Table 36: RAM and hardware registers Symbol Parameter VRM Data retention mode (1) Conditions Min Unit Halt mode (or reset) VIT-max (2) V (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. refer to Operating conditions for the value of VIT-max (2) Refer to the Operating conditions section for the value of VIT-max Flash program memory/data EEPROM memory General conditions: TA = -40 to 125C. Table 37: Flash program memory/data EEPROM memory 78/124 (1) Symbol Parameter Conditions Min VDD Operating voltage (all modes, execution/write/erase) fCPU 16 MHz 2.95 tprog Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) DocID14771 Rev 12 Typ 6.0 Max Unit 5.5 V 6.6 ms STM8S105xx Electrical characteristics Symbol Parameter (1) Conditions Typ Max Unit Fast programming time for 1 block (128 bytes) 3.0 3.3 ms terase Erase time for 1 block (128 bytes) 3.0 3.3 ms NRW Erase/write cycles (program memory) (2) (2) Erase/write cycles(data memory) tRET IDD (1) Min TA = +85 C 10 k TA = +125 C 300 k Data retention (program memory) TRET = 55 C after 10k erase/write cycles at TA = +85 C 20 Data retention (data memory) after TRET = 55 C 10k erase/write cycles at TA = +85 C 20 Data retention (data memory) after TRET = 85 C 300 k erase/write cyclesat TA = +125 C 1.0 Supply current (Flash programming or erasing for 1 to 128 bytes) cycles 1.0M years 2.0 mA Data based on characterization results, not tested in production. (2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 38: I/O static characteristics Symbol Parameter Conditions VIL VDD = 5 V Input low level voltage DocID14771 Rev 12 Min -0.3 Typ Max 0.3 x VDD Unit V 79/124 Electrical characteristics STM8S105xx Symbol Parameter Conditions VIH Input high level voltage Vhys Hysteresis Rpu Pull-up resistor tR, tF Rise and fall Fast I/Os load = 50 pF time(10 % - 90 %) Min Typ 0.7 x VDD (1) Max Unit VDD + 0.3 V 700 VDD = 5 V, VIN = VSS 30 55 mV 80 k (3) 35 Standard and high sink I/OsLoad = 50 pF 125 Fast I/Os load = 20 pF 20 (3) Standard and high sink I/OsLoad = 20 pF 50 (3) Ilkg Input leakage current, analog and digital VSS VIN VDD Ilkg ana Analog input leakage current VSS VIN VDD Ilkg(inj) Leakage current in Injection current 4 mA (2) adjacent I/O (1) V (3) ns 1.0 (2) A 250 (2) nA (2) 1.0 A Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2) Data based on characterization results, not tested in production. (3) Data guaranteed by design. 80/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures Figure 25: Typical pull-up resistance vs VDD @ 4 temperatures DocID14771 Rev 12 81/124 Electrical characteristics STM8S105xx Figure 26: Typical pull-up current vs VDD @ 4 temperatures 1. The pull-up is a pure resistor (slope goes through 0). Table 39: Output driving current (standard ports) Symbol Parameter VOL VOH (1) Conditions Min Max Unit (1) Output low level with four pins IIO = 4 mA, sunk VDD = 3.3 V 1.0 Output low level with eight pins sunk IIO= 10 mA, 2.0 Output high level with four pins sourced IIO = 4 mA, Output high level with eight pins sourced IIO = 10 mA, V VDD = 5 V (1) 2.0 V VDD = 3.3 V 2.4 VDD = 5 V Data based on characterization results, not tested in production Table 40: Output driving current (true open drain ports) 82/124 Symbol Parameter Conditions Max VOL IIO = 10 mA, VDD = 3.3 V 1.5 Output low level with two pins sunk DocID14771 Rev 12 (1) Unit V STM8S105xx Electrical characteristics Symbol Parameter (1) Conditions Max IIO = 10 mA, VDD = 5 V 1.0 IIO = 20 mA, VDD = 5 V 2.0 Unit (1) Data based on characterization results, not tested in production Table 41: Output driving current (high sink ports) Symbol Parameter Conditions VOL Output low level with four pins sunk IIO = 10 mA, Output low level with eight pins sunk IIO = 10 mA, Output low level with four pins sunk IIO = 20 mA, Output high level with four pins sourced IIO = 10 mA, VOH (1) 10.3.7 Min Max (1) 1.1 Unit V VDD = 3.3 V 0.9 VDD = 5 V (1) 1.6 VDD = 5 V (1) 1.9 VDD = 3.3 V Output high level with eight pins IIO = 10 mA, sourced VDD = 5 V 3.8 Output high level with four pins sourced 2.9 IIO = 20 mA, (1) VDD = 5 V Data based on characterization results, not tested in production Typical output level curves The following figures show typical output level curves measured with output on a single pin. DocID14771 Rev 12 83/124 Electrical characteristics STM8S105xx Figure 27: Typ. VOL @ VDD = 5 V (standard ports) Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports) 84/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports) Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports) DocID14771 Rev 12 85/124 Electrical characteristics STM8S105xx Figure 31: Typ. VOL @ VDD = 5 V (high sink ports) Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports) 86/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports) Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports) DocID14771 Rev 12 87/124 Electrical characteristics STM8S105xx Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports) Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 10.3.8 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42: NRST pin characteristics Symbol Parameter Conditions VIL(NRST) NRST input low Min -0.3 (1) Typ Max - level voltage VIH(NRST) 88/124 NRST input high Unit 0.3 x VDD V IOL=2 mA 0.7 x VDD DocID14771 Rev 12 - VDD + 0.3 STM8S105xx Symbol Electrical characteristics Parameter Conditions NRST output low Max Unit - - 0.5 30 55 80 - - 75 (1) level voltage RPU(NRST) Typ (1) level voltage VOL(NRST) Min NRST pull-up (2) k resistor tI FP(NRST) NRST input filtered (3) pulse ns tIN FP(NRST) NRST input not (3) 500 - - 15 - - filtered pulse tOP(NRST) NRST output pulse (3) (1) Data based on characterization results, not tested in production. (2) The RPU pull-up equivalent resistor is based on a resistive transistor (3) Data guaranteed by design, not tested in production. s Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures DocID14771 Rev 12 89/124 Electrical characteristics STM8S105xx Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table 38: I/O static characteristics ), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF. 90/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 40: Recommended reset pin protection STM8 VDD RPU External reset circuit NRST Internal reset Filter 0.1 F (optional) 10.3.9 SPI serial peripheral interface Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 43: SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK1 SPI clock frequency Master mode 0 8 MHz Slave mode 0 6 tc(SCK) tr(SCK) SPI clock rise and fall time tf(SCK) tsu(NSS) th(NSS) (1) (1) tw(SCKH) (1) tw(SCKL) (1) tsu(MI) tsu(SI) (1) (1) Capacitive load: C = 30 pF 25 ns NSS setup time Slave mode 4x tMASTER ns NSS hold time Slave mode 70 ns SCK high and low time Master mode tSCK/2 15 Data input setup time Master mode 5 Data input setup time Slave mode 5 DocID14771 Rev 12 tSCK/2 + 15 ns ns ns 91/124 Electrical characteristics Symbol (1) th(MI) th(SI) (1) ta(SO) (1) (2) tdis(SO) tv(SO) tv(MO) th(SO) th(MO) (1) (3) (1) (1) (1) (1) STM8S105xx Parameter Conditions Min Data input hold time Master mode 7 Data input hold time Slave mode 10 Data output access time Slave mode Data output disable time Slave mode Data output valid time Slave mode Data output valid time Master mode Data output hold time Slave mode Max ns ns 3x tMASTER 25 (after enable edge) 36 28 (after enable edge) Master mode (after enable edge) 12 ns ns 73 (after enable edge) Unit ns ns ns ns (1) Values based on design simulation and/or characterization results, and not tested in production. (2) Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (3) Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. 92/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 41: SPI timing diagram - slave mode and CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN B I T1 IN LSB IN th(SI) ai14134 (1) Figure 42: SPI timing diagram - slave mode and CPHA = 1 NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) M SB IN B I T1 IN LSB IN ai14135 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. DocID14771 Rev 12 93/124 Electrical characteristics STM8S105xx (1) Figure 43: SPI timing diagram - master mode High NSS input SCK intput SCK output tc(SCK) CPHA= 0 CPOL=0 CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136b 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 10.3.10 2 I C interface characteristics 2 Table 44: I C characteristics Symbol Parameter 2 Standard mode I C (2) Min (2) Max 2 (1) Fast mode I C (2) Min Unit (2) Max tw(SCLL) SCL clock low time 4.7 1.3 s tw(SCLH) SCL clock high time 4.0 0.6 s tsu(SDA) SDA setup time 250 100 ns th(SDA) SDA data hold time 0 tr(SDA) tr(SCL) tf(SDA) tf(SCL) 94/124 (3) (4) 0 (3) 900 ns SDA and SCL rise time 1000 300 ns SDA and SCL fall time 300 300 ns DocID14771 Rev 12 STM8S105xx Symbol Electrical characteristics 2 Parameter Standard mode I C (2) (2) Min th(STA) START condition hold time tsu(STA) Repeated START condition setup time tsu(STO) STOP condition setup time tw(STO:STA) STOP to START condition time (bus free) Cb Max 2 (1) Fast mode I C (2) Unit (2) Min Max 4.0 0.6 s 4.7 0.6 s 4.0 0.6 s 4.7 1.3 s Capacitive load for each bus line 400 400 (1) fMASTER, must be at least 8 MHz to achieve max fast I C speed (400kHz). (2) Data based on standard I C protocol requirement, not tested in production. pF 2 2 (3) The maximum hold time of the start condition has only to be met if the interface does not stretch the low time. (4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 2 Figure 44: Typical application with I C bus and timing diagram VDD (1) VDD STM8S105xx SDA IC bus SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) th(STA) SCL tw(SCLH) tsu(SDA) tw(SCLL) tr(SCL) th(SDA) tf(SCL) S TOP tsu(STA:STO) tsu(STO) ai15385b 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD DocID14771 Rev 12 95/124 Electrical characteristics 10.3.11 STM8S105xx 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 45: ADC characteristics Symbol Parameter Conditions fADC ADC clock frequency Min Typ Max Unit VDDA =2.95 to 5.5 V 1.0 4.0 MHz VDDA =4.5 to 5.5 V 1.0 6.0 5.5 V VDDA Analog supply 3.0 VREF+ Positive reference voltage 2.75 VDDA V VREF- Negative reference voltage (1) V SSA 0.5 V VAIN Conversion voltage range V SSA V DDA V VREF- VREF+ V (1) (2) Devices with external VREF+/VREF- pins CADC tS (2) Internal sample and hold capacitor Sampling time tSTAB Wakeup time from standby tCONV Total conversion time (including sampling time, 10-bit resolution) (1) 3.0 fADC = 4 MHz 0.75 fADC = 6 MHz 0.5 pF s 7.0 s fADC = 4 MHz 3.5 s fADC = 6 MHz 2.33 s 14 1/fADC Data guaranteed by design, not tested in production.. (2) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, 96/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. Table 46: ADC accuracy with RAIN < 10 k , VDDA= 5 V Symbol Parameter |ET| Total unadjusted error |EO| |EG| |ED| |EL| (1) (2) (2) Offset error (2) Gain error (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max Unit fADC = 2 MHz 1.0 2.5 LSB fADC = 4 MHz 1.4 3.0 fADC = 6 MHz 1.6 3.5 fADC = 2 MHz 0.6 2.0 fADC = 4 MHz 1.1 2.5 fADC = 6 MHz 1.2 2.5 fADC = 2 MHz 0.2 2.0 fADC = 4 MHz 0.6 2.5 fADC = 6 MHz 0.8 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 0.7 1.5 fADC = 6 MHz 0.8 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 fADC = 6 MHz 0.6 1.5 Data based on characterisation results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. DocID14771 Rev 12 97/124 Electrical characteristics STM8S105xx Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. Table 47: ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V Symbol Parameter |ET| Total unadjusted error |EO| |EG| |ED| |EL| (1) (2) (2) Offset error Gain error (2) (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max Unit fADC = 2 MHz 1.1 2.0 LSB fADC = 4 MHz 1.6 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 1.3 2.0 fADC = 2 MHz 0.2 1.5 fADC = 4 MHz 0.5 2.0 fADC = 2 MHz 0.7 1.0 fADC = 4 MHz 0.7 1.0 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 Data based on characterisation results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in I/O port pin characteristics does not affect the ADC accuracy. 98/124 DocID14771 Rev 12 STM8S105xx Electrical characteristics Figure 45: ADC accuracy characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 46: Typical application with ADC VDD VAIN RAIN CAIN 10.3.12 AINx STM8 VT 0.6 V 10-bit A/D conversion VT 0.6 V IL 1 A CADC EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. DocID14771 Rev 12 99/124 Electrical characteristics STM8S105xx 10.3.12.1 Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. * A burst of fast transient voltage (positive and negative) is applied to V and V * FTB: through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with DD SS the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STMicrocontrollers). 10.3.12.2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter * * Unexpected reset * Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance). Table 48: EMS data Symbol Parameter VFESD VEFTB 100/124 Conditions Level/ class Voltage limits to be applied on any I/O pin to VDD = 5 V, TA = 25 C, fMASTER = 16 MHz, induce a functional conforming to IEC 1000-4-2 disturbance 2/B (1) Fast transient voltage burst limits to be applied VDD= 5 V, TA = 25 C ,fMASTER = 16 through 100 pF on VDD MHz,conforming to IEC 1000-4-4 4/A (1) DocID14771 Rev 12 STM8S105xx Electrical characteristics Symbol Parameter Conditions Level/ class and VSS pins to induce a functional disturbance (1) Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). 10.3.12.3 Electromagnetic interference (EMI) Emission tests conform to the IEC61967-2 standard for test software, board layout and pin loading. Table 49: EMI data Symbol Parameter Conditions General conditions SEMI Peak level VDD = 5 V, TA = +25 C, LQFP48 package conforming to IEC61967-2 Unit Max fHSE/fCPU 8 MHz/ 8 MHz 8 MHz/ 16 MHz 0.1 MHz to 30 MHz 13 14 30 MHz to 130 MHz 23 19 130 MHz to 1 -4.0 GHz SAE EMI level (1) (1) Monitored frequency band 2.0 dBV -4.0 1.5 -- Data based on characterization results, not tested in production. 10.3.12.4 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. DocID14771 Rev 12 101/124 Electrical characteristics STM8S105xx 10.3.12.5 Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 50: ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge TA = +25C, voltage (Human body model) conforming to JESD22-A114 VESD(CDM) Electrostatic discharge voltage (Charge device model) (1) Class Maximum Unit (1) value A 2000 V TA=+25C, conforming IV to JESD22-C101 1000 V Data based on characterization results, not tested in production 10.3.12.6 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: A supply overvoltage (applied to each power supply pin) * injection (applied to each input, output and configurable I/O pin) are performed * Aoncurrent each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 51: Electrical sensitivities (1) Symbol Parameter Conditions Class LU Static latch-up class TA = +25 C A TA = +85 C A TA = +125 C A (1) Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 102/124 DocID14771 Rev 12 STM8S105xx 11 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of (R) (R) ECOPACK packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 11.1 48-pin LQFP package mechanical data Figure 47: 48-pin low profile quad flat package (7 x 7) D ccc C D1 D3 A A2 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K c 12 5B_ME Table 52: 48-pin low profile quad flat package mechanical data Dim. (1) mm Min inches Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 8.800 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 9.200 0.3465 9.000 DocID14771 Rev 12 0.0059 0.0079 0.3543 0.3622 103/124 Package information Dim. D1 STM8S105xx inches Min Typ Max Min Typ Max 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 5.500 0.2165 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.500 0.2165 e 0.500 0.0197 L 0.450 L1 0 ccc (1) 0.600 0.750 0.0177 1.000 k 104/124 (1) mm 3.5 0.0236 0.0295 0.0394 7.0 0 3.5 0.080 Values in inches are converted from mm and rounded to 4 decimal digits DocID14771 Rev 12 7.0 0.0031 STM8S105xx 11.2 Package information 44-pin LQFP package mechanical data Figure 48: 44-pin low profile quad flat package D ccc C D1 D3 A A2 23 33 22 34 L1 b E3 E1 E 44 Pin 1 identification 12 1 L A1 K c 11 4Y_ME Table 53: 44-pin low profile quad flat package mechanical data Dim. (1) mm Min inches Typ A Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 11.800 D1 9.800 D3 E Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 12.000 12.200 0.4646 0.4724 0.4803 10.000 10.200 0.3858 0.3937 0.4016 8.000 11.800 Max 12.000 0.0059 0.0079 0.3150 12.200 DocID14771 Rev 12 0.4646 0.4724 0.4803 105/124 Package information STM8S105xx Dim. (1) mm E1 inches Min Typ Max Min Typ Max 9.800 10.000 10.200 0.3858 0.3937 0.4016 E3 8.000 0.3150 e 0.800 0.0315 L 0.450 0.600 L1 0.750 0.0 0.0295 0.0394 3.5 7.0 ccc 11.3 0.0236 1.000 k (1) 0.0177 0.0 3.5 0.100 7.0 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits 32-pin LQFP package mechanical data Figure 49: 32-pin low profile quad flat package (7 x 7) ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 Pin 1 identification E1 E 9 A1 1 8 L K c 5V_ME 106/124 DocID14771 Rev 12 STM8S105xx Package information Table 54: 32-pin low profile quad flat package mechanical data Dim. (1) mm Min inches Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 9.000 9.200 0.3465 0.3543 0.3622 7.000 7.200 0.2677 0.2756 0.2835 5.600 0.0059 0.0079 0.2205 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.600 0.2205 e 0.800 0.0315 L 0.450 L1 0.750 0.0177 1.000 k 0 ccc (1) 0.600 3.5 0.0236 0.0295 0.0394 7.0 0 3.5 0.100 7.0 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits DocID14771 Rev 12 107/124 Package information 11.4 STM8S105xx 32-lead UFQFPN package mechanical data Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) AOB8_ME 1. Drawing is not to scale. 2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 4. Dimensions are in millimeters. Table 55: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data Dim. inches Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0 0.020 0.050 0.0008 0.0020 A3 b 108/124 (1) mm 0.200 0.180 0.250 0.0079 0.300 DocID14771 Rev 12 0.0071 0.0098 0.0118 STM8S105xx Package information Dim. (1) mm inches Min Typ Max Min Typ Max D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D2 3.200 3.450 3.700 0.1260 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e 0.500 L 0.300 0.0197 0.400 0.500 ddd (1) 11.5 0.1457 0.0118 0.0157 0.080 0.0197 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits. SDIP32 package mechanical data Figure 51: 32-lead shrink plastic DIP (400 ml) package E E1 A2 A1 B1 B A L e eA C eB D 32 17 1 16 76_ME Table 56: 32-lead shrink plastic DIP (400 ml) package mechanical data Dim. A (1) mm inches Min Typ Max Min Typ Max 3.556 3.759 5.080 0.1400 0.1480 0.2000 DocID14771 Rev 12 109/124 Package information Dim. STM8S105xx (1) mm Min inches Typ Min Typ Max A1 0.508 0.0200 A2 3.048 3.556 4.572 0.1200 0.1400 0.1800 B 0.356 0.457 0.584 0.0140 0.0180 0.0230 B1 0.762 1.016 1.397 0.0300 0.0400 0.0550 C 0.203 0.254 0.356 0.0079 0.0100 0.0140 D 27.430 27.940 28.450 1.0799 1.1000 1.1201 E 9.906 10.410 11.050 0.3900 0.4098 0.4350 E1 7.620 8.890 9.398 0.3000 0.3500 0.3700 e 1.778 0.0700 eA 10.160 0.4000 eB L (1) 110/124 Max 12.700 2.540 3.048 3.810 0.5000 0.1000 0.1200 Values in inches are converted from mm and rounded to 4 decimal digits DocID14771 Rev 12 0.1500 STM8S105xx 12 Thermal characteristics Thermal characteristics The maximum chip junction temperature (TJ max) must never exceed the values given in Operating conditions The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in C * * is the package junction-to-ambient thermal resistance in C/W * P is the sum of P and P (P = P + P ) * Ppower. is the product of I andV , expressed in Watts. This is the maximum chip internal the maximum power dissipation on output pinsWhere:P = (V *I ) * P+ ((V represents -V *I ), taking into account the actual V /I V /I of the I/Os at low JA Dmax INTmax INTmax DD I/Omax Dmax INTmax I/Omax DD I/Omax DD I/Omax OH) OH OL OL and OL OL OH OH and high level in the application. (1) Table 57: Thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient Unit 57 C/W 54 C/W 60 C/W 38 C/W 60 C/W LQFP 48 - 7 x 7 mm JA Thermal resistance junction-ambient LQFP 44 - 10 x 10 mm JA Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm JA Thermal resistance junction-ambient UFQFPN 32 - 5 x 5 mm JA Thermal resistance junction-ambient SDIP 32 - 400 mils 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. DocID14771 Rev 12 111/124 Thermal characteristics 12.1 STM8S105xx Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 12.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code. The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2) * * I = 15 mA, V = 5.5 V 8 standard I/Os used at the same time in output at low level with I = 10 mA, * Maximum V =2V 4 high sink I/Os used at the same time in output at low level with I = 20 mA, * Maximum V = 1.5 V 2 true open drain I/Os used at the same time in output at low level with I = * Maximum 20 mA, V = 2 V DDmax DD OL OL OL OL OL OL PINTmax = 15 mA x 5.5 V = 82.5 mW PIOmax = (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW This gives: PINTmax = 82.5 mW and PIOmax 360 mW: PDmax = 82.5 mW + 360 mW Thus: PDmax = 443 mW TJmax for LQFP32 can be calculated as follows, using the thermal resistance JA : TJmax = 82 C + (60 C/W x 443 mW) = 82C + 27C = 109 C This is within the range of the suffix 3 version parts (-40 < TJ < 131 C). In this case, parts must be ordered at least with the temperature range suffix 3. 112/124 DocID14771 Rev 12 STM8S105xx 13 Ordering information Ordering information Figure 52: STM8S105xx access line ordering information scheme Example: STM8 S 105 K 4 T 6 C TR Product class Family type S = Standard Sub-family type 105 = access line STM8S105x Pin count K = 32 pins S = 44 pins C = 48 pins Program memory size 4 = 16 Kbytes 6 = 32 Kbytes Package type B = SDIP T = LQFP U = UFQFPN Temperature range 3 = -40 C to 125 C 6 = -40 C to 85 C Package pitch/thickness No character = 0.5 mm C = 0.8 mm pitch A = 0.55 mm thickness for UFQFPN Packing No character = Tray or tube TR = Tape and reel 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST sales office nearest to you. 13.1 STM8S105 FASTROM microcontroller option list (last update: September 2010) Customer ............................................................................................. Address ............................................................................................. DocID14771 Rev 12 113/124 Ordering information STM8S105xx Contact ............................................................................................. Phone no. ............................................................................................. a Reference FASTROM code ............................................................................................. Preferable format for programing code is .Hex (.s19 is accepted) If data EEPROM programing is required, a seperate file must be sent with the requested data. Important: See the option byte section in the datasheet for authorized option byte combinations and a detailed explanation. Device type/memory size/package (check only one option) FASTROM device 16 Kbyte 32 Kbyte LQFP32 [ ] STM8S105K4 [ ] STM8S105K6 LQFP44 [ ] STM8S105S4 [ ] STM8S105S6 LQFP48 [ ] STM8S105C4 [ ] STM8S105C6 Conditioning (check only one option) [ ] Tape & reel or [ ] Tray Special marking (check only one option) [ ] No [ ] Yes Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts are: LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" LQFP44: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" LQFP48: 2 lines of 8 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" Temperature range [ ] -40C to +85C or [ ] -40C to +125C Padding value for unused program memory (check only one option) [ ]0xFF Fixed value [ ]0x83 TRAP instruction opcode [ ]0x75 Illegal opcode (causes a reset when executed) OPT0 memory readout protection (check only one option) [ ] Disable or [ ] Enable OPT1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below. UBC, bit0 a [ ] 0: Reset FASTROM code name is assigned by STMicroelectronics. 114/124 DocID14771 Rev 12 STM8S105xx Ordering information [ ] 1: Set UBC bit1 [ ] 0: Reset [ ] 1: Set UBC bit2 [ ] 0: Reset [ ] 1: Set UBC bit3 [ ] 0: Reset [ ] 1: Set UBC bit4 [ ] 0: Reset [ ] 1: Set UBC bit5 [ ] 0: Reset [ ] 1: Set OPT2 alternate function remapping AFR0 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D3 alternate function = ADC_ETR AFR1 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port A3 alternate function = TIM3_CH1, port D2 alternate function = TIM2_CH3. AFR2 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D0 alternate function = CLK_CCO. Note: If both AFR2 and AFR3 are activated, AFR2 option has priority over AFR3. AFR3 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D0 alternate function = TIM1_BKIN. AFR4 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D7 alternate function = TIM1_CH4. AFR5 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. DocID14771 Rev 12 115/124 Ordering information STM8S105xx [ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N. AFR6 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL. AFR7 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D4 alternate function = BEEP. OPT3 watchdog WWDG_HALT (check only one option) WWDG_HW (check only one option) IWDG_HW (check only one option) LSI_EN (check only one option) HSITRIM (check only one option) [ ] 0: No reset generated on halt if WWDG active. [ ] 1: Reset generated on halt if WWDG active. [ ] 0: WWDG activated by software. [ ] 1: WWDG activated by hardware. [ ] 0: IWDG activated by software. [ ] 1: IWDG activated by hardware. [ ] 0: LSI clock is not available as CPU clock source. [ ] 1: LSI clock is available as CPU clock source. [ ] 0: 3-bit trimming supported in CLK_HSITRIMR register. [ ] 1: 4-bit trimming supported in CLK_HSITRIMR register. OPT4 wakeup PRSC (check only one option) [ ] for 16 MHz to 128 kHz prescaler. [ ] for 8 MHz to 128 kHz prescaler. [ ] for 4 MHz to 128 kHz prescaler. CKAWUSEL (check only one option) EXTCLK (check only one option) 116/124 [ ] 0: LSI clock source selected for AWU. [ ] 1: HSE clock with prescaler selected as clock source for AWU. [ ] 0: External crystal connected to OSCIN/OSCOUT. [ ] 1: External clock signal on OSCIN. DocID14771 Rev 12 STM8S105xx Ordering information OPT5 crystal oscillator stabilization HSECNT (check only one option) [ ] 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles OPT6 is reserved OPT7 is reserved OPTBL bootloader option byte (check only one option) Refer to the UM0560 (STM8L/S bootloader manual) for more details. [ ] Disable (00h) [ ] Enable (55h) Comments: ........................................................................................................... Supply operating range ........................................................................................................... in the application: Notes: ........................................................................................................... Date: ........................................................................................................... Signature: ........................................................................................................... DocID14771 Rev 12 117/124 STM8 development tools 14 STM8S105xx STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 14.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features Occurrence and time profiling and code coverage (new features) * * Advanced breakpoints with up to 4 levels of conditions * Data breakpoints * Program and data trace recording up to 128 KB records * Read/write on the fly of memory during emulation * In-circuit debugging/programming via SWIM protocol * 8-bit probe analyzer * 1 input and 2 output triggers * Power supply follower managing application voltages between 1.62 to 5.5 V that allows you to specify the components you need to meet your development * Modularity requirements and adapt to future requirements by free software tools that include integrated development environment (IDE), * Supported programming software interface and assembler for STM8. 14.2 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code. 118/124 DocID14771 Rev 12 STM8S105xx 14.2.1 STM8 development tools STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop - Full-featured integrated development environment from ST, featuring Seamless integration of C and ASM toolsets * * Full-featured debugger * Project management * Syntax highlighting editor * Integrated programming interface * Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) - Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller's Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 14.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: Cosmic C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. * C compiler for STM8 - Available in a free version that outputs up to * Raisonance 16 Kbytes of code. For more information, see www.raisonance.com. assembler linker - Free assembly toolchain included in the STVD toolset, which * STM8 allows you to assemble and link your application source code. 14.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. DocID14771 Rev 12 119/124 Revision history 15 STM8S105xx Revision history Table 58: Document revision history Date Revision Changes 05-Jun-2008 1 Initial release. 23-Jun-2008 2 Corrected number of high sink outputs to 9 in I/Os on Features. Updated part numbers in Table 2: STM8S105xx access line features. 12-Aug-2008 3 Updated part numbers in Table 2: STM8S105xx access line features. USART renamed UART1, LINUART renamed UART2. Added Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices. 17-Sep-2008 4 Removed STM8S102xx and STM8S104xx root part numbers corresponding to devices without data EEPROM. Updated STM8S103 pinout in Section 5.2 on page 29. Added low and medium density Flash memory categories. Added Note 1 in Table 17: Current characteristics. Updated Table 12: Option bytes . 05-Feb-2009 5 Updated STM8S103 pinout in Section 5.2 on page 29 Updated number of High Sink I/Os in pinout. TSSOP20 pinout modified (PD4 moved to pin 1 etc.) Added WFQFN20 package Updated Option bytes. Added Memory and register map. 27-Feb-2009 6 Removed STM8S103x products (separate STM8S103 datasheet created) Updated Electrical characteristics. 12-May-2009 7 Added SDIP32 silhouette and package to Features and SDIP32 package mechanical data ; updated Pinout and pin description. Updated VDD range (2.95 V to 5.5 V) on Features. Amended name of package VQFPN32 120/124 DocID14771 Rev 12 STM8S105xx Date Revision history Revision Changes Added Table 5 on page 22 . Updated Auto wakeup counter. Updated pins 25, 30, and 31 in Pinout and pin description. Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices. Added Table 14: Description of alternate function remapping bits [7:0] of OPT2. Electrical characteristics: Updated VCAP specifications; updated Table 15, Table 18, Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Table 29, Table 35, and Table 42; added current consumption curves ; removed Figure 20: typical HSE frequency vs fcpu @ 4 temperatures; updated Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17 ; modified HSI accuracy in Table 33 ; added Figure 44 ; modified fSCK, tV(SO) and tV(MO) in Table 42 ; updated figures and tables of High speed internal RC oscillator (HSI) ; replaced Figure 23, Figure 24, Figure 26, and Figure 39 . Package information: Updated Table 57: Thermal characteristics(1) and removed Table 57: Junction temperature range. Updated Figure 52: STM8S105xx access line ordering information scheme. 10-Jun-2009 8 Document status changed from "preliminary data" to "datasheet". Standardized name of the VFQFPN package. Removed `wpu' from I2C pins in Pinout and pin description 21-Apr-2010 9 Added UFQFPN32 package silhouette to the title page. Features: added unique ID. Clock controller: updated bit positions for TIM2 and TIM3. Beeper: added information about availability of the beeper output port through option bit AFR7. Analog-to-digital converter (ADC1): added a note concerning additional AIN12 analog input. STM8S105 pinouts and pin description: added UFQFPN32 package details; updated default alternate function of PB2/AIN2[TIM1_CH3N] pin in the "Pin description for STM8S105 microcontrollers" table. Option bytes: added description of STM8L bootloader option bytes to the option byte description table. DocID14771 Rev 12 121/124 Revision history Date STM8S105xx Revision Changes Added Unique ID Operating conditions: added introductory text; removed low power dissipation condition for TA, replaced "CEXT" by "VCAP", and added ESR and ESL data in table "general operating conditions". Total current consumption in halt mode: replaced max value of IDD(H) at 85 C from 20 A to 25 A for the condition "Flash in powerdown mode, HSI clock after wakeup in the table "total current consumption in halt mode at VDD = 5 V. Low power mode wakeup times: added first condition (0 to 16 MHz) for the tWU(WFI) parameter in the table "wakeup times". Internal clock sources and timing characteristics: In the table "HSI oscillator characteristics", replaced min and max values of "ACCHSI factory calibrated parameter" and removed footnote 4 concerning further characterization of results. Functional EMS (electromagnetic susceptibility): IEC 1000 replaced with IEC 61000. Designing hardened software to avoid noise problems: IEC 1000 replaced with IEC 61000. Electromagnetic interference (EMI): SAE J 1752/3 replaced with IEC61967-2. Thermal characteristics: Replaced the thermal resistance junction ambient temperature of LQFP32 7X7 mm from 59 C to 60 C in the thermal characteristics table. Added 32-lead UFQFPN package mechanical data. Added STM8S105 FASTROM microcontroller option list. 21-Sep-2010 10 Table 5: Legend/abbreviations for pinout tables : updated "reset state"; removed "HS", (T), and "[ ]". Table 6: Pin description for STM8S105 microcontrollers: added footnotes to the PF4 and PD1 pins. Table 8: I/O port hardware register map: changed reset status of Px_IDR from 0x00 to 0xXX. Table 9: General hardware register map: Standardized all address and reset state values; updated the reset state values of the RST_SR, CLK_SWCR, CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR, UART2_DR, and ADC_DRx registers; replaced reserved address "0x00 5248" with the UART2_CR5. Figure 40: Recommended reset pin protection: replaced 0.01 F with 0.1 F 122/124 DocID14771 Rev 12 STM8S105xx Date Revision history Revision Changes Updated Figure 44: Typical application with I2C bus and timing diagram (1) . Updated footnote 1 in Table 46: ADC accuracy with RAIN < 10 k , VDDA= 5 V and Table 47: ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V . STM8S105 FASTROM microcontroller option list: removed bits 6 and 7 from OPT1 user boot code area (UBC); added "disable" to 00h and "enable" to 55h of OPTBL bootloader option byte. Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5): replaced note 1 and added note 2. 04-Apr-2012 11 Removed VFQFPN32 package. Modified Description. Remove weak pull-up input for PE1 and PE2 in Table 6: Pin description for STM8S105 microcontrollers Updated Table 11: Interrupt mapping for TIM2 and TIM4. Updated notes related to VCAP in Table 19: General operating conditions. Added values of tR/tF for 50 pF load capacitance, and updated note in Table 38: I/O static characteristics. Updated typical and maximum values of RPU in Table 38: I/O static characteristics and Table 42: NRST pin characteristics. Changed SCK input to SCK output in SPI serial peripheral interface Added JA for UFQFPN32 and SDIP32 in Table 57: Thermal characteristics(1) , and updated Selecting the product temperature range 28-Jun-2012 12 Added UFQFPN package thickness in Figure 52: STM8S105xx access line ordering information scheme. DocID14771 Rev 12 123/124 STM8S105xx Please Read Carefully Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom United States of America www.st.com 124/124 DocID14771 Rev 12