STM8S105xx
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,
integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
LQFP48 7x7 LQFP44 10x10 LQFP32 7x7
SDIP32 400 ml
UFQFPN32 5x5
Features
Core
•16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
•Extended instruction set
Memories
•Medium-density Flash/EEPROM:
-Program memory up to 32 Kbytes; data
retention 20 years at 55°C after 10 kcycles
-Data memory up to 1 Kbytes true data
EEPROM; endurance 300 kcycles
•RAM: Up to 2 Kbytes
Clock, reset and supply management
•2.95 V to 5.5 V operating voltage
•Flexible clock control, 4 master clock sources:
-Low power crystal resonator oscillator
-External clock input
-Internal, user-trimmable 16 MHz RC
-Internal low power 128 kHz RC
•Clock security system with clock monitor
•Power management:
-Low power modes (wait, active-halt, halt)
-Switch-off peripheral clocks individually
•Permanently active, low consumption power-on
and power-down reset
Interrupt management
•Nested interrupt controller with 32 interrupts
•Up to 37 external interrupts on 6 vectors
Timers
•2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
•Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
•8-bit basic timer with 8-bit prescaler
•Auto wake-up timer
•Window and independent watchdog timers
Communications interfaces
•UART with clock output for synchronous
operation, Smartcard, IrDA, LIN
•SPI interface up to 8 Mbit/s
•I2C interface up to 400 Kbit/s
Analog-to-digital converter (ADC)
•10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
I/Os
•Up to 38 I/Os on a 48-pin package including 16
high sink outputs
•Highly robust I/O design, immune against current
injection
Development support
•Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
debugging
Unique ID
•96-bit unique key for each device
Table 1: Device summary
Part numberReference
STM8S105K4, STM8S105K6, STM8S105S4,
STM8S105S6, STM8S105C4, STM8S105C6
STM8S105xx
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DocID14771 Rev 12
June 2012
www.st.com
Contents
1 Introduction ..............................................................................................................8
2 Description ...............................................................................................................9
3 Block diagram ........................................................................................................10
4 Product overview ...................................................................................................11
4.1 Central processing unit STM8 .....................................................................................11
4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11
4.3 Interrupt controller .......................................................................................................12
4.4 Flash program and data EEPROM memory ................................................................12
4.5 Clock controller ............................................................................................................13
4.6 Power management ....................................................................................................14
4.7 Watchdog timers ..........................................................................................................15
4.8 Auto wakeup counter ...................................................................................................15
4.9 Beeper ........................................................................................................................15
4.10 TIM1 - 16-bit advanced control timer .........................................................................16
4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................16
4.12 TIM4 - 8-bit basic timer ..............................................................................................16
4.13 Analog-to-digital converter (ADC1) ............................................................................17
4.14 Communication interfaces .........................................................................................17
4.14.1 UART2 ...............................................................................................17
4.14.2 SPI .....................................................................................................18
4.14.3 I²C ......................................................................................................19
5 Pinout and pin description ...................................................................................20
5.1 STM8S105 pinouts and pin description .......................................................................21
5.1.1 Alternate function remapping ...............................................................27
6 Memory and register map .....................................................................................29
6.1 Memory map ................................................................................................................29
6.2 Register map ...............................................................................................................30
6.2.1 I/O port hardware register map ............................................................30
6.2.2 General hardware register map ...........................................................33
6.2.3 CPU/SWIM/debug module/interrupt controller registers ......................44
7 Interrupt vector mapping ......................................................................................47
8 Option bytes ...........................................................................................................49
9 Unique ID ................................................................................................................54
10 Electrical characteristics ....................................................................................55
10.1 Parameter conditions .................................................................................................55
10.1.1 Minimum and maximum values .........................................................55
10.1.2 Typical values .....................................................................................55
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10.1.3 Typical curves ....................................................................................55
10.1.4 Typical current consumption ..............................................................55
10.1.5 Loading capacitor ...............................................................................56
10.1.6 Pin input voltage .................................................................................56
10.2 Absolute maximum ratings ........................................................................................56
10.3 Operating conditions ..................................................................................................58
10.3.1 VCAP external capacitor ....................................................................61
10.3.2 Supply current characteristics ............................................................61
10.3.3 External clock sources and timing characteristics .............................73
10.3.4 Internal clock sources and timing characteristics ...............................75
10.3.5 Memory characteristics ......................................................................78
10.3.6 I/O port pin characteristics .................................................................79
10.3.7 Typical output level curves .................................................................83
10.3.8 Reset pin characteristics ....................................................................88
10.3.9 SPI serial peripheral interface ............................................................91
10.3.10 I2C interface characteristics .............................................................94
10.3.11 10-bit ADC characteristics ................................................................96
10.3.12 EMC characteristics .........................................................................99
11 Package information ..........................................................................................103
11.1 48-pin LQFP package mechanical data ...................................................................103
11.2 44-pin LQFP package mechanical data ...................................................................105
11.3 32-pin LQFP package mechanical data ...................................................................106
11.4 32-lead UFQFPN package mechanical data ...........................................................108
11.5 SDIP32 package mechanical data ...........................................................................109
12 Thermal characteristics ....................................................................................111
12.1 Reference document ...............................................................................................112
12.2 Selecting the product temperature range ................................................................112
13 Ordering information .........................................................................................113
13.1 STM8S105 FASTROM microcontroller option list ...................................................113
14 STM8 development tools ..................................................................................118
14.1 Emulation and in-circuit debugging tools .................................................................118
14.2 Software tools ..........................................................................................................118
14.2.1 STM8 toolset ....................................................................................119
14.2.2 C and assembly toolchains ..............................................................119
14.3 Programming tools ..................................................................................................119
15 Revision history .................................................................................................120
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ContentsSTM8S105xx
List of tables
Table 1. Device summary .........................................................................................................................1
Table 2. STM8S105xx access line features .............................................................................................9
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14
Table 4. TIM timer features ...................................................................................................................16
Table 5. Legend/abbreviations for pinout tables ...................................................................................20
Table 6. Pin description for STM8S105 microcontrollers .......................................................................24
Table 7. Flash, Data EEPROM and RAM boundary addresses ..........................................................105
Table 8. I/O port hardware register map ..............................................................................................108
Table 9. General hardware register map ................................................................................................33
Table 10. CPU/SWIM/debug module/interrupt controller registers ......................................................109
Table 11. Interrupt mapping ....................................................................................................................47
Table 12. Option bytes ..........................................................................................................................54
Table 13. Option byte description ...........................................................................................................50
Table 14. Description of alternate function remapping bits [7:0] of OPT2 ..............................................52
Table 15. Unique ID registers (96 bits) ...................................................................................................54
Table 16. Voltage characteristics ...........................................................................................................56
Table 17. Current characteristics ...........................................................................................................57
Table 18. Thermal characteristics ..........................................................................................................58
Table 19. General operating conditions .................................................................................................59
Table 20. Operating conditions at power-up/power-down ......................................................................60
Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................61
Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................73
Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................64
Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................65
Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................65
Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................66
Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................67
Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................68
Table 29. Wakeup times .........................................................................................................................68
Table 30. Total current consumption and timing in forced reset state ..................................................102
Table 31. Peripheral current consumption .............................................................................................69
Table 32. HSE user external clock characteristics .................................................................................73
Table 33. HSE oscillator characteristics .................................................................................................74
Table 34. HSI oscillator characteristics ..................................................................................................75
Table 35. LSI oscillator characteristics ...................................................................................................77
Table 36. RAM and hardware registers ..................................................................................................78
Table 37. Flash program memory/data EEPROM memory ....................................................................78
Table 38. I/O static characteristics .........................................................................................................79
Table 39. Output driving current (standard ports) ..................................................................................82
Table 40. Output driving current (true open drain ports) ........................................................................82
Table 41. Output driving current (high sink ports) ..................................................................................83
Table 42. NRST pin characteristics ........................................................................................................88
Table 43. SPI characteristics ..................................................................................................................91
Table 44. I2C characteristics ..................................................................................................................94
Table 45. ADC characteristics ................................................................................................................96
Table 46. ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V .......................................................................97
Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V ............................................................98
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STM8S105xxList of tables
Table 48. EMS data ..............................................................................................................................100
Table 49. EMI data ...............................................................................................................................101
Table 50. ESD absolute maximum ratings ...........................................................................................102
Table 51. Electrical sensitivities ...........................................................................................................102
Table 52. 48-pin low profile quad flat package mechanical data .........................................................103
Table 53. 44-pin low profile quad flat package mechanical data .........................................................105
Table 54. 32-pin low profile quad flat package mechanical data .........................................................120
Table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data ...........................108
Table 56. 32-lead shrink plastic DIP (400 ml) package mechanical data ............................................109
Table 57. Thermal characteristics(1) ....................................................................................................111
Table 58. Document revision history ...................................................................................................120
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List of figures
Figure 1. STM8S105xx access line block diagram ................................................................................10
Figure 2. Flash memory organisation ....................................................................................................13
Figure 3. LQFP 48-pin pinout .................................................................................................................21
Figure 4. LQFP 44-pin pinout .................................................................................................................22
Figure 5. LQFP/UFQFPN 32-pin pinout ................................................................................................23
Figure 6. SDIP 32-pin pinout ..................................................................................................................24
Figure 7. Memory map ...........................................................................................................................29
Figure 8. Supply current measurement conditions ................................................................................55
Figure 9. Pin loading conditions .............................................................................................................56
Figure 10. Pin input voltage ...................................................................................................................56
Figure 11. fCPUmax versus VDD ..............................................................................................................60
Figure 12. External capacitor CEXT .......................................................................................................61
Figure 13. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................70
Figure 14. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................71
Figure 15. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................71
Figure 16. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................72
Figure 17. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................72
Figure 18. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................73
Figure 19. HSE external clocksource .....................................................................................................74
Figure 20. HSE oscillator circuit diagram ...............................................................................................75
Figure 21. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................76
Figure 22. Typical HSI accuracy vs VDD @ 4 temperatures ..................................................................77
Figure 23. Typical LSI accuracy vs VDD @ 4 temperatures ...................................................................78
Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................81
Figure 25. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................81
Figure 26. Typical pull-up current vs VDD @ 4 temperatures .................................................................82
Figure 27. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................84
Figure 28. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................84
Figure 29. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................85
Figure 30. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................85
Figure 31. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................86
Figure 32. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................86
Figure 33. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................87
Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................87
Figure 35. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................88
Figure 36. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................88
Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................89
Figure 38. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................90
Figure 39. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................90
Figure 40. Recommended reset pin protection ......................................................................................91
Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................93
Figure 42. SPI timing diagram - slave mode and CPHA = 1(1) .............................................................93
Figure 43. SPI timing diagram - master mode(1) ...................................................................................94
Figure 44. Typical application with I2C bus and timing diagram (1) .......................................................95
Figure 45. ADC accuracy characteristics ...............................................................................................99
Figure 46. Typical application with ADC ................................................................................................99
Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................103
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Figure 48. 44-pin low profile quad flat package ...................................................................................105
Figure 49. 32-pin low profile quad flat package (7 x 7) ........................................................................106
Figure 50. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ..........................................108
Figure 51. 32-lead shrink plastic DIP (400 ml) package ......................................................................109
Figure 52. STM8S105xx access line ordering information scheme .....................................................113
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Introduction1
This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
•For complete information on the STM8S microcontroller memory, registers and peripherals,
please refer to the STM8S microcontroller family reference manual (RM0016).
•For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
•For information on the debug and SWIM (single wire interface module) refer to the STM8
SWIM communication protocol and debug module user manual (UM0470).
•For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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STM8S105xxIntroduction
Description2
The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program
memory, plus integrated true data EEPROM. They are referred to as medium-density devices
in the STM8S microcontroller family reference manual (RM0016).
All devices of the STM8S105xx access line provide the following benefits: reduced system
cost, performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300
kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog,
and brown-out reset.
Device performance is ensured by a 16 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and and modular peripherals.
Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8S family thanks to their advanced core which is
made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
Table 2: STM8S105xx access line features
STM8S105K4STM8S105K6STM8S105S4STM8S105S6STM8S105C4STM8S105C6Device
323244444848Pin count
252534343838Maximum number
of GPIOs
232331313535Ext. Interrupt pins
888899Timer CAPCOM
channels
333333Timer
complementary
outputs
77991010A/D Converter
channels
121215151616High sink I/Os
16K32K16K32K16K32KMedium density
Flash Program
memory (bytes)
102410241024102410241024Data EEPROM
(bytes)
2K2K2K2K2K2KRAM (bytes)
Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C, UART,
Window WDG, Independent WDG, ADC
Peripheral set
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DescriptionSTM8S105xx
Block diagram3
Figure 1: STM8S105xx access line block diagram
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
I2C
SPI
UART2
16-bit general purpose
AWU timer
Reset block
Reset
POR BOR
Clock controller
Detector
Clock to peripherals and core
8 Mbit/s
Up to 10 channels
Address and data bus
Window WDG
Independent WDG
Up to 32 Kbytes
1 Kbytes
Up to 2 Kbytes
Boot ROM
ADC1
Reset
400 Kbit/s
Single wire
debug interf. program Flash
16-bit advanced control
timer (TIM1)
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
data EEPROM
RAM
Master/slave
autosynchro
LIN master
SPI emul.
Beeper
1/2/4 kHz
beep
5 CAPCOM
channels
Up to
4 CAPCOM
channels +3
Up to
complementary
outputs
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STM8S105xxBlock diagram
Product overview4
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM84.1
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
•Harvard architecture
•3-stage pipeline
•32-bit wide program memory bus - single cycle fetching for most instructions
•X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
and read-modify-write type data manipulations
•8-bit accumulator
•24-bit program counter - 16-Mbyte linear memory space
•16-bit stack pointer - access to a 64 K-level stack
•8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
•20 addressing modes
•Indexed indirect addressing mode for look-up tables located anywhere in the address
space
•Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
•80 instructions with 2-byte average instruction size
•Standard data movement and logic/arithmetic functions
•8-bit by 8-bit multiplication
•16-bit by 8-bit and 16-bit by 16-bit division
•Bit manipulation
•Data transfer between stack and accumulator (push/pop) with direct stack access
•Data transfer using the X and Y registers or direct memory-to-memory transfers
Single wire interface module (SWIM) and debug module (DM)4.2
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
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Product overviewSTM8S105xx
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
•R/W to RAM and peripheral registers in real-time
•R/W access to all resources by stalling the CPU
•Breakpoints on all program-memory instructions (software breakpoints)
•Two advanced breakpoints, 23 predefined configurations
Interrupt controller4.3
•Nested interrupts with three software priority levels
•32 interrupt vectors with hardware priority
•Up to 37 external interrupts on 6 vectors including TLI
•Trap and reset interrupts
Flash program and data EEPROM memory4.4
•Up to 32 Kbytes of Flash program single voltage Flash memory
•Up to 1 Kbytes true data EEPROM
•Read while write: Writing in data memory possible while executing code in program memory
•User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
•Main program memory: Up to 32 Kbytes minus UBC
•User-specific boot code (UBC): Configurable up to 32 Kbytes
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STM8S105xxProduct overview
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organisation
Programmable area
Data
Program memory area
Data memory area ( 1 Kbyte)
EEPROM
UBC area
Remains write protected during IAP
memory
Write access possible for IAP
(1 page steps)
Option bytes
(2 first pages) up to
Medium density
Flash program memory
(up to 32 Kbytes)
from 1 Kbyte
32 Kbytes
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller4.5
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
•Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
•Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•Master clock sources: Four different clock sources can be used to drive the master
clock:
-1-16 MHz high-speed external crystal (HSE)
-Up to 16 MHz high-speed user-external clock (HSE user-ext)
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-16 MHz high-speed internal RC oscillator (HSI)
-128 kHz low-speed internal RC (LSI)
•Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•Clock security system (CSS): This feature can be enabled by software. If an HSE clock
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
•Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
BitPeripheral
clock
BitPeripheral
clock
BitPeripheral
clock
Bit
ADCPCKEN2 3ReservedPCKEN2 7UART2PCKEN1 3TIM1PCKEN1 7
AWUPCKEN2 2ReservedPCKEN2 6ReservedPCKEN1 2TIM3PCKEN1 6
ReservedPCKEN2 1ReservedPCKEN2 5SPIPCKEN1 1TIM2PCKEN1 5
ReservedPCKEN2 0ReservedPCKEN2 4I2CPCKEN1 0TIM4PCKEN1 4
Power management4.6
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
•Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
•Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
•Active halt mode with regulator off: This mode is the same as active halt with regulator
on, except that the main voltage regulator is powered off, so the wake up time is slower.
•Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
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STM8S105xxProduct overview
Watchdog timers4.7
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
Auto wakeup counter4.8
•Used for auto wakeup from active halt mode
•Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
•LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
Beeper4.9
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
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TIM1 - 16-bit advanced control timer4.10
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
•16-bit up, down and up/down autoreload counter with 16-bit prescaler
•Four independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
•Synchronization module to control the timer with external signals
•Break input to force the timer outputs into a defined state
•Three complementary outputs with adjustable dead time
•Encoder mode
•Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2, TIM3 - 16-bit general purpose timers4.11
•16-bit autoreload (AR) up-counter
•15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
•Timers with 3 or 2 individually configurable capture/compare channels
•PWM mode
•Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
TIM4 - 8-bit basic timer4.12
•8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
•Clock source: CPU clock
•Interrupt source: 1 x overflow/update
Table 4: TIM timer features
Timer
synchronization/
chaining
Ext.
trigger
Complem.
outputs
CAPCOM
channels
Counting
mode
PrescalerCounter
size
(bits)
Timer
NoYes34Up/
down
Any integer from 1 to
65536
16TIM1
No03UpAny power of 2 from
1 to 32768
16TIM2
No02UpAny power of 2 from
1 to 32768
16TIM3
DocID14771 Rev 1216/124
STM8S105xxProduct overview
Timer
synchronization/
chaining
Ext.
trigger
Complem.
outputs
CAPCOM
channels
Counting
mode
PrescalerCounter
size
(bits)
Timer
No00UpAny power of 2 from
1 to 128
8TIM4
Analog-to-digital converter (ADC1)4.13
The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1)
with up to 10 multiplexed input channels and the following main features:
•Input voltage range: 0 to VDDA
•Conversion time: 14 clock cycles
•Single and continuous and buffered continuous conversion modes
•Buffer size (n x 10 bits) where n = number of input channels
•Scan mode for single and continuous conversion of a sequence of channels
•Analog watchdog capability with programmable upper and lower thresholds
•Analog watchdog interrupt
•External trigger input
•Trigger from TIM1 TRGO
•End of conversion (EOC) interrupt
Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog
watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL
registers.
Communication interfaces4.14
The following communication interfaces are implemented:
•UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, LIN2.1 master/slave capability
•SPI : Full and half-duplex, 8 Mbit/s
•I²C: Up to 400 Kbit/s
UART24.14.1
Main features
•One Mbit/s full duplex SCI
•SPI emulation
•High precision baud rate generator
•Smartcard emulation
•IrDA SIR encoder decoder
17/124DocID14771 Rev 12
Product overviewSTM8S105xx
•LIN master mode
•LIN slave mode
Asynchronous communication (UART mode)
•Full duplex communication - NRZ standard format (mark/space)
•Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
•Separate enable bits for transmitter and receiver
•Two receiver wakeup modes:
-Address bit (MSB)
-Idle line (interrupt)
•Transmission error detection with interrupt generation
•Parity control
Synchronous communication
•Full duplex synchronous transfers
•SPI master operation
•8-bit data communication
•Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode
•Emission: Generates 13-bit synch break frame
•Reception: Detects 11-bit break frame
LIN slave mode
•Autonomous header handling - one single interrupt per valid message header
•Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
•Synch delimiter checking
•11-bit LIN synch break detection - break detection always active
•Parity check on the LIN identifier field
•LIN error management
•Hot plugging support
SPI4.14.2
•Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
•Full duplex synchronous transfers
•Simplex synchronous transfers on two lines with a possible bidirectional data line
•Master or slave operation - selectable by hardware or software
•CRC calculation
•1 byte Tx and Rx buffer
•Slave/master selection input pin
DocID14771 Rev 1218/124
STM8S105xxProduct overview
I²C4.14.3
•I²C master features:
-Clock generation
-Start and stop generation
•I²C slave features:
-Programmable I2C address detection
-Stop bit detection
•Generation and detection of 7-bit/10-bit addressing and general call
•Supports different communication speeds:
-Standard speed (up to 100 kHz)
-Fast speed (up to 400 kHz)
19/124DocID14771 Rev 12
Product overviewSTM8S105xx
Pinout and pin description5
Table 5: Legend/abbreviations for pinout tables
I= Input, O = Output, S = Power supplyType
CM = CMOS
InputLevel
HS = High sinkOutput
O1 = Slow (up to 2 MHz)
Output speed
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
float = floating, wpu = weak pull-upInputPort and control
configuration T = True open drain, OD = Open drain, PP =
Push pull
Output
Bold X(pin state after internal reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
DocID14771 Rev 1220/124
STM8S105xxPinout and pin description
STM8S105 pinouts and pin description5.1
Figure 3: LQFP 48-pin pinout
44 43 42 41 40 39 38 3736
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
(HS) PA6
AIN8/PE7
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
PG1
AIN9/PE6
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDAA
PE3/TIM1_BKIN
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
VSSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
VDDA
VSSA
VSS
VCAP
VDD
VDDIO_1
[TIM3_CH1] TIM2_CH3/PA3
(HS) PA4
(HS) PA5
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
[I2C_SCL] AIN4/PB4
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
21/124DocID14771 Rev 12
Pinout and pin descriptionSTM8S105xx
Figure 4: LQFP 44-pin pinout
AIN6/PB6
[I2C_SDA] AIN5/PB5
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
AIN9/PE6
VDDA
VSSA
AIN7/PB7
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
VSS
VCAP
VDD
VDDIO_1
(HS) PA4
(HS) PA5
(HS) PA6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS/UART2_CK
PG1
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PE0 (HS)/CLK_CCO
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
[I2C_SCL] AIN4/PB4
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
DocID14771 Rev 1222/124
STM8S105xxPinout and pin description
Figure 5: LQFP/UFQFPN 32-pin pinout
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
VDDA
VSSA
32 31 30 29 28 27 26 2524
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
VCAP
VDD
VDDIO
AIN12/PF4
NRST
OSCIN/PA1
OSCOUT/PA2
VSS PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
1. (HS) high sink capability.
2. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
23/124DocID14771 Rev 12
Pinout and pin descriptionSTM8S105xx
Figure 6: SDIP 32-pin pinout
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ADC_ETR/TIM2_CH2/(HS) PD3
[BEEP] TIM2_CH1/(HS) PD4
UART2_TX/PD5
UART2_RX/PD6
[TIM1_CH4] TLI/PD7
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
AIN12/PF4
[I2C_SDA] AIN5/PB5 PB4/AIN4[ I2C_SCL]
PB3/AIN3 [TIM1_ETR]
PB2/AIN2 [TIM1_CH3N]
PB1/AIN1 [TIM1_CH2N]
PB0/AIN0 [TIM1_CH1N]
PE5/SPI_NSS
PC1 (HS)/TIM1_CH1/UART2_CK
PC2 (HS)/TIM1_CH2
PC3 (HS)/TIM1_CH3
PC4 (HS)/TIM1_CH4
PC5 (HS)/SPI_SCK
PC6 (HS)/SPI_MOSI
PC7 (HS)/SPI_MISO
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PD1 (HS)/SWIM
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
105_ai15057
VDDIO
VDDA
VSSA
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
Table 6: Pin description for STM8S105 microcontrollers
Alternate
function after
remap
[option bit]
Default alternate
function
Main function
(after reset)
OutputInputTypePin namePin number
PPODSpeedHigh
sink
Ext.
interrupt
wpufloatingSDIP32LQFP32/
UFQFPN32
LQFP44LQFP48
ResetXI/ONRST6111
Resonator/Port A1XXO1XXI/OPA1/
OSC IN
7222
crystal in
Resonator/Port A2XXO1XXXI/OPA2/
OSC
OUT
8333
crystal out
I/O groundSVSSIO_1
--44
Digital groundSVSS
9455
1.8 V regulator capacitorSVCAP10566
Digital power supplySVDD
11677
I/O power supplySVDDIO_1
12788
DocID14771 Rev 1224/124
STM8S105xxPinout and pin description
Alternate
function after
remap
[option bit]
Default alternate
function
Main function
(after reset)
OutputInputTypePin namePin number
PPODSpeedHigh
sink
Ext.
interrupt
wpufloatingSDIP32LQFP32/
UFQFPN32
LQFP44LQFP48
TIM3_ CH1
[AFR1]
Timer 2 -
channel 3
Port A3XXO1XXXI/OPA3/
TIM2
_CH3
[TIM3
_CH1]
---9
Port A4XXO3HSXXXI/OPA4--910
Port A5XXO3HSXXXI/OPA5--1011
Port A6XXO3HSXXXI/OPA6--1112
Analog input 12
(2)
Port F4XXO1XXI/OPF4/
AIN12
(1)
138--
Analog power supplySVDDA
1491213
Analog groundSVSSA
15101314
Analog input 7Port B7XXO1XXXI/OPB7/
AIN7
--1415
Analog input 6Port B6XXO1XXXI/OPB6/
AIN6
--1516
I2C_SDA
[AFR6]
Analog input 5Port B5XXO1XXXI/OPB5/
AIN5
[I2C_
SDA]
16111617
I2C_SCL
[AFR6]
Analog input 4Port B4XXO1XXXI/OPB4/
AIN4
[I2C_
SCL]
17121718
TIM1_ ETR
[AFR5]
Analog input 3Port B3XXO1XXXI/OPB3/
AIN3
[TIM1_
ETR]
18131819
TIM1_ CH3N
[AFR5]
Analog input 2Port B2XXO1XXXI/OPB2/
AIN2
[TIM1_
CH3N]
19141920
TIM1_ CH2N
[AFR5]
Analog input 1Port B1XXO1XXXI/OPB1/
AIN1
[TIM1_
CH2N]
20152021
TIM1_ CH1N
[AFR5]
Analog input 0Port B0XXO1XXXI/OPB0/
AIN0
[TIM1_
CH1N]
21162122
Analog input 8Port E7XXO1XXXI/OPE7/
AIN8
---23
25/124DocID14771 Rev 12
Pinout and pin descriptionSTM8S105xx
Alternate
function after
remap
[option bit]
Default alternate
function
Main function
(after reset)
OutputInputTypePin namePin number
PPODSpeedHigh
sink
Ext.
interrupt
wpufloatingSDIP32LQFP32/
UFQFPN32
LQFP44LQFP48
Analog input 9(3)
Port E6XXO1XXXI/OPE6/
AIN9
--2224
SPI master/slave
select
Port E5XXO1XXXI/OPE5/SPI_
NSS
22172325
Timer 1 -Port C1XXO3HSXXXI/OPC1/
TIM1_
23182426
channel 1/ UART2
synchronous clock
CH1/
UART2_CK
Timer 1-Port C2XXO3HSXXXI/OPC2/
TIM1_
CH2
24192527
channel 2
Timer 1 -Port C3XXO3HSXXXI/OPC3/
TIM1_
CH3
25202628
channel 3
Timer 1 -Port C4XXO3HSXXXI/OPC4/
TIM1_
CH4
2621-29
channel 4
SPI clockPort C5XXO3HSXXXI/OPC5/
SPI_
SCK
27222730
I/O groundSVSSIO_2
--2831
I/O power supplySVDDIO_2
--2932
SPI master
out/slave in
Port C6XXO3HSXXXI/OPC6/
SPI_
MOSI
28233033
SPI master in/
slave out
Port C7XXO3HSXXXI/OPC7/
SPI_
MISO
29243134
Port G0XXO1XXI/OPG0--3235
Port G1XXO1XXI/OPG1--3336
Timer 1 - break
input
Port E3XXO1XXXI/OPE3/
TIM1_
BKIN
---37
I2C dataPort E2
T(4)
O1XXI/OPE2/
I2C_
SDA
--3438
I2C clockPort E1
T(4)
O1XXI/OPE1/
I2C_
SCL
--3539
Configurable clock
output
Port E0XXO3HSXXXI/OPE0/
CLK_
CCO
--3640
DocID14771 Rev 1226/124
STM8S105xxPinout and pin description
Alternate
function after
remap
[option bit]
Default alternate
function
Main function
(after reset)
OutputInputTypePin namePin number
PPODSpeedHigh
sink
Ext.
interrupt
wpufloatingSDIP32LQFP32/
UFQFPN32
LQFP44LQFP48
TIM1_ BKIN
[AFR3]/
Timer 3 -
channel 2
Port D0XXO3HSXXXI/OPD0/
TIM3_
CH2
[TIM1_
30253741
CLK_ CCO
[AFR2]
BKIN]
[CLK_
CCO]
SWIM data
interface
Port D1XXO4HSXXXI/OPD1/
SWIM(5)
31263842
TIM2_CH3
[AFR1]
Timer 3 -
channel 1
Port D2XXO3HSXXXI/OPD2/
TIM3_
CH1
[TIM2_
CH3]
32273943
ADC_ ETR
[AFR0]
Timer 2 -
channel 2
Port D3XXO3HSXXXI/OPD3/
TIM2_
CH2
[ADC_
ETR]
1284044
BEEP output
[AFR7]
Timer 2 -
channel 1
Port D4XXO3HSXXXI/OPD4/
TIM2_
CH1
[BEEP]
2294145
UART2 data
transmit
Port D5XXO1XXXI/OPD5/
UART2_
TX
3304246
UART2 data
receive
Port D6XXO1XXXI/OPD6/
UART2_
RX
4314347
TIM1_ CH4
[AFR4]
Top level interruptPort D7XXO1XXXI/OPD7/ TLI
[TIM1_
CH4]
5324448
(1) A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
(2)AIN12 is not selectable in ADC scan mode or with analog watchdog.
(3) In 44-pin package, AIN9 cannot be used by ADC scan mode.
(4) In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented).
(5)The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Alternate function remapping5.1.1
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
27/124DocID14771 Rev 12
Pinout and pin descriptionSTM8S105xx
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
DocID14771 Rev 1228/124
STM8S105xxPinout and pin description
Memory and register map6
Memory map6.1
Figure 7: Memory map
0x00 FFFF
Flash program memory
(16 to32 Kbytes)
0x00 8000
Reserved
0x01 0000
0x02 7FFF
0x00 0000 RAM
0x00 07FF
(2 Kbytes)
0x00 4000
0x00 43FF 1 Kbyte data EEPROM
Reserved
Reserved
0x00 4400
0x00 47FF
32 interrupt vectors
0x00 807F
GPIO and periph. reg.
0x00 5000
0x00 57FF
0x00 5800
0x00 7FFF
0x00 4900
0x00 4FFF
2 Kbytes boot ROM
0x00 6000
0x00 67FF
0x00 6800
0x00 7EFF
CPU/SWIM/debug/ITC
registers
0x00 7F00
0x00 5FFF
Reserved
Reserved
Reserved
Option bytes
0x00 4800
0x00 487F
512 bytes stack
The following table lists the boundary addresses for each memory size. The top of the stack
is at the RAM end address in each case.
29/124DocID14771 Rev 12
Memory and register mapSTM8S105xx
Table 7: Flash, Data EEPROM and RAM boundary addresses
End addressStart addressSize (bytes)Memory area
0x00 FFFF0x00 800032KFlash program memory
0x00 BFFF0x00 800016K
0x00 07FF0x00 00002KRAM
0x00 43FF0x00 40001024Data EEPROM
Register map6.2
I/O port hardware register map6.2.1
Table 8: I/O port hardware register map
Reset
status
Register nameRegister labelBlockAddress
0x00Port A data output latch registerPA_ODRPort A0x00 5000
0xXXPort A input pin value registerPA_IDR0x00 5001
0x00Port A data direction registerPA_DDR0x00 5002
0x00Port A control register 1PA_CR10x00 5003
0x00Port A control register 2PA_CR20x00 5004
0x00Port B data output latch registerPB_ODRPort B0x00 5005
0xXXPort B input pin value registerPB_IDR0x00 5006
0x00Port B data direction registerPB_DDR0x00 5007
0x00Port B control register 1PB_CR10x00 5008
0x00Port B control register 2PB_CR20x00 5009
DocID14771 Rev 1230/124
STM8S105xxMemory and register map
Reset
status
Register nameRegister labelBlockAddress
0x00Port C data output latch registerPC_ODRPort C0x00 500A
0xXXPort C input pin value registerPC_IDR0x00 500B
0x00Port C data direction registerPC_DDR0x00 500C
0x00Port C control register 1PC_CR10x00 500D
0x00Port C control register 2PC_CR20x00 500E
0x00Port D data output latch registerPD_ODRPort D0x00 500F
0xXXPort D input pin value registerPD_IDR0x00 5010
0x00Port D data direction registerPD_DDR0x00 5011
0x02Port D control register 1PD_CR10x00 5012
0x00Port D control register 2PD_CR20x00 5013
0x00Port E data output latch registerPE_ODRPort E0x00 5014
0xXXPort E input pin value registerPE_IDR0x00 5015
0x00Port E data direction registerPE_DDR0x00 5016
0x00Port E control register 1PE_CR10x00 5017
0x00Port E control register 2PE_CR20x00 5018
0x00Port F data output latch registerPF_ODRPort F0x00 5019
0xXXPort F input pin value registerPF_IDR0x00 501A
0x00Port F data direction registerPF_DDR0x00 501B
0x00Port F control register 1PF_CR10x00 501C
31/124DocID14771 Rev 12
Memory and register mapSTM8S105xx
Reset
status
Register nameRegister labelBlockAddress
0x00Port F control register 2PF_CR20x00 501D
0x00Port G data output latch registerPG_ODRPort G0x00 501E
0xXXPort G input pin value registerPG_IDR0x00 501F
0x00Port G data direction registerPG_DDR0x00 5020
0x00Port G control register 1PG_CR10x00 5021
0x00Port G control register 2PG_CR20x00 5022
0x00Port H data output latch registerPH_ODRPort H0x00 5023
0xXXPort H input pin value registerPH_IDR0x00 5024
0x00Port H data direction registerPH_DDR0x00 5025
0x00Port H control register 1PH_CR10x00 5026
0x00Port H control register 2PH_CR20x00 5027
0x00Port I data output latch registerPI_ODRPort I0x00 5028
0xXXPort I input pin value registerPI_IDR0x00 5029
0x00Port I data direction registerPI_DDR0x00 502A
0x00Port I control register 1PI_CR10x00 502B
0x00Port I control register 2PI_CR20x00 502C
DocID14771 Rev 1232/124
STM8S105xxMemory and register map
General hardware register map6.2.2
Table 9: General hardware register map
Reset statusRegister nameRegister labelBlockAddress
Reserved area (10 bytes)0x00 5050 to
0x00 5059
0x00Flash control register 1FLASH_CR1
Flash0x00 505A
0x00Flash control register 2FLASH_CR20x00 505B
0xFFFlash complementary control
register 2
FLASH_NCR20x00 505C
0x00Flash protection registerFLASH _FPR0x00 505D
0xFFFlash complementary
protection register
FLASH _NFPR0x00 505E
0x00Flash in-application
programming status register
FLASH _IAPSR0x00 505F
Reserved area (2 bytes)0x00 5060 to
0x00 5061
0x00Flash program memory
unprotection register
FLASH _PUKRFlash0x00 5062
Reserved area (1 byte)0x00 5063
0x00Data EEPROM unprotection
register
FLASH _DUKRFlash0x00 5064
Reserved area (59 bytes)0x00 5065 to
0x00 509F
0x00External interrupt control
register 1
EXTI_CR1ITC0x00 50A0
0x00External interrupt control
register 2
EXTI_CR20x00 50A1
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Memory and register mapSTM8S105xx
Reset statusRegister nameRegister labelBlockAddress
Reserved area (17 bytes)0x00 50A2 to
0x00 50B2
0xXX(1)
Reset status registerRST_SRRST0x00 50B3
Reserved area (12 bytes)0x00 50B4 to
0x00 50BF
0x01Internal clock control registerCLK_ICKRCLK0x00 50C0
0x00External clock control registerCLK_ECKR0x00 50C1
Reserved area (1 byte)0x00 50C2
0xE1Clock master status registerCLK_CMSRCLK0x00 50C3
0xE1Clock master switch registerCLK_SWR0x00 50C4
0xXXClock switch control registerCLK_SWCR0x00 50C5
0x18Clock divider registerCLK_CKDIVR0x00 50C6
0xFFPeripheral clock gating register
1
CLK_PCKENR10x00 50C7
0x00Clock security system registerCLK_CSSR0x00 50C8
0x00Configurable clock control
register
CLK_CCOR0x00 50C9
0xFFPeripheral clock gating register
2
CLK_PCKENR20x00 50CA
0x00CAN clock control registerCLK_CANCCR0x00 50CB
0x00HSI clock calibration trimming
register
CLK_HSITRIMR0x00 50CC
0bXXXX
XXX0
SWIM clock control registerCLK_SWIMCCR0x00 50CD
DocID14771 Rev 1234/124
STM8S105xxMemory and register map
Reset statusRegister nameRegister labelBlockAddress
Reserved area (3 bytes)0x00 50CE to
0x00 50D0
0x7FWWDG control registerWWDG_CRWWDG0x00 50D1
0x7FWWDR window registerWWDG_WR0x00 50D2
Reserved area (13 bytes)0x00 50D3 to
0x00 50DF
0xXX(2)
IWDG key registerIWDG_KRIWDG0x00 50E0
0x00IWDG prescaler registerIWDG_PR0x00 50E1
0xFFIWDG reload registerIWDG_RLR0x00 50E2
Reserved area (13 bytes)0x00 50E3 to
0x00 50EF
0x00AWU control/ status register 1AWU_CSR1AWU0x00 50F0
0x3FAWU asynchronous prescaler
buffer register
AWU_APR0x00 50F1
0x00AWU timebase selection
register
AWU_TBR0x00 50F2
0x1FBEEP control/ status registerBEEP_CSRBEEP0x00 50F3
Reserved area (12 bytes)0x00 50F4 to
0x00 50FF
0x00SPI control register 1SPI_CR1SPI0x00 5200
0x00SPI control register 2SPI_CR20x00 5201
0x00SPI interrupt control registerSPI_ICR0x00 5202
0x02SPI status registerSPI_SR0x00 5203
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Memory and register mapSTM8S105xx
Reset statusRegister nameRegister labelBlockAddress
0x00SPI data registerSPI_DR0x00 5204
0x07SPI CRC polynomial registerSPI_CRCPR0x00 5205
0xFFSPI Rx CRC registerSPI_RXCRCR0x00 5206
0xFFSPI Tx CRC registerSPI_TXCRCR0x00 5207
Reserved area (8 bytes)0x00 5208 to
0x00 520F
0x00I2C control register 1I2C_CR1I2C0x00 5210
0x00I2C control register 2I2C_CR20x00 5211
0x00I2C frequency registerI2C_FREQR0x00 5212
0x00I2C Own address register lowI2C_OARL0x00 5213
0x00I2C own address register highI2C_OARH0x00 5214
Reserved0x00 5215
0x00I2C data registerI2C_DR0x00 5216
0x00I2C status register 1I2C_SR10x00 5217
0x00I2C status register 2I2C_SR20x00 5218
0x00I2C status register 3I2C_SR30x00 5219
0x00I2C interrupt control registerI2C_ITR0x00 521A
0x00I2C clock control register lowI2C_CCRL0x00 521B
0x00I2C clock control register highI2C_CCRH0x00 521C
0x02I2C TRISE registerI2C_TRISER0x00 521D
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STM8S105xxMemory and register map
Reset statusRegister nameRegister labelBlockAddress
0x00I2C packet error checking
register
I2C_PECR0x00 521E
Reserved area (17 bytes)0x00 521F to
0x00 522F
Reserved area (6 bytes)0x00 5230 to
0x00 523F
0xC0UART2 status registerUART2_SRUART20x00 5240
0xXXUART2 data registerUART2_DR0x00 5241
0x00UART2 baud rate register 1UART2_BRR10x00 5242
0x00UART2 baud rate register 2UART2_BRR20x00 5243
0x00UART2 control register 1UART2_CR10x00 5244
0x00UART2 control register 2UART2_CR20x00 5245
0x00UART2 control register 3UART2_CR30x00 5246
0x00UART2 control register 4UART2_CR40x00 5247
0x00UART2 control register 5UART2_CR50x00 5248
0x00UART2 control register 6UART2_CR60x00 5249
0x00UART2 guard time registerUART2_GTR0x00 524A
0x00UART2 prescaler registerUART2_PSCR0x00 524B
Reserved area (4 bytes)0x00 524C to
0x00 524F
0x00TIM1 control register 1TIM1_CR1TIM10x00 5250
0x00TIM1 control register 2TIM1_CR20x00 5251
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Memory and register mapSTM8S105xx
Reset statusRegister nameRegister labelBlockAddress
0x00TIM1 slave mode control
register
TIM1_SMCR0x00 5252
0x00TIM1 external trigger registerTIM1_ETR0x00 5253
0x00TIM1 interrupt enable registerTIM1_IER0x00 5254
0x00TIM1 status register 1TIM1_SR10x00 5255
0x00TIM1 status register 2TIM1_SR20x00 5256
0x00TIM1 event generation registerTIM1_EGR0x00 5257
0x00TIM1 capture/ compare mode
register 1
TIM1_CCMR10x00 5258
0x00TIM1 capture/compare mode
register 2
TIM1_CCMR20x00 5259
0x00TIM1 capture/ compare mode
register 3
TIM1_CCMR30x00 525A
0x00TIM1 capture/compare mode
register 4
TIM1_CCMR40x00 525B
0x00TIM1 capture/ compare enable
register 1
TIM1_CCER10x00 525C
0x00TIM1 capture/compare enable
register 2
TIM1_CCER20x00 525D
0x00TIM1 counter highTIM1_CNTRH0x00 525E
0x00TIM1 counter lowTIM1_CNTRL0x00 525F
0x00TIM1 prescaler register highTIM1_PSCRH0x00 5260
0x00TIM1 prescaler register lowTIM1_PSCRL0x00 5261
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STM8S105xxMemory and register map
Reset statusRegister nameRegister labelBlockAddress
0xFFTIM1 auto-reload register highTIM1_ARRH0x00 5262
0xFFTIM1 auto-reload register lowTIM1_ARRL0x00 5263
0x00TIM1 repetition counter
register
TIM1_RCR0x00 5264
0x00TIM1 capture/ compare
register 1 high
TIM1_CCR1H0x00 5265
0x00TIM1 capture/ compare
register 1 low
TIM1_CCR1L0x00 5266
0x00TIM1 capture/ compare
register 2 high
TIM1_CCR2H0x00 5267
0x00TIM1 capture/ compare
register 2 low
TIM1_CCR2L0x00 5268
0x00TIM1 capture/ compare
register 3 high
TIM1_CCR3H0x00 5269
0x00TIM1 capture/ compare
register 3 low
TIM1_CCR3L0x00 526A
0x00TIM1 capture/ compare
register 4 high
TIM1_CCR4H0x00 526B
0x00TIM1 capture/ compare
register 4 low
TIM1_CCR4L0x00 526C
0x00TIM1 break registerTIM1_BKR0x00 526D
0x00TIM1 dead-time registerTIM1_DTR0x00 526E
0x00TIM1 output idle state registerTIM1_OISR0x00 526F
Reserved area (147 bytes)0x00 5270 to
0x00 52FF
0x00TIM2 control register 1TIM2_CR1TIM20x00 5300
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Memory and register mapSTM8S105xx
Reset statusRegister nameRegister labelBlockAddress
0x00TIM2 interrupt enable registerTIM2_IER0x00 5301
0x00TIM2 status register 1TIM2_SR10x00 5302
0x00TIM2 status register 2TIM2_SR20x00 5303
0x00TIM2 event generation registerTIM2_EGR0x00 5304
0x00TIM2 capture/ compare mode
register 1
TIM2_CCMR10x00 5305
0x00TIM2 capture/ compare mode
register 2
TIM2_CCMR20x00 5306
0x00TIM2 capture/ compare mode
register 3
TIM2_CCMR30x00 5307
0x00TIM2 capture/ compare enable
register 1
TIM2_CCER10x00 5308
0x00TIM2 capture/ compare enable
register 2
TIM2_CCER20x00 5309
0x00TIM2 counter highTIM2_CNTRH0x00 530A
0x00TIM2 counter lowTIM2_CNTRL0x00 530B
0x00TIM2 prescaler registerTIM2_PSCR0x00 530C
0xFFTIM2 auto-reload register highTIM2_ARRH0x00 530D
0xFFTIM2 auto-reload register lowTIM2_ARRL0x00 530E
0x00TIM2 capture/ compare
register 1 high
TIM2_CCR1H0x00 530F
0x00TIM2 capture/ compare
register 1 low
TIM2_CCR1L0x00 5310
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STM8S105xxMemory and register map
Reset statusRegister nameRegister labelBlockAddress
0x00TIM2 capture/ compare reg. 2
high
TIM2_CCR2H0x00 5311
0x00TIM2 capture/ compare
register 2 low
TIM2_CCR2L0x00 5312
0x00TIM2 capture/ compare
register 3 high
TIM2_CCR3H0x00 5313
0x00TIM2 capture/ compare
register 3 low
TIM2_CCR3L0x00 5314
Reserved area (11 bytes)0x00 5315 to
0x00 531F
0x00TIM3 control register 1TIM3_CR1TIM30x00 5320
0x00TIM3 interrupt enable registerTIM3_IER0x00 5321
0x00TIM3 status register 1TIM3_SR10x00 5322
0x00TIM3 status register 2TIM3_SR20x00 5323
0x00TIM3 event generation registerTIM3_EGR0x00 5324
0x00TIM3 capture/ compare mode
register 1
TIM3_CCMR10x00 5325
0x00TIM3 capture/ compare mode
register 2
TIM3_CCMR20x00 5326
0x00TIM3 capture/ compare enable
register 1
TIM3_CCER10x00 5327
0x00TIM3 counter highTIM3_CNTRH0x00 5328
0x00TIM3 counter lowTIM3_CNTRL0x00 5329
0x00TIM3 prescaler registerTIM3_PSCR0x00 532A
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Memory and register mapSTM8S105xx
Reset statusRegister nameRegister labelBlockAddress
0xFFTIM3 auto-reload register highTIM3_ARRH0x00 532B
0xFFTIM3 auto-reload register lowTIM3_ARRL0x00 532C
0x00TIM3 capture/ compare
register 1 high
TIM3_CCR1H0x00 532D
0x00TIM3 capture/ compare
register 1 low
TIM3_CCR1L0x00 532E
0x00TIM3 capture/ compare
register 2 high
TIM3_CCR2H0x00 532F
0x00TIM3 capture/ compare
register 2 low
TIM3_CCR2L0x00 5330
Reserved area (15 bytes)0x00 5331 to
0x00 533F
0x00TIM4 control register 1TIM4_CR1TIM40x00 5340
0x00TIM4 interrupt enable registerTIM4_IER0x00 5341
0x00TIM4 status registerTIM4_SR0x00 5342
0x00TIM4 event generation registerTIM4_EGR0x00 5343
0x00TIM4 counterTIM4_CNTR0x00 5344
0x00TIM4 prescaler registerTIM4_PSCR0x00 5345
0xFFTIM4 auto-reload registerTIM4_ARR0x00 5346
Reserved area (153 bytes)0x00 5347 to
0x00 53DF
0x00ADC data buffer registersADC _DBxRADC10x00 53E0 to
0x00 53F3
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STM8S105xxMemory and register map
Reset statusRegister nameRegister labelBlockAddress
Reserved area (12 bytes)0x00 53F4 to
0x00 53FF
0x00ADC control/ status registerADC _CSRADC10x00 5400
0x00ADC configuration register 1ADC_CR10x00 5401
0x00ADC configuration register 2ADC_CR20x00 5402
0x00ADC configuration register 3ADC_CR30x00 5403
0xXXADC data register highADC_DRH0x00 5404
0xXXADC data register lowADC_DRL0x00 5405
0x00ADC Schmitt trigger disable
register high
ADC_TDRH0x00 5406
0x00ADC Schmitt trigger disable
register low
ADC_TDRL0x00 5407
0x03ADC high threshold register
high
ADC_HTRH0x00 5408
0xFFADC high threshold register
low
ADC_HTRL0x00 5409
0x00ADC low threshold register
high
ADC_LTRH0x00 540A
0x00ADC low threshold register lowADC_LTRL0x00 540B
0x00ADC analog watchdog status
register high
ADC_AWSRH0x00 540C
0x00ADC analog watchdog status
register low
ADC_AWSRL0x00 540D
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Memory and register mapSTM8S105xx
Reset statusRegister nameRegister labelBlockAddress
0x00ADC analog watchdog control
register high
ADC _AWCRH0x00 540E
0x00ADC analog watchdog control
register low
ADC_AWCRL0x00 540F
Reserved area (1008 bytes)0x00 5410 to
0x00 57FF
(1) Depends on the previous reset source.
(2) Write only register.
CPU/SWIM/debug module/interrupt controller registers6.2.3
Table 10: CPU/SWIM/debug module/interrupt controller registers
Reset
status
Register nameRegister labelBlockAddress
0x00AccumulatorACPU(1)
0x00 7F00
0x00Program counter extendedPCE0x00 7F01
0x00Program counter highPCH0x00 7F02
0x00Program counter lowPCL0x00 7F03
0x00X index register highXH0x00 7F04
0x00X index register lowXL0x00 7F05
0x00Y index register highYH0x00 7F06
0x00Y index register lowYL0x00 7F07
0x07Stack pointer highSPH0x00 7F08
0xFFStack pointer lowSPL0x00 7F09
DocID14771 Rev 1244/124
STM8S105xxMemory and register map
Reset
status
Register nameRegister labelBlockAddress
0x28Condition code registerCCR0x00 7F0A
Reserved area (85 bytes)0x00 7F0B to
0x00 7F5F
0x00Global configuration registerCFG_GCRCPU0x00 7F60
0xFFInterrupt software priority register 1ITC_SPR1ITC0x00 7F70
0xFFInterrupt software priority register 2ITC_SPR20x00 7F71
0xFFInterrupt software priority register 3ITC_SPR30x00 7F72
0xFFInterrupt software priority register 4ITC_SPR40x00 7F73
0xFFInterrupt software priority register 5ITC_SPR50x00 7F74
0xFFInterrupt software priority register 6ITC_SPR60x00 7F75
0xFFInterrupt software priority register 7ITC_SPR70x00 7F76
0xFFInterrupt software priority register 8ITC_SPR80x00 7F77
Reserved area (2 bytes)0x00 7F78 to
0x00 7F79
0x00SWIM control status registerSWIM_CSRSWIM0x00 7F80
Reserved area (15 bytes)0x00 7F81 to
0x00 7F8F
0xFFDM breakpoint 1 register extended
byte
DM_BK1REDM0x00 7F90
0xFFDM breakpoint 1 register high byteDM_BK1RH0x00 7F91
0xFFDM breakpoint 1 register low byteDM_BK1RL0x00 7F92
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Memory and register mapSTM8S105xx
Reset
status
Register nameRegister labelBlockAddress
0xFFDM breakpoint 2 register extended
byte
DM_BK2RE0x00 7F93
0xFFDM breakpoint 2 register high byteDM_BK2RH0x00 7F94
0xFFDM breakpoint 2 register low byteDM_BK2RL0x00 7F95
0x00DM debug module control register 1DM_CR10x00 7F96
0x00DM debug module control register 2DM_CR20x00 7F97
0x10DM debug module control/status
register 1
DM_CSR10x00 7F98
0x00DM debug module control/status
register 2
DM_CSR20x00 7F99
0xFFDM enable function registerDM_ENFCTR0x00 7F9A
Reserved area (5 bytes)0x00 7F9B to
0x00 7F9F
(1) Accessible by debug module only
DocID14771 Rev 1246/124
STM8S105xxMemory and register map
Interrupt vector mapping7
Table 11: Interrupt mapping
Vector
address
Wakeup from
active-halt
mode
Wakeup
from halt
mode
DescriptionSource
block
IRQ
no.
0x00 8000YesYesResetRESET
0x00 8004--Software interruptTRAP
0x00 8008--External top level interruptTLI0
0x00 800CYes-Auto wake up from haltAWU1
0x00 8010--Clock controllerCLK2
0x00 8014Yes(1)
Yes(1)
Port A external interruptsEXTI03
0x00 8018YesYesPort B external interruptsEXTI14
0x00 801CYesYesPort C external interruptsEXTI25
0x00 8020YesYesPort D external interruptsEXTI36
0x00 8024YesYesPort E external interruptsEXTI47
0x00 80288
0x00 802C--Reserved9
0x00 8030YesYesEnd of transferSPI10
0x00 8034--TIM1 update/ overflow/
underflow/ trigger/ break
TIM111
0x00 8038--TIM1 capture/ compareTIM112
0x00 803C--TIM update/ overflowTIM213
0x00 8040--TIM capture/ compareTIM214
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Interrupt vector mappingSTM8S105xx
Vector
address
Wakeup from
active-halt
mode
Wakeup
from halt
mode
DescriptionSource
block
IRQ
no.
0x00 8044--Update/ overflowTIM315
0x00 8048--Capture/ compareTIM316
0x00 804C--Reserved17
0x00 8050--Reserved18
0x00 8054YesYesI2C interruptI2C19
0x00 8058--Tx completeUART220
0x00 805C--Receive register DATA
FULL
UART221
0x00 8060--ADC1 end of conversion/
analog watchdog interrupt
ADC122
0x00 8064--TIM update/ overflowTIM423
0x00 8068--EOP/ WR_PG_DISFlash24
0x00 806C
to 0x00
807C
Reserved
(1) Except PA1
DocID14771 Rev 1248/124
STM8S105xxInterrupt vector mapping
Option bytes8
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 12: Option bytes
Factory
default
setting
Option bitsOption
byte no.
Option
name
Addr.
01234567
00hROP [7:0]OPT0Read-out
protection
(ROP)
0x4800
00hUBC [7:0]OPT1User boot
code(UBC)
0x4801
FFhNUBC [7:0]NOPT10x4802
00hAFR0AFR1AFR2AFR3AFR4AFR5
AFR6AFR7OPT2Alternate
function
0x4803
FFhNAFR0NAFR1NAFR2NAFR3NAFR4NAFR5NAFR6NAFR7NOPT20x4804 remapping
(AFR)
00hWWDG
_HALT
WWDG
_HW
IWDG
_HW
LSI_ ENHSI
TRIM
ReservedOPT3Miscell.
option
0x4805h
FFhNWW
G_HALT
NWWDG
_HW
NIWDG
_HW
NLSI_
EN
NHSI
TRIM
ReservedNOPT30x4806
00hPRS C0PRS C1CKAWU
SEL
EXT CLKReservedOPT4Clock
option
0x4807
FFhNPR
SC0
NPRSC1NCKA
WUSEL
NEXT
CLK
ReservedNOPT40x4808
00hHSECNT [7:0]OPT5HSE clock
startup
0x4809
FFhNHSECNT [7:0]NOPT50x480A
00hReserved
OPT6
Reserved0x480B
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Option bytesSTM8S105xx
Factory
default
setting
Option bitsOption
byte no.
Option
name
Addr.
01234567
FFhReserved
NOPT6
0x480C
00hReserved
OPT7
Reserved0x480D
FFhReserved
NOPT7
0x480E
00hBL[7:0]
OPTBL
Bootloader0x487E
FFhNBL[7:0]
NOPTBL
0x487F
Table 13: Option byte description
DescriptionOption byte no.
ROP[7:0] Memory readout protection (ROP)OPT0
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code areaOPT1
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03: Page 0 to 4 defined as UBC, memory write-protected
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
AFR[7:0]OPT2
Refer to following table for the alternate function remapping
decriptions of bits [7:2].
HSITRIM:High speed internal clock trimming register sizeOPT3
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
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STM8S105xxOption bytes
DescriptionOption byte no.
LSI_EN:Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selectionOPT4
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL:Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]:HSE crystal oscillator stabilization timeOPT5
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
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Option bytesSTM8S105xx
DescriptionOption byte no.
ReservedOPT6
ReservedOPT7
BL[7:0] Bootloader option byteOPTBL
For STM8S products, this option is checked by the boot ROM code
after reset. Depending on the content of addresses 0x487E, 0x487F,
and 0x8000 (reset vector), the CPU jumps to the bootloader or to
the reset vector. Refer to the UM0560 (STM8L/S bootloader manual)
for more details.
For STM8L products, the bootloader option bytes are on addresses
0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control
whether the bootloader is active or not. For more details, refer to the
UM0560 (STM8L/S bootloader manual) for more details.
Table 14: Description of alternate function remapping bits [7:0] of OPT2
Description(1)
Option byte no.
AFR7 Alternate function remapping option 7OPT2
0: AFR7 remapping option inactive: Default alternate function(2).
1: Port D4 alternate function = BEEP.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate functions(2).
1: Port B5 alternate function = I2C_SDA; port B4 alternate function
= I2C_SCL.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate functions(2).
1: Port B3 alternate function = TIM1_ETR; port B2 alternate function
= TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0
alternate function = TIM1_CH1N.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate function(2).
1: Port D7 alternate function = TIM1_CH4.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate function(2).
1: Port D0 alternate function = TIM1_BKIN.
AFR2 Alternate function remapping option 2
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STM8S105xxOption bytes
Description(1)
Option byte no.
0: AFR2 remapping option inactive: Default alternate function(2).
1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has
priority over AFR3 if both are activated.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions(2).
1: Port A3 alternate function = TIM3_CH1; port D2 alternate function
TIM2_CH3.
AFR0 Alternate function remapping option 0
0: AFR0 remapping option inactive: Default alternate function(2).
1: Port D3 alternate function = ADC_ETR.
(1) Do not use more than one remapping option in the same port.
(2) Refer to pinout description.
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Option bytesSTM8S105xx
Unique ID9
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
•For use as serial numbers
•For use as security keys to increase the code security in the program memory while using
and combining this unique ID with software cryptograhic primitives and protocols before
programming the internal memory.
•To activate secure boot processes
Table 15: Unique ID registers (96 bits)
Unique ID bitsContent
description
Address
01234567
U_ID[7:0]
X co-ordinate
on the wafer
0x48CD
U_ID[15:8]0x48CE
U_ID[23:16]
Y co-ordinate
on the wafer
0x48CF
U_ID[31:24]0x48D0
U_ID[39:32]Wafer number0x48D1
U_ID[47:40]
Lot number
0x48D2
U_ID[55:48]0x48D3
U_ID[63:56]0x48D4
U_ID[71:64]0x48D5
U_ID[79:72]0x48D6
U_ID[87:80]0x48D7
U_ID[95:88]0x48D8
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STM8S105xxUnique ID
Electrical characteristics10
Parameter conditions10.1
Unless otherwise specified, all voltages are referred to VSS.
Minimum and maximum values10.1.1
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA= 25 °C and TA= TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 Σ).
Typical values10.1.2
Unless otherwise specified, typical data are based on TA= 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
Typical curves10.1.3
Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.
Typical current consumption10.1.4
For typical current consumption measurements, VDD, VDDIO and VDDA are connected together
in the configuration shown in the following figure.
Figure 8: Supply current measurement conditions
5 V or 3.3 V
AV
V
V
V
V
V
DD
DDA
DDIO
SS
SSA
SSIO
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Electrical characteristicsSTM8S105xx
Loading capacitor10.1.5
The loading conditions used for pin parameter measurement are shown in the following figure.
Figure 9: Pin loading conditions
STM8 PIN
50 pF
Pin input voltage10.1.6
The input voltage measurement on a pin of the device is described in the following figure.
Figure 10: Pin input voltage
STM8 PIN
VIN
Absolute maximum ratings10.2
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 16: Voltage characteristics
UnitMaxMinRatingsSymbol
V6.5-0.3Supply voltage (including VDDA and VDDIO)(1)
VDDx - VSS
6.5VSS - 0.3Input voltage on true open drain pins (PE1,
PE2)(2)
VIN
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STM8S105xxElectrical characteristics
UnitMaxMinRatingsSymbol
VDD + 0.3VSS - 0.3Input voltage on any other pin(2)
mV50Variations between different power pins|VDDx -
VDD|
50Variations between all the different ground pins|VSSx - VSS|
see Absolute maximum
ratings (electrical sensitivity)
Electrostatic discharge voltageVESD
(1) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be
connected to the external power supply
(2) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected.
If VIN maximum cannot be respected, the injection current must be limited externally to the
IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced
by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
Table 17: Current characteristics
UnitMax.(1)
RatingsSymbol
mA60Total current into VDD power lines (source)(2)
IVDD
60Total current out of VSS ground lines (sink)(2)
IVSS
20Output current sunk by any I/O and control pinIIO
20Output current source by any I/Os and control pin
200Total output current sourced (sum of all I/O and control
pins) for devices with two VDDIO pins(3)
ΣIIO
100Total output current sourced (sum of all I/O and control
pins) for devices with one VDDIO pin(3)
160Total output current sunk (sum of all I/O and control
pins) for devices with two VSSIO pins(3)
80Total output current sunk (sum of all I/O and control
pins) for devices with one VSSIO pin(3)
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Electrical characteristicsSTM8S105xx
UnitMax.(1)
RatingsSymbol
±4Injected current on NRST pinIINJ(PIN)
(4) (5)
±4Injected current on OSCIN pin
±4Injected current on any other pin(6)
±20Total injected current (sum of all I/O and control pins)(6)
ΣIINJ(PIN)
(4)
(1) Data based on characterization results, not tested in production.
(2) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be
connected to the external supply.
(3) I/O pins used simultaneously for high current source/sink must be uniformly spaced
around the package between the VDDIO/VSSIO pins.
(4) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected.
If VIN maximum cannot be respected, the injection current must be limited externally to the
IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced
by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
(5) Negative injection disturbs the analog performance of the device. See note in I2C interface
characteristics.
(6) When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the
absolute sum of the positive and negative injected currents (instantaneous values). These
results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O
port pins of the device.
Table 18: Thermal characteristics
UnitValueRatingsSymbol
°C-65 to 150Storage temperature rangeTSTG
150Maximum junction temperatureTJ
Operating conditions10.3
The device must be used in operating conditions that respect the parameters in the table
below. In addition, full account must be taken of all physical capacitor characteristics and
tolerances.
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STM8S105xxElectrical characteristics
Table 19: General operating conditions
UnitMaxMinConditionsParameterSymbol
MHz160Internal CPU clock
frequency
fCPU
V5.52.95Standard operating
voltage
VDD/ VDD_IO
nF3300470CEXT: capacitance of
external capacitor
VCAP(1)
Ohm0.3
-
at 1 MHz
(2)
ESR of external
capacitor
nH15
-
ESL of external
capacitor
mW443
-
44 and 48-pin devices,
with output on eight
Power dissipation at
TA = 85 °C for suffix
PD
(3)
standard ports, two high6or TA= 125° C for
suffix 3 sink ports and two open
drain ports
simultaneously(4)
360
-
32-pin package, with
output on eight standard
ports and two high sink
ports simultaneously(4)
°C85-40Maximum power
dissipation
Ambient temperature
for 6 suffix version
TA
125-40Maximum power
dissipation
Ambient temperature
for 3 suffix version
105-406 suffix versionJunction temperature
range
TJ
130-403 suffix version
(1)Care should be taken when selecting the capacitor, due to its tolerance, as well as the
parameter dependency on temperature, DC bias and frequency in addition to other factors.
The parameter maximum value must be respected for the full application range.
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(2)This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal
regulator.
(3) To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Thermal
characteristics ) with the value for TJmax given in the current table and the value for ΘJA
given in Thermal characteristics.
(4)Refer to Thermal characteristics
Figure 11: fCPUmax versus VDD
16
12
8
4
02.95 4.0 5.0 5.5
fCPU (MHz)
Functionality guaranteed
@TA-40 to 125 °C
Supply voltage
Functionality
not
guaranteed
in this area
Table 20: Operating conditions at power-up/power-down
UnitMaxTypMinConditionsParameterSymbol
µs/V∞2.0 (1)
VDD rise time ratetVDD
∞2.0 (1)
VDD fall time rate
ms1.7 (1)
VDD risingReset releasedelaytTEMP
V2.952.82.65Power-on reset
threshold
VIT+
2.882.72.58Brown-out reset
threshold
VIT-
mV70Brown-out reset
hysteresis
VHYS(BOR)
(1) Guaranteed by design, not tested in production.
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STM8S105xxElectrical characteristics
VCAP external capacitor10.3.1
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
Figure 12: External capacitor CEXT
ESR
RLeak
ESL
C
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
Supply current characteristics10.3.2
The current consumption is measured as described in Pin input voltage.
Total current consumption in run mode10.3.2.1
Table 21: Total current consumption with code execution in run mode at VDD = 5 V
UnitMax(1)
TypConditionsParameterSymbol
mA3.2HSE crystal osc.
(16 MHz)
fCPU = fMASTER
= 16 MHz
Supply
current in run
mode, code
IDD(RUN)
executed
from RAM 3.22.6HSE user ext. clock
(16 MHz)
3.22.5HSI RC osc.
(16 MHz)
2.21.6HSE user ext. clock
(16 MHz)
fCPU = fMASTER/128 =
125 kHz
2.01.3HSI RC osc.
(16 MHz)
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UnitMax(1)
TypConditionsParameterSymbol
0.75HSI RC osc.
(16 MH3z/8)
fCPU = fMASTER/128 =
15.625 kHz
0.55LSI RC osc.
(128 kHz)
fCPU = fMASTER
= 128 kHz
7.7HSE crystal osc.
(16 MHz)
fCPU = fMASTER
= 16 MHz
Supply
current in run
mode, code
IDD(RUN)
executed
fromFlash 8.07.0HSE user ext. clock
(16 MHz)
8.07.0HSI RC osc.
(16 MHz)
1.5HSI RC osc.
(16 MHz/8)(2)
fCPU = fMASTER
= 2 MHz
2.01.35HSI RC osc.
(16 MHz)
fCPU = fMASTER/128 =
125 kHz
0.75HSI RC osc.
(16 MHz/8)
fCPU = fMASTER/128 =
15.625 kHz
0.6LSI RC osc.
(128 kHz)
fCPU = fMASTER
= 128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V
UnitMax(1)
TypConditionsParameterSymbol
mA2.8HSE crystal osc.
(16 MHz)
fCPU = fMASTER = 16 MHzSupply
current
in run
IDD(RUN)
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STM8S105xxElectrical characteristics
UnitMax(1)
TypConditionsParameterSymbol
3.22.6HSE user ext. clock
(16 MHz)
mode,
code
executed
from
RAM 3.22.5HSI RC osc.
(16 MHz)
2.21.6HSE user ext. clock
(16 MHz)
fCPU = fMASTER/128
= 125 kHz
2.01.3HSI RC osc.
(16 MHz)
0.75HSI RC osc. (16 MHz/8)fCPU = fMASTER/128 =
15.625 kHz
0.55LSI RC osc.
(128 kHz)
fCPU = fMASTER = 128 kHz
7.3HSE crystal osc.
(16 MHz)
fCPU = fMASTER = 16 MHzSupply
current
in run
mode,
8.07.0HSE user ext. clock
(16 MHz)
code
executed
from
Flash
8.07.0HSI RC osc.
(16 MHz)
1.5HSI RC osc.
(16 MHz/8)(2)
fCPU = fMASTER = 2 MHz
2.01.35HSI RC osc.
(16 MHz)
fCPU = fMASTER/128
= 125 kHz
0.75HSI RC osc.
(16 MHz/8)
fCPU = fMASTER/128 =
15.625 kHz
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UnitMax(1)
TypConditionsParameterSymbol
0.6LSI RC osc.
(128 kHz)
fCPU = fMASTER = 128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Total current consumption in wait mode10.3.2.2
Table 23: Total current consumption in wait mode at VDD = 5 V
UnitMax(1)
TypConditionsParameterSymbol
mA2.15HSE crystal osc.
(16 MHz)
fCPU = fMASTER = 16
MHz
Supply
current in
wait mode
IDD(WFI)
2.01.55HSE user ext. clock
(16 MHz)
1.91.5HSI RC osc.
(16 MHz)
1.3HSI RC osc.
(16 MHz)
fCPU = fMASTER/128
= 125 kHz
0.7HSI RC osc.
(16 MHz/8)(2)
fCPU = fMASTER/128
= 15.625 kHz
0.5LSI RC osc.
(128 kHz)
fCPU = fMASTER = 128
kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
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STM8S105xxElectrical characteristics
Table 24: Total current consumption in wait mode at VDD = 3.3 V
UnitMax(1)
TypConditionsParameterSymbol
mA1.75HSE crystal osc.
(16 MHz)
fCPU = fMASTER = 16
MHz
Supply
current in
wait mode
IDD(WFI)
2.01.55HSE user ext. clock
(16 MHz)
1.91.5HSI RC osc.
(16 MHz)
1.3HSI RC osc.
(16 MHz)
fCPU = fMASTER/128
= 125 kHz
0.7HSI RC osc.
(16 MHz/8)(2)
fCPU = fMASTER/128
= 15.625 kHz
0.5LSI RC osc.
(128 kHz)
fCPU = fMASTER =
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Total current consumption in active halt mode10.3.2.3
Table 25: Total current consumption in active halt mode at VDD = 5 V
UnitMax at
125
°C(1)
Max
at 85
°C(1)
TypConditionsParameterSymbol
Clock sourceFlash mode(3)
Main
voltage
regulator
(MVR)(2)
µA1080HSE crystal
osc.
Operating
mode
OnSupply
current in
active halt
mode
IDD(AH)
(16 MHz)
400320200LSI RC osc.
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UnitMax at
125
°C(1)
Max
at 85
°C(1)
TypConditionsParameterSymbol
Clock sourceFlash mode(3)
Main
voltage
regulator
(MVR)(2)
(128 kHz)
1030HSE crystal
osc.
Power-down
mode
(16 MHz)
350270140LSI RC osc.
(128 kHz)
22012068LSI RC osc.
(128 kHz)
Operating
mode
Off
1506012Power-down
mode
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
Table 26: Total current consumption in active halt mode at VDD = 3.3 V
UnitMax at
125
°C(1)
Max
at 85
°C(1)
TypConditionsParameterSymbol
Clock sourceFlash
mode(3)
Main
voltage
regulator
(MVR)(2)
µA680HSE crystal
osc.
Operating
mode
OnSupply
current in
active halt
mode
IDD(AH)
(16 MHz)
400320200LSI RC osc.
(128 kHz)
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STM8S105xxElectrical characteristics
UnitMax at
125
°C(1)
Max
at 85
°C(1)
TypConditionsParameterSymbol
Clock sourceFlash
mode(3)
Main
voltage
regulator
(MVR)(2)
630HSE crystal
osc.
Power-down
mode
(16 MHz)
350270140LSI RC osc.
(128 kHz)
22012066LSI RC osc.
(128 kHz)
Operating
mode
Off
1506010Power-down
mode
(1) Data based on characterization results, not tested in production.
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
Total current consumption in halt mode10.3.2.4
Table 27: Total current consumption in halt mode at VDD = 5 V
UnitMax at
125
°C(1)
Max at
85 °C(1)
TypConditionsParameterSymbol
µA1509062Flash in operating mode, HSI
clock after wakeup
Supply current
in halt mode
IDD(H)
80256.5Flash in powerdown mode,
HSI clock after wakeup
(1) Data based on characterization results, not tested in production.
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Table 28: Total current consumption in halt mode at VDD = 3.3 V
UnitMax at
125
°C(1)
Max at
85 °C(1)
TypConditionsParameterSymbol
µA1509060Flash in operating mode, HSI
clock after wakeup
Supply current
in halt mode
IDD(H)
80204.5Flash in powerdown mode,
HSI clock after wakeup
(1) Data based on characterization results, not tested in production.
Low power mode wakeup times10.3.2.5
Table 29: Wakeup times
Unit
Max(1)
TypConditionsParameterSymbol
μs
See
note(2)
0 to 16 MHz
Wakeup time from
wait mode to run
tWU(WFI)
0.56fCPU = fMASTER = 16 MHzmode(3)
2(6)
1(6)
HSI
(after
Flash in operating
mode(5)
MVR voltage
regulator
on(4)
Wakeup time active
halt mode to run
mode(3)
tWU(AH)
wakeup)
3(6)
HSI
(after
Flash in
power-down
MVR voltage
regulator
Wakeup time active
halt mode to run
wakeup)mode(5)
on(4)
mode(3)
48(6)
HSI
(after
Flash in operating
mode(5)
MVR voltage
regulator
off(4)
Wakeup time active
halt mode to run
mode(3) wakeup)
50(6)
HSI
(after
Flash in
power-down
MVR voltage
regulator
Wakeup time active
halt mode to run
wakeup)mode(5)
off(4)
mode(3)
52Flash in operating mode(5)
Wakeup time from
halt mode to run
tWU(H) 54Flash in power-down mode(5)
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STM8S105xxElectrical characteristics
Unit
Max(1)
TypConditionsParameterSymbol
mode(3)
(1) Data guaranteed by design, not tested in production.
(2) tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU.
(3) Measured from interrupt event to interrupt vector fetch.
(4) Configured by the REGAH bit in the CLK_ICKR register.
(5) Configured by the AHALT bit in the FLASH_CR1 register.
(6) Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state10.3.2.6
Table 30: Total current consumption and timing in forced reset state
UnitMax(1)
TypConditionsParameterSymbol
μA
500VDD = 5 VSupply current in reset
state(2)
IDD(R)
400VDD = 3.3 V
μs150
Reset pin release to
vector fetch
tRESETBL
(1) Data guaranteed by design, not tested in production.
(2) Characterized with all I/Os tied to VSS.
Current consumption of on-chip peripherals10.3.2.7
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz.
Table 31: Peripheral current consumption
UnitTyp.ParameterSymbol
µA
230TIM1 supply current(1)
IDD(TIM1)
115TIM2 supply current (1)
IDD(TIM2)
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UnitTyp.ParameterSymbol
90TIM3 timer supply current (1)
IDD(TIM3)
30TIM4 timer supply current (1)
IDD(TIM4)
110UART2 supply current(2)
IDD(UART2)
45SPI supply current (2)
IDD(SPI)
65I2C supply current (2)
IDD(I
2
C)
955ADC1 supply current when converting(3)
IDD(ADC1)
(1) Data based on a differential IDD measurement between reset configuration and timer
counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in
production.
(2) Data based on a differential IDD measurement between the on-chip peripheral when kept
under reset and not clocked and the on-chip peripheral when clocked and not kept under
reset. No I/O pads toggling. Not tested in production.
(3) Data based on a differential IDD measurement between reset configuration and continuous
A/D conversions. Not tested in production.
Current consumption curves10.3.2.8
The following figures show typical current consumption measured with code executing in
RAM.
Figure 13: Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz
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Figure 14: Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V
Figure 15: Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz
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Figure 16: Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz
Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V
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Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz
External clock sources and timing characteristics10.3.3
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 32: HSE user external clock characteristics
UnitMaxMinConditionsParameterSymbol
MHz160
User external clock source
frequency
fHSE_ext
V
VDD + 0.3 V0.7 x VDD
OSCIN input pin high level
voltage
VHSEH
(1)
0.3 x VDD
VSS
OSCIN input pin low level
voltage
VHSEL
(1)
μA+1-1
VSS < VIN < VDD
OSCIN input leakage currentILEAK_HSE
(1) Data based on characterization results, not tested in production.
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Figure 19: HSE external clocksource
VHSEH
VHSEL
External clock
source OSCIN
fHSE
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 33: HSE oscillator characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz161
External high speed
oscillator frequency
fHSE
kΩ220
Feedback resistorRF
pF20
Recommended load
capacitance(2)
C(1)
mA
6 (startup)
C = 20 pF,
HSE oscillator power
consumption
IDD(HSE)
1.6 (stabilized)(3)
fOSC = 16 MHz
6 (startup)
C = 10 pF,
1.2 (stabilized)(3)
fOSC =16 MHz
mA/V5
Oscillator
transconductance
gm
ms1
VDD is stabilizedStartup timetSU(HSE)
(4)
(1) C is approximately equivalent to 2 x crystal Cload.
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(2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rmvalue. Refer to crystal manufacturer for more details
(3) Data based on characterization results, not tested in production.
(4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Figure 20: HSE oscillator circuit diagram
OSCOUT
OSCIN
fHSE to core
CL1
CL2
RF
STM8
Resonator Consumption
control
gm
Rm
Cm
LmCO
Resonator
HSE oscillator critical g mequation
gmcrit= (2 × Π × fHSE)2× Rm(2Co + C)2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1= CL2 = C: Grounded external capacitance
gm>> gmcrit
Internal clock sources and timing characteristics10.3.4
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 34: HSI oscillator characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz16FrequencyfHSI
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UnitMaxTypMinConditionsParameterSymbol
%1.0(2)
User-trimmed with
CLK_HSITRIMR register
Accuracy of HSI
oscillator
ACCHSI
for given VDD and TA
conditions(1)
1.0-1.0VDD = 5 V, TA= 25°C(3)
Accuracy of HSI
oscillator (factory
calibrated) 2.0-2.0VDD = 5 V, 25 °C ≤ TA≤
85 °C
3.0(3)
-3.0(3)
2.95 ≤ VDD≤ 5.5 V,-40 °C
≤ TA≤ 125 °C
µs1.0(2)
HSI oscillator
wakeup time
including calibration
tsu(HSI)
µA250(3)
170HSI oscillator power
consumption
IDD(HSI)
(1) Refer to application note.
(2) Guaranteed by design, not tested in production.
(3) Data based on characterization results, not tested in production.
Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temperatures
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Figure 22: Typical HSI accuracy vs VDD @ 4 temperatures
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 35: LSI oscillator characteristics
UnitMaxTypMinParameterSymbol
kHz146128110FrequencyfLSI
µs7(1)
LSI oscillator wakeup timetsu(LSI)
µA5LSI oscillator power consumptionIDD(LSI)
(1) Guaranteeed by design, not tested in production.
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Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures
Memory characteristics10.3.5
RAM and hardware registers
Table 36: RAM and hardware registers
UnitMinConditionsParameterSymbol
VVIT-max
(2)
Halt mode (or reset)Data retention mode(1)
VRM
(1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)
or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
refer to Operating conditions for the value of VIT-max
(2)Refer to the Operating conditions section for the value of VIT-max
Flash program memory/data EEPROM memory
General conditions: TA= -40 to 125°C.
Table 37: Flash program memory/data EEPROM memory
UnitMaxTypMin(1)
ConditionsParameterSymbol
V5.52.95fCPU ≤ 16 MHzOperating voltage (all modes,
execution/write/erase)
VDD
ms6.66.0Standard programming time
(including erase) for
tprog
byte/word/block (1 byte/4
bytes/128 bytes)
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UnitMaxTypMin(1)
ConditionsParameterSymbol
ms3.33.0Fast programming time for 1 block
(128 bytes)
ms3.33.0Erase time for 1 block (128 bytes)terase
cycles10 kTA= +85 °CErase/write cycles(2)(program
memory)
NRW
1.0M300 kTA= +125 ° CErase/write cycles(data memory)(2)
years20TRET = 55° CData retention (program memory)
after 10k erase/write cycles at TA
= +85 °C
tRET
20TRET = 55° CData retention (data memory) after
10k erase/write cycles at TA= +85
°C
1.0TRET = 85° CData retention (data memory) after
300 k erase/write cyclesat TA=
+125 °C
mA2.0Supply current (Flash
programming or erasing for 1 to
128 bytes)
IDD
(1) Data based on characterization results, not tested in production.
(2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes
even when a write/erase operation addresses a single byte.
I/O port pin characteristics10.3.6
General characteristics
Subject to general operating conditions for VDD and TAunless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.
Table 38: I/O static characteristics
UnitMaxTypMinConditionsParameterSymbol
V
0.3 x VDD
-0.3
VDD = 5 VInput low level
voltage
VIL
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UnitMaxTypMinConditionsParameterSymbol
V
VDD + 0.3
V
0.7 x
VDD
Input high level
voltage
VIH
mV700
Hysteresis(1)
Vhys
kΩ805530
VDD = 5 V, VIN = VSS
Pull-up resistorRpu
35(3)
Fast I/Os load = 50 pFRise and fall
time(10 % - 90 %)
tR, tF
ns
125(3)
Standard and high sink
I/OsLoad = 50 pF
20 (3)
Fast I/Os load = 20 pF
50 (3)
Standard and high sink
I/OsLoad = 20 pF
µA
±1.0 (2)
VSS ≤ VIN ≤ VDD
Input leakage
current, analog
and digital
Ilkg
nA
±250 (2)
VSS ≤ VIN ≤ VDD
Analog input
leakage current
Ilkg ana
µA
±1.0(2)
Injection current ±4 mALeakage current in
adjacent I/O(2)
Ilkg(inj)
(1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization
results, not tested in production.
(2) Data based on characterization results, not tested in production.
(3)Data guaranteed by design.
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Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures
Figure 25: Typical pull-up resistance vs VDD @ 4 temperatures
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Figure 26: Typical pull-up current vs VDD @ 4 temperatures
1. The pull-up is a pure resistor (slope goes through 0).
Table 39: Output driving current (standard ports)
UnitMaxMinConditionsParameterSymbol
V1.0(1)
IIO = 4 mA,
VDD = 3.3 V
Output low level with four pins
sunk
VOL
2.0IIO= 10 mA,
VDD = 5 V
Output low level with eight
pins sunk
V2.0(1)
IIO = 4 mA,
VDD = 3.3 V
Output high level with four
pins sourced
VOH
2.4IIO = 10 mA,
VDD = 5 V
Output high level with eight
pins sourced
(1) Data based on characterization results, not tested in production
Table 40: Output driving current (true open drain ports)
UnitMaxConditionsParameterSymbol
V1.5(1)
IIO = 10 mA, VDD = 3.3 VOutput low level with two pins
sunk
VOL
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UnitMaxConditionsParameterSymbol
1.0IIO = 10 mA, VDD = 5 V
2.0(1)
IIO = 20 mA, VDD = 5 V
(1) Data based on characterization results, not tested in production
Table 41: Output driving current (high sink ports)
UnitMaxMinConditionsParameterSymbol
V1.1(1)
IIO = 10 mA,
VDD = 3.3 V
Output low level with four pins
sunk
VOL
0.9IIO = 10 mA,
VDD = 5 V
Output low level with eight pins
sunk
1.6(1)
IIO = 20 mA,
VDD = 5 V
Output low level with four pins
sunk
1.9(1)
IIO = 10 mA,
VDD = 3.3 V
Output high level with four pins
sourced
VOH
3.8IIO = 10 mA,
VDD = 5 V
Output high level with eight pins
sourced
2.9(1)
IIO = 20 mA,
VDD = 5 V
Output high level with four pins
sourced
(1) Data based on characterization results, not tested in production
Typical output level curves10.3.7
The following figures show typical output level curves measured with output on a single pin.
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Figure 27: Typ. VOL @ VDD = 5 V (standard ports)
Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports)
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Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports)
Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports)
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Figure 31: Typ. VOL @ VDD = 5 V (high sink ports)
Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports)
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Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports)
Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
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Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports)
Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
Reset pin characteristics10.3.8
Subject to general operating conditions for VDD and TAunless otherwise specified.
Table 42: NRST pin characteristics
UnitMaxTypMinConditionsParameterSymbol
V
0.3 x VDD
--0.3
NRST input low
VIL(NRST)
level voltage(1)
VDD + 0.3-0.7 x VDD
IOL=2 mA
NRST input high
VIH(NRST)
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UnitMaxTypMinConditionsParameterSymbol
level voltage (1)
0.5--
NRST output low
VOL(NRST)
level voltage (1)
kΩ805530
NRST pull-up
RPU(NRST)
resistor(2)
ns
75--
NRST input filtered
tI FP(NRST)
pulse(3)
--500
NRST input not
tIN FP(NRST)
filtered pulse(3)
μs--
15
NRST output
pulse (3)
tOP(NRST)
(1) Data based on characterization results, not tested in production.
(2) The RPU pull-up equivalent resistor is based on a resistive transistor
(3) Data guaranteed by design, not tested in production.
Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures
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Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures
Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table
38: I/O static characteristics ), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 100 nF.
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Figure 40: Recommended reset pin protection
External
reset
circuit
(optional) 0.1 μF
NRST
VDD
RPU
Filter Internal reset
STM8
SPI serial peripheral interface10.3.9
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.
tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43: SPI characteristics
UnitMaxMinConditionsParameterSymbol
MHz80Master modeSPI clock
frequency
fSCK1
tc(SCK)
60Slave mode
ns
25Capacitive load: C = 30 pFSPI clock rise
and fall time
tr(SCK)
tf(SCK)
ns
4 x
tMASTER
Slave modeNSS setup timetsu(NSS)
(1)
ns70Slave modeNSS hold timeth(NSS)
(1)
ns
tSCK/2 +
15
tSCK/2 -
15
Master modeSCK high and
low time
tw(SCKH)
(1)
tw(SCKL)
(1)
ns
5Master modeData input
setup time
tsu(MI)
(1)
tsu(SI)
(1)
ns
5Slave modeData input
setup time
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UnitMaxMinConditionsParameterSymbol
ns
7Master modeData input hold
time
th(MI)
(1)
th(SI)
(1)
ns
10Slave modeData input hold
time
ns
3 x
tMASTER
Slave modeData output
access time
ta(SO)
(1) (2)
ns
25Slave modeData output
disable time
tdis(SO)
(1) (3)
ns
73Slave mode
(after enable edge)
Data output
valid time
tv(SO)
(1)
ns
36Master mode
(after enable edge)
Data output
valid time
tv(MO)
(1)
ns
28Slave mode
(after enable edge)
Data output
hold time
th(SO)
(1)
ns
12Master mode
(after enable edge)
th(MO)
(1)
(1) Values based on design simulation and/or characterization results, and not tested in
production.
(2) Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(3) Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
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Figure 41: SPI timing diagram - slave mode and CPHA = 0
ai14134
SCK Input
CPHA=0
MOSI
INPUT
MISO
OUT PUT
CPHA=0
MSB O UT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
tsu(SI)
th(SI)
Figure 42: SPI timing diagram - slave mode and CPHA = 1(1)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT PUT
CPHA=1
MSB O UT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
tsu(SI) th(SI)
NSS input
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
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Figure 43: SPI timing diagram - master mode(1)
ai14136b
SCK intput
CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BIT6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BIT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
th(MI)
High
SCK output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
I2C interface characteristics10.3.10
Table 44: I2C characteristics
UnitFast mode I2C(1)
Standard mode I2CParameterSymbol
Max(2)
Min(2)
Max(2)
Min(2)
μs1.34.7SCL clock low timetw(SCLL)
μs0.64.0SCL clock high timetw(SCLH)
ns100250SDA setup timetsu(SDA)
ns900(3)
0(4)
0(3)
SDA data hold timeth(SDA)
ns3001000SDA and SCL rise time
tr(SDA)
tr(SCL)
ns300300SDA and SCL fall time
tf(SDA)
tf(SCL)
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UnitFast mode I2C(1)
Standard mode I2CParameterSymbol
Max(2)
Min(2)
Max(2)
Min(2)
μs0.64.0START condition hold timeth(STA)
μs0.64.7
Repeated START condition
setup time
tsu(STA)
μs0.64.0STOP condition setup timetsu(STO)
μs1.34.7
STOP to START condition time
(bus free)
tw(STO:STA)
pF400400Capacitive load for each bus lineCb
(1) fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400kHz).
(2) Data based on standard I2C protocol requirement, not tested in production.
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time.
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
Figure 44: Typical application with I2C bus and timing diagram (1)
ai15385b
START
SDA
I²C bus
VDD
VDD
STM8S105xx
SDA
SCL
tf(SDA) tr(SDA)
SCL
th(STA)
tw(SCLH)
tw(SCLL)
tsu(SDA)
tr(SCL) tf(SCL)
th(SDA)
START REPEATED
START
tsu(STA)
tsu(STO)
STOP tsu(STA:STO)
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD
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10-bit ADC characteristics10.3.11
Subject to general operating conditions for VDDA, fMASTER, and TAunless otherwise specified.
Table 45: ADC characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz4.01.0VDDA =2.95 to 5.5 VADC clock frequencyfADC
6.01.0VDDA =4.5 to 5.5 V
V5.53.0Analog supplyVDDA
VVDDA
2.75(1)
Positive reference voltageVREF+
V0.5(1)
V SSA
Negative reference voltageVREF-
V
V DDAV SSA
Conversion voltage range(2)
VAIN
VVREF+
VREF-
Devices with
external
VREF+/VREF- pins
pF3.0Internal sample and hold
capacitor
CADC
µs0.75fADC = 4 MHzSampling timetS
(2)
0.5fADC = 6 MHz
µs7.0Wakeup time from standbytSTAB
µs3.5fADC = 4 MHzTotal conversion time
(including sampling time,
10-bit resolution)
tCONV
µs2.33fADC = 6 MHz
1/fADC
14
(1) Data guaranteed by design, not tested in production..
(2) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS. After the end of the sample time tS,
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STM8S105xxElectrical characteristics
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tSdepend on programming.
Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V
UnitMax(1)
TypConditionsParameterSymbol
LSB2.51.0fADC = 2 MHzTotal unadjusted error(2)
|ET|
3.01.4fADC = 4 MHz
3.51.6fADC = 6 MHz
2.00.6fADC = 2 MHzOffset error(2)
|EO|
2.51.1fADC = 4 MHz
2.51.2fADC = 6 MHz
2.00.2fADC = 2 MHzGain error(2)
|EG|
2.50.6fADC = 4 MHz
2.50.8fADC = 6 MHz
1.50.7fADC = 2 MHzDifferential linearity error(2)
|ED|
1.50.7fADC = 4 MHz
1.50.8fADC = 6 MHz
1.50.6fADC = 2 MHzIntegral linearity error(2)
|EL|
1.50.6fADC = 4 MHz
1.50.6fADC = 6 MHz
(1) Data based on characterisation results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
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Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in the I/O
port pin characteristics section does not affect the ADC accuracy.
Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V
UnitMax(1)
TypConditionsParameterSymbol
LSB2.01.1fADC = 2 MHzTotal unadjusted error(2)
|ET|
2.51.6fADC = 4 MHz
1.50.7fADC = 2 MHzOffset error(2)
|EO|
2.01.3fADC = 4 MHz
1.50.2fADC = 2 MHzGain error (2)
|EG|
2.00.5fADC = 4 MHz
1.00.7fADC = 2 MHzDifferential linearity error(2)
|ED|
1.00.7fADC = 4 MHz
1.50.6fADC = 2 MHzIntegral linearity error(2)
|EL|
1.50.6fADC = 4 MHz
(1) Data based on characterisation results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in I/O port
pin characteristics does not affect the ADC accuracy.
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Figure 45: ADC accuracy characteristics
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
ET= Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.
EO= Offset error: deviation between the first actual transition and the first ideal one.
EG= Gain error: deviation between the last ideal transition and the last actual one.
ED= Differential linearity error: maximum deviation between actual steps and the ideal
one.
EL= Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.
Figure 46: Typical application with ADC
STM8
10-bit A/D
conversion
RAIN
CAIN
VAIN AINx
VDD
VT
0.6 V
VT
0.6 V IL
± 1 µA CADC
EMC characteristics10.3.12
Susceptibility tests are performed on a sample basis during product characterization.
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Functional EMS (electromagnetic susceptibility)10.3.12.1
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
•FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
Designing hardened software to avoid noise problems10.3.12.2
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
Table 48: EMS data
Level/
class
ConditionsParameterSymbol
2/B (1)
VDD = 5 V, TA= 25 °C, fMASTER = 16 MHz,
conforming to IEC 1000-4-2
Voltage limits to be
applied on any I/O pin to
induce a functional
disturbance
VFESD
4/A (1)
VDD= 5 V, TA= 25 °C ,fMASTER = 16
MHz,conforming to IEC 1000-4-4
Fast transient voltage
burst limits to be applied
through 100 pF on VDD
VEFTB
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Level/
class
ConditionsParameterSymbol
and VSS pins to induce a
functional disturbance
(1)Data obtained with HSI clock configuration, after applying HW recommendations described
in AN2860 (EMC guidelines for STM8S microcontrollers).
Electromagnetic interference (EMI)10.3.12.3
Emission tests conform to the IEC61967-2 standard for test software, board layout and pin
loading.
Table 49: EMI data
UnitConditionsParameterSymbol
Max fHSE/fCPU
(1)
Monitored
frequency
band
General
conditions
8 MHz/ 16
MHz
8 MHz/ 8
MHz
dBµV14130.1 MHz to
30 MHz
VDD = 5 V,
TA= +25 °C,
Peak levelSEMI
192330 MHz to
130 MHz
LQFP48
package
conforming to
IEC61967-2
-4.0-4.0130 MHz to 1
GHz
—1.52.0SAE EMI
level
(1) Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)10.3.12.4
Based on two different tests (ESD and LU) using specific measurement methods, the product
is stressed in order to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
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Electrostatic discharge (ESD)10.3.12.5
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the
JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Table 50: ESD absolute maximum ratings
UnitMaximum
value(1)
ClassConditionsRatingsSymbol
V2000ATA= +25°C,
conforming to
JESD22-A114
Electrostatic discharge
voltage (Human body model)
VESD(HBM)
V1000IVTA=+25°C, conforming
to JESD22-C101
Electrostatic discharge
voltage (Charge device
model)
VESD(CDM)
(1) Data based on characterization results, not tested in production
Static latch-up10.3.12.6
Two complementary static tests are required on 10 parts to assess the latch-up performance:
•A supply overvoltage (applied to each power supply pin)
•A current injection (applied to each input, output and configurable I/O pin) are performed
on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 51: Electrical sensitivities
Class(1)
ConditionsParameterSymbol
ATA= +25 °CStatic latch-up classLU
ATA= +85 °C
ATA= +125 °C
(1) Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).
DocID14771 Rev 12102/124
STM8S105xxElectrical characteristics
Package information11
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK®packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK®
is an ST trademark.
48-pin LQFP package mechanical data11.1
Figure 47: 48-pin low profile quad flat package (7 x 7)
5B_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
24
25
36
37
b
48
1
Pin 1
identification 12
13
Table 52: 48-pin low profile quad flat package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.06301.600A
0.00590.00200.1500.050A1
0.05710.05510.05311.4501.4001.350A2
0.01060.00870.00670.2700.2200.170b
0.00790.00350.2000.090c
0.36220.35430.34659.2009.0008.800D
103/124DocID14771 Rev 12
Package informationSTM8S105xx
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.28350.27560.26777.2007.0006.800D1
0.21655.500D3
0.36220.35430.34659.2009.0008.800E
0.28350.27560.26777.2007.0006.800E1
0.21655.500E3
0.01970.500e
0.02950.02360.01770.7500.6000.450L
0.03941.000L1
7.0°3.5°0°7.0°3.5°0°k
0.00310.080ccc
(1) Values in inches are converted from mm and rounded to 4 decimal digits
DocID14771 Rev 12104/124
STM8S105xxPackage information
44-pin LQFP package mechanical data11.2
Figure 48: 44-pin low profile quad flat package
4Y_ME
L
A1 K
L1
c
A
A2
D
D1
D3
E3 E1 E
22
23
33
34
b
44
1
Pin 1
identification 11
12
ccc C
Table 53: 44-pin low profile quad flat package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.06301.600A
0.00590.00200.1500.050A1
0.05710.05510.05311.4501.4001.350A2
0.01770.01460.01180.4500.3700.300b
0.00790.00350.2000.090c
0.48030.47240.464612.20012.00011.800D
0.40160.39370.385810.20010.0009.800D1
0.31508.000D3
0.48030.47240.464612.20012.00011.800E
105/124DocID14771 Rev 12
Package informationSTM8S105xx
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.40160.39370.385810.20010.0009.800E1
0.31508.000E3
0.03150.800e
0.02950.02360.01770.7500.6000.450L
0.03941.000L1
7.0°3.5°0.0°7.0°3.5°0.0°k
0.00390.100ccc
(1) Values in inches are converted from mm and rounded to 4 decimal digits
32-pin LQFP package mechanical data11.3
Figure 49: 32-pin low profile quad flat package (7 x 7)
5V_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
16
17
24
25
b
32
1
Pin 1
identification 8
9
DocID14771 Rev 12106/124
STM8S105xxPackage information
Table 54: 32-pin low profile quad flat package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.06301.600A
0.00590.00200.1500.050A1
0.05710.05510.05311.4501.4001.350A2
0.01770.01460.01180.4500.3700.300b
0.00790.00350.2000.090c
0.36220.35430.34659.2009.0008.800D
0.28350.27560.26777.2007.0006.800D1
0.22055.600D3
0.36220.35430.34659.2009.0008.800E
0.28350.27560.26777.2007.0006.800E1
0.22055.600E3
0.03150.800e
0.02950.02360.01770.7500.6000.450L
0.03941.000L1
7.0°3.5°0°7.0°3.5°0°k
0.00390.100ccc
(1) Values in inches are converted from mm and rounded to 4 decimal digits
107/124DocID14771 Rev 12
Package informationSTM8S105xx
32-lead UFQFPN package mechanical data11.4
Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5)
AOB8_ME
1. Drawing is not to scale.
2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended
to connect and solder this backside pad to PCB ground.
4. Dimensions are in millimeters.
Table 55: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.02360.02170.01970.6000.5500.500A
0.00200.00080.0500.0200A1
0.00790.200A3
0.01180.00980.00710.3000.2500.180b
DocID14771 Rev 12108/124
STM8S105xxPackage information
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.20280.19690.19095.1505.0004.850D
0.14570.12603.7003.4503.200D2
0.20280.19690.19095.1505.0004.850E
0.14570.13580.12603.7003.4503.200E2
0.01970.500e
0.01970.01570.01180.5000.4000.300L
0.00310.080ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
SDIP32 package mechanical data11.5
Figure 51: 32-lead shrink plastic DIP (400 ml) package
76_ME
A2
A1
A
L
B1 B e
eA
DD
1
32
16
17
E1
E
C
eB
Table 56: 32-lead shrink plastic DIP (400 ml) package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.20000.14800.14005.0803.7593.556A
109/124DocID14771 Rev 12
Package informationSTM8S105xx
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.02000.508A1
0.18000.14000.12004.5723.5563.048A2
0.02300.01800.01400.5840.4570.356B
0.05500.04000.03001.3971.0160.762B1
0.01400.01000.00790.3560.2540.203C
1.12011.10001.079928.45027.94027.430D
0.43500.40980.390011.05010.4109.906E
0.37000.35000.30009.3988.8907.620E1
0.07001.778e
0.400010.160eA
0.500012.700eB
0.15000.12000.10003.8103.0482.540L
(1) Values in inches are converted from mm and rounded to 4 decimal digits
DocID14771 Rev 12110/124
STM8S105xxPackage information
Thermal characteristics12
The maximum chip junction temperature (TJ max) must never exceed the values given in
Operating conditions
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
•TAmax is the maximum ambient temperature in °C
•ΘJA is the package junction-to-ambient thermal resistance in ° C/W
•PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
•PINTmax is the product of IDD andVDD, expressed in Watts. This is the maximum chip internal
power.
•PI/Omax represents the maximum power dissipation on output pinsWhere:PI/Omax =Σ (VOL*IOL)
+ Σ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low
and high level in the application.
Table 57: Thermal characteristics(1)
UnitValueParameterSymbol
°C/W57
Thermal resistance junction-ambientΘJA
LQFP 48 - 7 x 7 mm
°C/W54
Thermal resistance junction-ambientΘJA
LQFP 44 - 10 x 10 mm
°C/W60
Thermal resistance junction-ambientΘJA
LQFP 32 - 7 x 7 mm
°C/W38
Thermal resistance junction-ambientΘJA
UFQFPN 32 - 5 x 5 mm
°C/W60
Thermal resistance junction-ambientΘJA
SDIP 32 - 400 mils
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural
convection environment.
111/124DocID14771 Rev 12
Thermal characteristicsSTM8S105xx
Reference document12.1
JESD51-2 integrated circuits thermal test method environment conditions - natural convection
(still air). Available from www.jedec.org.
Selecting the product temperature range12.2
When ordering the microcontroller, the temperature range is specified in the order code.
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
•Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2)
•IDDmax = 15 mA, VDD = 5.5 V
•Maximum 8 standard I/Os used at the same time in output at low level with IOL = 10 mA,
VOL= 2 V
•Maximum 4 high sink I/Os used at the same time in output at low level with IOL = 20 mA,
VOL= 1.5 V
•Maximum 2 true open drain I/Os used at the same time in output at low level with IOL =
20 mA, VOL= 2 V
PINTmax = 15 mA x 5.5 V = 82.5 mW
PIOmax = (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW
This gives: PINTmax = 82.5 mW and PIOmax 360 mW:
PDmax = 82.5 mW + 360 mW
Thus: PDmax = 443 mW
TJmax for LQFP32 can be calculated as follows, using the thermal resistance ΘJA :
TJmax = 82° C + (60° C/W x 443 mW) = 82°C + 27°C = 109° C
This is within the range of the suffix 3 version parts (-40 < TJ< 131° C). In this case, parts
must be ordered at least with the temperature range suffix 3.
DocID14771 Rev 12112/124
STM8S105xxThermal characteristics
Ordering information13
Figure 52: STM8S105xx access line ordering information scheme
Product class
Pin count
K = 32 pins
S = 44 pins
C = 48 pins
Package type
B = SDIP
T = LQFP
U = UFQFPN
Example:
Sub-family type
105 = access line STM8S105x
Family type
S = Standard
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Program memory size
4 = 16 Kbytes
6 = 32 Kbytes
Package pitch/thickness
No character = 0.5 mm
C = 0.8 mm pitch
A = 0.55 mm thickness for UFQFPN
Packing
No character = Tray or tube
TR = Tape and reel
STM8 S105 K 4 T 6CTR
1. For a list of available options (e.g. memory size, package) and orderable part numbers or
for further information on any aspect of this device, please go to www.st.com or contact
the ST sales office nearest to you.
STM8S105 FASTROM microcontroller option list13.1
(last update: September 2010)
.............................................................................................Customer
.............................................................................................Address
113/124DocID14771 Rev 12
Ordering informationSTM8S105xx
.............................................................................................Contact
.............................................................................................Phone no.
.............................................................................................Reference FASTROM codea
Preferable format for programing code is .Hex (.s19 is accepted)
If data EEPROM programing is required, a seperate file must be sent with the requested data.
Important: See the option byte section in the datasheet for authorized option byte
combinations and a detailed explanation.
Device type/memory size/package (check only one option)
32 Kbyte16 KbyteFASTROM device
[ ] STM8S105K6[ ] STM8S105K4LQFP32
[ ] STM8S105S6[ ] STM8S105S4LQFP44
[ ] STM8S105C6[ ] STM8S105C4LQFP48
Conditioning (check only one option)
[ ] Tape & reel or [ ] Tray
Special marking (check only one option)
[ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts
are:
LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
LQFP44: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
LQFP48: 2 lines of 8 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
Temperature range
[ ] -40°C to +85°C or [ ] -40°C to +125°C
Padding value for unused program memory (check only one option)
Fixed value[ ]0xFF
TRAP instruction opcode[ ]0x83
Illegal opcode (causes a reset when executed)[ ]0x75
OPT0 memory readout protection (check only one option)
[ ] Disable or [ ] Enable
OPT1 user boot code area (UBC)
0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below.
[ ] 0: Reset
UBC, bit0
aFASTROM code name is assigned by STMicroelectronics.
DocID14771 Rev 12114/124
STM8S105xxOrdering information
[ ] 1: Set
[ ] 0: Reset
UBC bit1
[ ] 1: Set
[ ] 0: Reset
UBC bit2
[ ] 1: Set
[ ] 0: Reset
UBC bit3
[ ] 1: Set
[ ] 0: Reset
UBC bit4
[ ] 1: Set
[ ] 0: Reset
UBC bit5
[ ] 1: Set
OPT2 alternate function remapping
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR0
(check only one option)
[ ] 1: Port D3 alternate function = ADC_ETR
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR1
(check only one option)
[ ] 1: Port A3 alternate function = TIM3_CH1, port D2 alternate
function = TIM2_CH3.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR2
(check only one option)
[ ] 1: Port D0 alternate function = CLK_CCO.
Note: If both AFR2 and AFR3 are activated, AFR2 option
has priority over AFR3.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR3
(check only one option)
[ ] 1: Port D0 alternate function = TIM1_BKIN.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR4
(check only one option)
[ ] 1: Port D7 alternate function = TIM1_CH4.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR5
(check only one option)
115/124DocID14771 Rev 12
Ordering informationSTM8S105xx
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N,
port B0 alternate function = TIM1_CH1N.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description
AFR6
(check only one option)
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR7
(check only one option)
[ ] 1: Port D4 alternate function = BEEP.
OPT3 watchdog
[ ] 0: No reset generated on halt if WWDG active.
WWDG_HALT
(check only one option) [ ] 1: Reset generated on halt if WWDG active.
[ ] 0: WWDG activated by software.
WWDG_HW
(check only one option) [ ] 1: WWDG activated by hardware.
[ ] 0: IWDG activated by software.
IWDG_HW
(check only one option) [ ] 1: IWDG activated by hardware.
[ ] 0: LSI clock is not available as CPU clock source.
LSI_EN
(check only one option) [ ] 1: LSI clock is available as CPU clock source.
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR
register.
HSITRIM
(check only one option)
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR
register.
OPT4 wakeup
[ ] for 16 MHz to 128 kHz prescaler.
PRSC
(check only one option) [ ] for 8 MHz to 128 kHz prescaler.
[ ] for 4 MHz to 128 kHz prescaler.
[ ] 0: LSI clock source selected for AWU.
CKAWUSEL
(check only one option) [ ] 1: HSE clock with prescaler selected as clock source
for AWU.
[ ] 0: External crystal connected to OSCIN/OSCOUT.
EXTCLK
(check only one option) [ ] 1: External clock signal on OSCIN.
DocID14771 Rev 12116/124
STM8S105xxOrdering information
OPT5 crystal oscillator stabilization HSECNT (check only one option)
[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OPT6 is reserved
OPT7 is reserved
OPTBL bootloader option byte (check only one option)
Refer to the UM0560 (STM8L/S bootloader manual) for more details.
[ ] Disable (00h)
[ ] Enable (55h)
...........................................................................................................Comments:
...........................................................................................................Supply operating range
in the application:
...........................................................................................................Notes:
...........................................................................................................Date:
...........................................................................................................Signature:
117/124DocID14771 Rev 12
Ordering informationSTM8S105xx
STM8 development tools14
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards
and a low-cost in-circuit debugger/programmer.
Emulation and in-circuit debugging tools14.1
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8
application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers
new advanced debugging capabilities including profiling and coverage to help detect and
eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order
exactly what you need to meet your development requirements and to adapt your emulation
system to support existing and future ST microcontrollers.
STice key features
•Occurrence and time profiling and code coverage (new features)
•Advanced breakpoints with up to 4 levels of conditions
•Data breakpoints
•Program and data trace recording up to 128 KB records
•Read/write on the fly of memory during emulation
•In-circuit debugging/programming via SWIM protocol
•8-bit probe analyzer
•1 input and 2 output triggers
•Power supply follower managing application voltages between 1.62 to 5.5 V
•Modularity that allows you to specify the components you need to meet your development
requirements and adapt to future requirements
•Supported by free software tools that include integrated development environment (IDE),
programming software interface and assembler for STM8.
Software tools14.2
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
DocID14771 Rev 12118/124
STM8S105xxSTM8 development tools
STM8 toolset14.2.1
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
•Seamless integration of C and ASM toolsets
•Full-featured debugger
•Project management
•Syntax highlighting editor
•Integrated programming interface
•Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
C and assembly toolchains14.2.2
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
•Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes
of code. For more information, see www.cosmic-software.com.
•Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
•STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which
allows you to assemble and link your application source code.
Programming tools14.3
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to include
a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
119/124DocID14771 Rev 12
STM8 development toolsSTM8S105xx
Revision history15
Table 58: Document revision history
ChangesRevisionDate
Initial release.105-Jun-2008
Corrected number of high sink outputs to 9 in I/Os on Features.
223-Jun-2008
Updated part numbers in Table 2: STM8S105xx access line
features.
Updated part numbers in Table 2: STM8S105xx access line
features.
312-Aug-2008
USART renamed UART1, LINUART renamed UART2.
Added Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin
access line devices.
Removed STM8S102xx and STM8S104xx root part numbers
corresponding to devices without data EEPROM.
417-Sep-2008
Updated STM8S103 pinout in Section 5.2 on page 29.
Added low and medium density Flash memory categories.
Added Note 1 in Table 17: Current characteristics.
Updated Table 12: Option bytes .
Updated STM8S103 pinout in Section 5.2 on page 29505-Feb-2009
Updated number of High Sink I/Os in pinout.
TSSOP20 pinout modified (PD4 moved to pin 1 etc.)
Added WFQFN20 package
Updated Option bytes.
Added Memory and register map.
Removed STM8S103x products (separate STM8S103
datasheet created)
627-Feb-2009
Updated Electrical characteristics.
Added SDIP32 silhouette and package to Features and SDIP32
package mechanical data ; updated Pinout and pin description.
712-May-2009
Updated VDD range (2.95 V to 5.5 V) on Features.
Amended name of package VQFPN32
DocID14771 Rev 12120/124
STM8S105xxRevision history
ChangesRevisionDate
Added Table 5 on page 22 .
Updated Auto wakeup counter.
Updated pins 25, 30, and 31 in Pinout and pin description.
Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin
access line devices.
Added Table 14: Description of alternate function remapping
bits [7:0] of OPT2.
Electrical characteristics: Updated VCAP specifications;
updated Table 15, Table 18, Table 20, Table 21, Table 22,
Table 23, Table 24, Table 25, Table 26, Table 27, Table 29,
Table 35, and Table 42; added current consumption curves ;
removed Figure 20: typical HSE frequency vs fcpu @ 4
temperatures; updated Figure 13, Figure 14, Figure 15, Figure
16 and Figure 17 ; modified HSI accuracy in Table 33 ; added
Figure 44 ; modified fSCK, tV(SO) and tV(MO) in Table 42 ;
updated figures and tables of High speed internal RC oscillator
(HSI) ; replaced Figure 23, Figure 24, Figure 26, and Figure
39 .
Package information: Updated Table 57: Thermal
characteristics(1) and removed Table 57: Junction temperature
range. Updated Figure 52: STM8S105xx access line ordering
information scheme.
Document status changed from “preliminary data” to
“datasheet”.
810-Jun-2009
Standardized name of the VFQFPN package.
Removed ‘wpu’ from I2C pins in Pinout and pin description
Added UFQFPN32 package silhouette to the title page.921-Apr-2010
Features: added unique ID.
Clock controller: updated bit positions for TIM2 and TIM3.
Beeper: added information about availability of the beeper
output port through option bit AFR7.
Analog-to-digital converter (ADC1): added a note concerning
additional AIN12 analog input.
STM8S105 pinouts and pin description: added UFQFPN32
package details; updated default alternate function of
PB2/AIN2[TIM1_CH3N] pin in the "Pin description for
STM8S105 microcontrollers" table.
Option bytes: added description of STM8L bootloader option
bytes to the option byte description table.
121/124DocID14771 Rev 12
Revision historySTM8S105xx
ChangesRevisionDate
Added Unique ID
Operating conditions: added introductory text; removed low
power dissipation condition for TA, replaced "CEXT" by "VCAP",
and added ESR and ESL data in table "general operating
conditions".
Total current consumption in halt mode: replaced max value
of IDD(H) at 85 °C from 20 µA to 25 µA for the condition "Flash
in powerdown mode, HSI clock after wakeup in the table "total
current consumption in halt mode at VDD = 5 V.
Low power mode wakeup times: added first condition (0 to 16
MHz) for the tWU(WFI) parameter in the table "wakeup times".
Internal clock sources and timing characteristics: In the table
"HSI oscillator characteristics", replaced min and max values
of "ACCHSI factory calibrated parameter" and removed footnote
4 concerning further characterization of results.
Functional EMS (electromagnetic susceptibility): IEC 1000
replaced with IEC 61000.
Designing hardened software to avoid noise problems: IEC
1000 replaced with IEC 61000.
Electromagnetic interference (EMI): SAE J 1752/3 replaced
with IEC61967-2.
Thermal characteristics: Replaced the thermal resistance
junction ambient temperature of LQFP32 7X7 mm from 59 °C
to 60 °C in the thermal characteristics table.
Added 32-lead UFQFPN package mechanical data.
Added STM8S105 FASTROM microcontroller option list.
Table 5: Legend/abbreviations for pinout tables : updated "reset
state"; removed "HS", (T), and "[ ]".
1021-Sep-2010
Table 6: Pin description for STM8S105 microcontrollers: added
footnotes to the PF4 and PD1 pins.
Table 8: I/O port hardware register map: changed reset status
of Px_IDR from 0x00 to 0xXX.
Table 9: General hardware register map: Standardized all
address and reset state values; updated the reset state values
of the RST_SR, CLK_SWCR, CLK_HSITRIMR,
CLK_SWIMCCR, IWDG_KR, UART2_DR, and ADC_DRx
registers; replaced reserved address "0x00 5248" with the
UART2_CR5.
Figure 40: Recommended reset pin protection: replaced 0.01
µF with 0.1 µF
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STM8S105xxRevision history
ChangesRevisionDate
Updated Figure 44: Typical application with I2C bus and timing
diagram (1) .
Updated footnote 1 in Table 46: ADC accuracy with RAIN <
10 kΩ , VDDA= 5 V and Table 47: ADC accuracy with RAIN
< 10 kΩ RAIN, VDDA = 3.3 V .
STM8S105 FASTROM microcontroller option list: removed bits
6 and 7 from OPT1 user boot code area (UBC); added "disable"
to 00h and "enable" to 55h of OPTBL bootloader option byte.
Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead
package (5 x 5): replaced note 1 and added note 2.
Removed VFQFPN32 package.
1104-Apr-2012
Modified Description.
Remove weak pull-up input for PE1 and PE2 in Table 6: Pin
description for STM8S105 microcontrollers
Updated Table 11: Interrupt mapping for TIM2 and TIM4.
Updated notes related to VCAP in Table 19: General operating
conditions.
Added values of tR/tFfor 50 pF load capacitance, and updated
note in Table 38: I/O static characteristics.
Updated typical and maximum values of RPU in Table 38: I/O
static characteristics and Table 42: NRST pin characteristics.
Changed SCK input to SCK output in SPI serial peripheral
interface
Added ΘJA for UFQFPN32 and SDIP32 in Table 57: Thermal
characteristics(1) , and updated Selecting the product
temperature range
Added UFQFPN package thickness in Figure 52: STM8S105xx
access line ordering information scheme.
1228-Jun-2012
123/124DocID14771 Rev 12
Revision historySTM8S105xx
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