CY7C107D
CY7C1007D
1-Mbit (1M x 1) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05469 Rev. *H Revised April 7, 2011
Features
■Pin- and function-compatible with CY7C107B/CY7C1007B
■High speed
—t
AA = 10 ns
■Low active power
—I
CC = 80 mA @ 10 ns
■Low complementary metal oxide semiconductor (CMOS)
standby power
—I
SB2 = 3 mA
■2.0 V data retention
■Automatic power-down when deselected
■CMOS for optimum speed/power
■Transistor transistor logic (TTL) compatible inputs and outputs
■CY7C107D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil
wide Molded SOJ package
Functional Description [1]
The CY7C107D and CY7C1007D are high-performance CMOS
static RAMs organized as 1,048,576 words by 1 bit. Easy
memory expansion is provided by an active LOW Chip Enable
(CE) and tri-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected. The output pin (DOUT) is placed in a
high-impedance state when:
■Deselected (CE HIGH)
■When the write operation is active (CE and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the input pin (DIN) is written into the
memory location specified on the address pins (A0 through A19).
Read from the device by taking Chip Enable (CE) LOW while
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins appears on the data output (DOUT) pin.
SENSE AMPS
POWER
DOWN
CE
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
1M x 1
ARRAY
INPUT BUFFER
A9
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
DIN
DOUT
A19
A18
Logic Block Diagram
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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Document #: 38-05469 Rev. *H Page 2 of 14
Contents
Pin Configuration .............................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics..................................................4
Capacitance ....................................................................... 5
Thermal Resistance...........................................................5
AC Test Loads and Waveforms .......................................5
Switching Characteristics................................................. 6
Data Retention Characteristics ........................................ 7
Data Retention Waveform ................................................7
Switching Waveforms ...................................................... 7
Truth Table ........................................................................ 8
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
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Pin Configuration [2]
Selection Guide
CY7C107D-10
CY7C1007D-10 Unit
Maximum access time 10 ns
Maximum operating current 80 mA
Maximum CMOS standby current, ISB2 3mA
1
2
3
4
5
6
7
8
9
11
14 15
16
20
19
18
17
21
24
23
22
12
13
25
28
27
26
A
16
A
10
A
11
A
12
A
13
A
14
A
7
NC
A
17
A
18
A
19
NC
A
4
A
6
A
3
WE
A
15
CE
D
IN
A
0
A
1
A
2
V
CC
GND
10
Top View
SOJ
D
OUT
A
5
A
8
A
9
Note
2. NC pins are not connected on the die.
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Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature 65 °C to +150 °C
Ambient temperature with
power applied55 °C to +125 °C
Supply voltage on VCC relative to GND [3] 0.5 V to +6.0 V
DC voltage applied to outputs
in High-Z state [3] 0.5 V to VCC + 0.5 V
DC input voltage [3] 0.5 V to VCC + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current .....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40 °C to +85 °C 5 V 0.5 V 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
7C107D-10
7C1007D-10 Unit
Min Max
VOH Output HIGH voltage IOH = 4.0 mA 2.4 V
VOL Output LOW voltage IOL = 8.0 mA 0.4 V
VIH Input HIGH voltage 2.2 VCC + 0.5 V
VIL Input LOW voltage [3] 0.5 0.8 V
IIX Input leakage current GND < VI < VCC 1+1A
IOZ Output leakage current GND < VI < VCC, output disabled –1 +1 A
ICC VCC operating supply current VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz 80 mA
83 MHz 72 mA
66 MHz 58 mA
40 MHz 37 mA
ISB1 Automatic CE Power-down
current— TTL Inputs
Max VCC, CE > VIH,
VIN >VIH or VIN < VIL, f = f max
10 mA
ISB2 Automatic CE Power-down
current— CMOS Inputs
Max VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V, f = 0
3mA
Note
3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
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Capacitance [4]
Parameter Description Test Conditions Max Unit
CIN: Addresses Input capacitance TA = 25 °C, f = 1 MHz, VCC = 5.0 V 7 pF
CIN: Controls 10 pF
COUT Output capacitance 10 pF
Thermal Resistance [4]
Parameter Description Test Conditions 300-Mil
Wide SOJ
400-Mil
Wide SOJ Unit
JA Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.16 58.76 C/W
JC Thermal resistance
(junction to case)
40.84 40.54 C/W
AC Test Loads and Waveforms [5]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: 3 ns Fall Time: 3 ns
30 pF*
OUTPUT
Z = 50
50
1.5V
(b)
(a)
5V
OUTPUT
5 pF
(c)
R1 480
R2
255
High-Z characteristics:
INCLUDING
JIG AND
SCOPE
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
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Switching Characteristics (Over the Operating Range) [6]
Parameter Description
7C107D-10
7C1007D-10 Unit
Min Max
Read Cycle
tpower [7] VCC(typical) to the first access 100 s
tRC Read cycle time 10 ns
tAA Address to data valid 10 ns
tOHA Data hold from address change 3 ns
tACE CE LOW to data valid 10 ns
tLZCE CE LOW to Low Z [8] 3ns
tHZCE CE HIGH to High Z [8, 9] 5ns
tPU [10] CE LOW to power-up 0 ns
tPD [10] CE HIGH to power-down 10 ns
Write Cycle [11]
tWC Write cycle time 10 ns
tSCE CE LOW to write end 7 ns
tAW Address set-up to write end 7 ns
tHA Address hold from write end 0 ns
tSA Address set-up to write start 0 ns
tPWE WE pulse width 7 ns
tSD Data set-up to write end 6 ns
tHD Data hold from write end 0 ns
tLZWE WE HIGH to Low Z [8] 3ns
tHZWE WE LOW to High Z [8, 9] 6ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
9. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 5. Transition is measured when the outputs enter a
high impedance state.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Max Unit
VDR VCC for data retention 2.0 V
ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
3mA
tCDR [12] Chip deselect to data retention time 0 ns
tR [13] Operation recovery time tRC ns
Data Retention Waveform
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled) [14, 15]
Figure 2. Read Cycle No. 2 [15, 16]
4.5V4.5V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
V
CC
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZCE
t
PD
HIGH
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
Notes
12. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c)
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
14. Device is continuously selected, CE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
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Figure 3. Write Cycle No. 1 (CE Controlled) [17]
Figure 4. Write Cycle No. 2 (WE Controlled) [17]
Truth Table
CE WE DOUT Mode Power
H X High Z Power-down Standby (ISB)
L H Data out Read Active (ICC)
L L High Z Write Active (ICC)
Switching Waveforms(continued)
DATA VALID
tSCE
tAW
tSA
tPWE
tHA
tHD
tSD
tWC
HIGH IMPEDANCE
ADDRESS
CE
WE
DATA OUT
DATA IN
tWC
DATA VALID
DATA UNDEFINED
HIGH IMPEDANCE
tSCE
tAW
tSA tPWE
tHA
tHD
tHZWE tLZWE
tSD
ADDRESS
CE
WE
DATA OUT
DATA IN
Note
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
10 CY7C107D-10VXI 51-85032 28-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1007D-10VXI 51-85031 28-pin (300-Mil) Molded SOJ (Pb-free)
Ordering Code Definitions
Please contact your local Cypress sales representative for availability of these parts.
Temperature Range:
I = Industrial
Package Type:
VX = 28-pin Molded SOJ (Pb-free)
Speed: 10 ns
D = C9, 90 nm Technology
xx7 = 07 or 007 = (400-Mil / 300-Mil) 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 - 10 VX7 xx7 D I
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Package Diagrams
Figure 5. 28-pin (400-Mil) Molded SOJ, 51-85032
51-85032 *E
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Figure 6. 28-pin (300-Mil) Molded SOJ, 51-85031
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams(continued)
51-85031 *D
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Acronyms
Document Conventions
Units of Measure
Acronym Description
BGA
ball grid array
CMOS complementary metal oxide semiconductor
FBGA very fine ball gird array
I/O input/output
JTAG joint test action group
SRAM static random access memory
TTL Transistor transistor logic
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliampere
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
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Document History Page
Document Title: CY7C107D/CY7C1007D, 1-Mbit (1M x 1) Static RAM
Document Number: 38-05469
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 233722 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165)
Pb-free offering in Ordering Information
*B 263769 See ECN RKF Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C 307601 See ECN RKF Reduced Speed bins to –10 and –12 ns
*D 560995 See ECN VKN Converted from Preliminary to Final
Removed Commercial Operating range
Removed 12 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3
*E 802877 See ECN VKN Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz,
45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
*F 2898399 03/24/2010 AJU Updated Package Diagrams
*G 3104943 12/08/2010 AJU Added Ordering Code Definitions.
*H 3218989 04/07/2011 PRAS Added TOC
Added Acrnyms and Units of Measure table.
Updated Package diagrams from *C to *D (51-85032)
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All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C107D
CY7C1007D
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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