74AC14, 74ACT14 Hex Inverter with Schmitt Trigger Input Features General Description ICC reduced by 50% The 74AC14 and 74ACT14 contain six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional inverters. Outputs source/sink 24mA 74ACT14 has TTL-compatible inputs The 74AC14 and 74ACT14 have hysteresis between the positive-going and negative-going input thresholds (typically 1.0V) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations. Ordering Information Order Number Package Number Package Description 74AC14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC14PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT14MTC 74ACT14PC MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input January 2008 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names Description In Inputs On Outputs (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 Function Table Input Output A O L H H L www.fairchildsemi.com 2 Symbol VCC IIK Parameter Rating Supply Voltage -0.5V to +7.0V DC Input Diode Current VI = -0.5V -20mA VI = VCC + 0.5 +20mA VI DC Input Voltage -0.5V to VCC + 0.5V IOK DC Output Diode Current VO = -0.5V -20mA VO = VCC + 0.5V +20mA VO DC Output Voltage -0.5V to VCC + 0.5V IO DC Output Source or Sink Current 50mA ICC or IGND DC VCC or Ground Current per Output Pin TSTG Storage Temperature TJ 50mA -65C to +150C Junction Temperature 140C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Rating Supply Voltage AC 2.0V to 6.0V ACT 4.5V to 5.5V VI Input Voltage VO Output Voltage TA Operating Temperature (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 0V to VCC 0V to VCC -40C to +85C www.fairchildsemi.com 3 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = +25C VCC Symbol VOH Parameter (V) Minimum HIGH Level 3.0 Output Voltage 4.5 Conditions IOUT = -50A 5.5 VOL IIN (3) Vt+ Vt- VH(MAX) Maximum LOW Level Output Voltage Maximum Input Leakage Current Maximum Positive Threshold Minimum Negative Threshold Maximum Hysteresis 2.99 2.9 2.9 4.49 4.4 4.4 5.4 5.4 IOH = 12mA 5.49 2.56 2.46 4.5 IOH = 24mA 3.86 3.76 5.5 IOH = 4.86 4.76 3.0 IOUT = 50A 24mA(1) 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 V V 3.0 IOL = 12mA 0.36 0.44 4.5 IOL = 24mA 0.36 0.44 5.5 IOL = 0.36 0.44 5.5 VI = VCC, GND 0.1 1.0 A 3.0 TA = Worst Case V 24mA(1) 2.2 2.2 4.5 3.2 3.2 5.5 3.9 3.9 0.5 0.5 4.5 0.9 0.9 5.5 1.1 1.1 1.2 1.2 1.4 1.4 1.6 1.6 0.3 0.3 4.5 0.4 0.4 5.5 0.5 0.5 3.0 3.0 TA = Worst Case TA = Worst Case 5.5 Minimum Hysteresis Guaranteed Limits Units 3.0 4.5 VH(MIN) Typ TA = -40C to +85C 3.0 TA = Worst Case V V V IOLD Minimum Dynamic 5.5 VOLD = 1.65V Max. 75 mA IOHD Output Current(2) 5.5 VOHD = 3.85V Min. -75 mA ICC(3) Maximum Quiescent 5.5 VIN = VCC or GND 20.0 A 2.0 Supply Current Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 4 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter VCC (V) Conditions Typ. TA = -40C to +85C Guaranteed Limits VOUT = 0.1V or VCC - 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC - 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = -50A 4.49 4.34 4.4 Minimum HIGH Level Input Voltage 5.5 Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage TA = +25C 4.5 4.5 5.5 4.5 5.49 VIN = VIL or VIH, 5.4 5.4 3.86 3.76 4.86 4.76 0.1 0.1 Units V V V IOH = -24mA 5.5 VIN = VIL or VIH, IOH = -24mA(4) VOL Maximum LOW Level Output Voltage 4.5 IOUT = 50A 0.001 5.5 4.5 0.001 VIN = VIL or VIH, V 0.1 0.1 0.36 0.44 0.36 0.44 0.1 1.0 A V IOL = 24mA 5.5 VIN = VIL or VIH, IOL = 24mA(4) IIN VH(MAX) Maximum Input Leakage Current Maximum Hysteresis 5.5 VI = VCC, GND 4.5 TA = Worst Case 5.5 VH(MIN) Minimum Hysteresis 4.5 TA = Worst Case 5.5 Vt+ Vt- Maximum Positive Threshold Minimum Negative Threshold 4.5 TA = Worst Case 5.5 4.5 TA = Worst Case 5.5 1.4 1.4 1.6 1.6 0.4 0.4 0.5 0.5 2.0 2.0 2.0 2.0 0.8 0.8 0.8 0.8 V V V ICCT Maximum ICC/Input 5.5 VI = VCC - 2.1V 1.5 mA IOLD Minimum Dynamic Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA 5.5 VOHD = 3.85V Min. -75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 20.0 A IOHD ICC 0.6 2.0 Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 5 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input DC Electrical Characteristics for ACT TA = +25C, CL = 50pF Symbol tPLH tPHL Parameter TA = -40C to +85C, CL = 50pF VCC (V)(6) Min. Typ. Max. Min. Max. Units 3.3 1.5 9.5 13.5 1.5 15.0 ns 5.0 1.5 7.0 10.0 1.5 11.0 Propagation Delay Propagation Delay 3.3 1.5 7.5 11.5 1.5 13.0 5.0 1.5 6.0 8.5 1.5 9.5 ns Note: 6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V. AC Electrical Characteristics for ACT TA = +25C, CL = 50pF Symbol Parameter TA = -40C to +85C, CL = 50pF VCC (V)(7) Min. Typ. Max. Min. Max. Units tPLH Propagation Delay 5.0 3.0 8.0 10.0 3.0 11.0 ns tPHL Propagation Delay 5.0 3.0 8.0 10.0 3.0 11.0 ns Note: 7. Voltage Range 5.0 is 5.0V 0.5V. Capacitance Symbol Parameter Conditions CIN Input Capacitance VCC = OPEN CPD Power Dissipation Capacitance VCC = 5.0V AC ACT (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 Typ Units 4.5 pF 25.0 pF 80 www.fairchildsemi.com 6 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input AC Electrical Characteristics for AC 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45 0.25 R0.10 R0.10 8 0 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 7 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input Physical Dimensions 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 8 0.65 0.43 TYP 1.65 6.10 0.45 12.00 TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 9 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 10 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input Physical Dimensions (Continued) ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM PDP-SPMTM SyncFETTM (R) Power220(R) (R) Power247 The Power Franchise(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) TinyBoostTM Programmable Active DroopTM TinyBuckTM (R) QFET TinyLogic(R) QSTM TINYOPTOTM QT OptoelectronicsTM TinyPowerTM (R) Quiet SeriesTM TinyPWMTM RapidConfigureTM TinyWireTM Fairchild(R) SMART STARTTM Fairchild Semiconductor(R) SerDesTM (R) SPM FACT Quiet SeriesTM UHC(R) STEALTHTM FACT(R) Ultra FRFETTM SuperFETTM FAST(R) UniFETTM SuperSOTTM-3 FastvCoreTM VCXTM (R) (R)* SuperSOTTM-6 FlashWriter SuperSOTTM-8 * EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 (c)1988 Fairchild Semiconductor Corporation 74AC14, 74ACT14 Rev. 1.7.1 www.fairchildsemi.com 11 74AC14, 74ACT14 -- Hex Inverter with Schmitt Trigger Input TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.