V+
1
2
3
45
6
7
8
EF
CL
VIN
V-
VOUT
GND
NC
G = 1
G = 1
12 3 4 5 6 7
VIN
GND
VOUT
V+
V-
EF
CL
LMH6321
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
LMH6321 300 mA High Speed Buffer with Adjustable Current Limit
Check for Samples: LMH6321
1FEATURES DESCRIPTION
The LMH6321 is a high speed unity gain buffer that
2• High Slew Rate 1800 V/μsslews at 1800 V/µs and has a small signal bandwidth
• Wide Bandwidth 110 MHz of 110 MHz while driving a 50Ωload. It can drive
• Continuous Output Current ±300 mA ±300 mA continuously and will not oscillate while
driving large capacitive loads.
• Output Current Limit Tolerance ±5 mA ±5%
• Wide Supply Voltage Range 5V to ±15V The LMH6321 features an adjustable current limit.
The current limit is continuously adjustable from 10
• Wide Temperature Range −40°C to +125°C mA to 300 ma with a ±5 mA ±5% accuracy. The
• Adjustable Current Limit current limit is set by adjusting an external reference
• High Capacitive Load Drive current with a resistor. The current can be easily and
instantly adjusted, as needed by connecting the
• Thermal Shutdown Error Flag resistor to a DAC to form the reference current. The
sourcing and sinking currents share the same current
APPLICATIONS limit.
• Line Driver The LMH6321 is available in a space saving 8-pin SO
• Pin Driver PowerPAD or a 7-pin DDPAK power package. The
• Sonar Driver SO PowerPAD package features an exposed pad on
the bottom of the package to increase its heat sinking
• Motor Control capability. The LMH6321 can be used within the
feedback loop of an operational amplifier to boost the
current output or as a stand alone buffer.
CONNECTION DIAGRAM
A. V−pin is connected to tab on back of each package.
Figure 1. 8-Pin SO PowerPAD Figure 2. 7-Pin DDPAK(A)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6321
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
ESD Tolerance (3) Human Body Model 2.5 kV
Machine Model 250V
Supply Voltage 36V (±18V)
Input to Output Voltage (4) ±5V
Input Voltage ±VSUPPLY
Output Short-Circuit to GND (5) Continuous
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJMAX) +150°C
Lead Temperature (Soldering, 10 seconds) 260°C
Power Dissipation (6)
CLPin to GND Voltage ±1.2V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see the
Electrical Characteristics Table.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model is 1.5 kΩin series with 100 pF. Machine Model is 0Ωin series with 200 pF.
(4) If the input-output voltage differential exceeds ±5V, internal clamping diodes will turn on. The current through these diodes should be
limited to 5 mA max. Thus for an input voltage of ±15V and the output shorted to ground, a minimum of 2 kΩshould be placed in series
with the input.
(5) The maximum continuous current must be limited to 300mA. See APPLICATION HINTS for more details.
(6) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= TJ(MAX)–TA)/θJA. See THERMAL MANAGEMENT of APPLICATION HINTS.
OPERATING RATINGS
Operating Temperature Range −40°C to +125°C
Operating Supply Range 5V to ±16V
Thermal Resistance (θJA)
SO PowerPAD Package (1) 180°C/W
Thermal Resistance (θJC) DDPAK Package 4°C/W
Thermal Resistance (θJA) 80°C/W
(1) Soldered to PC board with copper foot print equal to DAP size. Natural convection (no air flow). Board material is FR-4.
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
±15V ELECTRICAL CHARACTERISTICS
The following specifications apply for Supply Voltage = ±15V, VCM = 0, RL≥100 kΩand RS= 50Ω, CLopen, unless otherwise
noted. Boldface limits apply for TA= TJ= TMIN to TMAX; all other limits TA= TJ= 25°C.
Symbol Parameter Conditions Min Typ Max Units
AVVoltage Gain RL= 1 kΩ, VIN = ±10V 0.99 0.995 V/V
0.98
RL= 50Ω, VIN = ±10V 0.86 0.92 V/V
0.84
VOS Input Offset Voltage RL= 1 kΩ, RS= 0V ±4 ±35 mV
±52
IBInput Bias Current VIN = 0V, RL= 1 kΩ, RS= 0V ±2 ±15 μA
±17
R.IN Input Resistance R.L= 50Ω250 kΩ
CIN Input Capacitance 3.5 pF
ROOutput Resistance IO= ±10 mA 5 Ω
ISPower Supply Current RL=∞, VIN = 0 11 14.5
16.5 mA
750 µA into 14.9 18.5
CLPin 20.5
VO1 Positive Output Swing IO= 300 mA, RS= 0V, VIN = ±VS11.2 11.9
10.8 V
Negative Output Swing IO= 300 mA, RS= 0V, VIN = ±VS−11.3 −10.3
−9.8
VO2 Positive Output Swing RL= 1 kΩ, RS= 0V, VIN = ±VS13.1 13.4
12.9 V
Negative Output Swing RL= 1 kΩ, RS= 0V, VIN = ±VS−13.4 −12.9
−12.6
VO3 Positive Output Swing RL= 50Ω, RS= 0V, VIN = ±VS11.6 12.2
11.2 V
Negative Output Swing RL= 50Ω, RS= 0V, VIN = ±VS−11.9 −10.9
−10.6
VEF Error Flag Output Voltage RL=∞, VIN = 0, Normal 5.00
EF pulled up with 5 kΩDuring 0.25 V
to +5V Thermal
Shutdown
TSH Thermal Shutdown Temperature Measure Quantity is Die (Junction) 168
Temperature °C
Hysteresis 10
ISH Supply Current at Thermal EF pulled up with 5 kΩto +5V 3 mA
Shutdown
PSSR Power Supply Rejection Ratio RL= 1 kΩ, VIN = 0V, Positive 58 66
VS= ±5V to ±15V 54 dB
Negative 58 64
54
SR Slew Rate VIN = ±11V, RL= 1 kΩ2900 V/μs
VIN = ±11V, RL= 50Ω1800
BW −3 dB Bandwidth VIN = ±20 mVPP, RL= 50Ω110 MHz
LSBW Large Signal Bandwidth VIN = 2 VPP, RL= 50Ω48 MHz
HD2 2nd Harmonic Distortion VO= 2 VPP, f = 100 kHz RL= 50Ω −59
RL= 100Ω −70 dBc
VO= 2 VPP, f = 1 MHz RL= 50Ω −57
RL= 100Ω −68
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±15V ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for Supply Voltage = ±15V, VCM = 0, RL≥100 kΩand RS= 50Ω, CLopen, unless otherwise
noted. Boldface limits apply for TA= TJ= TMIN to TMAX; all other limits TA= TJ= 25°C.
Symbol Parameter Conditions Min Typ Max Units
HD3 3rd Harmonic Distortion VO= 2 VPP, f = 100 kHz RL= 50Ω −59
RL= 100Ω −70 dBc
VO= 2 VPP, f = 1 MHz RL= 50Ω −62
RL= 100Ω −73
enInput Voltage Noise f ≥10 kHz 2.8 nV/√Hz
inInput Current Noise f ≥10 kHz 2.4 pA/√Hz
ISC1 Output Short Circuit Current VO= 0V, Sourcing 4.5 10 15.5
Source (1) Program Current VIN = +3V 4.5 15.5 mA
into CL= 25 µA Sinking 4.5 10 15.5
VIN =−3V 4.5 15.5
VO= 0V Sourcing 280 295 308
Program Current VIN = +3V 273 325 mA
into CL= 750 µA Sinking 280 295 310
VIN =−3V 275 325
ISC2 Output Short Circuit Current RS= 0V, VIN = +3V(1)(2) 320 570 750
Source 300 920 mA
Output Short Circuit Current Sink RS= 0V, VIN =−3V(1)(2) 300 515 750
305 910
V/I Section
CLVOS Current Limit Input Offset Voltage RL= 1 kΩ, GND = 0V ±0.5 ±4.0 mV
±8.0
CLIBCurrent Limit Input Bias Current RL= 1 kΩ −0.5 −0.2 μA
−0.8
CL Current Limit Common Mode RL= 1 kΩ, GND = −13 to +14V 60 69 dB
CMRR Rejection Ratio 56
(1) VIN = + or −4V at TJ=−40°C.
(2) For the condition where the CLpin is left open the output current should not be continuous, but instead, should be limited to low duty
cycle pulse mode such that the RMS output current is less than or equal to 300 mA.
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
±5V ELECTRICAL CHARACTERISTICS
The following specifications apply for Supply Voltage = ±5V, VCM = 0, RL≥100 kΩand RS= 50Ω, CLOpen, unless otherwise
noted. Boldface limits apply for TA= TJ= TMIN to TMAX; all other limits TA= TJ= 25°C.
Symbol Parameter Conditions Min Typ Max Units
AVVoltage Gain RL= 1 kΩ, VIN = ±3V 0.99 0.994
0.98 V/V
RL= 50Ω, VIN = ±3V 0.86 0.92
0.84
VOS Offset Voltage RL= 1 kΩ, RS= 0V ±2.5 ±35 mV
±50
IBInput Bias Current VIN = 0V, RL= 1 kΩ, RS= 0V ±2 ±15 μA
±17
RIN Input Resistance RL= 50Ω250 kΩ
CIN Input Capacitance 3.5 pF
ROOutput Resistance IOUT = ±10 mA 5 Ω
ISPower Supply Current RL=∞, VIN = 0V 10 13.5 mA
14.7
750 μA into CL Pin 14 17.5
19.5
VO1 Positive Output Swing IO= 300 mA, RS= 0V, VIN = ±VS1.3 1.9
0.9 V
Negative Output Swing IO= 300 mA, RS= 0V, VIN = ±VS−1.3 −0.5
−0.1
VO2 Positive Output Swing RL= 1 kΩ, RS= 0V, VIN = ±VS3.2 3.5 V
2.9
Negative Output Swing RL= 1 kΩ, RS= 0V, VIN = ±VS−3.5 −3.1 V
−2.9
VO3 Positive Output Swing RL= 50Ω, RS= 0V, VIN = ±VS2.8 3.1 V
2.5
Negative Output Swing RL= 50Ω, RS= 0V, VIN = ±VS−3.0 −2.6 V
−2.4
PSSR Power Supply Rejection Ratio RL= 1 kΩ, VIN = 0, Positive 58 66
VS= ±5V to ±15V 54 dB
Negative 58 64
54
ISC1 Output Short Circuit Current VO= 0V, Program Current Sourcing 4.5 9 14.0
into CL= 25 μA VIN = +3V 4.5 15.5
Sinking 4.5 9 14.0
VIN =−3V 4.5 15.5 mA
VO= 0V, Program Current Sourcing 275 290 305
into CL= 750 μA VIN = +3V 270 320
Sinking 275 290 310
VIN =−3V 270 320
ISC2 Output Short Circuit Current RS= 0V, VIN = +3V(1)(2) 300 470
Source mA
Output Short Circuit Current Sink RS= 0V, VIN =−3V (1)(2) 300 400
SR Slew Rate VIN = ±2 VPP, RL= 1 kΩ450 V/μs
VIN = ±2 VPP, RL= 50Ω210
BW −3 dB Bandwidth VIN = ±20 mVPP, RL= 50Ω90 MHz
LSBW Large Signal Bandwidth VIN = 2 VPP, RL= 50Ω39 MHz
TSD Thermal Shutdown Temperature 170 °C
Hysteresis 10
V/I Section
(1) For the condition where the CLpin is left open the output current should not be continuous, but instead, should be limited to low duty
cycle pulse mode such that the RMS output current is less than or equal to 300 mA.
(2) VIN = + or −4V at TJ=−40°C.
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±5V ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for Supply Voltage = ±5V, VCM = 0, RL≥100 kΩand RS= 50Ω, CLOpen, unless otherwise
noted. Boldface limits apply for TA= TJ= TMIN to TMAX; all other limits TA= TJ= 25°C.
Symbol Parameter Conditions Min Typ Max Units
CLVOS Current Limit Input Offset RL= 1 kΩ, GND = 0V 2.7 +5 mV
Voltage ±5.0
CLIBCurrent Limit Input Bias Current RL= 1 kΩ, CL= 0V −0.5 −0.2 μA
−0.6
CL Current Limit Common Mode RL= 1 kΩ, GND = −3V to +4V 60 65 dB
CMRR Rejection Ratio 56
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357 9 11 13 15
SUPPLY VOLTAGE (±V)
6
7
8
9
10
INPUT OFFSET VOLTAGE (mV)
125°C
85°C 25°C
-40°C
TIME (10 ns/DIV)
(100 mV/DIV)
INPUT SIGNAL OUTPUT SIGNAL
VIN = 200 mVPP
RL = 1 k:
VS = ±15V
0 4 8 12 16 20 24
200
3000
SLEW RATE (V/Ps)
INPUT AMPLITUDE (VPP)
600
1000
1400
1800
2200
2600
VS = ±15V
RL = 1 k:
RL = 50:
TIME (10 ns/DIV)
(100 mV/DIV)
INPUT SIGNAL OUTPUT SIGNAL
VIN = 200 mVPP
RL = 1 k:
VS = ±5V
10 100 1k 10k
CL (pF)
0
10
20
30
40
50
60
OVERSHOOT (%)
UNDERSHOOT
OVERSHOOT
VIN = 100 mVPP
RL = OPEN
VS = ±15V
0 4 8 12 16 20
200
600
1000
1400
1800
2200
2600
3000
SLEW RATE (V/Ps)
SUPPLY VOLTAGE (±V)
RL = 50:
RL = 1 k:
LMH6321
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Overshoot
vs.
Capacitive Load Slew Rate
Figure 3. Figure 4.
Slew Rate Small Signal Step Response
Figure 5. Figure 6.
Input Offset Voltage of Amplifier
vs.
Small Signal Step Response Supply Voltage
Figure 7. Figure 8.
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TIME (5 ns/DIV)
(5V/DIV)
VIN = 20 VPP
RL = 1 k:
VS = ±15V
INPUT SIGNAL OUTPUT SIGNAL
TIME (5 ns/DIV)
(5V/DIV)
VIN = 20 VPP
RL = 50:
VS = ±15V
INPUT SIGNAL OUTPUT SIGNAL
TIME (5 ns/DIV)
(5V/DIV)
VIN = 20 VPP
RL = 1 k:
VS = ±15V
INPUT SIGNAL OUTPUT SIGNAL
TIME (5 ns/DIV)
(5V/DIV)
VIN = 20 VPP
RL = 50:
VS = ±15V
INPUT SIGNAL OUTPUT SIGNAL
LMH6321
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Small Signal Step Response Small Signal Step Response
Figure 9. Figure 10.
Large Signal Step Response—Leading Edge Large Signal Step Response—Leading Edge
Figure 11. Figure 12.
Large Signal Step Response — Trailing Edge Large Signal Step Response — Trailing Edge
Figure 13. Figure 14.
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05 10 15 20 25 30
OUTPUT AMPLITUDE (VPP)
-80
-70
-60
-50
-40
-30
-20
HD2 and HD3 (dBc)
VS = ±15V
f = 1 MHz
HD3
HD2
05 10 15 20 25 30
OUTPUT AMPLITUDE (VPP)
-80
-70
-60
-50
-40
-30
-20
HD2 and HD3 (dBc)
HD2
HD3
VS = ±15V
f = 1 MHz
LMH6321
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Large Signal Step Response Large Signal Step Response
Figure 15. Figure 16.
Large Signal Step Response Large Signal Step Response
Figure 17. Figure 18.
Harmonic Distortion with 50ΩLoad Harmonic Distortion with 100ΩLoad
Figure 19. Figure 20.
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100k 1M 10M 100M 1G
FREQUENCY (Hz)
-20
-15
-10
-5
0
5
GAIN (dB)
VS = ±15V
RL = 1 k:
100k 1M 10M 100M 1G
FREQUENCY (Hz)
-20
-15
-10
-5
0
5
GAIN (dB)
VS = ±5V
RL = 1 k:
100k 1M 10M 100M 1G
FREQUENCY (Hz)
-25
-20
-15
-10
-5
0
5
GAIN (dB)
VS = ±5V
RL = 50:
100k 1M 10M 100M 1G
FREQUENCY (Hz)
-25
-20
-15
-10
-5
0
5
GAIN (dB)
VS = ±15V
RL = 50:
1.0 10 100 1k 100k
FREQUENCY (Hz)
0.1
1.0
1000
10000
NOISE
10k
10
100 VOLTAGE nV/ Hz)
CURRENT pA/ Hz)
0 5 10 15 20 25
-70
-65
-60
-55
-50
-45
-40
-35
-30
HD2 & HD3 (dBc)
OUTPUT VOLTAGE (V)
VS = ±15V
RL = 50:
f = 100 kHz
HD2
HD3
LMH6321
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Noise
vs.
Harmonic Distortion with 50ΩLoad Frequency
Figure 21. Figure 22.
Gain Gain
vs. vs.
Frequency Frequency
Figure 23. Figure 24.
Gain Gain
vs. vs.
Frequency Frequency
Figure 25. Figure 26.
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57 9 11 13 15 17 19
SINKING CURRENT (mA)
4.2
4.4
4.6
4.8
5
5.2
OUTPUT IMPEDANCE (:)
-40°C
VS = ±15V
125°C
25°C
85°C
25 125 225 325 425 525 625 725 825
PROGRAM CURRENT (PA)
0
100
200
300
400
OUTPUT CURRENT (mA)
125°C
-40°C
25°C
85°C
VS = ±15V
57 9 11 13 15 17 19
SINKING CURRENT (mA)
4.6
4.8
5
5.2
5.4
5.6
OUTPUT IMPEDANCE (:)
-40°C
VS = ±5V
125°C
25°C 85°C
57 9 11 13 15 17 19
SOURCING CURRENT (mA)
4
4.2
4.4
4.6
4.8
5
OUTPUT IMPEDANCE (:)
-40°C
VS = ±15V
125°C
25°C
85°C
57 9 11 13 15 17 19
SOURCING CURRENT (mA)
4.2
4.4
4.6
4.8
5
5.2
OUTPUT IMPEDANCE (:)
-40°C
125°C
25°C 85°C
VS = ±5V
1 3 5 7 9 11 13 15 17 19
0
2
4
6
8
10
14
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (±V)
12 125°C
25°C
-40°C
85°C
LMH6321
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Supply Current Output Impedance
vs. vs.
Supply Voltage Sourcing Current
Figure 27. Figure 28.
Output Impedance Output Impedance
vs. vs.
Sinking Current Sourcing Current
Figure 29. Figure 30.
Output Impedance
vs. Output Short Circuit Current—Sourcing vs.
Sinking Current Program Current
Figure 31. Figure 32.
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-500 -400 -300 -200 -100 0
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
OUTPUT SWING (V)
SINKING CURRENT (mA)
125°C
85°C
25°C
-40°C
VS = ±5V
VIN = V-
CL = OPEN
0 100 200 300 400 500
9
10
11
12
13
14
OUTPUT SWING (V)
SOURCING CURRENT (mA)
125°C85°C
25°C
-40°C
VS = ±15V
VIN = V+
CL = OPEN
0 100 200 300 400 500
0
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT SWING (V)
SOURCING CURRENT (mA)
125°C
85°C
25°C
-40°C
VS = ±5V
VIN = V+
CL = OPEN
25 125 225 325 425 525 625 725 825
PROGRAM CURRENT (PA)
0
100
200
300
400
OUTPUT CURRENT (mA)
125°C
-40°C
25°C
85°C
VS = ±5V
25 125 225 325 425 525 625 725 825
PROGRAM CURRENT (PA)
0
100
200
300
400
OUTPUT CURRENT (mA)
125°C
-40°C
25°C
85°C
VS = ±15V
25 125 225 325 425 525 625 725 825
PROGRAM CURRENT (PA)
0
100
200
300
400
OUTPUT CURRENT (mA)
125°C
-40°C
25°C
85°C
VS = ±5V
LMH6321
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Short Circuit Current—Sinking vs. Output Short Circuit Current—Sourcing vs.
Program Current Program Current
Figure 33. Figure 34.
Positive Output Swing
Output Short Circuit Current—Sinking vs. vs.
Program Current Sourcing Current
Figure 35. Figure 36.
Negative Output Swing Positive Output Swing
vs. vs.
Sinking Current Sourcing Current
Figure 37. Figure 38.
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5 7 9 11 13 15
3
5
7
9
11
13
15
OUTPUT SWING (V)
SUPPLY VOLTAGE (±V)
RL = 1 k:
125°C
85°C
25°C
-40°C
5 7 9 11 13 15
-15
-13
-11
-9
-7
-5
-3
OUTPUT SWING (V)
SUPPLY VOLTAGE (±V)
RL = 50:
125°C
85°C
-40°C
25°C
24 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±V)
0
200
400
600
800
OUTPUT CURRENT (mA)
-40°C
-40°C
25°C
85°C 125°C
VIN = -3V
CL = OPEN
5 7 9 11 13 15
3
5
7
9
11
13
15
OUTPUT SWING (V)
SUPPLY VOLTAGE (±V)
RL = 50:
125°C
85°C
25°C
-40°C
-500 -400 -300 -200 -100 0
-14
-13
-12
-11
-10
-9
OUTPUT SWING (V)
SINKING CURRENT (mA)
125°C 85°C
25°C -40°C
VS = ±15V
VIN = V-
CL = OPEN
24 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±V)
0
200
400
600
800
1000
OUTPUT CURRENT (mA)
-40°C
25°C
85°C 125°C
VIN = +3
CL = OPEN
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Negative Output Swing
vs. Output Short Circuit Current—Sourcing vs.
Sinking Current Supply Voltage
Figure 39. Figure 40.
Positive Output Swing
Output Short Circuit Current—Sinking vs. vs.
Supply Voltage Supply Voltage
Figure 41. Figure 42.
Positive Output Swing Negative Output Swing
vs. vs.
Supply Voltage Supply Voltage
Figure 43. Figure 44.
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-40°C
INPUT OFFSET VOLTAGE (mV)
-3 -2 -1 0 1 3
COMMON MODE VOLTAGE (V)
-2
-1
0
1
2
3
4
2
5VS = ±5V
25°C
85°C
-40°C
INPUT OFFSET VOLTAGE (mV)
-12 -8 -4 0 4 12
COMMON MODE VOLTAGE (V)
-10
-8
-6
-4
-2
0
2
8
4VS = ±15V
-40°C
85°C
125°C
25°C
-12 -8 -4 0 4 8 12
COMMON MODE VOLTAGE (V)
-25
-15
-5
5
15
25
INPUT OFFSET VOLTGE (mV)
VS = ±15V
125°C
85°C
-40°C 25°C -40°C
125°C
-40°C
85°C
125°C
35 7 9 11 13 15
SUPPLY VOLTAGE (±V)
-10
-8
-6
-4
-2
0
INPUT BIAS CURRENT (PA)
25°C
-3 -2 -1 1 2
COMMON MODE VOLTAGE (V)
-5
0
5
10
15
INPUT OFFSET VOLTAGE (mV)
03
-40°C
25°C
85°C 125°C
VS = ±5V
5 7 9 11 13 15
-15
-13
-11
-9
-7
-5
-3
OUTPUT SWING (V)
SUPPLY VOLTAGE (±V)
RL = 1 k:
85°C 25°C
-40°C
125°C
LMH6321
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Negative Output Swing Input Offset Voltage of Amplifier
vs. vs.
Supply Voltage Common Mode Voltage
Figure 45. Figure 46.
Input Bias Current of Amplifier
Input Offset Voltage of Amplifier vs. vs.
Common Mode Voltage Supply Voltage
Figure 47. Figure 48.
Input Offset Voltage of V/I Section vs. Input Offset Voltage of V/I Section vs.
Common Mode Voltage Common Mode Voltage
Figure 49. Figure 50.
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Product Folder Links: LMH6321
VOUT
VIN
V+
V
-
Q6
R2
Q2
Q1
R1
Q5
Q7
R3
2:
R4
2:
Q4
Q8
D2 D4 D6 D8D10 D12
D1 D3 D5 D7 D9 D11
Q3
LMH6321
www.ti.com
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
APPLICATION HINTS
BUFFERS
Buffers are often called voltage followers because they have largely unity voltage gain, thus the name has
generally come to mean a device that supplies current gain but no voltage gain. Buffers serve in applications
requiring isolation of source and load, i.e., high input impedance, low output impedance (high output current
drive). In addition, they offer gain flatness and wide bandwidth.
Most operational amplifiers, that meet the other given requirements in a particular application, can be configured
as buffers, though they are generally more complex and are, by and large, not optimized for unity gain operation.
The commercial buffer is a cost effective substitute for an op amp. Buffers serve several useful functions, either
in tandem with op amps or in standalone applications. As mentioned, their primary function is to isolate a high
impedance source from a low impedance load, since a high Z source can’t supply the needed current to the load.
For example, in the case where the signal source to an analog to digital converter is a sensor, it is recommended
that the sensor be isolated from the A/D converter. The use of a buffer ensures a low output impedance and
delivery of a stable output to the converter. In A/D converter applications buffers need to drive varying and
complex reactive loads.
Buffers come in two flavors: Open Loop and Closed Loop. While sacrificing the precision of some DC
characteristics, and generally displaying poorer gain linearity, open loop buffers offer lower cost and increased
bandwidth, along with less phase shift and propagation delay than do closed loop buffers. The LMH6321 is of the
open loop variety.
Figure 51 shows a simplified diagram of the LMH6321 topology, revealing the open loop complementary follower
design approach. Figure 52 shows the LMH6321 in a typical application, in this case, a 50Ωcoaxial cable driver.
Figure 51. Simplified Schematic
SUPPLY BYPASSING
The method of supply bypassing is not critical for frequency stability of the buffer, and, for light loads, capacitor
values in the neighborhood of 1 nF to 10 nF are adequate. However, under fast slewing and large loads, large
transient currents are demanded of the power supplies, and when combined with any significant wiring
inductance, these currents can produce voltage transients. For example, the LMH6321 can slew typically at 1000
V/μs. Therefore, under a 50Ωload condition the load can demand current at a rate, di/dt, of 20 A/μs. This current
flowing in an inductance of 50 nH (approximately 1.5” of 22 gage wire) will produce a 1V transient. Thus, it is
recommended that solid tantalum capacitors of 5 μF to 10 μF, in parallel with a ceramic 0.1 μF capacitor be
added as close as possible to the device supply pins.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
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|
R1
10 k:
INPUT
C1
1 nF
CIN
C3
0.1 PF
R4
50:
50: COAXIAL
CABLE
R6
50:
OUTPUT
R3
10 k: 1%
VCL
TP1
EF
V+
C2
0.1 PF
R2
10 k:1%
V
-
GND
CL
LMH6321
EF
V+
V
-
VOUT
VIN
LMH6321
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
www.ti.com
Figure 52. 50ΩCoaxial Cable Driver with Dual Supplies
For values of capacitors in the 10 μF to 100 μF range, ceramics are usually larger and more costly than
tantalums but give superior AC performance for bypassing high frequency noise because of their very low ESR
(typically less than 10 MΩ) and low ESL.
LOAD IMPEDANCE
The LMH6321 is stable under any capacitive load when driven by a 50Ωsource. As shown by Figure 3 in
TYPICAL PERFORMANCE CHARACTERISTICS, worst case overshoot is for a purely capacitive load of about 1
nF. Shunting the load capacitance with a resistor will reduce the overshoot.
SOURCE INDUCTANCE
Like any high frequency buffer, the LMH6321 can oscillate with high values of source inductance. The worst case
condition occurs with no input resistor, and a purely capacitive load of 50 pF, where up to 100 nH of source
inductance can be tolerated. With a 50Ωload, this goes up to 200 nH. However, a 100Ωresistor placed in series
with the buffer input will ensure stability with a source inductances up to 400 nH with any load.
OVERVOLTAGE PROTECTION
(Refer to the simplified schematic in Figure 51).
If the input-to-output differential voltage were allowed to exceed the Absolute Maximum Rating of 5V, an internal
diode clamp would turn on and divert the current around the compound emitter followers of Q1/Q3 (D1 – D11 for
positive input), or around Q2/Q4 (D2 – D12 for negative inputs). Without this clamp, the input transistors Q1 – Q4
would zener, thereby damaging the buffer.
To limit the current through this clamp, a series resistor should be added to the buffer input (see R1in Figure 52).
Although the allowed current in the clamp can be as high as 5 mA, which would suggest a 2 kΩresistor from a
15V source, it is recommended that the current be limited to about 1 mA, hence the 10 kΩshown.
The reason for this larger resistor is explained in the following: One way that the input/output voltage differential
can exceed the Abs Max value is under a short circuit condition to ground while driving the input with up to ±15V.
However, in the LMH6321 the maximum output current is set by the programmable Current Limit pin (CL). The
value set by this pin is specified to be accurate to 5 mA ±5%. If the input/output differential exceeds 5V while the
output is trying to supply the maximum set current to a shorted condition or to a very low resistance load, a
portion of that current will flow through the clamp diodes, thus creating an error in the total load current. If the
input resistor is too low, the error current can exceed the 5 mA ±5% budget.
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BANDWIDTH AND STABILITY
As can be seen in the schematic of Figure 52, a small capacitor is inserted in parallel with the series input
resistors. The reason for this is to compensate for the natural band-limiting effect of the 1st order filter formed by
this resistor and the input capacitance of the buffer. With a typical CIN of 3.5 pF (Figure 52), a pole is created at
fp2 = 1/(2πR1CIN) = 4.5 MHz (1)
This will band-limit the buffer and produce further phase lag. If used in an op amp-loop application with an
amplifier that has the same order of magnitude of unity gain crossing as fp2, this additional phase lag will
produce oscillation.
The solution is to add a small feed-forward capacitor (phase lead) around the input resistor, as shown in
Figure 52. The value of this capacitor is not critical but should be such that the time constant formed by it and the
input resistor that it is in parallel with (RIN) be at least five times the time constant of RINCIN. Therefore,
C1= (5RIN/R1)(CIN) (2)
from Electrical Characteristics, RIN is 250 kΩ.
In the case of the example in Figure 52, RINCIN produces a time-constant of 870 ns, so C1should be chosen to
be a minimum of 4.4 μs, or 438 pF. The value of C1(1000 pF) shown in Figure 52 gives 10 μs.
OUTPUT CURRENT AND SHORT CIRCUIT PROTECTION
The LMH6321 is designed to deliver a maximum continuous output current of 300 mA. However, the maximum
available current, set by internal circuitry, is about 700 mA at room temperature. The output current is
programmable up to 300 mA by a single external resistor and voltage source.
The LMH6321 is not designed to safely output 700 mA continuously and should not be used this way. However,
the available maximum continuous current will likely be limited by the particular application and by the package
type chosen, which together set the thermal conditions for the buffer (see THERMAL MANAGEMENT) and could
require less than 300 mA.
The programming of both the sourcing and sinking currents into the load is accomplished with a single resistor.
Figure 53 shows a simplified diagram of the V to I converter and ISC protection circuitry that, together, perform
this task.
Referring to Figure 53, the two simplified functional blocks, labeled V/I Converter and Short Circuit Protection,
comprise the circuitry of the Current Limit Control.
The V/I converter consists of error amplifier A1 driving two PNP transistors in a Darlington configuration. The two
input connections to this amplifier are VCL (inverting input) and GND (non-inverting input). If GND is connected to
zero volts, then the high open loop gain of A1, as well as the feedback through the Darlington, will force CL, and
thus one end REXT to be at zero volts also. Therefore, a voltage applied to the other end of REXT will force a
current
IEXT = VPROG/REXT (3)
into this pin. Via this pin, IOUT is programmable from 10 mA to 300 mA by setting IEXT from 25 μA to 750 µA by
means of a fixed REXT of 10 kΩand making VCL variable from 0.25V to 7.5V. Thus, an input voltage VCL is
converted to a current IEXT. This current is the output from the V/I converter. It is gained up by a factor of two and
sent to the Short Circuit Protection block as IPROG. IPROG sets a voltage drop across RSC which is applied to the
non-inverting input of error amp A2. The other input is across RSENSE. The current through RSENSE, and hence the
voltage drop across it, is proportional to the load current, via the current sense transistor QSENSE. The output of
A2 controls the drive (IDRIVE) to the base of the NPN output transistor, Q3 which is, proportional to the amount
and polarity of the voltage differential (VDIFF ) between AMP2 inputs, that is, how much the voltage across RSENSE
is greater than or less than the voltage across RSC. This loop gains IEXT up by another 200, thus
ISC = 2 x 200 (IEXT) = 400 IEXT (4)
Therefore, combining Equation 3 and Equation 4, and solving for REXT , we get
REXT = 400 VPROG/ISC (5)
If the VCL pin is left open, the output short circuit current will default to about 700 mA. At elevated temperatures
this current will decrease.
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+
-
V/I CONVERTER
|
+
-
SHORT CIRCUIT
PROTECTION
IEXT 25 PA to 750 PA
GND
VCL
A1
NPN OUTPUT
XTR
IDRIVE
V+
TO INPUT
STAGE R3
2:
V+
AMP2
QSENSE
RSENSE
200:
TO LOWER OUTPUT STAGE
OUTPUT
±VDIFF RSC
400:
IOUT SENSE
XTR
ISENSE
ILOAD
IPROG
50 PA to 1.5 mA
REXTERNAL
VPROG
CONNECT TO GROUND
(FOR DUAL SUPPLIES)
OR MID RAIL FOR
SINGLE SUPPLY
LMH6321
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
www.ti.com
Only the NPN output ISC protection is shown. Depending on the polarity of VDIFF, AMP2 will turn IDRIVE either on or
off.
Figure 53. Simplified Diagram of Current Limit Control
THERMAL MANAGEMENT
Heatsinking
For some applications, a heat sink may be required with the LMH6321. This depends on the maximum power
dissipation and maximum ambient temperature of the application. To accomplish heat sinking, the tabs on
DDPAK and SO PowerPAD package may be soldered to the copper plane of a PCB for heatsinking (note that
these tabs are electrically connected to the most negative point in the circuit, i. e.,V−).
Heat escapes from the device in all directions, mainly through the mechanisms of convection to the air above it
and conduction to the circuit board below it and then from the board to the air. Natural convection depends on
the amount of surface area that is in contact with the air. If a conductive plate serving as a heatsink is thick
enough to ensure perfect thermal conduction (heat spreading) into the far recesses of the plate, the temperature
rise would be simply inversely proportional to the total exposed area. PCB copper planes are, in that sense, an
aid to convection, the difference being that they are not thick enough to ensure perfect conduction. Therefore,
eventually we will reach a point of diminishing returns (as seen in Figure 55). Very large increases in the copper
area will produce smaller and smaller improvement in thermal resistance. This occurs, roughly, for a 1 inch
square of 1 oz copper board. Some improvement continues until about 3 square inches, especially for 2 oz
boards and better, but beyond that, external heatsinks are required. Ultimately, a reasonable practical value
attainable for the junction to ambient thermal resistance is about 30 °C/W under zero air flow.
A copper plane of appropriate size may be placed directly beneath the tab or on the other side of the board. If
the conductive plane is placed on the back side of the PCB, it is recommended that thermal vias be used per
JEDEC Standard JESD51-5.
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Determining Copper Area
One can determine the required copper area by following a few basic guidelines:
1. Determine the value of the circuit’s power dissipation, PD
2. Specify a maximum operating ambient temperature, TA(MAX). Note that when specifying this parameter, it
must be kept in mind that, because of internal temperature rise due to power dissipation, the die
temperature, TJ, will be higher than TAby an amount that is dependent on the thermal resistance from
junction to ambient, θJA. Therefore, TAmust be specified such that TJdoes not exceed the absolute
maximum die temperature of 150°C.
3. Specify a maximum allowable junction temperature, TJ(MAX), which is the temperature of the chip at maximum
operating current. Although no strict rules exist, typically one should design for a maximum continuous
junction temperature of 100°C to 130°C, but no higher than 150°C which is the absolute maximum rating for
the part.
4. Calculate the value of junction to ambient thermal resistance, θJA
5. Choose a copper area that will ensure the specified TJ(MAX) for the calculated θJA.θJA as a function of copper
area in square inches is shown in Figure 54.
The maximum value of thermal resistance, junction to ambient θJA, is defined as:
θJA = (TJ(MAX) - TA(MAX) )/ PD(MAX)
where
• TJ(MAX) = the maximum recommended junction temperature
• TA(MAX) = the maximum ambient temperature in the user’s environment
• PD(MAX) = the maximum recommended power dissipation (6)
NOTE
The allowable thermal resistance is determined by the maximum allowable heat rise ,
TRISE = TJ(MAX) - TA(MAX) = (θJA) (PD(MAX)). Thus, if ambient temperature extremes force
TRISE to exceed the design maximum, the part must be de-rated by either decreasing PD
to a safe level, reducing θJA, further, or, if available, using a larger copper area.
Procedure
1. First determine the maximum power dissipated by the buffer, PD(MAX). For the simple case of the buffer
driving a resistive load, and assuming equal supplies, PD(MAX) is given by:
PD(MAX) = IS(2V+) + V+2/4RL
where
• IS= quiescent supply current (7)
2. Determine the maximum allowable die temperature rise,
TR(MAX) = TJ(MAX)-TA(MAX) = PD(MAX)θJA (8)
3. Using the calculated value of TR(MAX) and PD(MAX) the required value for junction to ambient thermal
resistance can be found:
θJA = TR(MAX)/PD(MAX) (9)
4. Finally, using this value for θJA choose the minimum value of copper area from Figure 54.
Example
Assume the following conditions:
V+= V−= 15V, RL= 50Ω, IS= 15 mA TJ(MAX) = 125°C, TA(MAX) = 85°C.
1. From Equation 7
– PD(MAX) = IS(2V+)+V+2/4RL= (15 mA)(30V) + 15V2/200Ω= 1.58W
2. From Equation 8
– TR(MAX) = 125°C - 85°C = 40°C
3. From Equation 9
–θJA = 40°C/1.58W = 25.3°C/W
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-40 -25 25 75 125
MAX POWER DISSIPATION (W)
AMBIENT TEMPERATURE (°C)
0
1
2
3
4
5
TO-263 PACKAGE
PCB MOUNT
1 SQ. IN. COPPER
01 2 3
COPPER FOIL AREA (SQ. IN.)
20
30
40
50
60
70
80
THERMAL RESISTANCE TJA (°C/W)
LMH6321
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
www.ti.com
Examining Figure 54, we see that we cannot attain this low of a thermal resistance for one layer of 1 oz copper.
It will be necessary to derate the part by decreasing either the ambient temperature or the power dissipation.
Other solutions are to use two layers of 1 oz foil, or use 2 oz copper (see Table 1), or to provide forced air flow.
One should allow about an extra 15% heat sinking capability for safety margin.
Figure 54. Thermal Resistance (typ) for 7-L DDPAK Package Mounted on 1 oz. (0.036 mm) PC Board Foil
Figure 55. Derating Curve for DDPAK package. No Air Flow
Table 1. θJA vs. Copper Area and PDfor DDPAK. 1.0 oz cu Board. No Air Flow. Ambient Temperature =
24°C
Copper Area θJA @ 1.0W θJA @ 2.0W
(°C/W) (°C/W)
1 Layer = 1”x2” cu Bottom 62.4 54.7
2 Layer = 1”x2” cu Top & Bottom 36.4 32.1
2 Layer = 2”x2” cu Top & Bottom 23.5 22.0
2 Layer = 2”x4” cu Top & Bottom 19.8 17.2
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
As seen in the previous example, buffer dissipation in DC circuit applications is easily computed. However, in AC
circuits, signal wave shapes and the nature of the load (reactive, non-reactive) determine dissipation. Peak
dissipation can be several times the average with reactive loads. It is particularly important to determine
dissipation when driving large load capacitance.
A selection of thermal data for the SO PowerPAD package is shown in Table 2. The table summarizes θJA for
both 0.5 watts and 0.75 watts. Note that the thermal resistance, for both the DDPAK and the SO PowerPAD
package is lower for the higher power dissipation levels. This phenomenon is a result of the principle of Newtons
Law of Cooling. Restated in term of heatsink cooling, this principle says that the rate of cooling and hence the
thermal conduction, is proportional to the temperature difference between the junction and the outside
environment (ambient). This difference increases with increasing power levels, thereby producing higher die
temperatures with more rapid cooling.
Table 2. θJA vs. Copper Area and PDfor SO PowerPAD. 1.0 oz cu Board. No Airflow. Ambient
Temperature = 22°C
Copper Area/Vias θJA @ 0.5W θJA @ 0.75W
(°C/W) (°C/W)
1 Layer = 0.05 sq. in. (Bottom) + 3 Via Pads 141.4 138.2
1 Layer = 0.1 sq. in. (Bottom) + 3 Via Pads 134.4 131.2
1 Layer = 0.25 sq. in. (Bottom) + 3 Via Pads 115.4 113.9
1 Layer = 0.5 sq. in. (Bottom) + 3 Via Pads 105.4 104.7
1 Layer = 1.0 sq. in. (Bottom) + 3 Via Pads 100.5 100.2
2 Layer = 0.5 sq. in. (Top)/ 0.5 sq. in. (Bottom) + 33 93.7 92.5
Via Pads
2 Layer = 1.0 sq. in. (Top)/ 1.0 sq. in. (Bottom) + 53 82.7 82.2
Via Pads
ERROR FLAG OPERATION
The LMH6321 provides an open collector output at the EF pin that produces a low voltage when the Thermal
Shutdown Protection is engaged, due to a fault condition. Under normal operation, the Error Flag pin is pulled up
to V+by an external resistor. When a fault occurs, the EF pin drops to a low voltage and then returns to V+when
the fault disappears. This voltage change can be used as a diagnostic signal to alert a microprocessor of a
system fault condition. If the function is not used, the EF pin can be either tied to ground or left open. If this
function is used, a 10 kΩ, or larger, pull-up resistor (R2in Figure 52) is recommended. The larger the resistor the
lower the voltage will be at this pin under thermal shutdown. Table 3 shows some typical values of VEF for 10 kΩ
and 100 kΩ.
Table 3. VEF vs. R2
R2( inFigure 52) @ V+= 5V @V+= 15V
10 kΩ0.24V 0.55V
100 KΩ0.036V 0.072V
SINGLE SUPPLY OPERATION
If dual supplies are used, then the GND pin can be connected to a hard ground (0V) (as shown in Figure 52).
However, if only a single supply is used, this pin must be set to a voltage of one VBE (∼0.7V) or greater, or more
commonly, mid rail, by a stiff, low impedance source. This precludes applying a resistive voltage divider to the
GND pin for this purpose. Figure 56 shows one way that this can be done.
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0 4 8 12 16 20 24
200
3000
SLEW RATE (V/Ps)
INPUT AMPLITUDE (VPP)
600
1000
1400
1800
2200
2600
VS = ±15V
RL = 1 k:
RL = 50:
LMH6321
GND
V+
V
-
V+
OP AMP R1
R2
-
+
LMH6321
SNOSAL8C –APRIL 2006–REVISED MARCH 2013
www.ti.com
Figure 56. Using an Op Amp to Bias the GND Pin to ½ V+for Single Supply Operation
In Figure 56, the op amp circuit pre-biases the GND pin of the buffer for single supply operation.
The GND pin can be driven by an op amp configured as a constant voltage source, with the output voltage set by
the resistor voltage divider, R1and R2. It is recommended that These resistors be chosen so as to set the GND
pin to V+/2, for maximum common mode range.
SLEW RATE
Slew rate is the rate of change of output voltage for large-signal step input changes. For resistive load, slew rate
is limited by internal circuit capacitance and operating current (in general, the higher the operating current for a
given internal capacitance, the faster is the slew rate). Figure 57 shows the slew capabilities of the LMH6321
under large signal input conditions, using a resistive load.
Figure 57. Slew Rate vs. Peak-to-Peak Input Voltage
However, when driving capacitive loads, the slew rate may be limited by the available peak output current
according to the following expression.
dv/dt = IPK/CL(10)
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0.1 1 10 100 1000
CAPACITANCE (nF)
0.1
1
10
1000
10000
SLEW RATE (V/Ps)
100
LMH6321
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SNOSAL8C –APRIL 2006–REVISED MARCH 2013
and rapidly changing output voltages will require large output load currents. For example if the part is required to
slew at 1000 V/μs with a load capacitance of 1 nF the current demand from the LMH6321 would be 1A.
Therefore, fast slew rate is incompatible with large CL. Also, since CLis in parallel with the load, the peak current
available to the load decreases as CLincreases.
Figure 58 illustrates the effect of the load capacitance on slew rate. Slew rate tests are specified for resistive
loads and/or very small capacitive loads, otherwise the slew rate test would be a measure of the available output
current. For the highest slew rate, it is obvious that stray load capacitance should be minimized. Peak output
current should be kept below 500 mA. This translates to a maximum stray capacitance of 500 pF for a slew rate
of 1000 V/μs.
Figure 58. Slew Rate vs. Load Capacitance
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 23
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6321MR/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LMH63
21MR
LMH6321MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LMH63
21MR
LMH6321TS/NOPB ACTIVE DDPAK/
TO-263 KTW 7 45 RoHS-Exempt
& Green SN Level-3-245C-168 HR -40 to 125 LMH6321TS
LMH6321TSX/NOPB ACTIVE DDPAK/
TO-263 KTW 7 500 RoHS-Exempt
& Green SN Level-3-245C-168 HR -40 to 125 LMH6321TS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6321MRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6321TSX/NOPB DDPAK/
TO-263 KTW 7 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6321MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LMH6321TSX/NOPB DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
KTW0007B
www.ti.com
BOTTOM SIDE OF PACKAGE
TS7B (Rev E)
www.ti.com
PACKAGE OUTLINE
C
6X 1.27
8X 0.51
0.31
2X
3.81
TYP
0.25
0.10
0 - 8 0.15
0.00
2.71
2.11
3.4
2.8 0.25
GAGE PLANE
1.27
0.40
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
PowerPAD is a trademark of Texas Instruments.
TM
18
0.25 C A B
5
4
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
EXPOSED
THERMAL PAD
4
1
5
8
9
TYP
6.2
5.8
1.7 MAX
A
NOTE 3
5.0
4.8
B4.0
3.8
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EXAMPLE BOARD LAYOUT
(5.4)
(1.3) TYP
( ) TYP
VIA
0.2
(R ) TYP0.05
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.55)
8X (0.6)
6X (1.27)
(2.95)
NOTE 9
(4.9)
NOTE 9
(2.71)
(3.4)
SOLDER MASK
OPENING
(1.3)
TYP
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
9
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(R ) TYP0.05
8X (1.55)
8X (0.6)
6X (1.27)
(5.4)
(2.71)
(3.4)
BASED ON
0.125 THICK
STENCIL
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
SYMM
SYMM
1
45
8
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
9
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