Audio
Input
750
12 V / 1 W
±VEE
47 µF0.1 µF
750
+VCC
0.1 µF47 µF
1000
10 k
0.0022 µF
2.7 k
0.001 µF
2.7 k
VCC+OUT1
IN1±OUT2
IN2±
IN2+
IN1+
VCC±
47 k
1 µF
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LM833
SLOS481B –JULY 2010–REVISED OCTOBER 2014
LM833 Dual High-Speed Audio Operational Amplifier
1 Features 3 Description
The LM833 device is a dual operational amplifier with
1• Dual-Supply Operation: ±5 V to ±18 V high-performance specifications for use in quality
• Low Noise Voltage: 4.5 nV/√Hz audio and data-signal applications. Dual amplifiers
• Low Input Offset Voltage: 0.15 mV are utilized widely in audio circuits optimized for all
preamp and high level stages in PCM and HiFi
• Low Total Harmonic Distortion: 0.002% systems. The LM833 device is pin-for-pin compatible
• High Slew Rate: 7 V/μswith industry-standard dual operation amplifiers. With
• High-Gain Bandwidth Product: 16 MHz addition of a preamplifier, the gain of the power stage
can be greatly reduced to improve performance.
• High Open-Loop AC Gain: 800 at 20 kHz
• Large Output-Voltage Swing: –14.6 V to 14.1 V Device Information
• Excellent Gain and Phase Margins PART NUMBER PACKAGE BODY SIZE (NOM)
• Available in 8-Terminal MSOP Package SOIC (8) 4.90 mm × 3.91 mm
(3.0 mm x 4.9 mm x 0.65 mm) LM833 VSSOP (8) 3.00 mm × 3.00 mm
PDIP (8) 9.81 mm × 6.35 mm
2 Applications
• HiFi Audio System Equipment
• Preamplification and Filtering
• Set-Top Box
• Microphone Preamplifier Circuit
• General-Purpose Amplifier Applications
4 Typical Design Example Audio Pre-Amplifier
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM833
SLOS481B –JULY 2010–REVISED OCTOBER 2014
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Table of Contents
8.3 Feature Description................................................. 14
1 Features.................................................................. 18.4 Device Functional Modes........................................ 14
2 Applications ........................................................... 19 Application and Implementation ........................ 15
3 Description............................................................. 19.1 Application Information............................................ 15
4 Typical Design Example Audio Pre-Amplifier..... 19.2 Typical Application ................................................. 15
5 Revision History..................................................... 29.3 Typical Application — Reducing Oscillation from
6 Pin Configuration and Functions......................... 3High-Capacitive Loads............................................. 18
7 Specifications......................................................... 410 Power Supply Recommendations ..................... 20
7.1 Absolute Maximum Ratings ..................................... 411 Layout................................................................... 20
7.2 Handling Ratings....................................................... 411.1 Layout Guidelines ................................................. 20
7.3 Recommended Operating Conditions....................... 411.2 Layout Example .................................................... 20
7.4 Thermal Information.................................................. 412 Device and Documentation Support................. 22
7.5 Electrical Characteristics........................................... 512.1 Trademarks........................................................... 22
7.6 Operating Characteristics.......................................... 512.2 Electrostatic Discharge Caution............................ 22
7.7 Typical Characteristics.............................................. 612.3 Glossary................................................................ 22
8 Detailed Description............................................ 13 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 13 Information........................................................... 23
8.2 Functional Block Diagram....................................... 13
5 Revision History
Changes from Revision A (August 2010) to Revision B Page
• Updated document to new TI data sheet format.................................................................................................................... 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
• Added Device Information table. ............................................................................................................................................ 1
• Added Pin Functions table. .................................................................................................................................................... 3
• Added Handling Ratings table................................................................................................................................................ 4
• Added Thermal Information table........................................................................................................................................... 4
• Added Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging,
and Orderable Information sections .................................................................................................................................... 20
Changes from Original (July 2010) to Revision A Page
• Changed data sheet status from Product Preview to Production Data.................................................................................. 1
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1
2
3
45
6
7
8
IN2+
IN2–
OUT2
VCC+
VCC–
IN1+
IN1–
OUT1
D (SOIC), DGK (MSOP), OR P (PDIP) PACKAGE
(TOP VIEW)
LM833
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SLOS481B –JULY 2010–REVISED OCTOBER 2014
6 Pin Configuration and Functions
Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
IN1+ 3 Input Noninverting input
IN1– 2 Input Inverting Input
IN2+ 5 Input Noninverting input
IN2- 6 Input Inverting Input
OUT1 1 Output Output 1
OUT2 7 Output Output 2
VCC+ 8 — Positive Supply
VCC– 4 — Negative Supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC+ Supply voltage(2) 18 V
VCC– Supply voltage(2) –18 V
VCC+ – VCC– Supply voltage 36 V
Input voltage, either input(2)(3) VCC– VCC+ V
Input current(4) ±10 mA
Duration of output short circuit(5) Unlimited
TJOperating virtual junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
(3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage.
(4) Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless
some limiting resistance is used.
(5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the
maximum dissipation rating is not exceeded.
7.2 Handling Ratings
PARAMETER DEFINITION MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human-Body Model (HBM)(1) 0 2.5
V(ESD) kV
Charged-Device Model (CDM)(2) 0 1.5
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions MIN MAX UNIT
VCC– –5 –18
Supply voltage V
VCC+ 5 18
TAOperating free-air temperature range –40 85 °C
7.4 Thermal Information LM833
THERMAL METRIC(1) D DGK P UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance(2)(3) 97 172 85 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
(2) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD= (TJ(max) – TA) / θJA. Operating at the absolute maximum TJof 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
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SLOS481B –JULY 2010–REVISED OCTOBER 2014
7.5 Electrical Characteristics
VCC– = –15 V, VCC+ = 15 V, TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA= 25°C 0.15 2
VIO Input offset voltage VO= 0, RS= 10 Ω, VCM = 0 mV
TA= –40°C to 85°C 3
Input offset voltage
αVIO VO= 0, RS= 10 Ω, VCM = 0 TA= –40°C to 85°C 2 μV/°C
temperature coefficient TA= 25°C 300 750
IIB Input bias current VO= 0, VCM = 0 nA
TA= –40°C to 85°C 800
TA= 25°C 25 150
IIO Input offset current VO= 0, VCM = 0 nA
TA= –40°C to 85°C 175
Common-mode input voltage
VICR ΔVIO = 5 mV, VO= 0 ±13 ±14 V
range TA= 25°C 90 110
Large-signal differential
AVD RL≥2 kΩ, VO= ±10 V dB
voltage amplification TA= –40°C to 85°C 85
VOM+ 10.7
RL= 600 ΩVOM– –11.9
VOM+ 13.2 13.8
Maximum output voltage
VOM VID = ±1 V RL= 2000 ΩV
swing VOM– –13.2 –13.7
VOM+ 13.5 14.1
RL= 10,000 ΩVOM– –14 –14.6
CMMR Common-mode rejection ratio VIN = ±13 V 80 100 dB
kSVR(1) Supply-voltage rejection ratio VCC+ = 5 V to 15 V, VCC– = –5 V to –15 V 80 105 dB
Source current 15 29
IOS Output short-circuit current |VID| = 1 V, Output to GND mA
Sink current –20 –37
TA= 25°C 2.05 2.5
ICC Supply current (per channel) VO= 0 mA
TA= –40°C to 85°C 2.75
(1) Measured with VCC± differentially varied at the same time
7.6 Operating Characteristics
VCC– = –15 V, VCC+ = 15 V, TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR Slew rate at unity gain AVD = 1, VIN = –10 V to 10 V, RL= 2 kΩ, CL= 100 pF 5 7 V/μs
GBW Gain bandwidth product f = 100 kHz 10 16 MHz
B1Unity gain frequency Open loop 9 MHz
CL= 0 pF –11
GmGain margin RL= 2 kΩdB
CL= 100 pF –6
CL= 0 pF 55
ΦmPhase margin RL= 2 kΩdegrees
CL= 100 pF 40
Amp-to-amp isolation f = 20 Hz to 20 kHz –120 dB
Power bandwidth VO= 27 V(PP), RL= 2 kΩ, THD ≤1% 120 kHz
THD Total harmonic distortion VO= 3 Vrms, AVD = 1, RL= 2 kΩ, f = 20 Hz to 20 kHz 0.002%
zoOpen-loop output impedance VO= 0, f = 9 MHz 37 Ω
rid Differential input resistance VCM = 0 175 kΩ
Cid Differential input capacitance VCM = 0 12 pF
VnEquivalent input noise voltage f = 1 kHz, RS= 100 Ω4.5 nV/√Hz
InEquivalent input noise current f = 1 kHz 0.5 pA/√Hz
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0
100
200
300
400
500
600
-15 -10 -5 0 5 10 15
VCM – Common Mode Voltage – V
IIB – Input Bias Current – nA
VCC+ = 15 V
VCC– = –15 V
TA= 25°C
VCM = 0 V
TA= 25°C
D.U.T.
Voltage Gain = 50,000
Scope
x 1
RIN = 1.0 MΩ
+
−
100 kΩ
10 Ω
0.1 µF
100 kΩ
0.1 µF
24.3 kΩ
4.7 µF
2.0 kΩ
2.2 µF
22 µF
110 kΩ
4.3 kΩ
1/2
LM833
NOTE: All capacitors are non-polarized.
LM833
SLOS481B –JULY 2010–REVISED OCTOBER 2014
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7.7 Typical Characteristics
Figure 1. Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
Figure 2. Input Bias Current vs Common-Mode Voltage Figure 3. Input Bias Current vs Supply Voltage
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0
1
2
3
4
5
6
7
8
9
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
RL– Load Resistance – k@
Output Saturation Voltage
Proximity to V CC– – V
T = –55°C
A
T = 25°C
A
T = 125°C
A
kW
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
RL– Load Resistance – kh
Output Saturation Voltage
Proximity to V CC+ – V
T = –55°C
A
T = 25°C
A
T = 125°C
A
kW
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
-55 -25 5 35 65 95 125
TA– Temperature – °C
Input Common-Mode Voltage High
Proximity to V CC+ – V
VCC+ = 3 V to 15 V
VCC– = -3 V to -15 V
VIO = 5 mV
VO= 0 V
D
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-55 -25 5 35 65 95 125
TA– Temperature – °C
Input Common-Mode Voltage Low
Proximity to V CC– – V
VCC+ = 3 V to 15 V
VCC– = -3 V to -15 V
èVIO = 5 mV
VO= 0 V
D
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-55 -35 -15 5 25 45 65 85 105 125
TA– Temperature – °C
VIO – Input Offset Voltage – mV
VCC+ = 15 V
VCC– = –15 V
VCM = 0 V
0
100
200
300
400
500
600
700
800
900
1000
-55 -35 -15 5 25 45 65 85 105 125
TA– Temperature – °C
IIB – Input Bias Current – nA
VCC+ = 15 V
VCC– = –15 V
VCM = 0 V
LM833
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SLOS481B –JULY 2010–REVISED OCTOBER 2014
Typical Characteristics (continued)
Figure 4. Input Bias Current vs Temperature Figure 5. Input Offset Voltage vs Temperature
Figure 6. Input Common-Mode Voltage Low Proximity Figure 7. Input Common-Mode Voltage High Proximity
to VCC– vs Temperature to VCC+ vs Temperature
Figure 8. Output Saturation Voltage Proximity to VCC+ Figure 9. Output Saturation Voltage Proximity to VCC–
vs Load Resistance vs Load Resistance
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0
5
10
15
20
25
30
-55 -35 -15 5 25 45 65 85 105 125
TA– Temperature – °C
GBW – Gain Bandwidth Product – MHz
0
5
10
15
20
25
30
5 6 7 8 9 10 11 12 13 14 15 16 17 18
VCC+/–VCC– – Supply Voltage – V
GBW – Gaind Bandwidth Product – MHz
0
10
20
30
40
50
60
70
80
90
100
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
f – Frequency – Hz
CMMR – dB
100 1k 10k 100k 1M 10M
V = 15 V
V = –15 V
V = 0 V
V = 1.5 V
T = 25°C
CC+
CC–
CM
CM
A
D ±
0
10
20
30
40
50
60
70
80
90
100
110
120
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
f – Frequency – Hz
PSRR – dB
100 1k 10k 100k 1M 10M
V = 15 V
V = –15 V
T = 25°C
CC+
CC–
A
T3P
T3N
10
20
30
40
50
60
70
-55 -35 -15 5 25 45 65 85 105 125
TA– Temperature – °C
IOS – Output Short-Circuit Current – mA
VCC+ = 15 V
VCC– = –15 V
VID = 1 V
Sink
Source
0
1
2
3
4
5
6
7
8
9
10
-55 -35 -15 5 25 45 65 85 105 125
TA– Temperature – °C
ICC – Supply Current – mA
VCM = 0 V
RL= High Impedance
VO= 0 V
V = 15 V
CC±±
V = 10 V
CC±±
V = 5 V
CC±±
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Typical Characteristics (continued)
Figure 10. Output Short-Circuit Current vs Temperature Figure 11. Supply Current vs Temperature
Figure 12. CMRR vs Frequency Figure 13. PSSR vs Frequency
Figure 14. Gain Bandwidth Product vs Supply Voltage Figure 15. Gain Bandwidth Product vs Temperature
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0
5
10
15
20
25
30
35
40
45
50
1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
f – Frequency – Hz
ZO– Output Impedance –
VCC+ = 15 V
VCC– = –15 V
VO= 1 Vrms
TA= 25°C
W
1k 10k 100k 1M 10M
A = 1
V
A = 10
V
A = 100
V
A = 1000
V
100
110
120
130
140
150
160
170
180
190
200
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
f – Frequency – Hz
Crosstalk Rejection – dB
1k 10k 100k
Drive Channel
V = 15 V
V = –15 V
R = 2 k
V = 20 V
T = 25°C
CC+
CC–
L
O PP
A
W
10 100
80
85
90
95
100
105
110
5 6 7 8 9 10 11 12 13 14 15 16 17 18
VCC+/–VCC– – Supply Voltage – V
AV– Open-Loop Gain – dB
R = 2 k
f < 10 Hz
V = 2/3(V – V )
T = 25°C
L
O CC+ CC–
A
W
D
80
85
90
95
100
105
110
115
120
-55 -35 -15 5 25 45 65 85 105 125
TA– Temperature – °C
AV– Open-Loop Gain – dB
R = 2 k
f < 10 Hz
V = 2/3(V – V )
T = 25°C
L
O CC+ CC–
A
W
D
0
5
10
15
20
25
30
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
f – Frequency – Hz
VO– Output Voltage – V
100 1k 10k 100k 1M 10M
10
V = 15 V
V = –15 V
R = 2 k
A = 1
THD < 1%
T = 25°C
CC+
CC–
L
V
A
W
-20
-15
-10
-5
0
5
10
15
20
5 6 7 8 9 10 11 12 13 14 15 16 17 18
VCC+/–VCC– – Supply Voltage – V
VO – Output Voltage – V
R = 10 k
LW
R = 2 k
LW
R = 10 k
LW
R = 2 k
LW
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SLOS481B –JULY 2010–REVISED OCTOBER 2014
Typical Characteristics (continued)
Figure 16. Output Voltage vs Supply Voltage Figure 17. Output Voltage vs Frequency
Figure 18. Open-Loop Gain vs Supply Voltage Figure 19. Open-Loop Gain vs Temperature
Figure 20. Output Impedance vs Frequency Figure 21. Crosstalk Rejection vs Frequency
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0
10
20
30
40
50
60
70
80
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
f – Frequency – Hz
Gain – dB
-180
-135
-90
-45
0
Phase Shift – deg
V = 15 V
V = –15 V
CC+
CC–
R = 2 k
T = 25°C
L
A
W
100k 1M 10M
1k 10k
Phase
Gain
0
3
6
9
12
1 10 100 1000
Cout – Output Load Capacitance – pF
Gain Margin – dB
0
10
20
30
40
50
60
70
80
Phase Margin – deg
Gain, T = 125°C
A
Gain, T = 25°C
A
Gain, T = –55°C
A
Phase, T = 125°C
A
Phase, T = 25°C
A
Phase, T = –55°C
A
V = 15 V
V = –15 V
CC+
CC–
V = 0 V
O
2
3
4
5
6
7
8
9
10
-55 -35 -15 5 25 45 65 85 105 125
TA– Temperature – °C
SR – Slew Rate – V/µs
V = 15 V
V = –15 V
CC+
CC–
V = 20 V
A = 1
R = 2 k
D
W
IN
V
L
Falling Edge
Rising Edge
2
3
4
5
6
7
8
9
10
5 6 7 8 9 10 11 12 13 14 15 16 17 18
VCC+/–VCC– – Supply Voltage – V
SR – Slew Rate – V/µs
Falling Edge
Rising Edge
V = 2/3(V – V )
A = 1
R = 2 k
T = 25°C
D
W
IN CC+ CC–
V
L
A
0.0001
0.001
0.01
0.1
1
0 1 2 3 4 5 6 7 8 9
VO– Output Voltage – Vrms
THD – Total Harmonic Distortion – %
V = 15 V
V = –15 V
f = 2 kHz
R = 2 k
T = 25°C
CC+
CC–
L
A
W
A = 1
V
A = 10
V
A = 100
V
A = 1000
V
0.0001
0.001
0.01
0.1
1
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
f – Frequency – Hz
THD – Total Harmonic Distortion – %
1k 10k 100k
V = 15 V
V = –15 V
V = 1 V
A = 1
R = 2 k
T = 25°C
CC+
CC–
O rms
V
L
A
W
10 100
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Typical Characteristics (continued)
Figure 22. Total Harmonic Distortion vs Frequency Figure 23. Total Harmonic Distortion vs Output Voltage
Figure 24. Slew Rate vs Supply Voltage Figure 25. Slew Rate vs Temperature
Figure 26. Gain and Phase vs Frequency Figure 27. Gain and Phase Margin
vs Output Load Capacitance
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-15
-5
5
15
25
35
45
55
-2 2 6 10 14 18 22
Time – µs
VO– Output Voltage – V
-60
-50
-40
-30
-20
-10
0
10
VI– Input Voltage – V
V = 15 V
V = –15 V
A = 1
R = 2 k
C
T = 25°C
CC+
CC–
V
L
A
W
L= 100 pF
Input
Output
-15
-5
5
15
25
35
45
55
-2 2 6 10 14 18 22
Time – µs
VO– Output Voltage – V
-60
-50
-40
-30
-20
-10
0
10
VI– Input Voltage – V
V = 15 V
V = –15 V
A = –1
R = 2 k
C
T = 25°C
CC+
CC–
V
L
A
W
L= 100 pF
Input
Output
VCC+ = 15 V
VCC– = –15 V
AV= 100
VO= 0 V
TA= 25°C
Phase Margin
Gain Margin
W
1k 10k 100k
1000 110
1
10
100
1000
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
RS– Source Resistance – è
Input Referred Noise Voltage – nV/rtHz
VCC+ = 15 V
VCC– = –15 V
f = 1 Hz
TA= 25°C
W
10 100 1k 10k 100k
nV/ÖHz
1M
0
10
20
30
40
50
60
70
80
90
100
10 100 1000
Cout – Output Load Capacitance – pF
Overshoot – %
VCC+ = 15 V
VCC– = –15 V
VIN = 100 mVPP
T = 125°C
A
T = 25°C
A
T = –55°C
A
1
10
100
10 100 1000 10000 100000
f – Frequency – Hz
Input Voltage Noise – nV/rtHz
0.1
1
10
Input Current Noise – pA/rtHz
VCC+ = 15 V
VCC– = –15 V
TA= 25°C
Input Voltage Noise
Input Current Noise
10 100 1k 10k 100k
pA/ÖHz
nV/ÖHz
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SLOS481B –JULY 2010–REVISED OCTOBER 2014
Typical Characteristics (continued)
Figure 28. Overshoot vs Output Load Capacitance Figure 29. Input Voltage and Current Noise vs Frequency
Figure 30. Input Referred Noise Voltage Figure 31. Gain and Phase Margin
vs Source Resistance vs Differential Source Resistance
Figure 32. Large Signal Transient Response (AV= 1) Figure 33. Large Signal Transient Response (AV= –1)
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-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
-0.5 0.0 0.5 1.0 1.5
Time – µs
VO– Output Voltage – V
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
VI– Input Voltage – V
V = 15 V
V = –15 V
A = 1
R = 2 k
C
T = 25°C
CC+
CC–
V
L
A
W
L= 100 pF
Input
Output
-500
-400
-300
-200
-100
0
100
200
300
400
-5 -4 -3 -2 -1 0 1 2 3 4 5
Time – s
Input Voltage Noise – nV
T3
VCC+ = 15 V
VCC– = –15 V
BW = 0.1 Hz to 10 Hz
TA= 25°C
LM833
SLOS481B –JULY 2010–REVISED OCTOBER 2014
www.ti.com
Typical Characteristics (continued)
Figure 35. Low-Frequency Noise
Figure 34. Small Signal Transient Response
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Product Folder Links: LM833
INíIN+
VCC
VEE
VOUT
LM833
www.ti.com
SLOS481B –JULY 2010–REVISED OCTOBER 2014
8 Detailed Description
8.1 Overview
The LM833 device is a dual operational amplifier with high-performance specifications for use in quality audio
and data-signal applications. This device operates over a wide range of single- and dual-supply voltage with low
noise, high-gain bandwidth, and high slew rate. Additional features include low total harmonic distortion, excellent
phase and gain margins, large output voltage swing with no deadband crossover distortions, and symmetrical
sink/source performance. The dual amplifiers are utilized widely in circuit of audio optimized for all preamp and
high-level stages in PCM and HiFi systems. The LM833 device is pin-for-pin compatible with industry-standard
dual operation amplifiers' pin assignments. With addition of a preamplifier, the gain of the power stage can be
greatly reduced to improve performance.
8.2 Functional Block Diagram
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LM833
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www.ti.com
8.3 Feature Description
8.3.1 Operating Voltage
The LM833 operational amplifier is fully specified and ensured for operation from ±5 V to ±18 V. In addition,
many specifications apply from –40°C to 85°C. Parameters that vary significantly with operating voltages or
temperature are shown in Absolute Maximum Ratings .
8.3.2 High Gain Bandwidth Product
Gain bandwidth product is found by multiplying the measured bandwidth of an amplifier by the gain at which that
bandwidth was measured. The LM833 has a high gain bandwidth of 16 MHz which stays relatively stable over a
wide range of supply voltages. Parameters that vary significantly with temperature are shown in Figure 14.
8.3.3 Low Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. The LM833
has a very low THD of 0.002% meaning that the LM833 will add little harmonic distortion when used in audio
signal applications. More specific characteristics are shown in Figure 22.
8.4 Device Functional Modes
The LM833 is powered on when the supply is connected. It can be operated as a single supply operational
amplifier or dual supply amplifier depending on the application.
14 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: LM833
++
R5
4.3 k
R4
2 k
R3
2.37
R1
80.6 k
R6
54.9 k
C3
33 nF
C1
39 nF
C4
2 PF
R0
499
C0
200 PF
47 k
CP
VIN
VOUT
-15 V
15 V
½ LM833
½ LM833
3
24
1 5
6
87
R2
8.45 k
LM833
www.ti.com
SLOS481B –JULY 2010–REVISED OCTOBER 2014
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
An application of the LM833 is the two stage RIAA Phono Preamplifier. A primary task of the phono preamplifier
is to provide gain (usually 30 to 40 dB at 1 kHz) and accurate amplitude and phase equalization to the signal
from a moving magnet or a moving coil cartridge. In addition to the amplification and equalization functions, the
phono preamp must not add significant noise or distortion to the signal from the cartridge. The circuit shown in
Figure 36 uses two amplifiers, fulfills these qualifications, and has greatly improved performance over a single-
amplifier design.
9.2 Typical Application
Figure 36. RIAA Phono Preamplifier
9.2.1 Design Requirements
• Supply Voltage = ±15 V
• Low-Frequency −3 dB corner of the first amplifier (f0) > 20 Hz (below audible range)
• Low-Frequency −3 dB corner of the second stage (fL) = 20.2 Hz
9.2.2 Detailed Design Procedure
9.2.2.1 Introduction to Design Method
Equation 1 through Equation 5 show the design equations for the preamplifier.
R1= 8.058 R0A1
where
• A1is the 1 kHz voltage gain of the first amplifier (1)
Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM833
3
14
3.18 10
Example : C 0.03946 F
8.058 10
-
´
= = m
´
3
1
1
3.18 10
Calculate C
R
-
´
=
0
0 0
1
C
2 f R
»
p
5
V2
4
R
A 1
R
= +
( )
4
L
1
C
2 f R3 R6
=p +
5
53 6
3
3 6 P
(R R ) 7.5 10
C 7.5 10 R R R
-
-+´
= ´ =
1
2 0
R
R R
9
= -
3
1
1
3.18 10
C
R
-
´
=
LM833
SLOS481B –JULY 2010–REVISED OCTOBER 2014
www.ti.com
Typical Application (continued)
(2)
(3)
(4)
where
• fLis the low-frequency −3 dB corner of the second stage (5)
For standard RIAA preamplifiers, fLshould be kept well below the audible frequency range. If the preamplifier is
to follow the IEC recommendation (IEC Publication 98, Amendment #4), fLshould equal 20.2 Hz.
where
• AV2 is the voltage gain of the second amplifier (6)
where
• f0is the low-frequency −3 dB corner of the first amplifier (7)
This should be kept well below the audible frequency range.
A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close
conformance to the ideal RIAA curve. Because 1% tolerance capacitors are often difficult to find except in 5% or
10% standard values, the design procedure calls for re-calculation of a few component values so that standard
capacitor values can be used.
9.2.2.2 RIAA Phono Preamplifier Design Procedure
A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close
conformance to the ideal RIAA curve. Since 1% tolerance capacitors are often difficult to find except in 5% or
10% standard values, the design procedure calls for re-calculation of a few component values so that standard
capacitor values can be used.
Choose R0. R0should be small for minimum noise contribution, but not so small that the feedback network
excessively loads the amplifier.
Example: Choose R0= 500
Choose 1 kHz gain, AV1 of first amplifier. This will typically be around 20 dB to 30 dB.
Example: Choose AV1 = 26 dB = 20
Calculate R1= 8.058 R0AV1
Example: R1= 8.058 × 500 × 20 = 80.58 k
(8)
(9)
If C1is not a convenient value, choose the nearest convenient value and calculate a new R1from Equation 10.
16 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: LM833
5
P
3
5
P8
7.5 10
Calculate R C
7.5 10
Example: R 2.273k
3.3 10
-
-
-
´
=
´
= =
´
1
2 0
4
2
R
Calculate R R
9
8.06 10
Example : R 499 8456.56
9
= -
´
= - =
4
0
8.06 10
Example: New R 498.8
8.058 20
´
= =
´
1
0
V1
R
R
8.058 A
=
3
18
1
3.18 10
New R 81.54 k
3.9 10
Use R 80.6 k
-
-
´
= =
´
=
3
1
1
3.18 10
R
C
-
´
=
LM833
www.ti.com
SLOS481B –JULY 2010–REVISED OCTOBER 2014
Typical Application (continued)
(10)
Example: New C1= 0.039 μF.
(11)
Calculate a new value for R0from Equation 12.
(12)
(13)
Use R0= 499.
(14)
Use R2= 8.45 K.
Choose a convenient value for C3in the range from 0.01 μF to 0.05 μF.
Example: C3= 0.033 μF
(15)
Choose a standard value for R3that is slightly larger than RP.
Example: R3= 2.37 k
Calculate R6from 1 / R6=1/RP−1/R3
Example: R6= 55.36 k
Use 54.9 k
Calculate C4for low-frequency rolloff below 1 Hz from design Equation 5.
Example: C4= 2 μF. Use a good quality mylar, polystyrene, or polypropylene.
Choose gain of second amplifier.
Example: The 1 kHz gain up to the input of the second amplifier is about 26 dB for this example. For an
overall 1 kHz gain equal to about 36 dB we choose:
AV2 = 10 dB = 3.16
Choose value for R4.
Example: R4=2k
Calculate R5= (AV2 −1) R4
Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM833
5V
–5V
15V
–15V
ROVO
R = 2 k
LΩ
CL
LM833
SLOS481B –JULY 2010–REVISED OCTOBER 2014
www.ti.com
Typical Application (continued)
Example: R5= 4.32 k
Use R5= 4.3 k
Calculate C0for low-frequency rolloff below 1 Hz from design Equation 7.
Example: C0= 200 μF
9.2.3 Application Curves for Output Characteristics
The maximum observed error for the prototype was 0.1 dB.
Figure 37. Deviation from Ideal RIAA Response for
Circuit of Figure 36 Using 1% Resistors
The lower curve is for an output level of 300 mVrms and the upper curve is for an output level of 1 Vrms.
Figure 38. THD of Circuit in Figure 36 as a Function of Frequency
9.3 Typical Application — Reducing Oscillation from High-Capacitive Loads
While all the previously stated operating characteristics are specified with 100-pF load capacitance, the LM833
device can drive higher-capacitance loads. However, as the load capacitance increases, the resulting response
pole occurs at lower frequencies, causing ringing, peaking, or oscillation. The value of the load capacitance at
which oscillation occurs varies from lot-to-lot. If an application appears to be sensitive to oscillation due to load
capacitance, adding a small resistance in series with the load should alleviate the problem (see Figure 39).
9.3.1 Test Schematic
Figure 39. Capacitive Load Testing Circuit
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Product Folder Links: LM833
250 ns per Division
0.25 V per Division
250 ns per Division
0.25 V per Division
250 ns per Division
0.25 V per Division
250 ns per Division
0.25 V per Division
Maximum capacitance
before oscillation = 590 pF
0.25 V per Division
250 ns per Division
Maximum capacitance
before oscillation = 380 pF
250 ns per Division
0.25 V per Division
Maximum capacitance
before oscillation = 590 pF
LM833
www.ti.com
SLOS481B –JULY 2010–REVISED OCTOBER 2014
Typical Application — Reducing Oscillation from High-Capacitive Loads (continued)
9.3.2 Output Characteristics
Figure 40 through Figure 45 demonstrate the effect adding this small resistance has on the ringing in the output
signal.
Figure 40. Pulse Response Figure 41. Pulse Response
(RL= 600 Ω, CL= 380 pF) (RL= 2 kΩ, CL= 560 pF)
Figure 42. Pulse Response
(RL= 10 kΩ, CL= 590 pF) Figure 43. Pulse Response
(RO= 0 Ω, CO= 1000 pF,
RL= 2 kΩ)
Figure 44. Pulse Response
(RO= 4 Ω, CO= 1000 pF, Figure 45. Pulse Response
RL= 2 kΩ)(RO= 35 Ω, CO= 1000 pF,
RL= 2 kΩ)
Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM833
+
RIN
RG RF
VOUT
VIN
LM833
SLOS481B –JULY 2010–REVISED OCTOBER 2014
www.ti.com
10 Power Supply Recommendations
The LM833 is specified for operation from 10 to 36 V (±5 to ±18 V); many specifications apply from –40°C to
85°C. The Typical Characteristics section presents parameters that can exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 36 V can permanently damage the device (see Absolute
Maximum Ratings ).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Figure 46. Operational Amplifier Schematic for Noninverting Configuration
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Product Folder Links: LM833
OUT1
OUT2
IN1í
IN1+
VCCí
VCC+
IN2í
IN2+
RG
RIN
RF
GND
VIN
VS-GND
VS+
GND
Run the input traces as far
away from the supply lines
as possible
Only needed for
dual-supply
operation
Place components close to
device and to each other to
reduce parasitic errors
Use low-ESR, ceramic
bypass capacitor
(or GND for single supply) Ground (GND) plane on another layer
LM833
www.ti.com
SLOS481B –JULY 2010–REVISED OCTOBER 2014
Layout Example (continued)
Figure 47. Operational Amplifier Board Layout for Noninverting Configuration
Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 21
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www.ti.com
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLOS481B –JULY 2010–REVISED OCTOBER 2014
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM833
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM833D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LM833
LM833DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 RSU
LM833DGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 RSU
LM833DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LM833
LM833P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 LM833P
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM833DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
LM833DGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
LM833DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LM833DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM833DGKR VSSOP DGK 8 2500 346.0 346.0 35.0
LM833DGKT VSSOP DGK 8 250 203.0 203.0 35.0
LM833DR SOIC D 8 2500 367.0 367.0 35.0
LM833DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2
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