QPro XQ-XQR18V04 QML Programmable Configuration PROMs - Xilinx, Inc.

DS082 (v1.2) November 5, 2001 www.xilinx.com 1

Preliminary Product Specification 1-800-255-7778

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• In -system progr a mmable 3.3V PROMs fo r

configuration of Xilinx FPGAs

- Endurance of 2,000 program/erase cycles

- Program/erase ov er full military temperature range

• I EEE Std 1 149 .1 b oundary -sc an (JTAG ) support

• Cascadable for storing longer or multiple bitstreams

• Dual configuration mod es

- Serial Slow/F ast configuration (up to 33 MHz)

- Para llel (up to 264 Mbps at 33 MHz)

• Low-power advanced CMOS FLASH process

• 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals.

• 3.3V or 2.5V out put capab ilit y

• Available in CC44 and VQ44 packages.

• Design support using the Xilinx Alliance™ and

F oundation™ series software packages.

• JTAG co mmand ini tiation of standa rd FPGA

configuration.

• Available to Standard Microcircuit Drawing

5962-01525.

- For more infor ma tion contact Defense Su pply

Center Columbus (DSCC) at

http://www.dscc.dla.mil

Radiation Hardenned XQR18V04

• Fabri cated on Epitaxial Substrate

• Latch-Up Immu ne to >120 LET

• Guaranteed TID of 40 kRad(Si)

• Supports SEU Scrubbing

Description

Xilinx introduces the QPro™ XQ18V04 and XQR18V04

series of QML in-system programmable and radiation hard-

ened configu ration PROM s. Initial devices in this 3.3 V fam-

ily are a 4-megabit PROM that provide an easy-to-use,

cost-effective m ethod for re-programming and st orin g l arge

Xilinx FPGA configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time a fter the r ising CCLK, data is available on the PROM

DATA (D0 ) pin that is connected to the FPGA DIN pi n. The

FP GA generate s the ap propri ate number of clock pulses to

complete the configuration. When the FPGA is in Slave

Serial mode, the PROM and the FPGA are clocked by an

external clock.

When the FPGA is in Express or SelectMAP Mode, an

external oscillator will generate t he configuration clock t hat

drives the PROM and the FPGA. After the rising CCLK

edge, data are av ail abl e on the PROMs DATA (D0-D7) pins.

The dat a will be clocked into the FPGA on the following ris-

ing edge of the CC LK. Neither Express nor SelectM AP uti-

lize a Length Count, so a free-running oscillator may be

used . See Figure 6.

0QPro XQ18V04 (XQR18V04) QML

In-System Programmable

Configuration PROMs

DS082 (v1.2) November 5, 2001 05Preliminary Product Speci fication

Figure 1: XQ18V 04 Series Block Diag ram

Control

and

JTAG

Interface

Memory Serial

Parallel

Interface

D0 DATA

(Serial or Parallel

[Express/SelectMAP] Mode)

D[1:7]

Express Mode and

SelectMAP Interface

Data

Address

CLK CE

TCK

TMS

TDI

TDO

OE/Reset

CEO

Data

DS026_01_021000

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

2www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family or with

the XC1700L one-t im e programmable Serial PROM family.

Pinout and Pin Description

Table 1: Pin Names and Descriptions (pins not listed are “no connect”)

Name

Boundary

Scan

Order Function Pin Description

44-pin

VQFP

44-pin

CLCC

D0 4 D ATA OUT D0 is the D ATA output pin to provide data for configuring an

FPGA in serial mode. 40 2

3OUTPUT

ENABLE

D1 6 DATA OU T D0-D7 are the output pin s to provide parallel data for

configuring a Xilinx FPGA in Express/SelectMap mode. 29 35

5OUTPUT

ENABLE

D2 2 DATA OUT 42 4

1OUTPUT

ENABLE

D3 8 DATA OUT 27 33

7OUTPUT

ENABLE

D4 24 DATA OUT 9 1 5

23 OUTPUT

ENABLE

D5 10 DATA OUT 25 3 1

9OUTPUT

ENABLE

D6 17 DATA OUT 14 2 0

16 OUTPUT

ENABLE

D7 14 DATA OUT 19 2 5

13 OUTPUT

ENABLE

CLK 0 DATA IN Each rising edge on the CLK i nput increments the internal

address counter if both CE is L ow a n d OE/RESET i s Hi gh. 43 5

OE/

RESET 20 DATA IN When Low, this input holds the address counter reset and

the DATA output is in a high-i mpe dance stat e. T his is a

bidirectional open-drain pin that is held Low while the

PROM is reset. Polarity is NOT programmable.

13 19

19 DATA OUT

18 OUTPUT

ENABLE

CE 15 D ATA IN When CE is High, this pin puts the device into standby

mode and resets the address counter. The DATA output pin

is in a high-impedance state, and the device is in low power

standby mode.

15 21

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 3

Preliminary Product Specification 1-800-255-7778

CF 22 D ATA OUT Allows JTAG CONFIG instruction to initiate FPGA

configuration without powering down FPGA. This is an

open-drain output t hat is pulsed Lo w b y the JTA G CONFIG

command.

10 16

21 OUTPUT

ENABLE

CEO 13 DATA OUT Chip E n abl e Output (CEO) is connected to the CE input of

the next PROM in the chain. This output is Low when CE is

Low and OE/RESET input is High, AND t he intern al

address counter has been increm ented beyond its

Ter m inal Count (TC) value. When OE/RESET goes Low,

CEO stays High until the PROM is brought out of reset by

bringing OE/ RE SET High.

21 27

14 OUTPUT

ENABLE

GND GND is the ground co nnection. 6, 18,

28 &

3, 12,

24 &

TMS MODE SELECT The state of TMS on the rising edge of TCK determines the

state transitions at the Test Access Port (TAP) controller.

TMS has an inter nal 50K ohm resistive p ull-up on it to

provide a logic "1" to the device if the pin is not driven.

511

TCK CLOCK This pin is the JTAG test clock. It sequences the TA P

controller and a ll the JTAG test and program m ing

electronics.

713

TDI DATA IN This pin is the serial input to all JTAG ins truc tion and data

registers. TDI has an internal 50K ohm resistiv e pull-up on

it to provi de a logi c "1" to t he syst em if the pin i s n ot driv en.

TDO D ATA OUT This pin is the serial output f or all JTAG instruction and data

registers. TDO has an internal 50K ohm resistive pull-up on

it to provide a logic "1" to the system if the pin is not driven.

31 37

VCC Posi tive 3.3V supply voltage for internal logic and input

buffers. 17, 35

& 38 23, 41

& 44

VCCO Posi tive 3.3V or 2.5V supply voltage c onnect ed to the

output voltage dri vers. 8, 16,

26 &

14, 22,

32 &

Table 1: Pin Names and Descriptions (pins not listed are “no connect”) (Continued)

Name

Boundary

Scan

Order Function Pin Description

44-pin

VQFP

44-pin

CLCC

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

4www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

Xilinx FPGAs and Compatible PROMs

Capacity

In-System Programming

In-System Programmable PROMs can be programmed indi-

vidually, o r two or more can be dai sy-chained together and

programmed in-system via the standard 4-pin JTAG proto-

col as shown in Figure 2. In-system programming offers

quick and efficient design iteratio ns and eliminates unnec-

essary package handling or socketing of de vices. The Xilinx

development system provides the programming data

sequence using either Xilinx JTAG Programmer software

and a download c abl e, a third-party JTAG de velopment s ys-

tem, a JTAG-compa tible board tester, or a sim ple micropro-

cessor interface that emulates the JTAG instruction

sequence. The JTAG Programmer software also outputs

serial vector format (SVF) files for use with any tools that

accept SVF format and with automat ic test equipment.

All outputs are held in a high-impedance state or held at

clamp levels during in-system pro gramming.

OE/RESET

The ISP programming algorithm requires issuance of a

res et that w ill c au s e OE to go Low.

External Programming

Xilinx reprogrammab le PROMs can also be programmed by

the Xilinx HW-130 device programmer. This provides the

added f lexibility of using pre-programmed d evices in board

design and boundary-scan manufacturing tools, with an

in-system programmable option for future enhancements

and design changes.

Reliability and En durance

Xilinx i n-system programmable p roducts provide a guaran-

teed endurance level of 2,000 in-system program/erase

cycles and a minimum data retention of ten years. Each

device meets all functi onal, perf ormance, and data ret ention

speci fications within this endurance limit.

Design Security

The Xilinx in-syst em programmabl e PROM de vices incorpo-

rate advanced data security features to fully protect the pro-

gramming data against unauthorized reading. Table 2

shows the security setting av ai lab l e.

The read security bit can be set by the user to prevent the

inter na l programming patter n f rom bei ng read or copied via

JTAG. When set, it allows device erase. Erasing the entire

device is the only way to reset the read security bit.

Table 2: Data Security Options

Device Configuration

Bits XQ(R)18VO4

PROMs

XQV100 781,216 1

XQV(R)300 1,751,808 1

XQV(R)600 3,607,968 1

XQV(R)1000 6,127,744 2

XQV(R)600E 3,961,632 1

XQV(R)1000E 6,587,520 2

XQV(R)2000E 10,159,648 3

Devices Configuration Bits

XQ(R)18V04 4,194,304

Default = Reset Set

Read Allowed

Program/E rase Allowed Read Inhibited via JTAG

Erase Allowed

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 5

Preliminary Product Specification 1-800-255-7778

IEEE 1149.1 Boundary-Scan (JTAG)

The XQ(R)18V04 f amily is full y compliant wit h the IEEE Std .

1149.1 Boundary-Scan, also known as JTAG. A Test

Access Port (TAP) and regi sters are provided to s uppo rt all

required boundary scan instructions, as well as many of the

optional instructions specified b y IEEE Std. 1149.1. In addi-

tion , the JTAG inte rf ace is used to implement in-syst em pro-

gramming (ISP) to facilitate configuration, erasure, and

verificat ion operations on the XQ(R)18V04 device.

Table 3 lists the required and optional boundary-scan

instructions supported in the XQ(R)18V04. Refer to the

IEEE Std. 1149.1 spe cifica tion for a comp l e te d e scr iption o f

boundary-scan architecture and the required and optional

instructions.

Figure 2: In-System Programmin g Ope ration (a) Solder Device to PCB an d (b) Program Using Download Cable

DS026_02_011100

GND

(a) (b)

Table 3: Bou nd ary S can Instructions

Boundary-Scan

Command Bin ar y

Code [7:0] Description

Re q uire d Ins t r u ctions

BYPASS 11111111 Enables BYPASS

SAMPLE/

PRELOAD 00000001 Enables boundary-scan

SAMPLE/PRELOAD

operation

EXTEST 00000000 Enables boundary-scan

EXTES T operation

Optional Instructions

CLAMP 11111010 Enables boundary-scan

CLAMP operation

HIGHZ 11111100 All outputs in

high-impedanc e sta te

simultaneously

IDCODE 11111110 Enables shifting out

32-bit IDCODE

USERCODE 11111101 Enables shifting out

32-bit USERCODE

XQ(R)18V04 Speci fic Instructions

CONFIG 11101110 Initiates FPGA

configuration by pulsing

CF pin Low

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

6www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

Instruction Register

The Instruction Register (IR) for the XQ(R)18V04 is eight

bits wide and is connected between TDI and TDO during an

instruction sca n seq uence. In prepa ration for an instruc tion

scan sequence, the instruction register is parallel loaded

with a fixed instruction capture pattern. This pattern is

shifted out onto TDO (LSB first), while an instruction is

shifted into the instruction register from TDI. The detailed

composition of the instruction capture pattern is illustrated

in Figure 3.

The ISP Status field, IR(4), contains logic "1" if the de vice i s

currently in ISP mode; otherwise, it will contain logic "0".

The Security field, IR(3), will contain logic "1" if the device

has been programmed with the security option turned on;

otherwise, it will contain logic "0".

Boundary Scan Register

The boundar y -s can register i s used t o c ontro l and obs erve

the state of the device pins during the EXTEST, SAM-

PLE/PRELOAD, and CLAMP instructions. Each output pin

on the XQ(R)18V00 has two regi ster stages tha t contr ibu te

to the boundary-scan register, while each input pin only has

one register stage.

For ea ch output pin, t he register stage nearest to TDI con-

trols and observes the output state, and the second stage

closest to TDO controls and observes the High-Z enable

state of the p in.

F or each input pin, the regist er stage controls and observ es

the input state of the pin.

Identification Register s

The IDCODE is a fixed, vendor-assigned value that is used

to electrically identify the manufacturer and type of the

device being addressed. The IDCODE register is 32 bits

wide. The IDCODE register can be shifted out fo r exam ina-

tion b y using t he IDCODE instruction. The IDCODE is avail-

able to any other system componen t via JTAG.

The IDCODE register has the foll owing binary form at:

vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1

where

v = the die version number

f = the fam ily code (50h for XQ(R)18V 04 family)

a = the ISP PROM product ID (26h for the XQ(R)18V04)

c = the company code (49h for Xilinx)

Note: The LSB of the IDCODE register is always read as

logic "1" as defined by IE EE S td. 1149.1

Table 4 lists the IDCODE register values for the

XQ(R)18V00 devices. 0

The USERCODE instruction gives access to a 32-bit user

programmable scratch pad typically used to supply inf orma-

tion abo ut the device’s p rogrammed c ontent s. By us ing t he

USERCODE instruction, a user-programmable identifica-

tion code can be shifted out for examination. This code is

loaded into the USERCODE register during programming of

the XQ(R)18V04 device. If the device is blank or was not

loaded during programming, the USERCODE register will

contain FFFFFFFFh.

XQ(R)18V04 TAP Characteristics

The X Q(R)18V04 family perfor ms both in-system program -

ming an d IE EE 1149.1 boundar y-s can (JTAG) testing via a

single 4- wire Test Access Port (TAP). This simp lifies sys tem

designs and allows standard Automatic Test Equipment to

perform both functions. The AC characteristics of the

XQ(R)18 V04 TAP are described as follows.

TAP Timing

Figure 4 shows th e timing relationships of the TAP signals.

These TAP timing characteristics are identical for both

boundary -s can and ISP operations.

IR[7:5] IR[4] IR[3] IR[2] IR[1:0]

TDI-> 0 0 0 ISP

Status Security 0 0 1 ->TDO

Notes:

1. IR(1:0) = 01 is specified by IEEE Std. 1149.1

Figure 3: Instruction Register Values Loaded into IR as

Part of an Instru ction Scan Sequ ence

Table 4: IDCO DES Assigned to XQ(R)18V04 Devices

ISP-PROM IDCODE

XQ(R)18V04 05026093h

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 7

Preliminary Product Specification 1-800-255-7778

TAP AC Parameters

Table 5 shows th e timing parameters f or the TAP wa vef orms

shown in Figure 4

Figure 4: Test Access Port Timing

TCK

TCKMIN

TMSS

TMS

TDI

TDO

TMSH

DIH

TDOV

TDIS

DS026_04_020300

Table 5: Test Access P ort Timing Parameters

Symbol Parameter Min Max Units

TCKMIN1 TCK minimum clock period 100 - ns

TCKMIN2 TCK minimum clock period, Bypass mode 50 - ns

TMSS TMS setup time 10 - ns

TMSH TMS hold time 25 - ns

TDIS TDI setup time 10 - ns

TDIH TDI hold time 25 - ns

TDOV TD O valid de l ay - 25 ns

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

8www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

Connecting Configuration PROMs

Connecting the FPGA device with th e configuration PROM

(see Figure 6).

•The DATA output(s) of the PROM(s) drives the DIN

input of the l ead FPGA device.

•The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s) (in Master Ser ial mode only).

•The CEO output of a PROM dri ves the CE input of the

next PROM in a daisy chain (if any).

•The OE/RESET input of all PROMs is best driven by

the INIT output of the lead FPGA device. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration, even

when a reconfiguration is initiated by a VCC glitch.

•The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PRO M can be driven

by the DONE out put of the first FPGA devi ce, provided

that DONE is not permanently grounded. CE can also

be permanently tied Low, but this keeps the DATA

output active and causes an unnecessary supply

current of 20 mA maximum.

•Express/SelectMap mode is similar to slave serial

mode. The DATA i s clocked out of the PROM o ne byte

per CCLK instead of one bit per CCLK cycle. See

FPGA data sheets for special configuration

requirements.

Initiating FPGA Configuration

The XQ(R)18V 04 devices incorporate a pin nam ed CF that

is controllable through the JTAG CONFIG instruction. Exe-

cuting the CONFIG instruction through JTAG pulses the CF

low for 300-500 ns, which resets the FPGA and initiates

configuration.

The CF pin must be connected to the PROGRAM pin on the

FPGA(s) to use this feature.

The JTAG Programmer software can also issue a JTAG

CONFIG command to initiate FPGA configuration through

the "Load FPGA" setting.

Selecting Configuration Modes

The XQ(R)18V04 accommodates serial and parallel meth-

ods of configuration. The configuration modes are select-

able through a user control register in the XQ(R)18V04

device. This control register is accessible through JTAG,

and is set using the "Parallel mode" setting on the Xilinx

JTA G Programmer software . Serial output is the default pro-

gramming mode.

Master Serial Mode Summary

The I /O and logic func tions of the Configurable Log ic Block

(CLB) and their associated interconnections are established

by a configuration program. The program is loaded either

automatically upon power up, or on command, depending

on the stat e of the three F PG A mode pins. In Master Seria l

mode, the FPGA automatically loads the configuration pro-

gram from an external memory. Xilinx PROMs are designed

to accomm odate the Master Seri al mode.

Upon power-up or reconfiguration, an FPGA enters the

Master Serial mode whenever all three of the FPGA

mode-select pins are Low (M0=0, M1=0, M2=0). Data is

read from the PROM sequentially on a single data line. Syn-

chronization is provided by the rising edge of the temporary

signal C CLK, which is gene rated by the FPG A dur ing con-

figuration.

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line, a clock line, and two control

lines are required to configure an FPGA. Data from the

PROM is read sequentially, accessed via the internal

address and bit counters which are incremented on every

valid rising edge of CCLK. If the user-programmable,

dual-func tion DIN pin on the FP G A is used only for configu-

ration, it must still b e held a t a defined level dur ing nor mal

operation. The Xilinx FPGA families take care of this auto-

ma ti cally with an on-chip pu ll- up resi sto r.

Cascading Configuration PROMs

Fo r multiple FPGAs configured as a ser ial daisy-chai n, or a

single FPGA requiring larger configuration memories in a

serial or SelectMAP configuration mode, cascaded PROMs

provide additional memory (Figure 5). Multiple XQ(R)18V04

devices can be concatenated by using the CEO output to

drive the CE input of the downstream device. The clock

inputs and the data outputs of all XQ(R)18V04 devices in

the cha in are interco nnecte d. Afte r the last bit from the first

PROM is read, the next clock signal to the PROM asserts its

CEO output Low and drives its DATA line to a high-imped-

ance state. The seco nd PROM re co gnizes the Low level on

its CE input and enables i ts DATA out put. See Figure 6.

After configuration is complete, the address counters of all

cascaded PROMs are reset if the PROM OE/RESET pin

goes Low.

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 9

Preliminary Product Specification 1-800-255-7778

Figure 5: JTAG Chain for Configuring Devices in Master Serial Mode

4.7K

TDO

DOUT

TDI

TMS

TCK

Vcc

DIN

CCLK

DONE

INIT

Vcc MODE PINS*

Xilinx

FPGA

Master

Serial

Vcc

Vcco

TDI CLK

TMS CE

TCK CEO

OE/RESET

PROGRAM

TDO

TDI

TMS

TCK

DIN

CCLK

DONE

INIT

Vcc MODE PINS*

Xilinx

FPGA

Slave

Serial

PROGRAMCF

TDO

GND

* For Mode pin connections, refer to appropriate FPGA data sheet.

** Virtex, Virtex-E is 300 ohms, all others are 4.7K.

XC18V00

Cascaded

PROM

TDI

TMS

TCK

TDO

DS026_08_021000

VccVccoVcco

Vcc

Vcco

TDI CLK

TMS CE

TCK CEO

OE/RESET

TDO

GND

XC18V00

First

PROM

Vcc

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

10 www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

Figure 6: (a ) Master S erial Mode (b) Virtex Select MAP Mode (c) Spartan-X L Express Mode

(dotted lines indicates opt ional connection)

PROGRAM

DIN

CCLK

INIT

DONE

First

PROM

DATA

CEO

CLK

OPTIONAL

Slave FPGAs

with identical

configurations

Vcc

FPGA

(Low Resets the Address Pointer)

VCC VCCO

OPTIONAL

Daisy-chained

FPGAs with

different

configurations

OE/RESET

DOUT

Modes* Vcco

PROGRAM

VIRTEX

Select MAP

BUSY

WRITE

INIT

D[0:7]

CCLK

DONE

CLK

Virtex Select MAP Mode

D[0:7]

OE/RESET

XC18Vxx

Modes***

3.3V

External Osc

CEO

4.7K

VCC

4.7K

VCC

CCO

4.7K V

4.7K

I/O*

M0 M1

CS1

PROGRAM

Spartan-XL,

XC4000

DOUT

DONE

INIT

XC18Vxx

CEO

OE/RESET

Spartan-XL Express Mode

Master Serial Mode

CLK

D[0:7] D[0:7]

CCLK

M0 M1

CS1

PROGRAM

Optional

Daisy-chained

Spartan-XL,

XC4000

DOUT

DONE

INIT

D[0:7]

CCLK

To Additional

Optional

Daisy-chained

Devices

To Additional

Optional

Daisy-chained

Devices

External Osc

I/O*

*CS and WRITE must be pulled down to be used as I/O. One option is shown.

**Virtex, Virtex-E is 300 ohms, all others are 4.7K.

***For Mode pin connections, refer to the appropriate FPGA data sheet.

DS026_05_031000

*For Mode pin connections, refer to the appropriate FPGA data sheet.

**Virtex, Virtex-E is 300 ohms, all others are 4.7K.

Cascaded

PROM

DATA

CLK

OE/RESET

CCO

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 11

Preliminary Product Specification 1-800-255-7778

5V Tolerant I/Os

The I/Os on each re-programmable PROM are f ully 5 V tol-

erant even through the core power supply is 3.3V. This

allows 5V CMOS signals to connect directly to the PROM

inputs without damage. In addition, the 3.3V VCC power

supply can be applied before or after 5V signals are applied

to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,

the core power supply (VCC), and the output power supply

(VCCO) may have power applied in any order. This makes

the PROM devices immune to power supply sequencing

issues.

Reset Activati on

On power up, OE/RESET is held low until the XQ(R)18V 04

is active (1 ms) and able to supply data after receiving a

CCLK p u lse f r o m the FPGA. OE/ R ESET is connected to an

external resistor to pull OE/RESET HIGH releasing the

FPGA INIT and allowing configuration to begin. OE/RESET

is held low until the XQ(R)18V04 voltag e reaches th e oper-

ating voltage range. If the power drops below 2.0V, the

PROM will reset. OE/RESET polarity is NOT programma-

ble.

Standby Mode

The PROM enters a low- power st andby mode whenev er CE

is asser ted High. The output remains in a high-impedance

state regardless of the state of the OE input. JTAG pins

TMS, TDI and TDO can be in a high-impedance state or

High.

Custome r Contro l Pins

The XQ(R)18V04 PROMs have various control bits accessi-

ble by the customer. These can be set after the array has

been programmed using "Skip User Array" in Xilinx JTAG

Programmer Software.

Table 6: Truth Table for PROM Control Inputs

Con t ro l Inpu t s

Inte rnal A ddress

Outputs

OE/RESET CE DATA CEO ICC

High Low If address < TC(1): increment

If a ddres s > TC (1): don’t change Active

High-Z High

Low Active

Reduced

Low Low Held reset High-Z H igh Active

High High Held reset High-Z High Standby

Low High Held reset High-Z High Standby

Notes:

1. TC = Terminal Count = highest address value. TC + 1 = address 0.

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

12 www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

Absolute Maximum Ratings(1,2)

Recommended O perating Conditions

Quality and Reliability Characteristics

Radiation Tolerances for XQR18V04

Symbol Description Value Units

VCC Supply voltage relative to GND –0.5 to + 4.0 V

VIN Input voltage with respect to GND –0.5 to + 5.5 V

VTS Voltage appl ied to High-Z output –0.5 to + 5.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TJJuncti on temperature Ceramic +150 °C

Plastic +125 °C

Notes:

1. Maxim um DC under shoot belo w GND mus t be l imit ed to ei ther 0.5V or 10 mA, whiche v er is easi er to ach ie v e. Duri ng tr ansit ions , the

devi ce pins may undershoot to –2.0V or o vershoot to +7.0V, prov ided thi s over- or undershoot last s less then 10 ns and with the

forcing current being lim ited t o 200 mA.

2. Stresses beyond those l isted under Abs olute Maximum Rati ngs may cause permanent damage to the device. These are str ess

ratings only, and functio nal operation o f the device at these or any other conditions beyond those listed under Ope rating Co nditions

is not imp lied. Exposure to Absolute Maxi m um Ratings condition s for extended pe riods of tim e may affect device rel iability.

Symbol Parameter Min Max Units

VCCINT Internal v oltage supply (TC = –55°C to +125°C) Ceramic 3.0 3.6 V

Internal voltage supply (TJ = –55°C to +125°C) Plastic 3.0 3.6 V

VCCO Suppl y voltage for output drivers for 3.3V operation 3.0 3. 6 V

Suppl y voltage for output drivers for 2.5V operation 2.3 2. 7 V

VIL Low-level input voltage 0 0.8 V

VIH High-level input voltage 2.0 5.5 V

VOOutput voltage 0 VCCO V

Symbol Description Min Max Units

TDR Data retention 10 - Years

NPE Program/erase cycles (Endurance) 2,000 - Cycl es

VESD Electrostatic discharge (ESD) 2,000 - Volts

Symbol Description Min Max Units

TID Total Ionizing Dose - 40 krad(Si)

SEL Single Event Latch-Up

(No Latch-Up observed for LET > 120 MeV-mg/cm2)-0cm

SEU Sta tic Memory Cel l Satu ration Bit C ro ss- Se ction

(No Upset obser ved for LET > 120 MeV-mg/cm 2)-0cm

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 13

Preliminary Product Specification 1-800-255-7778

DC Char ac te ri stics Ove r Op er at ing Con dit ions

Symbol Parameter Test Conditions Min Max Units

VOH High-level output voltage for 3.3V outputs IOH = –4 mA 2.4 - V

High-level output vol tage f or 2.5V outputs IOH = –500 µA 90% V CCO -V

VOL Low-level output voltage for 3.3V outputs IOL = 8 mA - 0.4 V

Low-l evel output voltage for 2.5V outputs IOL = 500 µA-0.4V

ICC Supply current, active mode 25 MHz - 50 mA

ICCS Supply current, standby mode - 20 mA

IILJ JTAG pins TMS, TDI, and TDO VCC = MAX

VIN = GND –100 - µA

IIL Input leakage current VCC = Max

VIN = GND or VCC

–10 10 µA

IIH Input and output High-Z leakage current VCC = Max

VIN = GND or VCC

–10 10 µA

CIN and

COUT

Input and output capacitance VIN = GN D

f = 1.0 MHz -10pF

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

14 www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

.AC Characteristics Over Operating Conditions for XC18V04 .

Symbol Description Min Max Units

TOE OE/RESET to data d elay - 10 ns

TCE CE to data delay - 20 ns

TCAC CL K to data delay - 20 ns

TOH Data hold from CE, OE/RESET, or CLK 0 - ns

TDF CE or OE/RESET to data float delay(2) -25ns

TCYC Clock periods 50 - ns

TLC CLK Low time(3) 10 - ns

THC CLK High time(3) 10 - ns

TSCE CE setup time to CLK (to guarantee proper counting)(3) 25 - ms

THCE CE High time (to guarantee proper counting) 2 - µs

THOE OE/RESET hold time (guarantees counters are reset) 25 - ns

Notes:

1. A C test load = 50 pF.

2. Float delays are measure d with 5 pF AC loads. Tr ansiti on is mea sured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measur ed wit h VIL = 0.0V and VIH = 3.0V.

5. If THCE High < 2 µs, TCE = 2 µs.

OE/RESET

CLK

DATA TCE

TOE

TLC

TSCE THCE

THOE

TCAC TOH TDF

TOH

THC

DS026_06_012000

TCYC

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 15

Preliminary Product Specification 1-800-255-7778

AC Characteristics Over Operating Conditions When Cascading for XC18V04

Symbol Description Min Max Units

TCDF CLK to d ata float delay(2,3) -25 ns

TOCK CLK to CEO delay(3) -20 ns

TOCE CE to CEO delay(3) -20 ns

TOOE OE/RESET to C EO delay(3) -20 ns

Notes:

1. A C test load = 50 pF.

2. Float delays are measure d with 5 pF AC loads. Transition is measured at ±200 mV from stea dy

state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measur ed wit h VIL = 0.0V and VIH = 3.0V.

CLK

DATA

CEO

First Bit

Last Bit

TCDF

DS026_07_020300

OE/RESET

TOCK TOOE

TOCE

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

16 www.xilinx.com DS082 (v1.2 ) November 5, 2001

1-800-255-7778 Preliminary Product Specification

Ordering Information

XQ18V04 CC44 V

Grade (Manufactur ing Flow /

Temperature Range)

De vi ce Number

Package Type

Device Ordering Options

Device Ty p e Package Grade

XQ18V0 4 CC44 44-pi n Ceramic Chip Carrie r Package MMilit ary Ceramic TC = –55°C to +125°C

XQR18V04(1) VQ44 44-pi n Plastic Thin Quad Flat Package NMilitary Plastic TJ = –55°C to +1 2 5 °C

VQPro-Plus TC = –55°C to +125°C

Notes:

1. Radiation Hardened.

5962 - 01525 Q Y A

Lead Finish

Generic S tand ard

Microcircuit Drawing (SMD)

Radiation Hardened(1)

Package Type

QML Certified M IL-PRF-3 8535

SMD Ordering Options

Device Type QML Package Lead Finish

5962-01525 XQ18V04 - 44-pi n Ceramic Chip Car rie r Package Sold er Dip

5962R01525 XQR18V04 - 44-pin Plastic Thin Quad Flat Package Solder Plate

Notes:

1. Type R desi gnates Radiat ion Hardened.

Valid Ordering Combinations

Mil-Std SMD Rad Har d SMD

XQ18V04CC44M -XQR18V04CC44M -

XQ18V04VQ44N -XQR18V04CC44V

Device Type

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

DS082 (v1.2) November 5, 2001 www.xilinx.com 17

Preliminary Product Specification 1-800-255-7778

Revision History

The following table shows the revision histor y for this document .

Date Version Revision

5/1/01 1.0 First publication of this early access specification

7/23/01 1.1 Preliminary publication supporting Full Mil Temp range and corrected write cycles

11/05/01 1.2 Added Class V to ordering com binations for Rad Hard versio n. Updated for mat.