Semiconductor Components Industries, LLC, 2002
October, 2002 – Rev. 11 1Publication Order Number:
TL431/D
TL431, A, B Series
Programmable
Precision References
The TL431, A, B integrated circuits are three–terminal
programmable shunt regulator diodes. These monolithic IC voltage
references operate as a low temperature coefficient zener which is
programmable from Vref to 36 V with two external resistors. These
devices exhibit a wide operating current range of 1.0 mA to 100 mA
with a typical dynamic impedance of 0.22 . The characteristics of
these references make them excellent replacements for zener diodes in
many applications such as digital voltmeters, power supplies, and op
amp circuitry. The 2.5 V reference makes it convenient to obtain a
stable reference from 5.0 V logic supplies, and since the TL431, A, B
operates as a shunt regulator, it can be used as either a positive or
negative voltage reference.
•Programmable Output Voltage to 36 V
•Voltage Reference Tolerance: ±0.4%, Typ @ 25°C (TL431B)
•Low Dynamic Output Impedance, 0.22 Typical
•Sink Current Capability of 1.0 mA to 100 mA
•Equivalent Full–Range Temperature Coefficient of 50 ppm/°C
Typical
•Temperature Compensated for Operation over Full Rated Operating
Temperature Range
•Low Output Noise Voltage
ORDERING INFORMATION
Device Operating
Temperature Range Package
TL431CLP, ACLP, BCLP TO–92
TL431CP, ACP, BCP
T=0°to +70°C
Plastic
TL431CDM, ACDM, BCDM TA = 0° to +70°CMicro8
TL431CD, ACD, BCD SOP–8
TL431ILP, AILP, BILP TO–92
TL431IP, AIP, BIP
T40°to +85°C
Plastic
TL431IDM, AIDM, BIDM TA = –40° to +85°CMicro8
TL431ID, AID, BID SOP–8
(Top
View)
3
1Reference
N/C
N/C
N/C
2
4
8
7
6
5N/C
Anode
N/C
Cathode
Anode Anode
LP SUFFIX
PLASTIC PACKAGE
CASE 29
(TO–92)
P SUFFIX
PLASTIC PACKAGE
CASE 626
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SOP–8)
Pin 1. Reference
2. Anode
3. Cathode
(Top View)
3
1Reference
N/C
2
4
8
7
6
5N/C
Cathode
DM SUFFIX
PLASTIC PACKAGE
CASE 846A
(Micro8)
8
1
81
8
1
123
SOP–8 is an internally modified SO–8 package. Pins 2, 3, 6
and 7 are electrically common to the die attach flag. This
internal lead frame modification increases power dissipation
capability when appropriately mounted on a printed circuit
board. SOP–8 conforms to all external dimensions of the
standard SO–8 package.
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TL431, A, B Series
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2
Representative Block Diagram
1.0 k
Cathode
(K)
2.5 Vref
Anode (A)
Reference
(R)
4.0 k
150
Symbol
10 k
20 pF
800
Cathode (K)
3.28 k
Representative Schematic Diagram
Component values are nominal
Anode (A)
-
+
Anode
(A)
800
Reference
(R)
2.4 k 7.2 k
20 pF
800
Cathode
(K)
Reference
(R)
This device contains 12 active transistors.
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless
otherwise noted.)
Rating Symbol Value Unit
Cathode to Anode Voltage VKA 37 V
Cathode Current Range, Continuous IK–100 to +150 mA
Reference Input Current Range, Continuous Iref –0.05 to +10 mA
Operating Junction Temperature TJ150 °C
Operating Ambient Temperature Range TA°C
TL431I, TL431AI, TL431BI –40 to +85
TL431C, TL431AC, TL431BC 0 to +70
Storage Temperature Range Tstg –65 to +150 °C
Total Power Dissipation @ TA = 25°C PDW
Derate above 25°C Ambient Temperature
D, LP Suffix Plastic Package 0.70
P Suffix Plastic Package 1.10
DM Suffix Plastic Package 0.52
Total Power Dissipation @ TC = 25°C PDW
Derate above 25°C Case Temperature
D, LP Suffix Plastic Package 1.5
P Suffix Plastic Package 3.0
NOTE: ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Condition Symbol Min Max Unit
Cathode to Anode Voltage VKA Vref 36 V
Cathode Current IK1.0 100 mA
THERMAL CHARACTERISTICS
Characteristic Symbol D, LP Suffix
Package P Suffix
Package DM Suffix
Package Unit
Thermal Resistance, Junction–to–Ambient RJA 178 114 240 °C/W
Thermal Resistance, Junction–to–Case RJC 83 41 – °C/W
TL431, A, B Series
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ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
TL431I TL431C
Characteristic Symbol Min Typ Max Min Typ Max Unit
Reference Input Voltage (Figure 1) Vref V
VKA = Vref, IK = 10 mA
TA = 25°C 2.44 2.495 2.55 2.44 2.495 2.55
TA = Tlow to Thigh (Note 1) 2.41 – 2.58 2.423 – 2.567
Reference Input Voltage Deviation Over Vref – 7.0 30 – 3.0 17 mV
Temperature Range (Figure 1, Notes 1, 2)
VKA= Vref, IK = 10 mA
Ratio of Change in Reference Input Voltage V
ref
mV/V
to Change in Cathode to Anode Voltage
V
re
f
V
KA
IK = 10 mA (Figure 2),
V
KA
VKA = 10 V to Vref – –1.4 –2.7 – –1.4 –2.7
VKA = 36 V to 10 V – –1.0 –2.0 – –1.0 –2.0
Reference Input Current (Figure 2) Iref A
IK = 10 mA, R1 = 10 k, R2 = ∞
TA = 25°C – 1.8 4.0 – 1.8 4.0
TA = Tlow to Thigh (Note 1) – – 6.5 – – 5.2
Reference Input Current Deviation Over Iref – 0.8 2.5 – 0.4 1.2 A
Temperature Range (Figure 2, Note 1, 4)
IK = 10 mA, R1 = 10 k, R2 = ∞
Minimum Cathode Current For Regulation Imin – 0.5 1.0 – 0.5 1.0 mA
VKA = Vref (Figure 1)
Off–State Cathode Current (Figure 3) Ioff – 260 1000 – 260 1000 nA
VKA = 36 V, Vref = 0 V
Dynamic Impedance (Figure 1, Note 3) |ZKA| – 0.22 0.5 – 0.22 0.5
VKA = Vref, IK = 1.0 mA to 100 mA
f ≤ 1.0 kHz
NOTES: 1.Tlow = –40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM
=0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM
2.The deviation parameter Vref is defined as the difference between the maximum and minimum values obtained over the full operating ambient
temperature range that applies.
DVref = Vref max
-Vref min
TA = T2 - T1
T2
Ambient Temperature
T1
Vref min
Vref max
The average temperature coefficient of the reference input voltage, Vref is defined as:
Vref ppm
CVref
Vref @25CX10
6
TA
Vref x10
6
TA(Vref @25C)
Vref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example : Vref 8.0 mV and slope is positive,
Vref @25C2.495 V,TA70CVref 0.008 x 106
70 (2.495) 45.8 ppmC
3.The dynamic impedance ZKA is defined as |ZKA|
VKA
IK
When the device is programmed with two external resistors, R1 and R2, (refer to Figure 2) the total dynamic impedance of the circuit is defined as:
|ZKA||ZKA|1R1
R2
TL431, A, B Series
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ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
TL431AI TL431AC TL431BI
Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Reference Input Voltage (Figure 1) Vref V
VKA = Vref, IK = 10 mA
TA = 25°C 2.47 2.495 2.52 2.47 2.495 2.52 2.483 2.495 2.507
TA = Tlow to Thigh 2.44 – 2.55 2.453 – 2.537 2.475 2.495 2.515
Reference Input Voltage Deviation Over Vref – 7.0 30 – 3.0 17 – 3.0 17 mV
Temperature Range (Figure 1, Notes 1, 2)
VKA= Vref, IK = 10 mA
Ratio of Change in Reference Input Voltage V
ref
mV/V
to Change in Cathode to Anode Voltage
V
re
f
V
KA
IK = 10 mA (Figure 2),
V
KA
VKA = 10 V to Vref – –1.4 –2.7 – –1.4 –2.7 – –1.4 –2.7
VKA = 36 V to 10 V – –1.0 –2.0 – –1.0 –2.0 – –1.0 –2.0
Reference Input Current (Figure 2) Iref A
IK = 10 mA, R1 = 10 k, R2 = ∞
TA = 25°C – 1.8 4.0 – 1.8 4.0 – 1.1 2.0
TA = Tlow to Thigh (Note 1) – – 6.5 – – 5.2 – – 4.0
Reference Input Current Deviation Over Iref – 0.8 2.5 – 0.4 1.2 – 0.8 2.5 A
Temperature Range (Figure 2, Note 1)
IK = 10 mA, R1 = 10 k, R2 = ∞
Minimum Cathode Current For Regulation Imin – 0.5 1.0 – 0.5 1.0 – 0.5 1.0 mA
VKA = Vref (Figure 1)
Off–State Cathode Current (Figure 3) Ioff – 260 1000 – 260 1000 – 230 500 nA
VKA = 36 V, Vref = 0 V
Dynamic Impedance (Figure 1, Note 3) |ZKA| – 0.22 0.5 – 0.22 0.5 – 0.14 0.3
VKA = Vref, IK = 1.0 mA to 100 mA
f ≤ 1.0 kHz
NOTES: 1.Tlow = –40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM
=0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM
2.The deviation parameter Vref is defined as the difference between the maximum and minimum values obtained over the full operating ambient
temperature range that applies.
Vref = Vref max
-Vref min
TA = T2 - T1
T2
Ambient Temperature
T1
Vref min
Vref max
The average temperature coefficient of the reference input voltage, Vref is defined as:
Vref ppm
CVref
Vref @25CX10
6
TA
Vref x10
6
TA(Vref @25C)
Vref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example : Vref 8.0 mV and slope is positive,
Vref @25C2.495 V,TA70CVref 0.008 x 106
70 (2.495) 45.8 ppmC
3.The dynamic impedance ZKA is defined as |ZKA|
VKA
IK
When the device is programmed with two external resistors, R1 and R2, (refer to Figure 2) the total dynamic impedance of the circuit is defined as:
|ZKA||ZKA|1R1
R2
TL431, A, B Series
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IK
Vref
VKA
Input
Figure 1. Test Circuit for VKA = Vref
Input
IK
R2
Iref
Vref
VKA
R1
Figure 2. Test Circuit for VKA > Vref
VKA Vref1 R1
R2IrefR1
Ioff
Input VKA
Figure 3. Test Circuit for Ioff
-1.0
IMin
200
400
VKA, CATHODE VOLTAGE (V)
-200 0
0
1.0 2.0 3.0
800
600
-2.0 -1.0 0
-100 1.0 2.0 3.0
150
50
VKA, CATHODE VOLTAGE (V)
0
-50
Figure 4. Cathode Current versus
Cathode Voltage Figure 5. Cathode Current versus
Cathode Voltage
Input
100
VKA = Vref
TA = 25°C
IK
VKA
IK, CATHODE CURRENT (mA)
IK, CATHODE CURRENT ( A)µ
125
TA, AMBIENT TEMPERATURE (°C)
3.0
10050 75-55
0
2.5
0.5
2.0
1.0
250-25
1.5
2600
2580
2560
2540
2520
2500
2480
2460
VKA = Vref
IK = 10 mA
TA, AMBIENT TEMPERATURE (°C)
VKA
IK
-55
Input
Vref
75 100 125
2440
050
Figure 6. Reference Input Voltage versus
Ambient Temperature Figure 7. Reference Input Current versus
Ambient Temperature
2420
2400 25-25
Input
IK
IK = 10 mA
Iref
10k
VKA
ref
V , REFERENCE INPUT VOLTAGE (mV)
Iref, REFERENCE INPUT CURRENT ( A)µ
Vref Max = 2550 mV
Vref Typ = 2495 mV
Vref Min = 2440 mV
VKA = Vref
TA = 25°C
Input VKA
IK
TL431, A, B Series
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√
NOISE VOLTAGE (nV/ Hz)
-55
f, FREQUENCY (MHz)
100
10
1.0
100 k 10 M1.0 M1.0 k 10 k
0.1 75-25 0 25 50 100 125
TA, AMBIENT TEMPERATURE (°C)
0.200
0.220
0.240
0.300
0.320
0.260
0.280
IK
50 -
1.0 k
+
Output
Gnd Output
Gnd
IK
50 -
1.0k
+
VKA = Vref
IK = 1.0 mA to 100 mA
f ≤ 1.0 kHz
TA = 25°C
IK = 1.0 mA to 100 mA
|ZKA Ω|, DYNAMIC IMPEDANCE ( )
|ZKA Ω|, DYNAMIC IMPEDANCE ( )
f, FREQUENCY (Hz)
40
10 10 k1.0 k100
0
20
100 k
60
f, FREQUENCY (MHz)
100 k
0
10 M1.0 M
-10
10
20
30
60
50
40
1.0 k 10 k
VKA = Vref
IK = 10 mA
TA = 25°C
IK
OutputInput
80
, OPEN LOOP VOLTAGE GAIN (dB)
230
Gnd
Output
IK
9.0 F
8.25k
15k
IK = 10 mA
TA = 25°C
-55
0.01
100
10
1.0
0.1
TA, AMBIENT TEMPERATURE (5C)
75-25 0 25 50 100 125
40
1.0 k
VKA, CATHODE VOLTAGE (V)
30100
-32
-8.0
-16
20
0
-24 R2 Vref
R1 IK
Input VKA
Input Ioff
VKA = 36 V
Vref = 0 V VKA
Vref, REFERENCE INPUT VOLTAGE (mV)∆
Ioff, OFF-STATE CATHODE CURRENT (nA)
IK = 10 mA
TA = 25°C
Figure 8. Change in Reference Input
Voltage versus Cathode Voltage Figure 9. Off–State Cathode Current
versus Ambient Temperature
Figure 10. Dynamic Impedance
versus Frequency Figure 11. Dynamic Impedance
versus Ambient Temperature
Figure 12. Open–Loop Voltage Gain
versus Frequency Figure 13. Spectral Noise Density
VOL
A
TL431, A, B Series
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Input
Output
t, TIME (s)
Pulse
Generator
f = 100 kHz
0 8.04.0 20
0
16
2.0
3.0
12
0
1.0
5.0
Figure 14. Pulse Response Figure 15. Stability Boundary Conditions
50
220 Output
Gnd
Input
Monitor
TA = 25°C
VOLTAGE SWING (V)
TA = 25°C
C
A
B
CL, LOAD CAPACITANCE
120
80
100
60
0
IK, CATHODE CURRENT (mA)
140
1.0 nF 100 F1.0 F 10 F
Stable Stable
40
20
10 nF 100 nF
A
B
D
Unstable
Area
Programmed
VKA(V)
A
B
C
D
Vref
5.0
10
15
Figure 16. Test Circuit For Curve A
of Stability Boundary Conditions Figure 17. Test Circuit For Curves B, C, And D
of Stability Boundary Conditions
V+
IK
150
IK
V+
150
CL
10 k
CL
Figure 18. Shunt Regulator Figure 19. High Current Shunt Regulator
V+ Vout
R1
V+ Vout
R1
R2
R2
Vout 1R1
R2Vref Vout 1R1
R2Vref
TYPICAL APPLICATIONS
TL431, A, B Series
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Figure 20. Output Control for a
Three–Terminal Fixed Regulator Figure 21. Series Pass Regulator
V+ Vout
R1
R2
Out
In
MC7805
V+ Vout
R2
Common
R1
Vout 1R1
R2Vref
Vout min Vref 5.0V
Vout 1R1
R2Vref
Vout min Vref Vbe
Figure 22. Constant Current Source Figure 23. Constant Current Sink
V+
RCL Iout
V+
RS
ISink Vref
RS
Iout Vref
RCL
Isink
Figure 24. TRIAC Crowbar Figure 25. SRC Crowbar
Vout
V+
R2
V+ Vout
R1
R2
R1
Vout(trip) 1R1
R2Vref
Vout(trip) 1R1
R2Vref
TL431, A, B Series
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Figure 26. Voltage Monitor Figure 27. Single–Supply Comparator with
Temperature–Compensated Threshold
Vth = Vref
V+
Vout
Vin
R1 R3
V+ Vout
R2 R4
l
L.E.D. indicator is `on' when V+ is between the
upper and lower limits.
LowerLimit 1R1
R2Vref
UpperLimit 1R3
R4Vref
Vin Vout
< Vref V+
> Vref ≈2.0 V
Figure 28. Linear Ohmmeter Figure 29. Simple 400 mW Phono Amplifier
*Thermalloy
*THM 6024
*Heatsink on
*LP Package
*
Tl = 330 to 8.0
8.0
+
-
LM11
2.0 mA
25 V
25 V
-5.0 V
Vout
Range
V
1.0 M
V
100
k
V
V
1.0 k
RX
5.0 M
1%
500 k
1%
50 k
1%
5.0 k
1%
47 k
Tone
0.05 F
470 F
Volume
1N5305
1.0 F
TI
360 k
330
56 k 10 k 25 k
38 V
+
10 k
10 k
Calibrate
RxVout
V Range
TL431, A, B Series
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Figure 30. High Efficiency Step–Down Switching Converter
150 H @ 2.0 A
1N5823
0.01F
+
470 F
51 k
0.1 F
+2200 F
4.7 k
Vin = 10 V to 20 V TIP115
MPSA20
1.0 k
4.7 k
4.7 k
102.2 k
100 k
Vout = 5.0 V
Iout = 1.0 A
Test Conditions Results
Line Regulation Vin = 10 V to 20 V, Io = 1.0 A 53 mV (1.1%)
Load Regulation Vin = 15 V, Io = 0 A to 1.0 A 25 mV (0.5%)
Output Ripple Vin = 10 V, Io = 1.0 A 50 mVpp P.A.R.D.
Output Ripple Vin = 20 V, Io = 1.0 A 100 mVpp P.A.R.D.
Efficiency Vin = 15 V, Io = 1.0 A 82%
TL431, A, B Series
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APPLICATIONS INFORMATION
The TL431 is a programmable precision reference which
is used in a variety of ways. It serves as a reference voltage
in circuits where a non–standard reference voltage is
needed. Other uses include feedback control for driving an
optocoupler in power supplies, voltage monitor, constant
current source, constant current sink and series pass
regulator. In each of these applications, it is critical to
maintain stability of the device at various operating currents
and load capacitances. In some cases the circuit designer can
estimate the stabilization capacitance from the stability
boundary conditions curve provided in Figure 15. However,
these typical curves only provide stability information at
specific cathode voltages and at a specific load condition.
Additional information is needed to determine the
capacitance needed to optimize phase margin or allow for
process variation.
A simplified model of the TL431 is shown in Figure 31.
When tested for stability boundaries, the load resistance is
150 . The model reference input consists of an input
transistor and a dc emitter resistance connected to the device
anode. A dependent current source, Gm, develops a current
whose amplitude is determined by the difference between
the 1.78 V internal reference voltage source and the input
transistor emitter voltage. A portion of Gm flows through
compensation capacitance, CP2. The voltage across CP2
drives the output dependent current source, Go, which is
connected across the device cathode and anode.
Model component values are:
Vref = 1.78 V
Gm = 0.3 + 2.7 exp (–IC/26 mA)
where IC is the device cathode current and Gm is in mhos
Go = 1.25 (Vcp2) mhos.
Resistor and capacitor typical values are shown on the
model. Process tolerances are ±20% for resistors, ±10% for
capacitors, and ±40% for transconductances.
An examination of the device model reveals the location
of circuit poles and zeroes:
P1 1
2RGM CP1 1
2* 1.0 M * 20 pF 7.96 kHz
P2 1
2RP2CP2 1
2* 10 M * 0.265 pF 60 kHz
Z1 1
2RZ1CP1 1
2*15.9k*20pF500 kHz
In addition, there is an external circuit pole defined by the
load:
PL1
2RLCL
Also, the transfer dc voltage gain of the TL431 is:
GGMRGMGoRL
Example 1:
IC10mA,RL230 ,CL0.Define the transfer gain.
The DC gain is:
GGMRGMGoRL
(2.138)(1.0 M)(1.25 )(230) 615 56 dB
Loop gain G8.25 k
8.25 k 15 k 218 47 dB
The resulting transfer function Bode plot is shown in
Figure 32. The asymptotic plot may be expressed as the
following equation:
Av 615 1jf
500 kHz
1jf
8.0 kHz1jf
60 kHz
The Bode plot shows a unity gain crossover frequency of
approximately 600 kHz. The phase margin, calculated from
the equation, would be 55.9 degrees. This model matches the
Open–Loop Bode Plot of Figure 12. The total loop would
have a unity gain frequency of about 300 kHz with a phase
margin of about 44 degrees.
TL431, A, B Series
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Figure 31. Simplified TL431 Device Model
+
RL
VCC
-
CL
15 k
9.0 F
Input
8.25 k
3
Cathode
500 k
Vref
1.78 V
Rref
16
GM
Anode 2
RGM
1.0 M
Ref
1
Go
1.0 mho
CP2
0.265 pF
RP2
10 M
RZ1
15.9 k
CP1
20 pF
f, FREQUENCY (Hz)
102
101
-20
30
20
60
0
Av, OPEN-LOOP VOLTAGE GAIN (dB)
Figure 32. Example 1 Circuit Open Loop Gain Plot
TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY
40
104
103107
105106
10
-10
50
Example 2.
IC = 7.5 mA, RL = 2.2 k, CL = 0.01 F. Cathode tied to
reference input pin. An examination of the data sheet
stability boundary curve (Figure 15) shows that this value of
load capacitance and cathode current is on the boundary.
Define the transfer gain.
The DC gain is:
GGMRGMGoRL
(2.323)(1.0 M)(1.25 )(2200) 6389 76 dB
The resulting open loop Bode plot is shown in Figure 33.
The asymptotic plot may be expressed as the following
equation:
Av 615 1jf
500 kHz
1jf
8.0 kHz1jf
60 kHz 1jf
7.2 kHz
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about –46 degrees.
Therefore, instability of this circuit is likely.
f, FREQUENCY (Hz)
102
101
-20
40
20
80
0
Av, OPEN-LOOP GAIN (dB)
Figure 33. Example 2 Circuit Open Loop Gain Plot
TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP
60
104
103106
105
With three poles, this system is unstable. The only hope
for s tabilizing this circuit is to add a z ero. H owever , that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage
applications, t he b est solution a ppears to b e to u se a smaller
value of capacitance in low noise applications or a very
large value to provide noise filtering and a dominant pole
rolloff of the system.
TL431, A, B Series
http://onsemi.com
13
PACKAGE DIMENSIONS
LP SUFFIX
PLASTIC PACKAGE
CASE 29–11
(TO–92)
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X–X
C
V
D
N
N
XX
SEATING
PLANE DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.45 5.20
B0.170 0.210 4.32 5.33
C0.125 0.165 3.18 4.19
D0.016 0.021 0.407 0.533
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.015 0.020 0.39 0.50
K0.500 --- 12.70 ---
L0.250 --- 6.35 ---
N0.080 0.105 2.04 2.66
P--- 0.100 --- 2.54
R0.115 --- 2.93 ---
V0.135 --- 3.43 ---
1
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040

TL431, A, B Series
http://onsemi.com
14
PACKAGE DIMENSIONS
DM SUFFIX
PLASTIC PACKAGE
CASE 846A–02
(Micro8)
ISSUE F
S
B
M
0.08 (0.003) A S
TDIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C--- 1.10 --- 0.043
D0.25 0.40 0.010 0.016
G0.65 BSC 0.026 BSC
H0.05 0.15 0.002 0.006
J0.13 0.23 0.005 0.009
K4.75 5.05 0.187 0.199
L0.40 0.70 0.016 0.028
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
–B–
–A–
D
K
G
PIN 1 ID
8 PL
0.038 (0.0015)
–T– SEATING
PLANE
C
HJL
D SUFFIX
PLASTIC PACKAGE
CASE 751–07
(SOP–8)
ISSUE AA
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDAARD IS 751-07
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
–X–
–Y–
G
M
Y
M
0.25 (0.010)
–Z–
Y
M
0.25 (0.010) Z SXS
M

TL431, A, B Series
http://onsemi.com
15
Notes
TL431, A, B Series
http://onsemi.com
16
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