L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK04000 Family Precision Clock Conditioner with Dual PLLs and Integrated VCO Evaluation Board Operating Instructions for rev3 PCBs 2011-08-23 LMK04000BEVAL LMK04000BEVAL-XO LMK04031BEVAL LMK04031BEVAL-XO LMK04002BEVAL LMK04033BEVAL National Semiconductor Corporation Interface Division Precision Timing Devices 1 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Table of Contents TABLE OF CONTENTS ....................................................................................................................... 2 GENERAL DESCRIPTION ................................................................................................................... 4 Evaluation Board Kit Contents ................................................................................................................................... 4 Available Evaluation Boards ...................................................................................................................................... 4 Available LMK04000 Family NSIDs......................................................................................................................... 5 QUICK START................................................................................................................................... 6 Default CodeLoader modes for evaluation boards ..................................................................................................... 7 USING CODELOADER TO PROGRAM THE LMK040XXB ................................................................... 8 1. Start CodeLoader 4 Application ............................................................................................................................. 8 2. Select Device .......................................................................................................................................................... 8 3. Program/Load Device............................................................................................................................................. 9 4. Restoring a Default Mode ...................................................................................................................................... 9 5. Visual Confirmation of Frequency Lock .............................................................................................................. 10 6. Enable Fout........................................................................................................................................................... 10 7. Enable Clock Outputs ........................................................................................................................................... 11 PLL LOOP FILTERS AND LOOP PARAMETERS ................................................................................. 12 PLL 1 Loop Filter ..................................................................................................................................................... 12 122.88 MHz VCXO option ................................................................................................... 12 12.288 MHz Crystal (-XO) option ........................................................................................ 12 PLL2 Loop Filter ...................................................................................................................................................... 13 122.88 MHz VCXO (Reference Input) ................................................................................. 13 12.288 MHz Crystal (-XO) option (Reference Input) .......................................................... 13 EVALUATION BOARD INPUTS/OUTPUTS ......................................................................................... 14 RECOMMENDED TEST EQUIPMENT ................................................................................................. 17 APPENDIX A: CODELOADER USAGE .............................................................................................. 18 Port Setup Tab .......................................................................................................................................................... 18 Clock Outputs Tab.................................................................................................................................................... 19 PLL1 Tab.................................................................................................................................................................. 20 PLL2 Tab.................................................................................................................................................................. 21 Bits/Pins Tab ............................................................................................................................................................ 22 Registers Tab ............................................................................................................................................................ 24 APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ......................................................... 25 PLL1 ......................................................................................................................................................................... 25 Crystek 122.88 MHz VCXO................................................................................................. 25 Vectron 12.288 MHz Crystal ................................................................................................ 26 PLL2 ......................................................................................................................................................................... 27 Clock Outputs ........................................................................................................................................................... 28 Clock Output Measurement Technique ................................................................................ 28 LMK040x0B Phase Noise ........................................................................................................................................ 29 LMK040x1B Phase Noise ........................................................................................................................................ 30 LMK040x2B Phase Noise ........................................................................................................................................ 31 LMK040x3B Phase Noise ........................................................................................................................................ 32 APPENDIX C: SCHEMATICS ............................................................................................................ 33 Power........................................................................................................................................................................ 33 Main ......................................................................................................................................................................... 34 Clock Outputs ........................................................................................................................................................... 35 APPENDIX D: BOARD LAYERS STACKUP ....................................................................................... 36 APPENDIX E: BILL OF MATERIALS ................................................................................................ 37 Common Bill of Materials for Evaluation Boards .................................................................................................... 37 2 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bill of Material Custom to LMK04000BEVAL ....................................................................................................... 40 Bill of Material Custom to LMK04000BEVAL-XO ................................................................................................ 40 Bill of Material Custom to LMK04031BEVAL ....................................................................................................... 41 Bill of Material Custom to LMK04031BEVAL-XO ................................................................................................ 41 Bill of Material Custom to LMK04002BEVAL ....................................................................................................... 42 Bill of Material Custom to LMK04033BEVAL ....................................................................................................... 42 APPENDIX F: BALUN INFORMATION ............................................................................................... 43 Typical Balun Frequency Response ......................................................................................................................... 43 APPENDIX G: VCXO/CRYSTAL CHANGES...................................................................................... 44 Changing from Crystal Resonator to VCXO ............................................................................................................ 44 Changing from VCXO to Crystal Resonator ............................................................................................................ 47 APPENDIX H: LMK04000 .............................................................................................................. 50 APPENDIX I: PROPERLY CONFIGURING LPT PORT ......................................................................... 53 LPT Driver Loading ................................................................................................................................................. 53 Correct LPT Port/Address ........................................................................................................................................ 53 Correct LPT Mode.................................................................................................................................................... 54 APPENDIX J: TROUBLESHOOTING INFORMATION ........................................................................... 55 1) 2) 3) Confirm Communications ............................................................................................................................. 55 Confirm PLL1 operation/locking .................................................................................................................. 55 Confirm PLL2 operation/locking .................................................................................................................. 56 3 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S General Description The LMK040xx Evaluation Board simplifies evaluation of the LMK040xxB Precision Clock Conditioner with Dual PLLs and Integrated VCO. Configuring and controlling the board is accomplished using National Semiconductor's CodeLoader software, which can be downloaded from: http://www.national.com/timing/software/. The CodeLoader software will run on a Windows 2000 or Windows XP PC. The CodeLoader software is used to program the internal registers of the LMK040xxB device through a MICROWIRETM interface. Evaluation Board Kit Contents The evaluation board kit contains... * An LMK040xx Evaluation board (one from Table 1). * LMK04000 Family quick start guide. o Evaluation board instructions are downloadable from the product folder on National's website, www.national.com/. * CodeLoader uWire cable (LPT --> uWire). Available Evaluation Boards National Semiconductor has released a series of evaluation boards which allow the customer to evaluate the different output types and VCO frequency ranges made available by the LMK04000 Family. Note: It is possible to mount a VCXO on a -XO board or a Crystal on a non -XO board. See Appendix G: VCXO/Crystal changes for more details. Table 1. Available Evaluation boards and configuration Evaluation Board NSID LMK04000BEVAL LMK04000BEVAL-XO LMK04031BEVAL LMK04031BEVAL-XO LMK04002BEVAL LMK04033BEVAL VCXO 122.88 MHz Crystek 122.88 MHz Crystek 122.88 MHz Crystek 122.88 MHz Crystek 4 Crystal (XTAL) Vectron 12.288 MHz crystal Vectron 12.288 MHz crystal - L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Available LMK04000 Family NSIDs Please refer to the datasheet for the most up to date list of available devices in the LMK04000 Family. Table 2. LMK040xxB Clock Output Configuration Part Number CLKout0 CLKout1 CLKout2 CLKout3 CLKout4 LVCMOS LVCMOS (x2) (x2) LVCMOS LVCMOS LMK04001BISQ (x2) (x2) LVCMOS LVCMOS LMK04002BISQ (x2) (x2) LVPECL/ LVPECL/ LMK04010BISQ 2VPECL 2VPECL LVPECL/ LVPECL/ LMK04011BISQ 2VPECL 2VPECL LVPECL/ LVCMOS LMK04031BISQ LVDS 2VPECL (x2) LVPECL/ LVCMOS LMK04033BISQ LVDS 2VPECL (x2) Note: LVPECL/2VPECL is software programmable. LMK04000BISQ LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL 5 LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVPECL/ 2VPECL LVDS LVDS VCO Frequency 1185 to 1296 MHz 1430 to 1570 MHz 1566 to 1724 MHz 1185 to 1296 MHz 1430 to 1570 MHz 1430 to 1570 MHz 1840 to 2160 MHz L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Quick Start Full evaluation board instructions with data are downloadable from the product folder of the device at National Semiconductor's website, www.national.com/. 1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector. 2. Connect a reference clock from a signal generator or other source. Exact frequency depends on programming. Default modes use a 122.88 MHz reference. 3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A USB communication option is available, search at www.national.com/ for: USB2UWIRE-IFACE. 4. Program the device with CodeLoader. Ctrl-L must be pressed at least once to load all registers once after CodeLoader is started or after restoring a Mode. CodeLoader is available for download at www.national.com/timing/software/. 5. Measurements may be made at any clock output or Fout if enabled by programming. Figure 1 - Quick Start Diagram 6 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Default CodeLoader modes for evaluation boards CodeLoader saves the state of the device when exiting the software. To ensure a common starting point, the following modes listed in Table 3 may be restored by clicking "Mode" AE <Default Mode for evaluation board>. After restoring a mode, be sure to press Ctrl-L to program the device. The default modes also disable all outputs, so be sure to enable an output to make measurements. Table 3 - Default Evaluation Board Modes Evaluation Board NSID LMK04000BEVAL LMK04000BEVAL-XO LMK04031BEVAL LMK04031BEVAL-XO LMK04002BEVAL LMK04033BEVAL Default Mode 122.88 MHz VCXO Default 12.288 MHz Crystal Default, or 12.288 MHz Crystal with Doubler Default 122.88 MHz VCXO Default 12.288 MHz Crystal Default, or 12.288 MHz Crystal with Doubler Default 122.88 MHz VCXO Default 122.88 MHz VCXO Default The next section outlines step-by-step procedures for using an LMK04031B evaluation board. The process is the same for other evaluation boards except the part number is different. 7 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Using CodeLoader to Program the LMK040xxB The purpose of this section is to walk the user through using CodeLoader to make some measurements with the LMK040xxB device. For more information on CodeLoader refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at http://www.national.com/timing/software/. Before proceeding, be sure to follow the Quick Start section above to ensure proper connections. 1. Start CodeLoader 4 Application Click "Start" AE "Programs" AE "CodeLoader 4" AE "CodeLoader 4" The CodeLoader 4 program is installed by default to the CodeLoader 4 application group. 2. Select Device Click "Select Device" AE "Clock Conditioners" AE "LMK04031B" Once started CodeLoader 4 will load the last used device. To load a new device click "Select Device" from the menu bar, then select the subgroup and finally device to load. For this example, the LMK04031B is chosen. Selecting the device does cause the device to be programmed. Figure 2 - Selecting the LMK04031B 8 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 3. Program/Load Device Press "Ctrl - L" Assuming the Port Settings are correct, it is now possible to click "Keyboard Controls" AE "Load Device" from the menu to program the device to the current state of the newly loaded LMK04031B file. Ctrl-L is the accelerator assigned to the Load Device option and is very convenient. Figure 3 - Loading the Device Once the device has been loaded, by default CodeLoader will automatically program changed registers, so it is not necessary to load the device again completely. It is possible to disable this functionality by ensuring there is no checkmark by the "Mode" AE "AutoReload with Changes." Since a default mode will be restored in the next step, this step isn't really needed but included to emphasize the importance of pressing "Ctrl-L" to load the device at least once after starting CodeLoader, restoring a mode, or restoring a saved setup using the File menu. See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at http://www.national.com/timing/software/ for more information on port setup. Appendix J: Troubleshooting Information contains information on troubleshooting communications. 4. Restoring a Default Mode Click "Mode" AE "122.88 MHz VCXO Default"; then Press "Ctrl - L" Figure 4 - Setting the 122.88 MHz VCXO Default mode For the purposes of this walkthrough a default mode will be loaded to ensure a common starting point. This is important because when CodeLoader is closed, it remembers the last settings used for a particular device. By loading the default mode a common starting point is ensured. Loading a mode does not automatically program the device so it is necessary to press "Ctrl - L" again to program the device. 9 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 5. Visual Confirmation of Frequency Lock After a device is selected and a default mode restored and loaded, the visual display on the board should indicate a clock present at CLKin0 (LED D3 off) and that the PLL is locked (LED D1 on). D1 will be on because the mode default sets PLL_MUX = PLL1/2 DLD Active High. Red LED off LED D3 on if no signal detected on CLKin0 port. Green LED on LED D1 on if locked when PLL_MUX = PLL1/2 DLD Active High. (mode default) Figure 5 - Visual indicators of proper operation of evaluation board 6. Enable Fout To measure the phase noise of the VCO, 1. Go to the Bits/Pins tab and enable the "EN_Fout" bit. 2. Connect the Fout SMA on the left hand side of the board to a spectrum analyzer or signal source analyzer. See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the VCO. 10 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 7. Enable Clock Outputs To measure phase noise at the clock outputs, 1. Click on the "Clock Outputs" tab, 2. Enable an output, 3. Then set the a. CLKout MUX mode, b. divide value, and c. delay value. Figure 6 - Setting Divide, Delay, CLKout_MUX, Enabled for CLKout1 on "Clock Outputs" tab. 4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer. a. For LVDS, a balun is recommended such as the ADT2-1T. b. For LVPECL, i. A balun can be used, or ii. One side of the LVPECL signal can be terminated with a 50 ohm load and the other side can be run to the test equipment single ended. c. For LVCMOS, i. Only one side of the LVCMOS signal can be turned on by setting the CLKout_#a / CLKout_#b states in the CLKout CMOS Options on the Bits/Pins tab. ii. One side of the LVCMOS signal can be terminated with a 50 ohm load and the other side can be run to the test equipment single ended. Figure 7 - Setting iii. A balun may be used. Ensure CLKout_#a and LVCMOS modes. CLKout_#b states are complementary, for example: Non-inverted and Inverted. 5. The phase noise may be measured with a spectrum analyzer or signal source analyzer. See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock outputs. National's Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies. See: http://www.national.com/timing/software/. 11 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL Loop Filters and Loop Parameters In jitter cleaning applications that use a cascaded PLL architecture, the first PLL's purpose is to substitute the phase noise of a low noise oscillator (VCXO or crystal resonator) for the phase noise of a "dirty" reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a frequency reference rather than a phase reference. The loop filters on the LMK040xx evaluation board are setup using the approach above. The loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board. The following tables contain the parameters for PLL1 and PLL2 for each oscillator option. National's Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See: http://www.national.com/timing/software/. PLL 1 Loop Filter Table 4. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO and 12.288 MHz Vectron Crystal 122.88 MHz VCXO option Phase Margin 50 K (Charge Pump) 100 uA Loop Bandwidth 12 Hz Phase Detector Freq 1.024 MHz VCO Gain 2.5 kHz/Volt Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2) Loop Filter Components C1 = 100 nF C2 = 680 nF R2 = 39 k 12.288 MHz Crystal (-XO) option Phase Margin 60 K (Charge Pump) 100 uA Loop Bandwidth 8 Hz Phase Detector Freq VCO Gain 1.024 MHz 1.5 kHz/Volt Reference Clock Frequency 122.88 MHz Output Frequency 12.288 MHz (To PLL 2) Loop Filter Components C1 = 330 nF C2 = 10 uF R2 = 3.9 k Note: PLL Loop Bandwidth is a function of K, Kvco, N as well as loop components. Changing K and N will change the loop bandwidth. 12 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL2 Loop Filter 122.88 MHz VCXO (Reference Input) LMK040x0B C1 C2 C3 C4 R2 R3 R4 Charge Pump Current, K Phase Detector Frequency Frequency Kvco N Phase Margin Loop Bandwidth 1228.8 8 20 85.5 366 LMK040x1B LMK040x2B Open 12 0 0.01 1.8 0.6 0.2 1474.56 9 24 85.5 343 LMK040x3B Units nF nF nF k k k 3.2 mA 61.44 MHz 1720.32 13 28 85.0 424 1966.08 19 32 84.0 542 MHz MHz/V LMK040x3B Units degrees kHz 12.288 MHz Crystal (-XO) option (Reference Input) LMK040x0B LMK040x1B LMK040x2B Open 6.8 0 0.01 2.7 0.6 0.2 C1 C2 nF C3 nF C4 nF R2 k R3 k R4 k Charge Pump 3.2 mA Current, K Phase Detector 12.288 MHz Frequency Frequency 1228.8 1474.56 1720.32 1966.08 MHz Kvco 8 9 13 19 MHz/V N 100 120 140 160 Phase Margin 62 63 60 56 degrees Loop Bandwidth 98 93 112 136 kHz Note: PLL Loop Bandwidth is a function of K, Kvco, N as well as loop components. Changing K and N will change the loop bandwidth. 13 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Evaluation Board Inputs/Outputs The following table contains descriptions of the various inputs and outputs for the evaluation board. Table 5. LMK040xx Evaluation Board I/O Connector Name Input/Output Description Populated connectors. Differential clock output pairs. See Table 2 for format of the output depending on part number. If an LVCMOS output, each output can be independently configured (noninverted, inverted, tri-state, and LOW). CLKout0 / CLKout0*, CLKout1 / CLKout1*, CLKout2 / CLKout2*, CLKout3 / CLKout3*, CLKout4 / CLKout4* Output Fout Output Vcc On the evaluation board, all clock outputs are AC-coupled to allow safe testing with RF test equipment. * All LVPECL/2VPECL clock outputs are terminated to GND with a 120 ohm resistor, one on each output pin of the pair. CLKout4 is configured with an on board balun. Part number is Mini-circuits' ADT2-1T. According to the ADT2-1T datasheet the 3 dB frequency range is 0.4 to 450 MHz. See Appendix F: Balun Information for more detail. Populated connector. Input When enabled, buffered VCO output. AC-coupled. The default configuration on the board contains a 3-dB attenuator on the Fout signal. Populated connector. DC power supply for the PCB. Removing R1, R2, or R3 allow for splitting the power to various devices on the board. For example, the VCXO is powered from the VccAUXPlane connected via R3. Note: The LMK04000 Family contains internal voltage regulators for the VCO, PLL and related circuitry. The clock outputs do not have an internal regulator. A clean power supply is required for best performance. Unpopulated connector. VccLDO Input Vcc input for LDOs on bottom of PCB. Refer to schematics for more information. 14 L M K 0 4 0 X X - R E V 3 Connector Name E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Input/Output Description Populated connectors. Reference clock inputs for PLL1. The default board configuration is setup for a single-ended reference source at CLKin0* (CLKin0 pin is AC-coupled to ground). The mode of the clock input buffer is programmable in CodeLoader on the Bits/Pins tab, and may be either bipolar junction mode or MOS mode. CLKin0/CLKin0*, CLKin1/CLKin1* Input The input level for the various modes is as in the datasheet: AC Coupled Input Clock Voltage Levels Input Mode Min Max Units Differential Bipolar 0.25 2.0 Vpp Differential MOS 0.25 2.0 Vpp Single Ended Bipolar 0.5 3.1 Vpp Single Ended MOS 0.5 3.1 Vpp If a DC-coupled clock is used to drive either of the inputs, the high voltage level must be at least 2 volts and the low voltage no greater than 0.4 volts. By default CLKin0 is the active input in either of the autoswitching modes (CLKin0 non-revertive, CLKin0 revertive). When loss of CLKin0 is detected, the device automatically switches to CLKin1 if an active reference clock is attached. See datasheet for further explanation. Unpopulated connectors. LOS0, LOS1 OSCin/OSCin* Output Input Loss-of-Signal indicator (when LOS_TYPE = Active CMOS, default) for CLKin0/0* and CLKin1/1*. The LEDs D5 and D3 are light red when no signal is detected according to the datasheet specification for LOS pins. Bits/Pins, LOS_TYPE = Active CMOS for default operation. Populated connectors. By altering the PCB an external VCXO may be attached to the OSCin/OSCin* SMA connectors. Either a differential or single-ended device may be used. If a single-end device is used, OSCin* should be tied to GND through a capacitor that matches the AC-coupling capacitor value used for the OSCin pin. See datasheet for OSCin port signal specifications. 15 L M K 0 4 0 X X - R E V 3 Connector Name Vtune1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Input/Output Description Unpopulated connector. Output Tuning voltage output from the loop filter for PLL1. If an external VCXO is used, this tuning voltage should be connected to the voltage control pin of the external VCXO. Note: Resistor R38 must be populated with a zero ohm resistor to control an off-board VCXO. Populated connector. uWire Input/Output 10-pin header programming interface for the board. Of Most important are the CLKuWire, DATAuWire, and LEuWire programming lines from this header. Each of these signals, GEO, and SYNC* can be monitored through test points on the board. Unpopulated connector. Output The LD pin is attached to a multiplexer inside the device and may be programmed with a variety of internal signals for monitoring internal device functions and troubleshooting. See datasheet for further explanation. LD_TP Output The lock detect signal is accessible through this pin. Test point attached to the LD pin of the device. See LD above for more information. Unpopulated connector. GOE Input LD Access to GOE of device. Unpopulated connector. SYNC* Input Access to SYNC* of device. Unpopulated connector. PTO Output Vcc SMA located close to OSCin SMAs for powering external oscillator boards. 16 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Recommended Test Equipment Power Supply The Power Supply should be a low noise power supply. Phase Noise / Spectrum Analyzer For measuring phase noise an Agilent E5052A Signal Source Analyzer is recommended. An Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the architecture of the E5052A is superior for phase noise measurements. At frequencies less than 100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A's internal local oscillator performance, not the device under test. 17 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix A: CodeLoader Usage Code Loader is used to program the evaluation board with either an LPT port using the included CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from http://store.national.com/. The part number is USB2UWIRE-IFACE. Port Setup Tab Figure 8 - Port Setup tab On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that will be used to program the device on the evaluation board. If parallel port is selected, the user should ensure that the correct port address is entered. The Pin Configuration field is hardware dependent and normally SHOULD NOT be changed by the user. Figure 8 shows the default settings. 18 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs Tab Figure 9 - Clock Outputs tab The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock mode (Bypass/Divided/Delayed/Divided & Delayed), set the clock output delay value (if delay is enabled), and the clock output divider value (2, 4, 6, ..., 510). This tab also allows the user to select the VCO Divider value (2, 3, ..., 8). Note that the total PLL2 N divider value is composed of both the VCO Divider value and the N value shown in the blue box in the image, and is given by: N_TOTAL = VCO Divider * N. Clicking on the blue box that contains R, PDF and N values takes the user to the PLL2 tab where these values may be changed. Clicking on the components in the box containing the Internal Loop Filter values allows the user to change these component values. The Reference Oscillator value field may be changed in either the Clock Outputs tab or the PLL2 tab. Note this value should match the value of the on-board VCXO or Crystal. When using the EN_PLL2_REF2X = 1, then Reference Oscillator field should be twice the VCXO or Crystal frequency. 19 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL1 Tab Figure 10 - PLL1 tab. The PLL1 tab allows the user to change: * External VCXO (or Crystal oscillator) frequency. Note: This value must be entered in both the PLL1 and PLL2 tabs. * PLL1 Phase detector frequency * PLL1 R-counter value * PLL1 N-counter value * CLKin (Reference) oscillator frequency * PLL1 Phase Detector polarity (for external VCXO tuning slope, click on the polarity value) * PLL1 Charge pump gain (left click and right click on the charge pump current value) * PLL1 Charge pump state (click on the charge pump state value) Note that the value entered in the VCO frequency field on the PLL1 tab must match the Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X mode is enabled. 20 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL2 Tab Figure 11 - PLL2 tab. The PLL2 tab allows the user to change: * VCO frequency * PLL2 Phase detector frequency * PLL2 R-counter value * PLL2 N-counter value * The frequency of the external VCXO (or XTAL oscillator). Note: This value must be entered in both the PLL1 and PLL2 tabs. * PLL2 Charge pump gain * PLL2 Charge pump state Any changes made on this tab are reflected in the Clock Outputs tab. Note that the PLL2 Phase Detector polarity is fixed and cannot be changed by the user. Also note that the VCO frequency should conform to the specified frequency range for the device. Note that the value entered in the VCO frequency field on the PLL1 tab must match the Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X mode is enabled. 21 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bits/Pins Tab Figure 12 - Bits/Pins tab. The Bits/Pins tab allows the user to program bits directly. Many of which are not available on other tabs. Refer to the datasheet for more detailed information. The bits available are: * Common Box o RESET - Set the reset bit. This will reset the device. In a normal application it is not necessary to program this bit clear since it is auto-clearing. However in the CodeLoader software, RESET must be clicked again (cleared) to not cause a reset every time R7 is programmed. o POWERDOWN - Place the device in powerdown mode. o EN_Fout - Enable the Fout port. * PLL Box o PLL_MUX - Set the function of the LD pin. o RC_DLD1_Start - Prevent PLL2 from locking until digital lock detect from PLL1 is achieved. o EN_PLL2_XTAL - Enables Crystal mode for PLL2. For use with Crystals as opposed to a VCXO. o EN_PLL2_REF2X - Doubles the reference frequency of PLL2. Note with this is enabled, the PLL_R value is invalid. Program the Reference Oscillator on PLL2 Tab to be twice the VCO frequency on PLL1 tab. This adjustment must be done manually. 22 L M K 0 4 0 X X - R E V 3 * * * * * * E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CLKin Options Box o CLKin_SEL - Sets manual or automatic switching modes for selecting a reference oscillator for PLL1. o LOS_TIMEOUT - The timeout value before a loss of signal on a clock input is registered on the LOS pins. o LOS_TYPE - Set the type of output for the LOS pins. o CLKin0_BUFTYPE & CLKin1_BUFTYPE - Select the input buffer used for the respective clock input. PLL2_LF Box o Set the integrated loop filter values for PLL2 including, PLL2_R3_LF - R3 value PLL2_R4_LF - R4 value PLL2_C3_C4_LF - C3 and C4 value at the same time o It is also possible to set these values by clicking on the loop filter values on the Clock Outputs tab. CLKout Options Box o EN_CLKout_Global - A global enable for clocks, if unchecked no outputs will be observed! o EN_CLKout0 through EN_CLKout4 - Individual clock output enables. These can also be set on the Clock Outputs tab. o The number of options vary depending on the option of the LMK device selected. CLKout#_PECL_LVL - Set the level of an LVPECL output to LVPECL or 2VPECL. The 2VPECL a higher output level than LVPECL. CLKout CMOS Options Box o The presence of this box and the number of options on this tab depends upon the option of the LMK device. CLKout##_STATE - Set the state of the individual LVCMOS output. VCO Control - FC Box o OSCin_FREQ - Must be set to the reference frequency of PLL2 in MHz, which should normally be the VCO frequency of PLL1. NOTE: It is important to enter the correct frequency value in this field, as it is used by the internal state machine of the LMK040xxB to execute its calibration routine for the internal VCO. An incorrect value may result in an unlocked condition for the synthesizer. Entering a reference oscillator frequency on PLL2 tab will automatically update this register with the frequency to the nearest MHz. Program Pins Box o GOE - Set high or low voltage on GOE pin. Checked is high voltage. If GOE is low, then no clock outputs will be observed! o SYNC* - Set high or low voltage on SYNC* pin. Checked is high voltage. If SYNC* is low, then no clock outputs will be observed on divided clock outputs! o TRIGGER - Set high or low voltage on pin 10 of uWire header. 23 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Registers Tab The registers tab shows the value of each register. This is convenient for programming the device to the desired settings, then recording the hex values for programming in your own application. By clicking in the "bit field" it is possible to manually change the value of registers by typing `1' and `0.' 24 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix B: Typical Phase Noise Performance Plots PLL1 The LMK040xxB's two stage jitter cleaning process involves masking the reference noise with a VCXO or Crystal. Therefore the phase noise performance of the VCXO or Crystal of PLL1 is a very important contributor to the final phase noise of the system. Crystek 122.88 MHz VCXO The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow loop bandwidth. This VCXO sets the reference noise to PLL2. Figure 13 shows the open loop typical phase noise performance of the CVHD-950-122.88 Crystek VCXO. Phase Noise (dBc/Hz) VCXO Phase Noise -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 CVHD-950-122.88 10 100 1000 10000 100000 1000000 10000000 1E+08 Offset (Hz) Figure 13 - CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz Table 6 - VCXO Phase Noise at 122.88 MHz (dBc/Hz) Phase Offset Noise 10 Hz -76.6 100 Hz -108.9 1 kHz -137.4 10 kHz -153.3 100 kHz -162.0 1 MHz -165.7 10 MHz -168.1 40 MHz -168.1 Table 7 - VCXO RMS Jitter to high offset of 20 MHz at 122.88 MHz (rms fs) Low Jitter Offset 10 Hz 515.4 100 Hz 60.5 1 kHz 36.2 10 kHz 35.0 100 kHz 34.5 1 MHz 32.9 10 MHz 22.7 25 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Vectron 12.288 MHz Crystal The phase noise of the reference is masked by the phase noise of the crystal by using a narrow loop bandwidth. The crystal sets the reference noise to PLL2. Figure 14 shows the typical open loop phase noise performance of the VXB1-1127-12M288 Vectron Crystal. Phase Noise (dBc/Hz) Crystal Phase Noise -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 VXB1-1127-12M288 100 1000 10000 100000 1000000 10000000 Offset (Hz) Figure 14 - Vectron VXB1-1127-12M288 Crystal Phase Noise at 12.288 MHz Table 8 - VCXO Phase Noise at 12.288 MHz (dBc/Hz) Phase Offset Noise 100 Hz -111.6 1 kHz -143.3 10 kHz -151.6 100 kHz -152.7 1 MHz -152.8 5 MHz -153.3 Table 9 - VCXO RMS Jitter to high offset of 20 MHz at 12.288 MHz (rms fs) Low Jitter Offset 100 Hz 964.1 1 kHz 934.5 10 kHz 932.7 100 kHz 924.0 1 MHz 834.5 26 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL2 The closed loop performance of the system as measured at the VCO output Fout. Fout phase noise performance of the various LMK options is plotted in Figure 15. Table 10 and Table 11 summarize the phase noise and jitter of Fout. LMK040xxB Fout Phase Noise LMK040x0B LMK040x1B LMK040x2B LMK040x3B Phase Noise (dBc/Hz) -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1000 10000 100000 1000000 10000000 100000000 Offset (Hz) Figure 15 - LMK040xxB PLL2 Phase Noise (Fout) Table 10 - LMK040x0B Phase Noise (dBc/Hz) Offset LMK040x0B LMK040x1B LMK040x2B LMK040x3B 10 Hz -58.7 -58.3 -61.3 -61.1 100 Hz -88.0 -88.3 -85.7 -90.4 1 kHz -111.6 -110.2 -108.9 -107.5 10 kHz -118.2 -116.3 -115.7 -113.5 100 kHz -121.1 -119.5 -118.4 -117.0 1 MHz -132.0 -131.1 -128.6 -125.6 10 MHz -157.1 -155.8 -154.0 -152.7 40 MHz -165.9 -164.2 -162.3 -160.8 Table 11 - LMK040x0B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) Low LMK040x0B LMK040x1B LMK040x2B LMK040x3B Offset 10 Hz 580.0 506.6 443.4 356.0 100 Hz 127.2 117.5 124.5 132.8 1 kHz 114.8 111.3 114.9 128.1 10 kHz 111.7 108.0 112.0 125.0 100 kHz 97.3 92.7 99.2 112.2 1 MHz 39.7 36.2 41.6 50.9 10 MHz 6.0 5.9 6.0 5.5 27 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs The LMK04000 Family features LVDS, LVPECL, 2VPECL, and LVCMOS types of outputs. Included below are various phase noise measurements for each output. Device LVDS LVPECL/2VPECL LVCMOS VCO Frequency LMK040x0B X X 1185 to 1296 MHz (LMK04000B) LMK040x1B X X X 1430 to 1570 MHz (LMK04031B) LMK040x2B X X 1566 to 1724 MHz (LMK04002B) LMK040x3B X X X 1840 to 2160 MHz (LMK04033B) Note: The device in parenthesis is the device used for the measurement in these evaluation board instructions. Clock Output Measurement Technique The measurement technique for each output type varies. LVDS - measured with an ADT2-1T balun to test equipment. LVPECL/2VPECL - Measured by terminating complementary output with 50 ohm load, then taking output to test equipment. LVCMOS - Measured by enabling only one side of the LVCMOS output and taking the operating output to test equipment. The following table lists the test conditions used for the phase noise measurements for the VCXO option: Table 12 . LMK040xxB test conditions Parameter PLL1 Reference clock input PLL1 Reference Clock frequency PLL1 Phase detector frequency PLL1 Charge Pump Gain VCXO frequency PLL2 phase detector frequency PLL2 Charge Pump Gain PLL2 REF2X mode Value CLKin0* single-ended input, CLKin0 AC-coupled to GND 122.88 MHz 1024 kHz 100 uA 122.88 MHz 61.44 MHz 3200 uA Disabled 28 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK040x0B Phase Noise Phase Noise (dBc/Hz) LMK040x0B Phase Noise -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1000 10000 100000 1000000 Fout LVPECL 2VPECL LVCMOS LVPECL; div4 2VPECL; div4 LVCMOS; div4 1E+07 1E+08 Offset (Hz) Figure 16 - LMK040x0B Phase Noise The Fout frequency is 1228.8 MHz. The clock out frequency is 614.4 MHz, and the clock out div 4 frequency is 153.6 MHz. Table 13 - LMK040x0B Phase Noise (dBc/Hz) Offset Fout 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -58.7 -88.0 -111.6 -118.2 -121.1 -132.0 -157.1 -165.9 LVPECL 2VPECL LVCMOS -67.1 -95.8 -117.6 -123.8 -127.0 -137.9 -153.8 -154.8 -67.1 -96.8 -117.7 -123.8 -127.0 -137.8 -153.8 -154.8 -66.3 -94.8 -117.9 -124.2 -127.3 -138.1 -152.8 -153.6 LVPECL div4 -79.8 -107.5 -129.5 -134.8 -139.4 -149.5 -157.4 -157.3 2VPECL LVCMOS div4 div4 -81.5 -79.7 -109.1 -106.6 -130.2 -129.4 -135.2 -136.0 -139.3 -139.6 -149.6 -150.0 -158.1 -159.2 -158.0 -159.7 Table 14 - LMK040x0B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) LVPECL 2VPECL LVCMOS Low Fout LVPECL 2VPECL LVCMOS div4 div4 div4 Limit 10 Hz 580.0 474.7 449.2 522.4 493.9 466.5 493.5 100 Hz 127.2 128.3 127.9 127.1 148.9 145.6 139.4 1 kHz 114.8 119.9 120.4 117.9 141.8 138.7 129.9 10 kHz 111.7 116.8 117.3 114.9 139.3 136.2 127.3 100 kHz 97.3 102.9 103.3 101.6 128.8 125.3 116.3 1 MHz 39.7 50.5 50.6 52.4 94.3 89.5 79.5 29 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK040x1B Phase Noise LMK040x1B Phase Noise Fout Phase Noise (dBc/Hz) LVDS LVPECL -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 2VPECL LVCMOS LVDS; div4 LVPECL; div4 2VPECL; div4 LVCMOS; div4 10 100 1000 10000 100000 1000000 1000000 0 Offset (Hz) 1E+08 Figure 17 - LMK040x1B Phase Noise The Fout frequency is 1474.56 MHz. The clock out frequency is 737.28 MHz, and the clock out div 4 frequency is 184.32 MHz. Note that the LVDS performance at 737.28 MHz is degraded because it is outside of the balun's operational bandwidth. Table 15 - LMK040x1B Phase Noise (dBc/Hz) LVDS LVPECL div4 div4 -74.8 -76.7 -106.7 -107.7 -128.3 -128.3 -132.8 -134.0 -137.7 -137.7 -148.5 -148.7 -156.9 -157.1 -157.5 -157.3 2VPECL div4 -73.8 -105.3 -128.1 -134.3 -137.8 -148.7 -157.5 -158.0 LVCMOS div4 -74.6 -106.7 -128.3 -134.7 -137.9 -148.9 -158.3 -158.8 Table 16 - LMK040x1B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) LVDS LVPECL Low Fout LVDS LVPECL 2VPECL LVCMOS div4 div4 Limit 10 Hz 506.6 538.4 425.5 458.5 501.9 532.2 445.6 100 Hz 117.5 178.3 132.4 131.8 123.1 141.0 138.6 1 kHz 111.3 174.2 127.0 126.4 116.2 135.1 133.3 10 kHz 108.0 169.5 123.4 122.8 113.0 132.4 130.7 100 kHz 92.7 147.7 107.2 106.7 98.7 120.7 119.0 1 MHz 36.2 72.9 50.4 50.1 49.1 85.2 83.4 2VPECL div4 591.0 139.1 131.4 128.7 116.8 80.3 LVCMOS div4 544.1 132.5 125.5 122.8 110.8 73.4 Offset Fout LVDS 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -58.3 -88.3 -110.2 -116.3 -119.5 -131.1 -155.8 -164.2 -62.0 -96.4 -115.3 -118.1 -122.0 -133.5 -148.2 -149.5 LVPECL 2VPECL LVCMOS -65.4 -95.9 -115.7 -121.2 -124.7 -136.2 -152.3 -153.5 -66.4 -96.0 -115.8 -121.3 -124.7 -136.2 -152.3 -153.6 30 -63.4 -94.8 -116.2 -122.0 -125.5 -137.0 -151.7 -152.5 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK040x2B Phase Noise LMK040x2B Phase Noise Fout LVPECL Phase Noise (dBc/Hz) 2VPECL -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 LVCMOS LVPECL; div4 2VPECL; div4 LVCMOS; div4 10 100 1000 10000 100000 Offset (Hz) 1000000 1000000 0 1E+08 The Fout frequency is 1720.32 MHz. The clock out frequency is 860.16 MHz, and the clock out div 4 frequency is 215.04 MHz. Table 17 - LMK040x2B Phase Noise (dBc/Hz) Offset Fout 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -61.3 -85.7 -108.9 -115.7 -118.4 -128.6 -154.0 -162.3 LVPECL 2VPECL LVCMOS -66.6 -91.5 -114.3 -120.7 -123.5 -133.4 -151.5 -153.0 -67.3 -90.4 -114.2 -120.7 -123.5 -133.4 -151.5 -153.2 -67.7 -91.9 -114.6 -120.6 -123.5 -133.4 -151.6 -153.2 LVPECL div4 -80.1 -103.3 -126.7 -133.5 -136.7 -146.2 -156.7 -157.0 2VPECL LVCMOS div4 div4 -78.7 -78.9 -103.2 -103.8 -127.2 -126.5 -133.7 -134.1 -136.7 -136.8 -146.3 -146.5 -157.0 -157.7 -157.3 -158.2 Table 18 - LMK040x2B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) LVPECL 2VPECL LVCMOS Low Fout LVPECL 2VPECL LVCMOS div4 div4 div4 Limit 10 Hz 443.4 498.1 477.3 450.5 439.3 473.4 458.5 100 Hz 124.5 143.1 140.8 140.4 141.0 140.7 136.6 1 kHz 114.9 132.7 132.1 132.0 132.3 131.1 126.6 10 kHz 112.0 129.6 129.0 129.0 130.0 128.7 124.2 100 kHz 99.2 115.7 115.2 115.2 119.7 118.3 113.7 1 MHz 41.6 54.9 54.8 54.7 79.2 77.1 71.8 31 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK040x3B Phase Noise Fout Phase Noise (dBc/Hz) LMK040x3B Phase Noise LVDS LVPECL -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 2VPECL LVCMOS LVDS; div4 LVPECL; div4 2VPECL; div4 LVCMOS; div4 10 100 1000 10000 100000 1000000 1E+07 1E+08 Offset (Hz) The Fout frequency is 1966.08 MHz. The clock out frequency is 983.04 MHz, and the clock out div 4 frequency is 245.76 MHz. Note that the LVDS performance at 737.28 MHz is degraded because it is outside of the balun's operational bandwidth. Table 19 - LMK040x3B Phase Noise (dBc/Hz) LVDS LVPECL div4 div4 -76.1 -75.2 -103.5 -103.7 -125.5 -125.8 -130.3 -131.4 -135.2 -135.3 -143.5 -143.6 -156.3 -156.1 -156.8 -156.4 2VPECL div4 -75.9 -104.4 -125.5 -131.5 -135.3 -143.6 -156.3 -156.6 LVCMOS div4 -80.1 -106.3 -125.4 -132.0 -135.3 -143.7 -156.8 -157.3 Table 20 - LMK040x3B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) Low LVDS LVPECL Limit Fout LVDS LVPECL 2VPECL LVCMOS div4 div4 10 Hz 356.0 531.5 367.7 339.0 367.6 471.8 499.6 100 Hz 132.8 210.0 153.3 153.4 137.4 147.1 146.5 1 kHz 128.1 205.5 149.2 149.5 132.6 140.7 140.5 10 kHz 125.0 200.9 145.8 146.1 129.6 138.1 137.9 100 kHz 112.2 181.2 131.6 131.9 117.3 127.2 127.1 1 MHz 50.9 88.9 64.4 64.5 59.5 79.6 80.6 2VPECL div4 464.0 146.2 140.2 137.6 126.7 79.7 LVCMOS div4 338.9 141.5 137.1 134.4 123.5 75.8 Offset Fout LVDS 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -61.1 -90.4 -107.5 -113.5 -117.0 -125.6 -152.7 -160.8 -63.9 -92.1 -112.2 -115.1 -119.1 -127.6 -148.0 -147.2 LVPECL 2VPECL LVCMOS -66.2 -94.6 -112.8 -118.1 -121.8 -130.4 -150.6 -151.9 -67.6 -93.9 -112.8 -118.2 -121.9 -130.4 -150.6 -151.9 32 -67.0 -94.3 -113.6 -119.7 -123.0 -131.5 -150.0 -151.2 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK04000BEVAL schematic. Refer to BOM for differences. Appendix C: Schematics Power Direct Power Vcc VccPLLPlane R1 Vcc SMA VccCLKoutPlane R2 1 2 VccAuxPlane R3 1 2 Open VccPLLPlane 0 ohm J1 Fout [inc LDO] C200 Power Plane for LMK Except Outputs 0 ohm C1 C2 C3 C201 10 uF 1 uF 0.1 uF Open C4 C5 C6 C7 C8 C9 1 uF 0.1 uF 10 nF 1 uF 0.1 uF 10 nF VCO [inc LDO] 0 ohm POWER_SMALL C202 Open Digital C203 CLKin LDO Power Options R200 Open Open LM317 VccLDO Open Vin Vout TAB 4 Vadj 2 1 V_LM317 U201 Open R203 Open 3 R204 Open R201 R202 Open Open R205 Open R207 R206 VccPLLPlane Power Plane for LMK CLKout Outputs VccCLKoutPlane Open Open Open C206 C207 Open Open R208 R209 Open C209 C204 VccCLKoutPlane C11 C12 C13 C205 10 uF 1 uF 0.1 uF Open VccAuxPlane C208 C210 LDO_Out Open C214 Open R211 Open U200 VIN VOUT SD ADJ NC BYP NC DAP GND C14 C15 C16 1 uF 0.1 uF 10 nF V_LM3878-ADJ 5 6 1 Open R210 PDCP1 Open VCXO_IC CLK1 C211 OSCin Open C212 LP3878-ADJ 0.1 uF CLK0 Open Open 4 8 2 7 C10 CLK2 C213 Open C17 0.1 uF PDCP2 Open C215 Open R212 C216 Open Open C218 Open 3 Open C18 C19 C20 1 uF 0.1 uF 10 nF C217 Open CLK3 C219 PLL2 Open R213 Open C220 Open LP3878-ADJ 3.3 V component values: C214(C1) = 4.7 uF R212 (R1) = 2.3 k C218 (C2) = 0.01 uF R213 (R2) = 1 k C216 (C3) = 10 uF R211(R3) = 51 k C215 (C4) = 3.9 nF Power Plane for XO and VCXOs, LDOs, etc. VccAuxPlane R214 Open LP5900SD-3.3 6 C222 Open R216 Open 4 U202 VIN VEN DAP GND 3 LP5900 Component values C222 = 0.47 uF C223 = 0.47 uF R216 = 51 k VOUT NC NC V_LM5900 1 5 2 C223 R215 C21 C22 C23 10 uF 1 uF 0.1 uF Power Take Off for external Oscillator boards VccAuxPlane VccCLKoutPlane PTO Open C221 Open Open Open Vcc Header Open GND CLK4 VccCLKoutPlane VccPLLPlane Vcc VccAuxPlane 1 3 5 7 2 4 6 8 Vcc_TP Open 33 VccCLKoutPlane VccPLLPlane Vcc VccAuxPlane GND Header GND 1 3 5 2 4 6 GND_TP Open Designators greater than and equal to 200 are placed on bottom of PCB L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G LMK04000BEVAL schematic. Refer to BOM for differences. I N S T R U C T I O N S Main CLKout2_N Fout Balun and Impedance Matching VccAuxPlane SMA D6 Red LED CLKout1_N Open CLKout1_P CLKout4_P CLKout4_N Fout Designators greater than and equal to 200 are placed on bottomof PCB D5 CLKout2_P CLKout3_P CLKout3_N R4 270 ohm LOS1 C24 R5 Open VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccPLLPlane 18 ohm C25 37 38 39 40 41 42 43 44 45 270 ohm 46 270 ohm LMK04000B 47 R7 48 R6 LOS Indication U1 100 pF LOS0 Open 1 uF 33 pF 9 C29 10 10 uF C30 0.1 uF CLKuWire 11 12 CLKout1 33 pF Vcc11 C27 C28 CLKout1* 8 Vcc12 VccPLLPlane CLKout2 33 pF 7 CLKout2* 6 C26 Vcc1 Vcc13 5 uWire Voltage Translation Fout CLKout3 4 CLKout3* 3 CLKout4* 2 CLKout4 VccPLLPlane GND Vcc14 1 Bias CLKin1_LOS CLKin0_LOS CLKuWire Vcc10 DATAuWire CPout2 LMK040xxB LEuWire Vcc9 NC Vcc8 Vcc2 0 LDObyp1 OSCin* DAP PAD OSCin LDObyp2 SYNC* GOE CLKin1* LD CLKin1 R8 36 270 ohm VccAuxPlane 35 VTUNE2_TP1 D4 R9 32 VCXO Loop Filter C2pA2 0 ohm R10 C2_A2 Open Open VccPLLPlane C1_A2 29 28 Red LED VTUNE2 VccPLLPlane 31 30 D3 Open 34 33 12 nF R2_A2 Open 1.8 k PLL2 Loop Filters SYNC* 27 26 25 Crystal Loop Filter SYNC*_TP C1_B2 C2_B2 C2pB2 Open 6.8 nF Open R2_B2 Vcc7 2.7 k R13 24 22 CPout1 23 Vcc6 CLKin0* 21 19 18 17 CLKin0 20 Vcc5 Vcc4 GOE_TP GND DATAuWire DLD_BYP 16 CLKout0* 15 13 R12 R11 CLKout0 14 Vcc3 15 k 27 k VccCLKoutPlane 51 ohm C31 VccPLLPlane VccPLLPlane C32 LD_TP R14 0.1 uF Open VccPLLPlane OSCin* Open 0.47 uF R15 OSCin Tuneable Crystal Open C33 R16 100 ohm 15 k 27 k R17 CLKout0_N C34 C35 R19 R18 R20 2.0 pF Open U4 0.1 uF 4 R21 CLKout0_P Open 4.7 k 2.2 nF 1 LEuWire Y200 Open Open 15 k 27 k 10 k Open Open VccAuxPlane R30 2.2 nF RF GND RF* NC Vs Vtune 3 2 Vtune_VCXO 1 CVHD-950-122.88 C3_AB1 R26 0 ohm Open C38 C39 100 pF 1 uF 4.7 k R31 Open R24 0.1 uF 1 nF C40 LD C36 C37 2 R29 R28 SMV-1249-074 R27 6 Vtune_XTAL R23 3 Y1 5 Open R25 Open R22 D9 C41 R32 0 ohm 2.0 pF OSCin Open 10 8 6 4 2 C42 uWire VccAuxPlane 0.1 uF R33 C43 Open R34 Open OSCin VCXO Open HEADER_2X5(POLARIZED) R35 SYNC* Open 9 7 5 3 1 2.2 k SYNC* R36 PLL1 Loop Filters D8 180 ohm 3.3 V zener C44 Open SYNC* VoltageTranslation R39 VccAuxPlane C45 C46 0.1 uF Open Vtune_VCXO VCXO Loop Filter Vtune1 C1_A1 C2_A1 C2pA1 100 nF 680 nF Open 0 ohm Vtune1 R37 R2_A1 Open 39 k R38 Vtune1 Open Open R40 2.2 k R41 180 ohm GOE Voltage Translation GOE Open D7 VccAuxPlane LD C47 1 uF LD Open R42 R43 Open Open LDD2 Indicator D1 VccAuxPlane R44 Open R46 Open Open C1_B1 C2_B1 C2pB1 330 nF Open 10 uF Green LED R2_B1 3.9 k 0 ohm C49 Vtune_XTAL Crystal Loop Filter 3.3 V zener C48 R45 Analog LD 270 ohm C50 0.1 uF Open C51 0 ohm R47 CLKin1* 0 ohm R51 CLKin0 Open R50 R49 Open Open C52 SMA R48 Open Open 100 ohm C53 Open 4 C54 R52 R54 R53 Open Open Open R55 Open R58 Open Open 5 VccAuxPlane 6 R59 U3 RF RF* Vs GND NC Vtune 3 VccAuxPlane 2 1 C55 Open R56 Open R57 Open Open Open C56 CLKin0* SMA C58 0 ohm C59 R61 R65 R62 Open 0 ohm 51 ohm 0.1 uF CLKin0 Impedance Matching and Attenuation C61 0.1 uF Open R60 R63 Open CLKin1 Crystal 34 Open C57 C60 0 ohm Open CLKin1 R64 C62 Open 0 ohm CLKin1 Impedance Matching and Attenuation CLKin1 XO SMA L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G LMK04000BEVAL schematic. Refer to BOM for differences. I N S T R U C T I O N S Clock Outputs CLKout0 VccCLKoutPlane R73 CLKout0_P VccCLKoutPlane R66 R67 R68 R69 Open Open 0 ohm Open C63 R71 CLKout0_1_P CLKout0_2_P CLKout0 SMA 0 ohm R74 Output option 0 - LVPECL/2VPECL Output option 1 - LVPECL/2VPECL Output option 3 - LVDS CLKout4 Output option 0 - LVPECL/2VPECL Output option 1 - LVPECL/2VPECL Output option 3 - LVDS 0 ohm 120 ohm Open 120 ohm R80 R78 R81 Open 120 ohm 6 SD 5 R84 Open CLKout1 R90 Open Open CLKout1_1_P 0.1 uF PD 2 3 ADT2-1T CLKout4_1_N 0 ohm R85 R79 C66 CLKout4_2_N Open R86 0.1 uF CLKout4* Open R87 Open CLKout4_3_N SMA R88 Open VccCLKoutPlane SMA Open R94 R95 CLKout1_1_N 0 ohm C68 0.1 uF CLKout1_2_N R97 R98 Open Open SMA VccCLKoutPlane CLKout3 CLKout2 Output option 0 - LVCMOS Output option 1 - LVPECL/2VPECL Output option 3 - LVCMOS VccCLKoutPlane R103 R99 R100 Open Open CLKout2_2_P 0 ohm 0.1 uF Open R107 Open 120 ohm R110 R115 Open VccCLKoutPlane 0 ohm Open CLKout2_2_N R112 R114 CLKout3_N R116 Open SMA Open 120 ohm SMA CLKout3 CLKout3_2_P R108 0.1 uF C72 CLKout3_1_N 0 ohm 0.1 uF CLKout3* Open Load Simulation 0.1 uF R102 Open R111 CLKout2* Open Emitter Resistors 0 ohm R106 C71 Load Simulation Emitter Resistors CLKout2_1_N R101 C70 CLKout3_1_P CLKout3_P Vcc Bias R113 DC Block Open R104 SMA DC Block Vcc Bias R109 Output option 0 - LVPECL/2VPECL Output option 1 - LVPECL/2VPECL Output option 3 - LVPECL/2VPECL VccCLKoutPlane CLKout2 C69 CLKout2_1_P CLKout2_P R105 CLKout1* Open Load Simulation Emitter Resistors R96 Vcc Bias DC Block Open CLKout2_N NC S R93 Open CLKout1_N Open Open CLKout1 CLKout1_2_P 0 ohm R92 R89 C67 R91 P SCT Open 1 Output option 0 - LVCMOS Output option 1 - LVPECL/2VPECL Output option 3 - LVPECL/2VPECL VccCLKoutPlane CLKout1_P CLKout4_N CLKout4_3_P R77 Load Simulation VccCLKoutPlane SMA 4 Vcc Bias Open CLKout0* Emitter Resistors R83 0.1 uF CLKout0_2_N Probe Test Point 0 ohm C65 Load Simulation CLKout0_1_N Vcc Bias R82 Emitter Resistors CLKout0_N DC Block 120 ohm CLKout4 Open Open B1 Vcc Bias R76 R70 C64 CLKout4_2_P DC Block R75 0.1 uF R72 CLKout4_1_P CLKout4_P CLKout3_2_N R117 R118 Open Open SMA VccCLKoutPlane Notes: 1. A stub will be placed near all CLKout SMA connectors to test the effects of capacitive loading. 2. CLKout0 and CLKout4 are both the same type and never CMOS. Designators greater than and equal to 200 are placed on bottomof PCB 3. CLKout1, CLKout2 and CLKout3 can be made LVPECL or CMOS via metal mask. 35 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix D: Board Layers Stackup Layers of the 6 layer evaluation board include: Blue is dielectrics * RO4003 (Er = 3.38) CONTROLLED THICKNESS of 16 mils thick GND plane [LMK04000.GP1] FR4 (Er = ~4.6) CONTROLLED THICKNESS: 2.5 mils VccCLK plane [LMK04000.GP2] FR4 Top to bottom layer order: LMK04000.GTL (1) top copper LMK04000.GP1 (2) gnd LMK04000.GP2 (3) vcc LMK04000.GP3 (4) gnd LMK04000.G1 (5) vcc LMK04000.GBL (6) bottom copper Middle Ground Plane FR4 Vcc mixed plane [LMK04000.G1] FR4 Bottom Copper - Thermal relief [LMK04000.GBL] 36 62 mils thick total * * * * * * * * * * Top Copper. 1oz thick [LMK04000.GTL] Top layer for high priority high frequency signals o 1 oz CU RO4003 Dielectric, 16 mils Ground plane FR4, 2.5 mils thick. Power plane #1 - VccCLK FR4, xx mils middle ground plane FR4, xx mils VccPLL, VccAux FR4, xx mils Bottom layer copper clad for thermal relief L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix E: Bill of Materials Common Bill of Materials for Evaluation Boards (page 1/3) Part Capacitors 2.0 pF 33 pF 100 pF 1 nF 2.2 nF 6.8 nF 10 nF 12 nF Manufacturer Part Number Kemet Kemet Kemet Kemet Kemet Kemet Kemet Panasonic C0603C209C5GAC C0402C330J5GAC C0603C101J5GAC C0603C102J5GAC C0603C222K5RAC C0603C682K1RACTU C0603C103K1RACTU ECH-U01123JX5 2 3 2 1 2 1 4 1 0.1 uF Kemet C0603C104J3RAC 25 100 nF 330 nF 0.47 uF 680 nF 1 uF 10 uF Kemet Kemet Kemet Kemet Kemet Kemet C0603C104J3RAC C0603C334K4RACTU C0603C474K8PACTU C0603C684K8PAC C0603C105K8PAC C0805C106K9PAC 1 1 1 1 10 5 37 Qnt Identifier C33, C41 C26, C27, C28 C24, C38 C37 C35, C40 C2_B2 C6, C9, C16, C20 C2_A2 C3, C5, C8, C10, C13, C15, C17, C19, C23, C30, C34, C36, C45, C48, C59, C60, C63, C65, C66, C67, C68, C69, C70, C71, C72 C1_A1 C1_B1 C32 C2_A1 C2, C4, C7, C12, C14, C18, C22, C25, C39, C47 C1, C2pB1, C11, C21, C29 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Common Bill of Materials for Evaluation Boards (continued, 2/3) Resistors 0 ohm Vishay/Dale CRCW06030000Z0EA 23 18 ohm 51 ohm 100 ohm 120 ohm 180 ohm 270 ohm 1.8 k 2.2 k 2.7 k 3.9 k 4.7 k 10 k 15 k 27 k 39 k Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale CRCW060318R0JNEA CRCW060351R0JNEA CRCW0603100RJNEA CRCW0603120RJNEA CRCW0603180RJNEA CRCW0603270RJNEA CRCW06031K80JNEA CRCW06032K20JNEA CRCW06032K70JNEA CRCW06033K90JNEA CRCW06034K70JNEA CRCW060310K0JNEA CRCW060315K0JNEA CRCW060327K0JNEA CRCW060339K0JNEA 1 2 2 2 2 5 1 2 1 1 2 1 3 3 1 Other POWER_SMALL Weidmuller 1594540000 1 SMA Johnson Components 142-0701-851 14 SMA_FRAME Red LED Green LED 0.875" Standoff ADT2-1T HEADER_2X5(POLARIZED) 3.3 V zener SMV-1249-074 Printed Circuits Corp. Lumex Lumex SPC Technology Minicircuits FCI Electronics Comchip Skyworks PCB SML-LX2832IC-TR SML-LX2832GC-TR SPCS-14 ADT2-1T+ 52601-S10-8 CZRU52C3V3 SMV1249-074LF 1 2 1 4 1 1 2 1 38 C51, C58, C62, R1, R2, R3, R26, R32, R44, R47, R60, R65, R68, R71, R73, R82, R85, R91, R96, R103, R104, R113, R114 R5 R13, R62 R16, R51 R107, R111 R36, R41 R4, R6, R7, R8, R45 R2_A2 R35, R40 R2_B2 R2_B1 R20, R30 R23 R12, R19, R29 R11, R18, R28 R2_A1 J1 CLKin0*, CLKin1, CLKin1*, CLKout0*, CLKout0, CLKout1*, CLKout1, CLKout2*, CLKout2, CLKout3*, CLKout3, CLKout4*, Fout, Vcc F1 D3, D5 D1 S1, S2, S3, S4 B1 uWire D7, D8 D9 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Common Bill of Materials for Evaluation Boards (continued, 3/3) Open Open R 78 Open C 44 Open U 4 Open SMA 12 Open Open Y D 1 3 39 R14, R17, R21, R22, R24, R25, R27, R33, R34, R38, R42, R43, R46, R48, R49, R50, R52, R53, R54, R55, R56, R57, R58, R59, R61, R63, R64, R66, R67, R69, R70, R72, R75, R77, R78, R79, R83, R84, R86, R87, R88, R89, R90, R93, R94, R97, R98, R99, R100, R101, R102, R105, R106, R108, R109, R110, R112, R115, R116, R117, R118, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216 C1_A2, C1_B2, C2pB2, C2pA2, C2pA1, C2_B1, C3_AB1, C43, C44, C46, C49, C50, C52, C53, C54, C55, C56, C57, C61, C64, C200, C201, C202, C203, C204, C205, C206, C207, C208, C209, C210, C211, C212, C213, C214, C215, C216, C217, C218, C219, C220, C221, C222, C223 U3, U200, U201, U202 OSCin*, OSCin, LOS0, LOS1, VccLDO, LD, PTO, GOE, SYNC*, CLKout4, Vtune1, CLKin0 Y200 D2, D4, D6 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bill of Material Custom to LMK04000BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Kemet C0603C104J3RAC 2 C31, C42 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 4 R9, R39 R74, R76, R80, R81 Other LMK04000B CVHD-950-122.88 National Semiconductor Crystek LMK04000B CVHD-950-122.88 1 1 U1 U4 6 1 R10, R15, R31, R37, R92, R95 Y1 Open Open Open Qnt Identifier Bill of Material Custom to LMK04000BEVAL-XO Part Capacitors Manufacturer Part Number Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 4 4 R10, R15, R31, R37 R74, R76, R80, R81 Other LMK04000B 12.288 MHz XTAL National Semiconductor Vectron LMK04000B VXB1-1127-12M288 1 1 U1 Y1 2 4 1 C31, C42 R9, R39, R92, R95 U4 Open Open Open Open 40 Qnt Identifier L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bill of Material Custom to LMK04031BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Qnt Identifier Kemet C0603C104J3RAC 2 C31, C43 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 2 R9, R39 R92, R95 Other LMK04031B CVHD-950-122.88 National Semiconductor Crystek LMK04031B CVHD-950-122.88 1 1 U1 U4 Open Open 8 Open 1 R10, R15, R31, R37, R74, R76, R80, R81 Y1 Bill of Material Custom to LMK04031BEVAL-XO Part Capacitors Manufacturer Part Number Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 4 2 R10, R15, R31, R37 R92, R95 Other LMK04031B 12.288 MHz XTAL National Semiconductor Vectron LMK04031B VXB1-1127-12M288 1 1 U1 Y1 2 6 1 C31, C42 R9, R39, R74, R76, R80, R81 U4 Open Open Open Open 41 Qnt Identifier L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bill of Material Custom to LMK04002BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Kemet C0603C104J3RAC 2 C31, C42 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 4 R9, R39 R74, R76, R80, R81 Other LMK04002B CVHD-950-122.88 National Semiconductor Crystek LMK04002B CVHD-950-122.88 1 1 U1 U4 6 1 R10, R15, R31, R37, R92, R95 Y1 Open Open Open Qnt Identifier Bill of Material Custom to LMK04033BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Qnt Identifier Kemet C0603C104J3RAC 2 C31, C42 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 2 R9, R39 R92, R95 Other LMK04033B CVHD-950-122.88 National Semiconductor Crystek LMK04033B CVHD-950-122.88 1 1 U1 U4 Open Open 8 Open 1 42 R10, R15, R31, R37, R74, R76, R80, R81 Y1 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix F: Balun Information Typical Balun Frequency Response The following figure illustrates the typical frequency response of the Mini-circuit's ADT2-1T balun. Figure 18 - Typical Balun Frequency Response 43 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix G: VCXO/Crystal changes This appendix contains instructions for changing the active on-board oscillator for PLL1. Changing from Crystal Resonator to VCXO If the board has been setup to use the crystal-based oscillator with PLL1, the crystal may be disabled and the VCXO enabled as described on the following pages: Summary 1. Connect power to VCXO 2. Disconnect Crystal RF path and connect VCXO RF path 3. Connect charge pump output from PLL1 to VCXO Loop Filter (A1) and VCXO. 4. Connect charge pump output from PLL2 to VCXO Loop filter (A2). Procedures 1. Connect power to VCXO a. Install a 0 ohm resistor in R26 (near the VCXO) Figure 19 44 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 2. Disconnect Crystal RF path and connect VCXO RF path a. Remove resistors R15 and R31. b. Install 0.1 uF capacitors in C31 and C43. Figure 20 3. Connect charge pump output from PLL1 to VCXO Loop Filter (A1) and VCXO. a. Remove R37 and install a 0 ohm resistor in R39. This resistor can be "switched" between the two footprints. Figure 21 45 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 4. Connect charge pump output from PLL2 to VCXO Loop filter (A2). a. Remove R10 and install a 0 ohm resistor in R9. This resistor can be "switched" between the two footprints. Figure 22 46 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Changing from VCXO to Crystal Resonator If the board has been setup to use the VCXO for PLL1, the VCXO may be disabled and the crystal enabled as described on the following pages: Summary 1. Remove power from VCXO 2. Disconnect VCXO RF path and connect Crystal RF path 3. Connect charge pump output from PLL1 to Crystal Loop Filter (B1) and Crystal 4. Connect charge pump output from PLL2 to Crystal Loop filter (B2) Procedures 1. Remove power from VCXO a. Remove 0 ohm resistor in R26 (near the VCXO) Figure 23 47 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 2. Disconnect VCXO RF path and connect Crystal RF path a. Install 0 ohm resistors R15 and R31. b. Remove 0.1 uF capacitors in C31 and C43. Figure 24 3. Connect charge pump output from PLL1 to Crystal Loop Filter (B1) and Crystal a. Remove R39 and install a 0 ohm resistor in R37. This resistor can be "switched" between the two footprints. Figure 25 48 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 4. Connect charge pump output from PLL2 to Crystal Loop filter (B2) a. Remove R9 and install a 0 ohm resistor in R10. This resistor can be "switched" between the two footprints. Figure 26 49 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix H: LMK04000 The block diagram in Figure 27 illustrates the functional architecture of the LMK040xxB clock conditioner. It features a cascaded, dual PLL arrangement, available internal loop filter components for PLL2, internal VCO with PLL2 for frequency synthesis, and clock distribution section with individual clock output dividers and delay adjustment blocks. The dual reference clock input to PLL1 provides fail-safe redundancy for phase locked loop operation. The cascaded PLL architecture allows PLL1 to be used as a jitter cleaner for an incoming reference clock that contains excessive phase noise. This requires the user to select an external oscillator (VCXO or crystal) that provides the desired phase noise performance at the clock output. This external oscillator becomes the reference clock for PLL2 and along with the phase noise characteristics of PLL2 and the internal VCO, determines the final phase noise performance at FOUT and the output of the clock distribution section. vcxo CLKin0 R1 FOUT R2 VCO CLKin1 N1 PLL1 N2 PLL2 CLKout_0 CHAN DIV DATA CLK VCO DIV uWire Interface 5 Output Clock Channels LVPECL, LVDS, LVCMOS LE CHAN DIV CLKout_4 Figure 27 - Functional Block Diagram of the LMK040xxB Dual PLL Precision Clock Conditioner with External VCXO module. 50 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL1 has been designed to work with either an off-the-shelf VCXO package or with a userdesigned discrete implementation that employs a crystal resonator and associated tuning components. The Figure 28 shows an example of a discretely implemented VCXO using a crystal resonator. CLKin0 R1 FOUT R2 VCO CLKin1 N1 PLL1 N2 PLL2 CLKout_0 CHAN DIV DATA CLK VCO DIV uWire Interface 5 Output Clock Channels LVPECL, LVDS, LVCMOS LE CHAN DIV CLKout_4 Figure 28 - LMK040xxB with the XTAL Resonator option and Tuning Circuit LMK04000 Family evaluation boards are configured with either a VCXO or Crystal (-XO) on board. It is possible to place a VCXO on a Crystal board or a Crystal on a VCXO board by removing and replacing certain components on the board. Instructions for modifying the board are presented in Appendix G: VCXO/Crystal changes. Figure 29 below shows the crystal oscillator circuit diagram. 51 E V A L U A T I O N B O A R D O P E R A T I N G CPout1 L M K 0 4 0 X X - R E V 3 Figure 29 - Crystal Oscillator Circuit diagram 52 I N S T R U C T I O N S L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix I: Properly Configuring LPT Port When trying to solve any communications issue, it is convenient to program the POWERDOWN bit to confirm high/low current draw of the evaluation board or the PLL_MUX between "Logic Low" and "Logic High" LD output to confirm successful communications. LPT Driver Loading The parallel port must be configured for proper operation. To confirm that the LPT port driver is successfully loading click "LPT/USB" AE "Check LPT Port." If the driver properly loads then the following message is displayed: Figure 30 - Successfully Opened LPT Driver Successful loading of LPT driver does not mean LPT communications in CodeLoader are setup properly. The proper LPT port must be selected and the LPT port must not be in an improper mode. The PC must be rebooted after install for LPT support to work properly. Correct LPT Port/Address To determine the correct LPT port in Windows, open the device manager (On Windows XP, Start AE Settings AE Control Panel AE System AE Hardware Tab AE Device Manager) and check the LPT port under the Ports (COM & LPT) node of the tree. It can be helpful to confirm that the LPT port is mapped to the expected port address, for instance to confirm that LPT1 is really mapped to address 0x378. This can be checked by viewing the properties of the LPT1 port and viewing resources tab to verify that the I/O Range starts at 0x378. CodeLoader expects the a traditional port mapping: Port Address LPT1 0x378 LPT2 0x278 LPT3 0x3BC If a non-standard address is used, use the "Other" port address in CodeLoader and type in the port address in hexadecimal. It is possible to change the port address in the computer's BIOS settings. The port address is set in CodeLoader at the Port Setup tab as shown in Figure 31. 53 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Figure 31 - Selecting the LPT Port Correct LPT Mode If communications are not working, then it is possible the LPT port mode is set improperly. It is recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS of the computer. Common terms for this desired parallel port mode are "Normal," "Output," or "AT." It is possible to enter BIOS setup during the initial boot up sequence of the computer. 54 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix J: Troubleshooting Information If the evaluation board is not behaving as expected, the most likely issues are... 1) Board communication issue 2) Incorrect Programming of the device 3) Setup Error Refer to this checklist for a practical guide on identifying/exposing possible issues. 1) Confirm Communications Refer to Appendix I: Properly Configuring LPT Port to trouble shoot this item. Remember to load device with Ctrl-L! 2) Confirm PLL1 operation/locking 1) Program PLL_MUX = "PLL 1 R Divider /2" 2) Confirm that LD pin output is half the expected phase detector frequency of PLL1. i. If not, examine CLKin_SEL programming. ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE. iii. If not, examine PLL1 register R programming. iv. If not, examine physical CLKin input. 3) Program PLL_MUX = "PLL 1 N Divider /2" 4) Confirm that LD pin output is half the expected phase detector frequency of PLL1. i. If not, examine PLL1 register N programming. ii. If not, examine physical OSCin input. Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider /2, on LD pin should be the same frequency. 5) Program PLL_MUX = "PLL1 DLD Active High" 6) Confirm the LD pin output is high. i. If high, then PLL1 is locked, continue to PLL2 operation/locking. (continued on next page) 55 L M K 0 4 0 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 7) If LD pin output is low, but the frequencies are the same, it is possible that excessive leakage on Vtune pin is causing the digital lock detect to not activate. By default PLL2 waits for the digital lock detect to go high before allowing PLL2 and the integrated VCO to lock. Different VCXO models have different input leakage specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1 charge pump current settings can cause the PLL1 charge pump to operate longer than the digital lock detect timeout which allows the device to lock, but prevents the digital lock detect from activating. i. Redesign PLL1 loop filter with higher phase detector frequency ii. Redesign PLL1 loop filter with higher charge pump current iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp. iv. Program RC_DLD1_Start = 0, this will allow PLL2 to starting lock even if the digital lock detect on PLL1 is not high. 3) Confirm PLL2 operation/locking 1) Program PLL_MUX = "PLL 2 R Divider /2" 2) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, examine PLL2 register R programming. ii. If not, examine physical OSCin input. 3) Program PLL_MUX = "PLL 2 N Divider /2" 4) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, confirm OSCin_FREQ is programmed to OSCin frequency. ii. If not, examine PLL2 register N programming. Naturally, the output frequency of the above two items should be the same frequency. 5) Program PLL_MUX = "PLL2 DLD Active High" 6) Confirm the LD pin output is high. 7) Program PLL_MUX = "PLL1/2 DLD Active High" 8) Confirm the LD pin output is high. 56 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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