ActualSize
9mmSquare
1 µFAVDD
AGND (Connect to PowerPAD)
ROSC
COSC
AREF
IN+
IN−IN−
FAULT1
FAULT0
PVDD
PVDD
PVDD
H/C
H/C
H/C
H/C
PGND
PGND
PGND
PGND
PGND
PGND
PWM
PWM
PWM
PWM
PVDD
PVDD
PVDD
FREQ
120 k
220 pF
1 µF
Shutdown Control
1 k
1 k
DC Control
Voltage
10 µF
VDD
10 µH
1 µF
FAULT1
FAULT0
To TEC or Laser
Diode Anode
To TEC or Laser
Diode Cathode
1 µF
SHUTDOWN
INT/EXT
DRV593
DRV594
10 µF
DRV593
DRV594
www.ti.com
SLOS401C OCTOBER 2002REVISED JULY 2010
±3-A HIGH-EFFICIENCY PWM POWER DRIVER
Check for Samples: DRV593,DRV594
1FEATURES DESCRIPTION
2 Operation Reduces Output Filter Size and Cost
by 50% Compared to DRV591 The DRV593 and DRV594 are high-efficiency,
high-current power amplifiers ideal for driving a wide
±3-A Maximum Output Current variety of thermoelectric cooler elements in systems
Low Supply Voltage Operation: 2.8 V to 5.5 V powered from 2.8 V to 5.5 V. The operation of the
High Efficiency Generates Less Heat device requires only one inductor and capacitor for
Overcurrent and Thermal Protection the output filter, saving significant printed-circuit
board area. Pulse-width modulation (PWM) operation
Fault Indicators for Overcurrent, Thermal and and low output stage on-resistance significantly
Undervoltage Conditions decrease power dissipation in the amplifier.
Two Selectable Switching Frequencies The DRV593 and DRV594 are internally protected
Internal or External Clock Sync against thermal and current overloads. Logic-level
PWM Scheme Optimized for EMI fault indicators signal when the junction temperature
has reached approximately 128°C to allow for
9×9 mm PowerPAD™ Quad Flatpack Package system-level shutdown before the amplifier's internal
thermal shutdown circuitry activates. The fault
APPLICATIONS indicators also signal when an overcurrent event has
Thermoelectric Cooler (TEC) Driver occurred. If the overcurrent circuitry is tripped, the
Laser Diode Biasing devices automatically reset (see application
information section for more details).
The PWM switching frequency may be set to 500 kHz
or 100 kHz depending on system requirements. To
eliminate external components, the gain is fixed at
2.3 V/V for the DRV593. For the DRV594, the gain is
fixed at 14.5 V/V.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DRV593
DRV594
SLOS401C OCTOBER 2002REVISED JULY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
PowerPAD QUAD FLATPACK
TA(VFP)
DRV593VFP(2)
–40°C to 85°C DRV594VFP(2)
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com
(2) This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number (e.g., DRV593VFPR or DRV594VFPR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
DRV593, DRV594
AVDD, PVDD Supply voltage –0.3 V to 5.5 V
VIInput voltage –0.3 V to VDD + 0.3 V
IO(FAULT0, FAULT1) Output current 1 mA
Continuous total power dissipation See Dissipation Rating Table
TAOperating free-air temperature range –40°C to 85°C
TJOperating junction temperature range –40°C to 150°C
Tstg Storage temperature range –65°C to 165°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
AVDD, PVDD Supply voltage 2.8 5.5 V
VIH High-level input voltage FREQ, INT/EXT, SHUTDOWN, COSC 2 V
VIL Low-level input voltage FREQ, INT/EXT, SHUTDOWN, COSC 0.8 V
TAOperating free-air temperature –40 85 °C
PACKAGE DISSIPATION RATINGS
qJA (1) qJC TA=25°C
PACKAGE (°C/W) (°C/W) POWER RATING
VFP 29.4 1.2 4.1 W
(1) This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard
4-layer 3 in × 3 in PCB.
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DRV593
DRV594
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SLOS401C OCTOBER 2002REVISED JULY 2010
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOO| Output offset voltage (measured differentially) VI= VDD/2, IO= 0 A 14 100 mV
|IIH| High-level input current VDD = 5.5V, VI= VDD 1mA
|IIL| Low-level input current VDD = 5.5V, VI= 0 V 1 mA
VnIntegrated output noise voltage f = <1 Hz to 10 kHz 40 mV
VDD = 5 V 1.2 3.8
VICM Common-mode voltage range V
VDD = 3.3 V 1.2 2.1
DRV593 2.1 2.3 2.6 V/V
AvClosed-loop voltage gain DRV594 13.7 14.5 15.3 V/V
Full power bandwidth 60 kHz
IO= ±1 A, rDS(on) = 65 m, VDD = 5 V 4.87
VOVoltage output (measured differentially) V
IO= ±3 A, rDS(on) = 65 m, VDD = 5 V 4.61
High side 25 60 95
VDD = 5 V, IO= 4 A, m
TA= 25°C Low side 25 65 95
rDS(on) Drain-source on-state resistance High side 25 80 140
VDD = 3.3 V, IO= 4 A, m
TA= 25°C Low side 25 90 140
Maximum continuous current output 3 A
Status flag output pins (FAULT0, FAULT1) Sinking 200 mA 0.1 V
Fault active (open drain output) For 500 kHz operation 225 250 300
External clock frequency range kHz
For 100 kHz operation 45 50 55
VDD = 5 V, No load or filter 4 12
IqQuiescent current mA
VDD = 3.3 V, No load or filter 2.5 8
Iq(SD) Quiescent current in shutdown mode VDD = 5 V, SHUTDOWN = 0.8 V 0 40 80 mA
Output resistance in shutdown SHUTDOWN = 0.8 V 1 2 k
Power-on threshold 1.7 2.8 V
Power-off threshold 1.6 2.6 V
Thermal trip point FAULT0 active 128 °C
Thermal shutdown Power off 158 °C
ZIInput impedance (IN+, IN-) 100 k
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): DRV593 DRV594
VFP PACKAGE
(TOP VIEW)
31 30 29 28 27
9 10
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PWM
PGND
PGND
PGND
PGND
PGND
PGND
H/C
AVDD
AGND
ROSC
COSC
AREF
IN+
IN−
SHUTDOWN
32 26
11 12 13 14 15
FAULT1
FAULT0
PVDD
PVDD
H/C
FREQ
INT/EXT
PVDD
PVDD
PWM
16
PWM
25
H/C
PVDD
H/C
PowerPAD
PVDD
PWM
DRV593
DRV594
SLOS401C OCTOBER 2002REVISED JULY 2010
www.ti.com
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
AGND 2 Analog ground
AREF 5 O Connect 1 mF capacitor to ground for AREF voltage filtering
AVDD 1 I Analog power supply
COSC 4 I Connect capacitor to ground to set oscillation frequency (220 pF for 500 kHz, 1 nF for 100 kHz) when
the internal oscillator is selected; connect clock signal when an external oscillator is used
FAULT0 10 O Fault flag 0, low when active open drain output (see application information)
FAULT1 9 O Fault flag 1, high when active open drain output (see application information)
FREQ 32 I Selects 500 kHz switching frequency when a TTL logic low is applied to this terminal; selects 100 kHz
switching frequency when a TTL logic high is applied
IN– 7 I Negative differential input
IN+ 6 I Positive differential input
INT/EXT 31 I Selects the internal oscillator when a TTL logic high is applied to this terminal; selects the use of an
external oscillator when a TTL logic low is applied to this terminal
H/C 14, 15, O Direction control output for heat and cool modes (4 pins)
16, 17
PWM 24, 25, O PWM output for voltage magnitude (4 pins)
26, 27
PGND 18, 19, High-current ground (6 pins)
20, 21,
22, 23
PVDD 11, 12, I High-current power supply (6 pins)
13, 28,
29, 30
ROSC 3 I Connect 120-kresistor to AGND to set oscillation frequency (either 500 kHz or 100 kHz). Not needed
if an external clock is used.
SHUTDOWN 8 I Places the amplifier in shutdown mode when a TTL logic low is applied to this terminal; places the
amplifier in normal operation when a TTL logic high is applied
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Product Folder Link(s): DRV593 DRV594
2.3xR(DRV593)
14.5xR(DRV594)
_
+_
+
_
+_
+
2.3xR(DRV593)
14.5xR(DRV594)
_
+
_
+
Gate
Drive
Gate
Drive
AVDD
OC
Detect
Start-Up
Protection
Logic
Thermal VDDok
Ramp
Generator
Biases
and
References
TTL
Input
Buffer
IN−
IN+
SHUTDOWN
R
R
AGND
AVDD
PVDD
H/C
PGND
PVDD
PWM
PGND
FAULT0
FAULT1
INT/EXT
FREQ
COSC
ROSC
AREF
DRV593
DRV594
www.ti.com
SLOS401C OCTOBER 2002REVISED JULY 2010
FUNCTIONAL BLOCK DIAGRAM
TYPICAL CHARACTERISTICS
Table of Graphs FIGURE
Efficiency vs Load resistance 2, 3
vs Supply voltage 4
rDS(on) Drain-source on-state resistance vs Free-air temperature 5
vs Free-air temperature 6
IqSupply current vs Supply voltage 7
PSRR Power supply rejection ratio vs Frequency 8, 9
Closed loop response 12, 13
vs Output voltage 14
IOMaximum output current vs Ambient temperature 15
VIO Input offset voltage Common-mode input voltage 16, 17
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): DRV593 DRV594
C1
PWM
H/C
RL
L1
L1 = 10 µH (part number: CDRH104R, manufacturer: Sumida)
C1 = 10 µF (part number: ECJ-4YB1C106K, manufacturer: Panasonic)
0
10
20
30
40
50
60
70
80
90
100
1 2 3 4 5 6 7 8 9 10
PO = 2 W
PO = 1 W
PO = 0.5 W
Efficiency − %
RL − Load Resistance −
VDD = 5 V
fS = 500 kHz
1 2 3 4 5 6 7 8 9 10
PO = 1 W
PO = 0.5 W
PO = 0.25 W
Efficiency − %
RL − Load Resistance −
0
10
20
30
40
50
60
70
80
90
100
VDD = 3.3 V
fS = 500 kHz
DRV593
DRV594
SLOS401C OCTOBER 2002REVISED JULY 2010
www.ti.com
TEST SETUP FOR GRAPHS
The LC output filter used in Figure 2,Figure 3,Figure 8, and Figure 9 is shown below.
Figure 1. LC Output Filter
EFFICIENCY EFFICIENCY
vs vs
LOAD RESISTANCE LOAD RESISTANCE
Figure 2. Figure 3.
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Product Folder Link(s): DRV593 DRV594
Total
−40 −15 10 35 60 85
Low Side
High Side
VDD = 5 V
IO = 1 A
VFP Package
TA − Free-Air Temperature − °C
0
50
100
150
200
250
300
rDS(on) − Drain-Source On-State Resistance − m
0
50
100
150
200
250
300
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Total
Low Side
High Side
IO = 1 A
TA = 25°C
VDD − Supply V oltage − V
rDS(on) − Drain-Source On-State Resistance − m
0
1
2
3
4
5
6
7
8
9
10
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD − Supply V oltage − V
No Load
Iq − Supply Current − mA
DRV593
DRV594
www.ti.com
SLOS401C OCTOBER 2002REVISED JULY 2010
DRAIN-SOURCE ON-STATE RESISTANCE DRAIN-SOURCE ON-STATE RESISTANCE
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 4. Figure 5.
DRAIN-SOURCE ON-STATE RESISTANCE SUPPLY CURRENT
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 6. Figure 7.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): DRV593 DRV594
10 100 1k 10k 100k
−80
−70
−60
−50
−40
−30
−20
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
VDD = 3.3 V
fS = 500 kHz
RL = 1
Vripple = 100 mVpp
10 100 1k 10k 100k
−80
−70
−60
−50
−40
−30
−20
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
VDD = 5 V
fS = 500 kHz
RL = 1
Vripple = 100 mVpp
0
2
4
6
8
10
12
14
16
10 100 1k 10k 100k
−70
−60
−50
−40
−30
−20
−10
0
10
Gain
Phase
Gain V/V
f Frequency Hz
Phase °
VDD =5V
NoLoad
Gain
Phase
0
1
2
3
4
−80
−70
−60
−50
−40
−30
−20
−10
0
10
Gain − V/V
f − Frequency − Hz
Phase − °
VDD = 5 V
No Load
10 100 1k 10k 100k
DRV593
DRV594
SLOS401C OCTOBER 2002REVISED JULY 2010
www.ti.com
POWER SUPPLY REJECTION RATIO POWER SUPPLY REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 8. Figure 9.
DRV593 DRV594
CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE
Figure 10. Figure 11.
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Product Folder Link(s): DRV593 DRV594
0
2
4
6
8
10
12
14
16
10 100 1k 10k 100k
−70
−60
−50
−40
−30
−20
−10
0
10
Gain
Phase
Gain V/V
f Frequency Hz
Phase °
VDD =3.3V
NoLoad
10 100 1k 10k 100k−80
−70
−60
−50
−40
−30
−20
−10
0
10
Gain − V/V
f − Frequency − Hz
Phase − °
Gain
Phase
0
1
2
3
4
VDD = 3.3 V
No Load
0
0.5
1
1.5
2
2.5
3
3.5
−40 −30 −20−10 0 10 20 30 40 50 60 70 80
− Maximum Output Current − A
IO
TA − Ambient Temperature − °C
TJ 125°C
VFP Package
DRV593
DRV594
www.ti.com
SLOS401C OCTOBER 2002REVISED JULY 2010
DRV593 DRV594
CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE
Figure 12. Figure 13.
MAXIMUM OUTPUT CURRENT MAXIMUM OUTPUT CURRENT
vs vs
OUTPUT VOLTAGE AMBIENT TEMPERATURE
Figure 14. Figure 15.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): DRV593 DRV594
10
11
12
13
14
15
16
17
18
19
20
1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1
VIC − Common-Mode Input Voltage − V
VDD = 3.3 V
No Load
VIO − Input Offset Voltage − mV
0
1
2
3
4
5
6
7
8
9
10
1.2 1.6 2.0 2.4 2.8 3.2 3.6 3.8
VIC − Common-Mode Input Voltage − V
VDD = 5 V
No Load
VIO − Input Offset Voltage − mV
DRV593
DRV594
SLOS401C OCTOBER 2002REVISED JULY 2010
www.ti.com
INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE
vs vs
COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE
Figure 16. Figure 17.
10 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV593 DRV594
VLoad +D VDD
D+AvǒVIN)–VIN–Ǔ
VDD
H/C
PWM
Load
Voltage
VDD
VDD
VDD
VDD/2
0
0
0
DRV593
DRV594
www.ti.com
SLOS401C OCTOBER 2002REVISED JULY 2010
APPLICATION INFORMATION
PULSE-WIDTH MODULATION SCHEME FOR DRV593 AND DRV594
The pulse-width modulation scheme implemented in the DRV593 and DRV594 eliminates one-half of the full
output filter previously required for PWM drivers. The DRV593 and DRV594 require only one inductor and
capacitor for the output filter. The H/C outputs determine the direction of the current and do not switch back and
forth. The PWM outputs switch to produce a voltage across the load that is proportional to the input control
voltage.
COOLING MODE
Figure 18 shows the DRV593 and DRV594 in cooling mode. The H/C outputs (pins 14-17) are at ground and the
PWM outputs (pins 24-27) create a voltage across the load that is proportional to the input voltage.
The differential voltage across the load is determined using Equation 1 and the duty cycle using Equation 2. The
differential voltage is defined as the voltage measured after the filter on the PWM output relative to the H/C
output.
(1)
(2)
where D duty cycle of the PWM signal AvGain of DRV593/594 (DRV593: 2.3 V/V, DRV594: 14.5 V/V) VIN+
Positive input terminal of the DRV593/594 VIN– Negative input terminal of the DRV593/594 VDD Power supply
voltage
For example, a 50% duty cycle, shown in Figure 18, results in 2.5 V across the load for VDD = 5 V.
Figure 18. Cooling Mode
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Product Folder Link(s): DRV593 DRV594
VLoad +–(1–D) VDD
H/C
PWM
Load
Voltage
−VDD
VDD
VDD
−VDD/2
0
0
0
DRV593
DRV594
SLOS401C OCTOBER 2002REVISED JULY 2010
www.ti.com
HEATING MODE
Figure 19 shows the DRV593 and DRV594 in heating mode. The H/C output is at VDD and the PWM output is
proportional to the voltage across the load.
The differential voltage across the load is determined using Equation 3. The variables are the same as used
previously for Equation 1 and Equation 2.
(3)
For example, a 50% duty cycle, shown in Figure 19, results in –2.5 V across the load for VDD = 5 V. The
differential voltage across the load is defined as the voltage measured after the filter on the PWM output relative
to the H/C output.
Figure 19. Heating Mode
HEAT/COOL TRANSITION
As the device transitions from cooling to heating, the duty cycle of the PWM outputs decrease to a small value
and the H/C outputs remains at ground. When the device transitions to heating mode, the H/C outputs change
from zero volts to VDD and the PWM outputs change to a high duty cycle. The direction of the current flow is
reversed, but a low voltage is maintained across the load. The duty cycle decreases as the part is put further into
heating mode to drive more current through the load. Figure 20 illustrates the transition from cooling to heating.
ZERO-CROSSING REGION
When the differential output voltage is near zero, the control logic in the DRV593 and DRV594 causes the
outputs to change between heating and cooling modes. There are two possible states for the PWM and H/C
outputs to obtain zero volts differentially: both outputs can be at VDD or both outputs can be at ground.
Therefore, random noise causes the outputs to change between the two states when the two input voltages are
equal. The outputs switch from zero to VDD, although not at a fixed frequency rate. Some of the pulses may be
wider than others, but the two outputs (PWM and H/C) track each other to provide zero differential voltage.
These uneven pulse widths can increase the switching noise during the zero-crossing condition.
12 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV593 DRV594
PWM
VDD
VDD
0
IN −
IN +
0
H/C
VDD
0
1 µFAVDD
AGND (Connect to PowerPAD)
ROSC
COSC
AREF
IN+
IN−IN−
FAULT1
FAULT0
PVDD
PVDD
PVDD
H/C
H/C
H/C
H/C
PGND
PGND
PGND
PGND
PGND
PGND
PWM
PWM
PWM
PWM
PVDD
PVDD
PVDD
FREQ
120 k
220 pF
1 µF
Shutdown Control
1 k
1 k
DC Control
Voltage
10 µF
VDD
10 µH
1 µF
FAULT1
FAULT0
To TEC or Laser
Diode Anode
To TEC or Laser
Diode Cathode
1 µF
SHUTDOWN
INT/EXT
DRV593
DRV594
10 µF
DRV593
DRV594
www.ti.com
SLOS401C OCTOBER 2002REVISED JULY 2010
To avoid this phenomenon, hysteresis should be implemented in the control loop to prevent the device from
operating within this region. Although planning for operation during the zero-crossing is important, the normal
operating points for the DRV593 and DRV594 are outside of this region. For laser temperature/wavelength
regulation, the zero volts output condition is only a concern when the laser temperature or wavelength, relative to
the ambient temperature, requires no heating or cooling from the TEC element.
Figure 20. Transition From Cooling to Heating
Figure 21. Typical Application Circuit
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): DRV593 DRV594
DT+1
ǒ1)N2Ǔ DTmax
CTEC
PWM
H/C
R
L
HLP(jw)+1
ǒw
w0Ǔ2
)1
Qjw
w0)1
w0+1
LC
Ǹ
w+DRV593 or DRV594 switching frequency
Q+quality factor
DRV593
DRV594
SLOS401C OCTOBER 2002REVISED JULY 2010
www.ti.com
OUTPUT FILTER CONSIDERATIONS
TEC element manufacturers provide electrical specifications for maximum dc current and maximum output
voltage for each particular element. The maximum ripple current, however, is typically only recommended to be
less than 10% with no reference to the frequency components of the current. The maximum temperature
differential across the element, which decreases as ripple current increases, may be calculated with the following
equation:
(4)
where
ΔT = actual temperature differential
ΔTmax = maximum temperature differential (specified by manufacturer)
N = ratio of ripple current to dc current
According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. An LC
network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more
importantly, protect the rest of the system from any electromagnetic interference (EMI).
FILTER COMPONENT SELECTION
The LC filter, which may be designed from two different perspectives, both described below, helps estimate the
overall performance of the system. The filter should be designed for the worst-case conditions during operation,
which is typically when the differential output is at 50% duty cycle. The following section serves as a starting
point for the design, and any calculations should be confirmed with a prototype circuit in the lab.
Any filter should always be placed as close as possible to the DRV593 and DRV594 to reduce EMI.
Figure 22. Output Filter
LC FILTER IN THE FREQUENCY DOMAIN
The transfer function for a second-order low-pass filter (Figure 22) is shown in Equation 5:
(5)
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Product Folder Link(s): DRV593 DRV594
ŤHLPŤdB +–40 log ǒfs
foǓ
fo+1
2pLC
Ǹ
fs+500 kHz (DRV593 or DRV594 switching frequency)
DIL+ǒVO–VTECǓDTs
L
D+duty cycle (0.5 worst case)
Ts+1ńfs+1ń500 kHz
DVC+p2
2ǒ1–DǓǒfo
fsǓ2VTEC
fo+1
2pLC
Ǹ
fs+500 kHz
D+duty cycle
DVC+DIL RESR
DIL+inductor ripple current
RESR +filter capacitor ESR
DRV593
DRV594
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SLOS401C OCTOBER 2002REVISED JULY 2010
For the DRV593 and DRV594, the differential output switching frequency is typically selected to be 500 kHz. The
resonant frequency for the filter is typically chosen to be at least one order of magnitude lower than the switching
frequency. Equation 5 may then be simplified to give the following magnitude Equation 6. These equations
assume the use of the filter in Figure 22.
(6)
If L=10 mH and C=10 mF, the cutoff frequency is 15.9 kHz, which corresponds to –60 dB of attenuation at the 500
kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element is approximately 5
mV.
The average TEC element has a resistance of 1.5 , so the ripple current through the TEC is approximately 3.4
mA. At the 3-A maximum output current of the DRV593 and DRV594, this 5.4 mA corresponds to 0.11% ripple
current, causing less than 0.0001% reduction of the maximum temperature differential of the TEC element (see
Equation 4).
LC FILTER IN THE TIME DOMAIN
The ripple current of an inductor may be calculated using Equation 7:
(7)
For VO=5V,VTEC = 2.5 V, and L = 10 mH, the inductor ripple current is 250 mA. To calculate how much of that
ripple current flows through the TEC element, however, the properties of the filter capacitor must be considered.
For relatively small capacitors (less than 22 mF) with very low equivalent series resistance (ESR, less than
10 m, such as ceramic capacitors, the following Equation 8 may be used to estimate the ripple voltage on the
capacitor due to the change in charge:
(8)
For L = 10 mH and C = 10 mF, the cutoff frequency, fo, is 15.9 kHz. For worst case duty cycle of 0.5 and
VTEC=2.5 V, the ripple voltage on the capacitors is 6.2 mV. The ripple current may be calculated by dividing the
ripple voltage by the TEC resistance of 1.5, resulting in a ripple current through the TEC element of 4.1 mA.
Note that this is similar to the value calculated using the frequency domain approach.
For larger capacitors (greater than 22 mF) with relatively high ESR (greater than 100 m), such as electrolytic
capacitors, the ESR dominates over the charging/discharging of the capacitor. The following simple Equation 9
may be used to estimate the ripple voltage:
(9)
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For a 100 mF electrolytic capacitor, an ESR of 0.1 is common. If the 10 µH inductor is used, delivering 250 mA
of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times
that of the 10 mF ceramic capacitor, as ceramic capacitors typically have negligible ESR.
SWITCHING FREQUENCY CONFIGURATION: OSCILLATOR COMPONENTS ROSC and COSC AND
FREQ OPERATION
The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. The
frequency may be either 500 kHz or 100 kHz by selecting the proper capacitor value and by holding the FREQ
pin either low (500 kHz) or high (100 kHz). Table 2 shows the values required and FREQ pin configuration for
each switching frequency.
Table 2. Frequency Configuration Options
SWITCHING FREQUENCY ROSC COSC FREQ
500 kHz 120 k220 pF LOW (GND)
100 kHz 120 k1 nF HIGH (VDD)
For proper operation, the resistor ROSC should have 1% tolerance while capacitor COSC should be a ceramic type
with 10% tolerance. Both components should be grounded to AGND, which should be connected to PGND at a
single point, typically where power and ground are physically connected to the printed-circuit board.
EXTERNAL CLOCKING OPERATION
To synchronize the switching to an external clock signal, pull the INT/EXT terminal low, and drive the clock signal
into the COSC terminal. This clock signal must be from 10% to 90% duty cycle and meet the voltage
requirements specified in the electrical specifications table. Since the DRV593 and DRV594 include an internal
frequency doubler, the external clock signal must be approximately 250 kHz. Deviations from the 250 kHz clock
frequency are allowed and are specified in the electrical characteristic table. The resistor connected from ROSC
to ground may be omitted from the circuit in this mode of operation—the source is disconnected internally.
INPUT CONFIGURATION: DIFFERENTIAL AND SINGLE-ENDED
If a differential input is used, it should be biased around the midrail of the DRV593 or DRV594 and must not
exceed the common-mode input range of the input stage (see the operating characteristics at the beginning of
the data sheet).
The most common configuration employs a single-ended input. The unused input should be tied to VDD/2, which
may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values
chosen should be at least 100 times lower than the input resistance of the DRV593 or DRV594. This prevents
the bias voltage at the unused input from shifting when the signal input is applied. A small ceramic capacitor
should also be placed from the input to ground to filter noise and keep the voltage stable. An op amp configured
as a buffer may also be used to set the voltage at the unused input.
FIXED INTERNAL GAIN
The differential output voltage may be calculated using Equation 10:
(10)
AVis the voltage gain, which is fixed internally at 2.3 V/V for DRV593 and 14.5 V/V for DRV594. The maximum
and minimum ratings are provided in the electrical specification table at the beginning of the data sheet.
POWER SUPPLY DECOUPLING
To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor, typically 0.1 mF to 1 mF,
should be placed as close to each set of PVDD pins of the DRV593 and DRV594 as possible. For bulk
decoupling, a 10 mF to 100 mF tantalum or aluminum electrolytic capacitor should be placed relatively close to
the DRV593 and DRV594.
16 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
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SLOS401C OCTOBER 2002REVISED JULY 2010
AREF CAPACITOR
The AREF terminal is the output of an internal mid-rail voltage regulator used for the onboard oscillator and ramp
generator. The regulator may not be used to provide power to any additional circuitry. A 1 mF ceramic capacitor
must be connected from AREF to AGND for stability (see oscillator components above for AGND connection
information).
SHUTDOWN OPERATION
The DRV593 and DRV594 include a shutdown mode that disables the outputs and places the device in a low
supply current state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is held
high, the device operates normally. When SHUTDOWN is held low, the device is placed in shutdown. The
SHUTDOWN pin must not be left floating. If the shutdown feature is unused, the pin may be connected to VDD.
FAULT REPORTING
The DRV593 and DRV594 include circuitry to sense three faults:
Overcurrent
Undervoltage
Overtemperature
These three fault conditions are decoded via the FAULT1 and FAULT0 terminals. Internally, these are open-drain
outputs, so an external pullup resistor of 5 kor greater is required.
Table 3. Fault Indicators
FAULT1 FAULT0
0 0 Overcurrent
1 0 Undervoltage
0 1 Overtemperature
1 1 Normal operation
The overcurrent fault is reported when the output current exceeds four amps. As soon as the condition is sensed,
the overcurrent fault is set and the outputs go into a high-impedance state for approximately 3 msto5ms
(500 kHz operation). After 3 msto5ms, the outputs are re-enabled. If the overcurrent condition has ended, the
fault is cleared and the device resumes normal operation. If the overcurrent condition still exists, the above
sequence repeats.
The undervoltage fault is reported when the operating voltage is reduced below 2.8 V. This fault is not latched,
so as soon as the power supply recovers, the fault is cleared and normal operation resumes. During the
undervoltage condition, the outputs go into a high-impedance state to prevent overdissipation due to increased
rDS(on).
The overtemperature fault is reported when the junction temperature exceeds 128°C. The device continues
operating normally until the junction temperature reaches 158°C, at which point the IC is disabled to prevent
permanent damage from occurring. The system's controller must reduce the power demanded from the DRV593
or DRV594 once the overtemperature flag is set, or else the device switches off when it reaches 158°C. This
fault is not latched; once the junction temperature drops below 128°C, the fault is cleared, and normal operation
resumes.
POWER DISSIPATION AND MAXIMUM AMBIENT TEMPERATURE
Though the DRV593 and DRV594 are much more efficient than traditional linear solutions, the power drop
across the on-resistance of the output transistors does generate some heat in the package, which may be
calculated as shown in Equation 11:
(11)
For example, at the maximum output current of 3 A through a total on-resistance of 130 m(at TJ= 25°C), the
power dissipated in the package is 1.17 W.
Calculate the maximum ambient temperature using Equation 12:
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
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TA+TJ*ǒθJA PDISSǓ
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SLOS401C OCTOBER 2002REVISED JULY 2010
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(12)
PRINTED-CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS
Since the DRV593 and DRV594 are high-current switching devices, a few guidelines for the layout of the
printed-circuit board (PCB) must be considered:
1. Grounding. Analog ground (AGND) and power ground (PGND) must be kept separated, ideally back to
where the power supply physically connects to the PCB, minimally back to the bulk decoupling capacitor (10
µF ceramic minimum). Furthermore, the PowerPAD ground connection should be made to AGND, not
PGND. Ground planes are not recommended for AGND or PGND, traces should be used to route the
currents. Wide traces (100 mils) should be used for PGND while narrow traces (15 mils) should be used for
AGND.
2. Power supply decoupling. A small 0.1 mF to 1 mF ceramic capacitor should be placed as close to each set
of PVDD pins as possible, connecting from PVDD to PGND. A 0.1 mF to 1 mF ceramic capacitor should also
be placed close to the AVDD pin, connecting from AVDD to AGND. A bulk decoupling capacitor of at least
10 mF, preferably ceramic, should be placed close to the DRV593 or DRV594, from PVDD to PGND. If power
supply lines are long, additional decoupling may be required.
3. Power and output traces. The power and output traces should be sized to handle the desired maximum
output current. The output traces should be kept as short as possible to reduce EMI, i.e., the output filter
should be placed as close to the DRV593 or DRV594 outputs as possible.
4. PowerPAD. The DRV593 and DRV594 in the Quad Flatpack package use TI's PowerPAD technology to
enhance the thermal performance. The PowerPAD is physically connected to the substrate of the DRV593
and DRV594 silicon, which is connected to AGND. The PowerPAD ground connection should therefore be
kept separate from PGND as described above. The pad underneath the AGND pin may be connected
underneath the device to the PowerPAD ground connection for ease of routing. For additional information on
PowerPAD PCB layout, refer to the PowerPAD Thermally Enhanced Package application note, (SLMA002).
5. Thermal performance. For proper thermal performance, the PowerPAD must be soldered down to a thermal
land, as described in the PowerPAD Thermally Enhanced Package application note, (SLMA002). In addition,
at high current levels (greater than 2 A) or high ambient temperatures (greater than 25°C), an internal plane
may be used for heat sinking. The vias under the PowerPAD should make a solid connection, and the plane
should not be tied to ground except through the PowerPAD connection, as described above.
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Product Folder Link(s): DRV593 DRV594
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SLOS401C OCTOBER 2002REVISED JULY 2010
Changes from Revision A (October 2002) to Revision B Page
Changed Thermal trip point from 115°C to 128°C ................................................................................................................ 3
Changed Thermal shtudown point from 128°C to 158°C ..................................................................................................... 3
Changes from Revision B (November 2008) to Revision C Page
Changed figure cross reference from "Figure 17 and Figure 18" to "Figure 22" in the "LC FILTER......." section. ............ 14
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
DRV593VFP ACTIVE HLQFP VFP 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DRV593VFPG4 ACTIVE HLQFP VFP 32 TBD Call TI Call TI
DRV593VFPR ACTIVE HLQFP VFP 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DRV593VFPRG4 ACTIVE HLQFP VFP 32 TBD Call TI Call TI
DRV594VFP ACTIVE HLQFP VFP 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DRV594VFPG4 ACTIVE HLQFP VFP 32 TBD Call TI Call TI
DRV594VFPR ACTIVE HLQFP VFP 32 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DRV594VFPRG4 ACTIVE HLQFP VFP 32 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Jan-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DRV593VFPR HLQFP VFP 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
DRV594VFPR HLQFP VFP 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV593VFPR HLQFP VFP 32 1000 367.0 367.0 38.0
DRV594VFPR HLQFP VFP 32 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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