Publication Number S29AL032D_00 Revision A Amendment 3 Issue Date June 13, 2005
S29AL032D
32 Megabit CMOS 3.0 Volt-only Flash Memory
4 M x 8-Bit Uniform Sector
4 M x 8-Bit/2 M x 16-Bit Boot Sector
Data Sheet ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
ii S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Ad vance Information or Prelim inary design ations to advise
readers of prod uct information or intended specifications throughout the product life cycle, in-
cluding development, qualifica tion, initial production, and full produ ction. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.
Advanc e I nformatio n
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but ha s not committed any de sign to production. Inform ation presented in a doc-
ument with this designation is likely to change, and in s ome cases, developmen t on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-
tion content:
“This document contains information on one or more products under development at Spansion LLC. The
inform ation is inten ded to help yo u evaluate this produ ct. Do no t design in this pro duct withou t con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
prod u ct wit h o u t n o tice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
uct life cycle, including product qualification, initial pr oduction, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specification s presented in a Pre liminary do cument should be expe cted while keeping t hese as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:
“This docu ment states the c urrent tec hnical spe cific ations rega rding the S pansio n produc t(s ) des cribe d
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions du e to chan ge s in tec hnical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In -
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics t able and AC E ra se and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designatio n on Document)
When a product has been in pr oducti on for a period of time suc h that no changes or only nomina l
changes a re expected, the P reliminary design ation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO ran ge . Ch an g es
may also include those need ed to clarify a description or to correct a typographical error or incor -
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This docu ment states the c urrent tec hnical spe cific ations rega rding the S pansio n produc t(s ) des cribe d
herein . Spans ion LLC deem s the pro ducts to have been in suff ici ent prod ucti on volum e such that su b-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifi ca tions to the valid combinatio ns offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right t o change or discontinue work on this proposed product without notice.
Publication Number S29AL032D_00 Revision A Amendment 3 Issue Date June 13, 2005
Distinctive Characteristics
Architectural Advantages
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write op-
erations for battery-powered applications
Manufa ctured on 200 nm proce ss technology
— Fully compat ible wi th 0.23 µm Am29LV320D , 0.32 µm
Am29LV033C, and 0.33 µm MBM29LV320E devices
Flexible sector architecture
— Boot sector models: Eight 8-Kbyte sectors; sixty-
three 64-Kbyte sectors; top or bot tom boot block
configurations available
— Uniform sector models: Sixty-four 64-Kbyte sectors
Sector Protection features
— A hardware method of locking a sector to prevent any
program or erase operatio ns withi n that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Secured Silicon Sector
— 128-word sector for permanent, secure identification
through an 8-wo rd random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
Compatibility with JEDEC standards
— Pinout and software compatible wit h singl e-p ower
supply Flash
— Superior inadvertent write protection
Package Options
48-ball FBGA
48-pin TSOP
40-pin TSOP
Performance Characteristics
High perfo r mance
— Access times as fast as 70 ns
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical
Soft w a re Features
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend/ Er as e Re su me
— Suspends an eras e ope ration to read data from, or
progr a m da ta to, a sector that is not bei ng erased,
then resumes the erase operation
Data# Polling and toggle bits
— Provides a software me thod of detecting program or
erase operation completion
— Unlock Byp ass Prog ram Comm a nd
Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
WP#/ A CC input pi n
— Write protect (WP#) function allows protection of two
outermos t boot sec tors (boot se ctor mo dels on ly ),
regardless of sector protect status
— Acceleration (ACC) function provides accelera ted
program times
S29AL032D
32 Megabit CMOS 3.0 Volt-only Flash Memory
4 M x 8-Bit Uniform Sector
4 M x 8-Bit/2 M x 16-Bit Boot Sector
Data Sheet ADVANCE
INFORMATION
2 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
General Description
The S29AL032D is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152
words of 16 bits ea ch or 4,194,304 byte s of 8 bits each. W ord mode dat a appears on DQ0-DQ15;
byte mode data appears on DQ0-DQ7. The devi ce is designed to be progra mmed in-sys tem with
the standard 3.0 volt VCC supply , and can also be programmed in standard EPROM programmers.
The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP,
48-pin TSOP and 48-ball FBGA pack ages. Standard control pin s- chip enable (CE#) , write enable
(WE#) , and output enable (O E#)-contr ol normal read and writ e operations, and avoid bus con-
tenti on issu e s.
The device requires only a single 3.0 volt power supply for both read and write functions. In-
ternally generated an d regulated voltages are provi ded for the pro-gram and erase operations.
S29AL032D Features
The Secured Silicon Sector is an ext ra sector capable of bei ng permanently locked by Spansi on
or custom e r s. The Secured Silicon Indicator B it (DQ7) is permanently se t to a 1 if the part is
factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never
be used to replace a factory locked part. Note that the S29AL032D has a Secured Silicon
Sector size of 128 words (256 bytes).
F actory locked pa rts provi de sev eral options. The Secured Si licon Sec tor may store a secure, r an -
dom 16 byte ESN (El ectronic Seri al Number), cu stomer code (progr ammed through t he Spansion
progra mmi ng service), or both.
The S29AL032D is entirely command set compatible with the JEDEC single-power-supply
Flash standard. Commands are written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal state-machine that controls the
eras e and progr amming circu itry. Writ e cycles also intern ally latch addresses and data needed f or
the programming and erase operations. Reading data out of the device is similar to reading from
other Fla sh or EPROM devi ces.
Device progr amming occurs by executing the program command sequence. This initiates the Em-
bedded Program algo rithm— an i ntern al alg orith m t hat a utom atica lly times the pro gram pu lse
widths and v erifi es proper c ell margin. The Unlock Byp a ss mode fa ci lita te s fa ster pro gr a mming
times by requiring only t wo write cycles to progr am data instead of four.
Device erasure occurs by execut ing the erase command sequence. This initiates the Embedded
Erase algorithm —an in terna l alg orithm tha t autom ati call y pre prog rams the a rray (if it is no t al-
ready programmed) bef ore executing the erase oper ation. During erase, the device automatically
times the er ase pulse widths and veri fi es proper cell margin.
The host system can detect whether a program or erase opera tion is complete by observing the
RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) statu s bits . After a pro-
gram or er ase cycle has been completed, the devi ce is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The device is fully erased when shipped from the
factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write
operations during power transitions. The hardware sector protection feature disables both
progra m and erase oper ations in an y combination of t he sectors of memory. This can be ach ieved
in-syste m or via programming equipment.
June 13, 2005 S29AL032D_00_A3 S29AL032D 3
Advance Information
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period
of ti me to re ad da ta from , or pr ogram data to, any sector that is not se lected fo r erasur e. Tr ue
background erase can thus be achieved.
The hardware RESET# pin terminates any o peration in progress and resets th e internal state
machine to reading arr ay data. The RESET# pin ma y be tied to the syst em reset circ uitry. A sys-
tem reset would thus also reset the device, enabling the system microprocessor to read the
boot-up fi rmware from th e Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified
amo unt of time, the d evice enters th e automatic sleep mode. The sys tem can also place the
device int o the standby mode. Power consumption is greatly reduced in both these modes.
The Spansion Flash technology combines years of Flash memory manufacturing experience to
produce the highest levels of quality, reliability and cost effectiveness. The device electrically
erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
4 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11
Table 1. S29AL032D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .11
Word/Byte Configuration (Models 03, 04 Only) . . . . . . . . . . . 11
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . . 11
Writing Commands/Command Sequences . . . . . . . . . . . . . . . 12
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 12
Accelerated Program Operation . . . . . . . . . . . . . . . . . . . . . . . 12
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Model 00 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Model 00 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 15
Table 4. Model 03 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Model 03 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 17
Table 6. Model 04 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Model 04 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 19
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. S29AL032D Autoselect Codes (High Voltage Method) . . . . . 20
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Sector Block Addresses for Protection/Unprotection
— Model 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Sector Block Addresses for Protection/Unprotection
— Model 03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Sector Block Addresses for Protection/Unprotection
— Model 04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write Protect (WP#) — Models 03, 04 Only . . . . . . . . . . . . 23
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . . . . 24
Figure 2. In-System Sector Protect/Unprotect Algorithms. . . . . . . . . . 25
Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . 26
Figure 3. Secured Silicon Sector Protect Verify. . . . . . . . . . . . . . . . . . . 27
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Common Flash Memory Interface (CFI). . . . . . . 28
Table 12. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . 30
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 31
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 32
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Word/Byte Program Command Sequence . . . . . . . . . . . . . . . 32
Figure 4. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 34
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . 35
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . .35
Figure 5. Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 16. S29AL032D Command Definitions — Model 00 . . . . . . . . . . 37
Table 17. S29AL032D Command Definitions — Models 03, 04 . . . . . . 38
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 39
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 6. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 7. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . .43
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 45
Figure 8. Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . 45
Figure 9. Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . 45
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. Typical I
CC1
vs. Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 12. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Input Waveforms and Measurement Levels . . . . . . . . . . . . . 49
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. Read Operations Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 15. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16. BYTE# Timings for Read Operations . . . . . . . . . . . . . . . . . . 52
Figure 17. BYTE# Timings for Write Operations . . . . . . . . . . . . . . . . . . 53
Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 18. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 19. Chip/Sector Erase Operation Timings. . . . . . . . . . . . . . . . . . 56
Figure 20. Back to Back Read/Write Cycle Timing. . . . . . . . . . . . . . . . 56
Figure 21. Data# Polling Timings (During Embedded Algorithms) . . . . 57
Figure 22. Toggle Bit Timings (During Embedded Algorithms) . . . . . . 57
Figure 23. DQ2 vs. DQ6 for Erase and Erase Suspend Operations. . . 58
Figure 24. Temporary Sector Unprotect/Timing Diagram . . . . . . . . . . 58
Figure 25. Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . 59
Figure 26. Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . 59
Figure 27. Alternate CE# Controlled Write Operation Timings. . . . . . 61
Erase and Programming Performance . . . . . . . . 62
TSOP and BGA Pin Capacitance . . . . . . . . . . . . . 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 63
TS040—40-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . .63
TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . 64
VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
10.0 x 6.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 66
June 13, 2005 S29AL032D_00_A3 S29AL032D 5
Advance Information
Product Selector Guide
Note: See AC Characteristics on page 50 for full specifica tions.
Block Diagram
Family Part Number
S29AL032D
Speed O ption Voltage Range: V
CC
= 2.7–3.6 V
70 90
Max access time, ns (t
ACC
)70 90
Max CE# access time, ns (t
CE
)70 90
Max OE # access time, ns (t
OE
)30 35
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detec tor
State
Control
Command
Register
V
CC
V
SS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ1 5 (A-1), (DQ0-DQ7 M ode l 00)
Sector Switc hes
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address La tch
A0–A20 (A0-A21 Model 00)
6 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Connection Diagrams
1
16
2
3
4
5
6
7
8
17
18
19
20
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
30
29
28
27
26
24
23
22
21
A16
A5
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
A17
DQ0
VSS
A20
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VCC
A21
DQ3
DQ2
DQ1
40-pin Standard TSOP
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48-pin Standard TSOP
June 13, 2005 S29AL032D_00_A3 S29AL032D 7
Advance Information
Connection Diagrams
For Model 00 Only
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
A20 VSSNCA17A16A15A13A14
DQ6 DQ7A10A19A12A11A8A9
VCC DQ4NCDQ5NCNCRESET#WE#
VCC A21DQ3DQ2NCNCACCRY/BY#
NC DQ1NCDQ0A5A6A18A7
OE# VSSCE#A0A1A2A4A3
48-ball FBGA Top view balls facing down
8 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
For Models 03, 04 Only
Special Handling Instructions
Special handling is required for Flash Memor y products in FBGA packa g es.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth -
ods. The package and/or data integrity m ay be compromised if the package body is exposed to
temperatures above 150°C for prolonged per iods of time.
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
DQ15/A-1 VSSBYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5A19NCRESET#WE#
DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSSCE#A0A1A2A4A3
48-ball FBGA Top view balls facing down
June 13, 2005 S29AL032D_00_A3 S29AL032D 9
Advance Information
Pin Configuration
A0–A21 = 22 address inputs
A0- A20 = 21 address inputs
DQ0–DQ7 = 8 data inputs/outputs
DQ0-DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input /output, word mode),
A -1 (LSB address input, byte mode)
BYTE# = Select s 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = W rite enable
RESET# = Hardware reset pin
WP#/ACC = Hardware Write Protect input/Programming
Acceleration input.
ACC = Hardware Write Pro tect input
RY/BY# = Ready/Busy output
VCC = 3.0 volt-only single power supply
see Product Selector Guide on page 5 for speed
options an d voltage supply tolerances)
VSS =Device ground
NC = Pin not connected internally
Logic Symbol
Model 00 Models 03, 04
22 8
DQ0–DQ7
A0–A21
CE#
OE#
WE#
RESET#
RY/BY#
ACC
21 16 or 8
DQ0–DQ15
(A-1)
A0–A20
CE#
OE#
WE#
RESET#
RY/BY#
BYTE#
WP#/ACC
10 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Ordering Information
S29AL032D Standard Products
Spansion standard products are available in several packages and operating
rang es. The order number (V al id Combination) is fo rmed by a combination of the
elements below.
Notes:
1. Type 0 is standard. Specify other options as re qu ired.
2. TSOP package marking om its packin g type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type design ator from ordering part number.
Valid C omb ina t ions
Valid Combinations list configurations planned to be supported in volume for this device. Consult your
loc al sale s office to conf irm avai labili ty of spe cific valid com binat ions an d to ch eck on newly re leas ed
combinations.
S29AL032D 70 T A I 00 0
PACKING TYPE
0=Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER
00 = x8, V
CC
= 2.7 V to 3.6 V, Uniform sector device
03 = x8/x16, V
CC
= 2.7 V to 3.6 V, T op boot sector device, top two address
sectors protected when WP#/ACC = V
IL
04 = x 8/x16, V
CC
= 2.7 V to 3.6 V, Bottom boot sector device, botto m two
address se ctors protec te d when WP#/ACC = V
IL
TEMPERATURE RANGE
I = Industrial (–40
°
C to +8 5
°
C)
E = Engineering Samples (a vailable prior to Production Release only)
PACKAGE MATERIAL SET
A=Standard
F=Pb-Free
PACKA GE TYP E
T = Thin Small Outl ine Package (TSOP) Standard Pinou t
B = Fine-pitch Ball-Grid Array Package
SPEED OPTION
See “Prod uc t Selec tor G uid e” and Valid Combinatio ns
DEVICE NUMBER/DESCRIPTION
S29AL032D
3.0 Volt-only, 32 Megabit Standard Flash Memory
manufac tured us ing 20 0 nm proces s techno logy
S29AL 032D Valid Com bin at io ns
Package Description
Device Number Speed
Option
Package Type,
Mater ial, and
Temperatu re Ra n ge
Model
Number Packing Type
S29AL032D 70, 90 TAI, TFI 00 0, 3 (Note 1) TS040 (Note 2 ) TSOP
03, 04 TS048 (Note 2 ) TSOP
BAI, BFI 00, 03, 04 0, 2, 3 (Note 1) VBN048 (Note 3) Fine-Pitch BGA
June 13, 2005 S29AL032D_00_A3 S29AL032D 11
Advance Information
Device Bus Operations
This sectio n descri bes t he requ irements and u se of the devic e bus oper ati ons, wh ich are i niti ated
through the internal command regi ster. The command regi ster itse lf does not occupy an y addres -
sable memory locati on. Th e regist er is co mposed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the d evic e. Table 1 lists the device bus operations, the inputs and control levels they require, and
the resulting output. The foll owing subsections descri be each of t hese oper ations in further detail.
Ta b l e 1 . S29AL032D Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’ t Ca re, AIN = Addre ss In, DIN = Data In, DOUT
= Data Out
Notes:
1. When the ACC pin is at VHH, the device enters the accelerated program mode. See
2. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
3. The sector protect and sector unpro tect functions may also be implemented via programming equipment.
4. If WP#/ACC = VIL, the tw o outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector
protec tion depends on wh ether they were last protected or unprotected. If WP#/ACC = VHH, all sectors are unprotected.
5. DIN or DOUT as required by comma n d se quence, data poll ing, or sector protection algorithm.
6. Models 03, 04 only
Word/Byte Configuration (Models 03, 04 Only)
The BYTE# pin cont rols whethe r the device data I/ O pins DQ15–DQ0 oper ate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the dev ice is in wo rd con figu ration , DQ1 5–DQ 0
are active and co ntrolled by CE# and OE#.
If the BYTE # pi n is set at l ogic 0, the dev ice is in byte config ur ation, a nd only data I /O pins DQ0–
DQ7 are activ e and contro lled by CE# and OE#. The data I/O pins DQ8–DQ14 are tr i-stated, and
the DQ15 pin is used as an input for the LSB (A-1) address functio n.
Requirements for Reading Array Data
To read array data from the outputs, the sy stem must drive the CE# and OE# pins to VIL. CE# is
the power contro l and selects the device. OE# is the output contr ol and gates array data to the
output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs
array data in words or bytes.
Operation CE# OE# WE# RESET# WP#(Note 6)/
ACC Addresses
(Note 3) DQ0–
DQ7
DQ8–DQ15 (Note 6)
BYTE#
= VIH BYTE# = VIL
Read LLH H L/H A
IN DOUT DOUT DQ8–DQ14 =
High-Z, DQ15 =
A-1
Write (Note 1) LHL H (Note 4) AIN (Note 5 ) (Note 5)
Ac celerated Pro gra m
(No t e 6) LHL H V
HH AIN (Note 5) (Note 5)
Standby VCC ±
0.3 V XXVCC ±
0.3 V H X High-Z High-Z High-Z
Output Dis a ble L H H H L/H X High-Z High-Z High-Z
Reset X X X L L/H X High-Z High-Z High-Z
Sector Prot ec t (Note 3) LHL V
ID L/H SA, A6 = L,
A1 = H, A0 = L (Not e 5) XX
Sector Unprotect
(No t e 3) LHL V
ID (Note 4) SA, A6 = H,
A1 = H, A0 = L (Not e 5) XX
Temporary Sector
Unprotect XXX V
ID (Note 4) AIN (Note 5 ) (Note 5) High-Z
12 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset . This e nsures t hat no spurious alteration o f the m emory content occurs during th e powe r
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data out puts. The device remains enabled for read access until t he command register con -
tents are altered.
See Re a d i n g A rra y D at a on page 31 for more information. Refer to the AC Read Operations on
page 50 table for timing specifications and to Figu re 14, on page 50 f or the ti ming diagra m. ICC1
in the DC Characterist ics table represen ts t he active current specification for r eadi ng arr ay data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must dri ve WE# and CE# to VIL, and OE# to VIH.
For program opera tions, the BYTE# pin determines whether the device accepts program data in
bytes or words. Refer to Word/Byte Configuration (Models 03, 04 Only) on page 11 for more
information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program a word or byte,
instead of four. The Word/Byte Progra m Command Sequence on page 32 section has details on
programming data to the devi ce using both sta nda rd and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 14
and Table 4 on page 16 indicate the address space that each sector occupies. A sector address
consists of the address bits required to uniquely select a sector. The Command Definitions on
page 31 contains details on erasin g a sector or the enti re chip, or suspending/resumi ng the erase
operation.
After the system writes the autoselect command sequence, the device enters the autoselect
mode . The syste m can th en re ad au tosele ct code s from the i ntern al regi ster (w hich is sepa rate
from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to
Autoselect Mode on page 20 and Autoselect Command Sequence on page 32 for more
information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode.
AC Characteristics on page 50 contai ns ti ming s pecif ica tion ta bles a nd ti ming d ia gr ams f or write
operations.
Program and Erase Operation Status
During an er ase or progr am operation, the system may c heck the status of the oper ation by read-
ing th e status bits on DQ7 –DQ0. S tandard r ead cycle timi ngs and ICC re ad specificatio ns apply.
Refe r to Write Operation Status on page 39 for more information, and to AC Characteristi cs on
page 50 for timing diagrams.
Accelerated Program Operation
The d evice offers ac celerated program operations through the ACC function. This i s one of two
functi ons pro vided by the WP#/AC C (ACC on Model 00 ) pin. T his fu ncti on is pri marily intended t o
allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock
Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the
pin to reduce the time required for program operations. The system would use a two-cycle pro-
gram command seq uence as requir ed by the Unlock Bypas s mode. Removi ng VHH from the WP#/
ACC pi n r e turns the dev ice to no r m al ope ration . N o te that the WP#/ ACC pin must n o t be at VHH
for operations other than accelerated programming, or device damage may result. In addition,
June 13, 2005 S29AL032D_00_A3 S29AL032D 13
Advance Information
the WP#/ACC pin must not be left floa ting or unconnected; inconsistent behavior of the device
ma y result.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedanc e state, independent of the OE# input.
The device ent ers t he CMOS st andby mode when the CE# and RE SET# pins are bot h held at V CC
± 0.3 V. (Note that this i s a mor e restri cted vol tage r ange t han VIH.) If CE# and RESET# are held
at V IH, but no t with in VCC ± 0.3 V, the device will be in the standby mode, but the standby curren t
will be greate r. The device r equires st andard access time (t CE) for rea d access when the device i s
in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
In the DC Characteristics table, ICC3 and ICC4 represents the standby cur rent spec ification.
Automatic Sleep Mode
The automatic sleep mode mini mizes Flash device en ergy consumption. The devi ce automatically
enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. ICC4 in DC Characteristics on page 46 represents the automatic sleep
mode current specificat ion.
RESET#: Hardware Reset Pin
The RESET# pin pro vides a hardwa re method of resetting the device to reading array data. When
the system drives the RESET# pin to VIL for at least a period of tRP, the device immedia tely ter-
minates any operation in progress, tristates all data output pins, and ignores all read/write
attempts for the duration of the RESET# pulse. The device also resets the internal state machine
to reading ar ra y data. The oper ation that was in terrupted s hould be rein itiated onc e the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the
device dr aws CMOS s tandby curren t (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the
standby cur rent will be greate r.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read the boot-up firmware f rom the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (bu sy)
until the internal reset operation is complete, which requires a time of tREADY (during Embedded
Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is
complete. If RESET# is asserted when a progr am or erase operation is not executing (R Y/BY# pin
is 1), the reset operation is completed within a time of tREADY (not du ring Embedded Algorit hms).
The system can read data tRH after the RESET# pin returns to VIH.
Refer to AC Characteristics on page 50 for RESET# pa r ameters and to Figu re 15, on page 5 1 for
the timing diagra m.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in
the high impedance state.
14 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Ta b l e 2 . Model 00 Sector Addresses (Sheet 1 of 2)
Sector A21 A20 A19 A18 A17 A16 Address Range
(in hexadecimal)
SA0 0 0 0 0 0 0 000000–00FFFF
SA1 0 0 0 0 0 1 010000–01FFFF
SA2 0 0 0 0 1 0 020000–02FFFF
SA3 0 0 0 0 1 1 030000–03FFFF
SA4 0 0 0 1 0 0 040000–04FFFF
SA5 0 0 0 1 0 1 050000–05FFFF
SA6 0 0 0 1 1 0 060000–06FFFF
SA7 0 0 0 1 1 1 070000–07FFFF
SA8 0 0 1 0 0 0 080000–08FFFF
SA9 0 0 1 0 0 1 090000–09FFFF
SA10 0 0 1 0 1 0 0A0000–0AFFFF
SA11 0 0 1 0 1 1 0B0000–0BFFFF
SA12 0 0 1 1 0 0 0C0000–0CFFFF
SA13 0 0 1 1 0 1 0D0000–0DFFFF
SA14 0 0 1 1 1 0 0E0000–0EFFFF
SA15 0 0 1 1 1 1 0F0000–0FFFFF
SA16 0 1 0 0 0 0 100000–10FFFF
SA17 0 1 0 0 0 1 110000–11FFFF
SA18 0 1 0 0 1 0 120000–12FFFF
SA19 0 1 0 0 1 1 130000–13FFFF
SA20 0 1 0 1 0 0 140000–14FFFF
SA21 0 1 0 1 0 1 150000–15FFFF
SA22 0 1 0 1 1 0 160000–16FFFF
SA23 0 1 0 1 1 1 170000–17FFFF
SA24 0 1 1 0 0 0 180000–18FFFF
SA25 0 1 1 0 0 1 190000–19FFFF
SA26 0 1 1 0 1 0 1A0000–1AFFFF
SA27 0 1 1 0 1 1 1B0000–1BFFFF
SA28 0 1 1 1 0 0 1C0000–1CFFFF
SA29 0 1 1 1 0 1 1D0000–1DFFFF
SA30 0 1 1 1 1 0 1E0000–1EFFFF
SA31 0 1 1 1 1 1 1F0000–1FFFFF
SA32 1 0 0 0 0 0 200000–20FFFF
SA33 1 0 0 0 0 1 210000–21FFFF
SA34 1 0 0 0 1 0 220000–22FFFF
SA35 1 0 0 0 1 1 230000–23FFFF
SA36 1 0 0 1 0 0 240000–24FFFF
SA37 1 0 0 1 0 1 250000–25FFFF
SA38 1 0 0 1 1 0 260000–26FFFF
June 13, 2005 S29AL032D_00_A3 S29AL032D 15
Advance Information
Notes:
1. All sectors are 64 Kbytes in size.
Ta b l e 3 . Model 00 Secured Silicon Sector Addresses
SA39 1 0 0 1 1 1 270000–27FFFF
SA40 1 0 1 0 0 0 280000–28FFFF
SA41 1 0 1 0 0 1 290000–29FFFF
SA42 1 0 1 0 1 0 2A0000–2AFFFF
SA43 1 0 1 0 1 1 2B0000–2BFFFF
SA44 1 0 1 1 0 0 2C0000–2CFFFF
SA45 1 0 1 1 0 1 2D0000–2DFFFF
SA46 1 0 1 1 1 0 2E0000–2EFFFF
SA47 1 0 1 1 1 1 2F0000–2FFFFF
SA48 1 1 0 0 0 0 300000–30FFFF
SA49 1 1 0 0 0 1 310000–31FFFF
SA50 1 1 0 0 1 0 320000–32FFFF
SA51 1 1 0 0 1 1 330000–33FFFF
SA52 1 1 0 1 0 0 340000–34FFFF
SA53 1 1 0 1 0 1 350000–35FFFF
SA54 1 1 0 1 1 0 360000–36FFFF
SA55 1 1 0 1 1 1 370000–37FFFF
SA56 1 1 1 0 0 0 380000–38FFFF
SA57 1 1 1 0 0 1 390000–39FFFF
SA58 1 1 1 0 1 0 3A0000–3AFFFF
SA59 1 1 1 0 1 1 3B0000–3BFFFF
SA60 1 1 1 1 0 0 3C0000–3CFFFF
SA61 1 1 1 1 0 1 3D0000–3DFFFF
SA62 1 1 1 1 1 0 3E0000–3EFFFF
SA63 1 1 1 1 1 1 3F0000–3FFFFF
Sector Address
A20–A12 Sector Siz e
(bytes/words) (x8)
Address Range (x16)
Address Range
111111111 256/128 3FFF00h–3FFFFFh 1FFF80h–1FFFFFh
Table 2. Model 00 Sector Addresses (Sheet 2 of 2)
Sector A21 A20 A19 A18 A17 A16 Address Ra ng e
(in hexadecimal)
16 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Ta b l e 4 . Model 03 Sector Addresses (Sheet 1 of 2)
Sector Sector Address
A20–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
SA0 000000xxx 64/32 000000h–00FFFFh 000000h–07FFFh
SA1 000001xxx 64/32 010000h–01FFFFh 008000h–0FFFFh
SA2 000010xxx 64/32 020000h–02FFFFh 010000h–17FFFh
SA3 000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh
SA4 000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh
SA5 000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh
SA6 000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh
SA7 000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh
SA8 001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh
SA9 001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh
SA10 001010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh
SA11 001011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
SA12 001100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh
SA13 001101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
SA14 001110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh
SA15 001111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
SA16 010000xxx 64/32 100000h–10FFFFh 080000h–087FFFh
SA17 010001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh
SA18 010010xxx 64/32 120000h–12FFFFh 090000h–097FFFh
SA19 010011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh
SA20 010100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh
SA21 010101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
SA22 010110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
SA23 010111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
SA24 011000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh
SA25 011001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
SA26 011010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
SA27 011011xxx 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh
SA28 011100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh
SA29 011101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
SA30 011110xxx 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh
SA31 011111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
SA32 100000xxx 64/32 200000h–20FFFFh 100000h–107FFFh
SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA35 100011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
June 13, 2005 S29AL032D_00_A3 S29AL032D 17
Advance Information
Note: Th e ad d ress range is A2 0:A-1 in b yte mode (BYTE# =V
IL
) or A 2 0 :A0 in w o rd m o d e (B YT E # =V
IH
).
Ta b l e 5 . Model 03 Secured Silicon Sector Addresses
SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA52 110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh
SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh
SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh
SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh
SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh
SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh
SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh
SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh
Sector Address
A20–A12 Sector Siz e
(bytes/words) (x8)
Address Range (x16)
Address Range
111111111 256/128 3FFF00h–3FFFFFh 1FFF80h–1FFFFFh
Table 4. Model 03 Sector Addresses (Sheet 2 of 2)
Sector Sector Address
A20–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
18 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Ta b l e 6 . Model 04 Sector Addresses (Sheet 1 of 2)
Sector Sector Address
A20–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
SA0 000000000 8/4 000000h-001FFFh 000000h–000FFFh
SA1 000000001 8/4 002000h-003FFFh 001000h–001FFFh
SA2 000000010 8/4 004000h-005FFFh 002000h–002FFFh
SA3 000000011 8/4 006000h-007FFFh 003000h–003FFFh
SA4 000000100 8/4 008000h-009FFFh 004000h–004FFFh
SA5 000000101 8/4 00A000h-00BFFFh 005000h–005FFFh
SA6 000000110 8/4 00C000h-00DFFFh 006000h–006FFFh
SA7 000000111 8/4 00E000h-00FFFFh 007000h–007FFFh
SA8 000001xxx 64/32 010000h-01FFFFh 008000h–00FFFFh
SA9 000010xxx 64/32 020000h-02FFFFh 010000h–017FFFh
SA10 000011xxx 64/32 030000h-03FFFFh 018000h–01FFFFh
SA11 000100xxx 64/32 040000h-04FFFFh 020000h–027FFFh
SA12 000101xxx 64/32 050000h-05FFFFh 028000h–02FFFFh
SA13 000110xxx 64/32 060000h-06FFFFh 030000h–037FFFh
SA14 000111xxx 64/32 070000h-07FFFFh 038000h–03FFFFh
SA15 001000xxx 64/32 080000h-08FFFFh 040000h–047FFFh
SA16 001001xxx 64/32 090000h-09FFFFh 048000h–04FFFFh
SA17 001010xxx 64/32 0A0000h-0AFFFFh 050000h–057FFFh
SA18 001011xxx 64/32 0B0000h-0BFFFFh 058000h–05FFFFh
SA19 001100xxx 64/32 0C0000h-0CFFFFh 060000h–067FFFh
SA20 001101xxx 64/32 0D0000h-0DFFFFh 068000h–06FFFFh
SA21 001110xxx 64/32 0E0000h-0EFFFFh 070000h–077FFFh
SA22 001111xxx 64/32 0F0000h-0FFFFFh 078000h–07FFFFh
SA23 010000xxx 64/32 100000h-10FFFFh 080000h–087FFFh
SA24 010001xxx 64/32 110000h-11FFFFh 088000h–08FFFFh
SA25 010010xxx 64/32 120000h-12FFFFh 090000h–097FFFh
SA26 010011xxx 64/32 130000h-13FFFFh 098000h–09FFFFh
SA27 010100xxx 64/32 140000h-14FFFFh 0A0000h–0A7FFFh
SA28 010101xxx 64/32 150000h-15FFFFh 0A8000h–0AFFFFh
SA29 010110xxx 64/32 160000h-16FFFFh 0B0000h–0B7FFFh
SA30 010111xxx 64/32 170000h-17FFFFh 0B8000h–0BFFFFh
SA31 011000xxx 64/32 180000h-18FFFFh 0C0000h–0C7FFFh
SA32 011001xxx 64/32 190000h-19FFFFh 0C8000h–0CFFFFh
SA33 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh
SA34 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh
SA35 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h–0E7FFFh
SA36 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh
SA37 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh
SA38 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh
June 13, 2005 S29AL032D_00_A3 S29AL032D 19
Advance Information
Note: Th e ad d ress range is A2 0:A-1 in b yte mode (BYTE# =V
IL
) or A 2 0 :A0 in w o rd m o d e (B YT E # =V
IH
).
Ta b l e 7 . Model 04 Secured Silicon Sector Addresses
SA39 100000xxx 64/32 200000h-20FFFFh 100000h–107FFFh
SA40 100001xxx 64/32 210000h-21FFFFh 108000h–10FFFFh
SA41 100010xxx 64/32 220000h-22FFFFh 110000h–117FFFh
SA42 100011xxx 64/32 230000h-23FFFFh 118000h–11FFFFh
SA43 100100xxx 64/32 240000h-24FFFFh 120000h–127FFFh
SA44 100101xxx 64/32 250000h-25FFFFh 128000h–12FFFFh
SA45 100110xxx 64/32 260000h-26FFFFh 130000h–137FFFh
SA46 100111xxx 64/32 270000h-27FFFFh 138000h–13FFFFh
SA47 101000xxx 64/32 280000h-28FFFFh 140000h–147FFFh
SA48 101001xxx 64/32 290000h-29FFFFh 148000h–14FFFFh
SA49 101010xxx 64/32 2A0000h-2AFFFFh 150000h–157FFFh
SA50 101011xxx 64/32 2B0000h-2BFFFFh 158000h–15FFFFh
SA51 101100xxx 64/32 2C0000h-2CFFFFh 160000h–167FFFh
SA52 101101xxx 64/32 2D0000h-2DFFFFh 168000h–16FFFFh
SA53 101110xxx 64/32 2E0000h-2EFFFFh 170000h–177FFFh
SA54 101111xxx 64/32 2F0000h-2FFFFFh 178000h–17FFFFh
SA55 111000xxx 64/32 300000h-30FFFFh 180000h–187FFFh
SA56 110001xxx 64/32 310000h-31FFFFh 188000h–18FFFFh
SA57 110010xxx 64/32 320000h-32FFFFh 190000h–197FFFh
SA58 110011xxx 64/32 330000h-33FFFFh 198000h–19FFFFh
SA59 110100xxx 64/32 340000h-34FFFFh 1A0000h–1A7FFFh
SA60 110101xxx 64/32 350000h-35FFFFh 1A8000h–1AFFFFh
SA61 110110xxx 64/32 360000h-36FFFFh 1B0000h–1B7FFFh
SA62 110111xxx 64/32 370000h-37FFFFh 1B8000h–1BFFFFh
SA63 111000xxx 64/32 380000h-38FFFFh 1C0000h–1C7FFFh
SA64 111001xxx 64/32 390000h-39FFFFh 1C8000h–1CFFFFh
SA65 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh
SA66 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh
SA67 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h–1E7FFFh
SA68 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh
SA69 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh
SA70 111111xxx 64/32 3F0000h-3FFFFFh 1F8000h–1FFFFFh
Sect or Address
A20–A12 Sector Size
(bytes/words) (x8)
Address Range (x16)
Address Range
000000000 256/128 000000h-0000FFh 00000h-0007Fh
Table 6. Model 04 Sector Addresses (Sheet 2 of 2)
Sector Sector Address
A20–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
20 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Autoselect Mode
The autoselect mode provides manufacturer and device ident ification, and sector protection ve r-
ification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
progra mming equipment to automatic ally match a device t o be programmed with it s correspond -
ing programming algorithm. However, the autoselect codes can also be accessed in-system
through the command regis ter.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on
address pin A9. Addres s pins A6, A1, and A0 mu st be as sh own in Table 8. In addition, when ver-
ifying sector protection, the sector address must appear on th e appropriate highes t order address
bits (see Table 2 on page 14 and Table 4 on page 16). Table 8 sh o w s th e re maini ng ad dress bits
that are don’t care. When all necessary bits have been set as required, the programming equip-
ment may then read the corres ponding identif ier code on DQ7-DQ0.
To access the auto select codes in-s ystem, th e host sys tem can i ssue the au tosele ct command vi a
the command register, as shown in Table 17 on page 38. This m e tho d d o e s no t r e qui r e V ID. See
“Command Definitions” for det ails on usin g th e au toselect mode.
Ta b l e 8 . S29AL032D Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: T he auto select codes may also be accessed in-system via comman d sequences. See Table 17 on page 38.
Sector Protection/Unprotection
The hardware sect or protection feature disables bot h program and erase oper ations in any sect or.
The hardware sector unprotection feature re-enables both progra m and erase opera tions in pre-
viously protected sectors.
Description Mode CE# OE# WE# A19
to
A12
A11
to
A10 A9 A8
to
A7 A6 A5
to
A4
A3
to
A2 A1 A0 DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: Spansion LLHXXV
ID XLXLLL X 01h
Device ID:
S29AL032D
(Model 00) Byte L L H X X VID XLXLLHN/A A3h
Device ID:
S29AL032D
(Model 03)
Word L L H XXV
ID XLXLLH22h F6h
Byte L L H XF6h
Device ID:
S29AL032D
(Model 04)
Word L L H XXV
ID XLXLLH22h F9h
Byte L L H XF9h
Sector Protection
Verification LLHSAXV
ID XLXLHL
X 01h (protected)
X00h
(unprotected)
Secured Silicon Sector
Indicator B it (DQ7)
(Model 00) LLHXXV
ID XLXLHH
X85 (factory
locked)
X05 (not factory
locked)
Secured Silicon Sector
Indicator B it (DQ7)
(Model 03) LLHXXV
ID XLXLHH
X8D (factory
locked)
X0D (not factory
locked)
Secured Silicon Sector
Indicator B it (DQ7)
(Model 04) LLHXXV
ID XLXLHH
X9D (factory
locked)
X1D (not factory
locked)
June 13, 2005 S29AL032D_00_A3 S29AL032D 21
Advance Information
The device is shipped with all sectors unprotected. Spansion offers the option of programming
and protecting sectors at its factory prior to shipping the device through the Spansion Express-
Flash™ Service. Cont act a Spansion repres e n tative for further details.
It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode”
for d etai ls.
Sector protection/unprotection can be implemented via two methods.
The primary method req uires VID on the RE SET# pin only, and can be implemented ei ther in-sys-
tem or via programming equipment. Figure 2, on page 25 show s the algorith ms and Figure 2 6,
on page 59 sh ows th e tim ing dia gr am . T his me thod us es st anda rd mi cro proce ssor bus cy cl e t im -
ing. For sect or un prote ct, all unpro tec ted se ctor s must first b e prot ected prior to the fir st sec tor
unprotect wri te cycle.
The alternate method intended only for programming equipmen t requ ires VID on address pin A9
and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only
Spansio n flash devi ces. Detail s on this met hod are provided in a su pplement, publicat ion number
21468. Contact a Spansion repre sent ative to request a copy.
Ta b l e 9 . Sector Block Addresses for Protection/Unprotection — Model 00
Sector/S ector Block A21–A16 Sector/Sector Block Size
SA0 000000 64 Kbytes
SA1-SA3 000001,000010,
000011 192 (3x64) Kbytes
SA4-SA7 000100, 000101,
000110, 000111 256 (4x64) Kbytes
SA8-SA11 001000, 001001,
001010, 001011 256 (4x64) Kbytes
SA12-SA15 001100, 001101,
001110, 001111 256 (4x64) Kbytes
SA16-SA19 010000, 010001,
010010, 010011 256 (4x64) Kbytes
SA20-SA23 010100, 010101,
010110, 010111 256 (4x64) Kbytes
SA24-SA27 011000, 011001,
011010, 011011 256 (4x64) Kbytes
SA28-SA31 011100, 011101,
011110, 011111 256 (4x64) Kbytes
SA32-SA35 100000, 100001,
100010, 100011 256 (4x64) Kbytes
SA36-SA39 100100, 100101,
100110, 100111 256 (4x64) Kbytes
SA40-SA43 101000, 101001,
101010, 101011 256 (4x64) Kbytes
SA44-SA47 101100, 101101,
101110, 101111 256 (4x64) Kbytes
SA48-SA51 110000, 110001,
110010, 110011 256 (4x64) Kbytes
SA52-SA55 110100, 110101,
110110, 110111 256 (4x64) Kbytes
SA56-SA59 111000, 111001,
111010, 111011 256 (4x64) Kbytes
SA60-SA62 111100, 111101,
111110 192 (4x64) Kbytes
SA63 111111 64 Kbytes
22 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Ta b l e 1 0 . Sector Block Addresses for Protection/Unprotection — Model 03
Sector / Sector Block A20–A12 Sector/Sector Block Size
SA0-SA3
000000XXX,
000001XXX,
000010XXX
000011XXX
256 (4x64) Kbytes
SA4-SA7 0001XXXXX 256 (4x64) Kbytes
SA8-SA11 0010XXXXX 256 (4x64) Kbytes
SA12-SA15 0011XXXXX 256 (4x64) Kbytes
SA16-SA19 0100XXXXX 256 (4x64) Kbytes
SA20-SA23 0101XXXXX 256 (4x64) Kbytes
SA24-SA27 0110XXXXX 256 (4x64) Kbytes
SA28-SA31 0111XXXXX 256 (4x64) Kbytes
SA32-SA35 1000XXXXX 256 (4x64) Kbytes
SA36-SA39 1001XXXXX 256 (4x64) Kbytes
SA40-SA43 1010XXXXX 256 (4x64) Kbytes
SA44-SA47 1011XXXXX 256 (4x64) Kbytes
SA48-SA51 1100XXXXX 256 (4x64) Kbytes
SA52-SA55 1101XXXXX 256 (4x64) Kbytes
SA56-SA59 1110XXXXX 256 (4x64) Kbytes
SA60-SA62 111100XXX,
111101XXX,
111110XXX 192 (3x64) Kbytes
SA63 111111000 8 Kbytes
SA64 111111001 8 Kbytes
SA65 111111010 8 Kbytes
SA66 111111011 8 Kbytes
SA67 111111100 8 Kbytes
SA68 111111101 8 Kbytes
SA69 111111110 8 Kbytes
SA70 111111111 8 Kbytes
June 13, 2005 S29AL032D_00_A3 S29AL032D 23
Advance Information
Write Protect (WP#) — Models 03, 04 Only
The W rite Protect function pr ovides a hardw are method of pr otecting c ertain boot sectors withou t
using VID. This fu nction i s one of two prov ided by the WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the device disables progra m and erase functions
in the two outermost 8 Kbyte boot sectors independently of whether those sectors were protected
or unprotected using the method described in Sector Protection/Unprotection on page 20. The
two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bot-
tom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-
configured device.
If the system asserts V IH on the WP#/ACC pin, the device reverts to whether the two outermost
8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or
unprotection for these two sectors depends on whether they were last protected or unprotected
using the method described in Sector Protec tion/Unprotection on page 20.
Note tha t the WP#/ACC pin must not be le ft floa ting or unconnected ; inconsis tent beh avior of the
device may result.
Ta b l e 1 1 . Sector Block Addresses for Protection/Unprotection — Model 04
Sector / Sector Block A20–A12 Sector/Sector Block Size
SA70-SA67
111111XXX,
111110XXX,
111101XXX,
111100XXX
256 (4x64) Kbytes
SA66-SA63 1110XXXXX 256 (4x64) Kbytes
SA62-SA59 1101XXXXX 256 (4x64) Kbytes
SA58-SA55 1100XXXXX 256 (4x64) Kbytes
SA54-SA51 1011XXXXX 256 (4x64) Kbytes
SA50-SA47 1010XXXXX 256 (4x64) Kbytes
SA46-SA43 1001XXXXX 256 (4x64) Kbytes
SA42-SA39 1000XXXXX 256 (4x64) Kbytes
SA38-SA35 0111XXXXX 256 (4x64) Kbytes
SA34-SA31 0110XXXXX 256 (4x64) Kbytes
SA30-SA27 0101XXXXX 256 (4x64) Kbytes
SA26-SA23 0100XXXXX 256 (4x64) Kbytes
SA22–SA19 0011XXXXX 256 (4x64) Kbytes
SA18-SA15 0010XXXXX 256 (4x64) Kbytes
SA14-SA11 0001XXXXX 256 (4x64) Kbytes
SA10-SA8 000011XXX,
000010XXX,
000001XXX 192 (3x64) Kbytes
SA7 000000111 8 Kbytes
SA6 000000110 8 Kbytes
SA5 000000101 8 Kbytes
SA4 000000100 8 Kbytes
SA3 000000011 8 Kbytes
SA2 000000010 8 Kbytes
SA1 000000001 8 Kbytes
SA0 000000000 8 Kbytes
24 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Temporary Sector Unprotect
This f eature allows tempor ary unprot ection of previ ously protected sectors to ch ange dat a in- sys -
tem. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode,
formerly protected sectors can be programmed or erased by selecting the sector addresses. Once
VID is removed from the RESET# pin, all the previously protected sectors are protected again.
shows the a l gorithm, and Fi gure 24, on page 58 shows the timing diagrams, for this feature.
Figure 1. Temporary Sector Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protecte d sectors a re protected once
again.
June 13, 2005 S29AL032D_00_A3 S29AL032D 25
Advance Information
Figure 2. In-System Sector Protect/Unprotect Algorithms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
Data = 00h?
Last sector
verified?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm
Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
26 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a 256 byte Flash memory region that enables per-
manent part ident ification through an Electroni c Serial Number ( ESN). The Secur ed Sili con Sector
uses a Se cu r e d Si li co n Se ctor I nd i cator Bit (DQ7 ) to indicat e whe ther o r no t the Se cu r e d Si li co n
Sector is locked when shipped from the factory. This bit is permanently set at the factory and can-
not be c hanged, which prevents cloning of a factory lo ck ed part. This ensures the security of the
ESN once the product is shipped to the f ield.
Spansion offers the devi ce with the Secured Sil icon Sect or either factory locked or customer loc k-
able. The factory-locked version is always protected when shipped from the factory, and has the
Secured Silicon Sector Indicator Bit permanently set to a 1. The customer-lockable version is
shipped with the Secured Silicon Sector unprotected, allowing customers to utilize the that sector
in any manner they choose. The customer-lockable version h as th e Secur ed Si licon Sect or Ind i-
cator Bit permanently set to a 0. Thus, the Secured Silicon Sector Indicator Bit prevents
customer-lockable devices from being used to replace devices that are factory loc ked.
The system a ccesses the Secur ed Silicon Sector through a comm and sequ ence (s ee Enter Se-
cured Silicon Sector/Exit Secured Silicon Sector Command Sequence on page 32). After the
syste m writes t he Ent er Secur ed Sili con Sec tor command se quenc e, it ma y read th e Secure d Sil -
icon Sector by using the addresses normally occupied by the boot sectors. Thi s mode of opera tion
continues until the system issues the Exit Secured Silicon Sector command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts
to sending commands to the boot sectors.
Factory Loc ked: Secu re d Si l ic on Sector Pro gr ammed
and Protected at the Factory
In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from
the factory. The Secured Silicon Sector cannot be modified in any way . The device is available pre-
progra mmed wi th one of th e fo llowing:
A random, secure ESN only
Customer code through the ExpressFlash service
Both a random, secure ESN and customer code through the ExpressFlash service.
In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at
addresses 00000h–0000Fh i n byte mode (or 00000h–00007h in word mode). In the Top Boot de -
vice the ESN is in sector 70 at addresses 3FFF00h–3FFF0Fh in byte mode (or 1FFF80h–1FFF87h
in word mode). In the Uniform device the ESN is in sector 63 at addresses 3FFF00h-3FFF0Fh in
byte mode (or 1FFF80h-1FFF87h in word mode).
Customers ma y opt to have their code pr ogrammed by Spansion through t he S p ansion Ex press-
Flash service. Spansion programs the customer’s code, with or without the random ESN. The
devices are then shipped from the Spansion factory with the Secured Silicon Sector permanently
locked. Contact a Spansion representat ive for details on us ing the Spansion ExpressFlash ser vice.
Customer Lockable: Secured Silicon Sector NOT Programmed
or Protected at the Factory
The customer lockable version allows the Secured Silicon Sector to be programmed once and then
perman en tly lo cked after i t sh ips fr om Span sion. Not e that the acc elerated p rogramm ing ( AC C)
and unlock bypass functions are not available when programming the Secured Sili con Sector.
The Secured Silicon Sector ar ea can be protected using the following procedures:
Write the three-cycle Enter Secured Silicon Region comman d sequence, and t hen follow the
in-system sector protect algorithm as shown in Figure 2, on page 25, except that RESET#
may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector
June 13, 2005 S29AL032D_00_A3 S29AL032D 27
Advance Information
without raising any device pin to a high voltage. Note that this method is only applicable to
the Secured Silicon Sector.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm
shown in Figure 3, on page 27.
Once the Secur ed Silicon Sector is locked and verified, th e system must writ e the Exit Secured
Silic on Secto r Region com mand seq uence to return to rea ding and w riting the remain der of th e
array.
The Secured Silicon Sector protection must be used with caution since, once protected, there is
no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in
the Secured Silicon Sector memory space can be modified in any way.
Figure 3. Secured Silicon Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (refer to Table 17 on page 38 for co m mand definition s) . In
addition, the following hardware data protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spurious system level signals during VCC
power-up and power -down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less th an VLKO, the device does no t accept any write cy cles. This protects data during
VCC power-up and power-down. The command register an d all internal program/er ase circuit s are
disabled, and t he device resets. Subsequent writes are ignored un til VCC is greater than VLKO. The
system must provide the proper s ignals to the control pins to prevent unintentional writes when
VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logi ca l I nhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To init ia te
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
START
RESET# =
V
IH
or V
ID
Wait 1 μs
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove V
IH
or V
ID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
28 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on
the rising edge of WE#. The internal state machine is automatically reset to reading array data
on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified software algorithms to be used for
entire famil ies of dev ic es. Softwar e support can then be devi ce-in depende nt, JED EC ID-inde pen-
dent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize th eir existing int erf aces fo r long-term compatibility.
This device e nters the CFI Qu ery mode when t he system writes the CFI Query c ommand, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read
arra y data. The system can read CFI infor mation at the addresses given in Tables 12–15. In word
mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the
system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode.
The device enter s th e CFI query mode, and the system can read CFI data at the addresses given
in Tables 12–15. The system must write t he reset com mand to r eturn the de vice to the aut oselect
mode.
For further information, plea se contact a Spa nsion representativ e for a copy of this document.
Ta b l e 1 2 . CFI Query Identification String
Addresses
Addresses
(Models 03, 04
Byte Mode
Only) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h Query Unique ASCII string QRY
13h
14h 26h
28h 0002h
0000h Primary OEM Command Set
15h
16h 2Ah
2Ch 0040h
0000h A ddres s for Primary Extended Table
17h
18h 2Eh
30h 0000h
0000h A lternate OEM Command Set ( 0 0h = none ex is ts)
19h
1Ah 32h
34h 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
June 13, 2005 S29AL032D_00_A3 S29AL032D 29
Advance Information
Ta b l e 1 3 . System Interface String
Addresses
Addresses
(Models 03, 04
Byte Mode
Only) Data Description
1Bh 36h 0027h V
CC
Min. (w rite/er a s e )
D7– D4: vo lt , D3–D0: 100 millivolt
1Ch 38h 0036h V
CC
Max. (write/erase )
D7– D4: vo lt , D3–D0: 100 millivolt
1Dh 3Ah 0000h V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh 3Ch 0000h V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh 3Eh 0004h Typic al time out per single byte/word write 2
N
µs
20h 40h 0000h Ty pica l timeout for Min. size b uffer write 2
N
µs (00h = n ot su pported)
21h 42h 000Ah Typical timeou t per individual block er a s e 2
N
ms
22h 44h 0000h Ty pic a l timeout for full chi p e rase 2
N
ms (00h = not supported)
23h 46h 0005h Max. time out for byt e/word write 2
N
time s t ypical
24h 48h 0000h Max. timeout for bu ffer write 2
N
times typical
25h 4Ah 0004h Max. time out pe r individua l block er a s e 2
N
time s ty pical
26h 4Ch 0000h Max. timeout for full chip erase 2
N
times typical (00h = not supported)
30 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Ta b l e 1 4 . Device Geometry Definition
Addresses
Addresses
(Models 03, 04
Byte Mode
Only) Data Description
27h 4Eh 0016h Device Size = 2
N
byte
28h
29h 50h
52h 000xh
0000h Fla sh Device I nte rface description (refer to CFI publication 100)
(0 = Model 00, 2 = Models 03, 04)
2Ah
2Bh 54h
56h 0000h
0000h Ma x. numbe r of byte in multi-byte w rite = 2
N
(00h = not supported)
2Ch 58h 000xh Nu m ber of Era s e Block Regions within dev ice
(1 = Model 00, 2 = Models 03, 04)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
0000h
00x0h
000xh
Erase Block Region 1 Information
(refe r to the CFI specific a tion or CFI publication 10 0)
(003F, 0000, 0000, 00 01) = Mo del 00
(0007, 0000, 0020, 0000) = Models 03, 04
31h
32h
33h
34h
62h
64h
66h
68h
00xxh
0000h
0020h
000xh
Erase Block Region 2 Information
(0000, 0000, 0000, 0000) = Model 00
(003E, 0000, 0000, 0001) = Mod e ls 03, 04
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
Ta b l e 1 5 . Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Addresses
Addresses
(Models 03, 04
Byte Mode
Only) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 86h 0031h Major v ersion number, ASCII
44h 88h 0031h Minor version number, ASCII
45h 8Ah 000xh Addre s s Se nsitive Unlock
0 = Required (Models 03, 04), 1 = Not Required (Mo del 00)
46h 8Ch 0002h Erase Suspend
0 = Not Su pported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = No t Su pported, X = Nu m ber of sectors in per grou p
June 13, 2005 S29AL032D_00_A3 S29AL032D 31
Advance Information
Command Definitions
Writing specific address and data commands or sequences into the command register initiates
device operations. Table 17 on page 38 defines the valid register command sequences. Writing
incorrect address and data values or writing t hem in the improper seq uence resets t he de-
vice to reading array data.
All address es are latc hed on t he fal lin g edge of WE# or CE#, wh ichev er happens later. All data is
latched on the ri sing ed ge of WE# or C E#, whiche ver happ ens first . R efer to the appro priate tim -
ing diagr a ms in the “A C Ch aracteris tics ” section.
Reading Array Data
The de vice is auto matically s et to readi ng array data af ter devi ce power-up. No commands are
required to retrieve data. The device is also ready to read array data after completing an Embed -
ded Progr am or E mbedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an ad-
dress within erase-suspended sectors, the device outputs status data. After completing a
progra mming oper ation in the Er ase Sus pend mode, the system may once again read array data
with the same exceptio n. See Erase Suspend/Erase R esume Commands on page 35 for more in-
formation on this mode.
The system must issue the reset command to re-enable the device for readi ng arra y dat a if DQ5
goes high, or while in the autoselect mode. See the Reset Command on page 32 sectio n, next.
See also Requirements for Reading Array Data on page 11 for more information. The Read
Operations on page 50 provides the read parameters, and Figure 14, on page 50 shows the timing
diagram.
48h 90h 0001h Sector Tempor a ry U n protect
00 = N o t Supported, 01 = Supported
49h 92h 0004h Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV 800A mode
4Ah 94h 0000h Simu lta ne ous Oper ation
00 = N o t Supported, 01 = Supported
4Bh 96h 0000h Burst Mode Type
00 = N o t Supported, 01 = Supported
4Ch 98h 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 9Ah 00B5h ACC (Accelera tion) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 9Ch 00C5h ACC (Ac c e le ratio n) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 9Eh 000xh Top/Bottom Boot Sector Flag
(0 = Model 00, 2 = Model 03, 3 = Model 04)
Table 15. Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses
Addresses
(Models 03, 04
Byte Mode
Only) Data Description
32 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Reset Command
Wr iting the reset command to the devi ce resets the device to reading arra y data. Address bits are
don’t care for this command.
The reset command may be written between the sequence cy cles in an er ase command sequence
before erasing begins. This resets the device to reading array data. Once erasure begins, however,
the device ignores reset commands until the operat ion is complete.
The reset command may be written between the sequence cycles in a program command se-
quence before programming begins. This resets the device to reading array data (also applies to
programming in Erase Suspend mode). Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command se-
quence. Once in the autoselect mode, the reset command must be w ritte n to r eturn t o rea ding
array data (als o applies to a ut oselect during Er as e Su spend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the
device to rea ding array data (also applies du ring Er as e Su spend).
Autoselect Command Sequence
The au toselect c ommand seq uence allo ws the host syste m to access the manufac turer and d e-
vices codes, and determine whether a sector is protected. Table 17 on page 38 shows the address
and data requirements. This method is an alternative to that shown in Table 8 on page 20, which
is intended for PROM programmers and requires VID on address bit A9 .
The autoselect command sequence is initiated by writing two unlock cycles, followed by the au-
tosel ect command. The device t hen ente rs the aut oselect mode, and the s ystem ma y read at an y
address any number of times, without initiating another command sequence.
A read cycle at address 0XXX00h retrieves the manufacturer code. A read cycle at address
0XXX01h returns the device code. A read cycle containing a sector address (SA) and the address
02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is
unprote cted. Refer to Table 2 on page 14 and Table 4 on page 16 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading
array data.
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, sixteen-
byte electron ic serial nu mber (ESN). The system can access the Secu red Silicon Sector region by
issuing t he three-c ycle En ter Sec ured Sili con Sector comman d sequence. The device co ntinues to
access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Sili-
con Sector command sequence. The Exit Secured Silicon Sector command sequence returns the
device to normal operation. Table 16. S29AL032D Command Definitions — Model 00 on page 37
and Table 17. S29AL032D Command Definitions — Models 03, 04 on page 38 show the ad-
dresses and data requirements for both command sequences. Note that the ACC function and
unlock bypass modes are not available when the device enters the Secured Silicon Sector. See
also Secured Silicon Sector Flash Memory Region on page 26 for fur ther in format i on.
Word/Byte Program Command Sequence
Models 03, 04 may program the device by word or byte, depending on the state of the BYTE#
pin. Model 00 may pro gram the device by byte only. Programming is a four-bus-cycle opera tion.
The program command sequence is initiated by writing two unlock write cycles, followed by the
progra m set-up com mand. The progr am address a nd data are writte n next, which in turn initi ate
June 13, 2005 S29AL032D_00_A3 S29AL032D 33
Advance Information
the Embedded Program algor it hm. T he s ys tem i s not required to provide further controls or tim-
ings. The device automatically generates the program pulses a nd verifies the programmed cell
margin. Table 17 on page 38 shows the address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array
data and addresses are no longer latched. The system can determine the status of the program
operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status on page 39 for information
on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note
that a hardware reset immediately terminates the programming operation. The Byte Program
command s e que nce sh ould be reinitiated once the de vice ha s reset to read ing array data, t o en-
sure data inte grity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-
gram me d from a 0 back to a 1. A tt empt ing to do so ma y halt the operation and set D Q5 to 1,
or cause the Data# Polling algorithm to indicate the operation was successful. However, a suc-
ceeding read will show that the data is still 0. Only erase oper ations can conv ert a 0 to a 1.
Unlock Bypass Command Sequence
The unlock by pass featur e allows the system to p rogra m bytes or words to t he device faster than
using th e standard program command sequence. The un lock bypass command sequen ce is ini ti-
ated by firs t writ ing two unlock cy cles. This is fo llowed by a third write cy cle containing t he unlock
bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program command, A0h; the second cycle contains
the program address and data. Additional data is program med in the same manner. This mode
dispenses with the initial two unlock cycles required in the standard program command sequence,
resultin g in faster total prog ramming time. Table 17 on pa ge 38 shows the requirements for the
command sequence.
During the u nlock bypas s mode, onl y the U nlock Bypass Progr am a nd Unlo ck Byp ass R es et com -
mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the
data 00h. Addresses a re don’t care for both cyc les. The device then returns to reading arr ay data.
Figure 4, on page 34 il lustr ates the algo rithm for t he progr am oper ation. See the Erase/Program
Operations on page 54 for paramet ers, and to Figur e 18, on page 55 for timing diagrams.
34 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
NOTE: S ee Tabl e 17 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip eras e is a six bus cycle operation. The chip erase command sequenc e is in itiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogr am prior to er ase. The Embedded Er ase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required t o prov ide any cont rols o r timings during t hese o per -
ations. Table 17 on page 38 shows the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that
a hardware reset during the chip erase operation immediately terminates the operation. The
Chip Erase command sequence should be reinitiated once the device has returned to reading
array data, to ensure da ta integrit y.
The system can determine the status of the erase oper ation by using DQ7, DQ6, DQ2, or RY/BY#.
See Write Operation Status on page 39 for information on these status bits. When the Embedded
Erase algorithm is complete, the device returns to reading array data and addresses are no longer
latched.
Figure 5, on page 36 illustrates the algorithm for the erase operation. See Erase/Program
Operations on page 54 for paramet ers, and to Figur e 19, on page 56 for timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
June 13, 2005 S29AL032D_00_A3 S29AL032D 35
Advance Information
Sector Erase Command Sequence
Sector er ase is a six bus cycle o peration. The sector er ase command sequence is initi ated by writ -
ing two unlo ck cycles, foll owed by a set-up command. Two additional unlock wr ite cycles ar e then
followed by the address of the sector to be erased, and the sector erase command. Table 17 on
page 38 shows the address and data requirements for the sector erase command sequence.
The device do es not require the system to preprogr am the memory prior t o erase. The Embedded
Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior
to electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-
out period, additional sector addresses and sector erase commands may be written. Loading the
sector erase buffer may be done in any sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise
the last address and command might not be accepted, and er asure may begin. It is recommended
that proc essor int errupts be disabled dur ing this ti me to ensure all commands are accept ed. The
interrupts c an be re-enabled after the l ast Sec tor Er ase c ommand is wri tten. If t he t ime between
additional sector erase commands can be assumed to be less than 50 µs, the system need not
monitor DQ3. Any command othe r than Sec tor Erase or Erase Suspend during the time-
out period reset s the devic e to readi n g array data. The system must rewrite the command
sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3:
Sect or Er as e Tim er” secti on.) The time-ou t begins from the rising edge of the final WE# pulse in
the comm and sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands a re ignored. Note tha t a h ard ware reset during the sector erase operation immedi-
ately terminates the operation. The Sector Erase command sequence should be reinitiated once
the device has returned to reading arr ay data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of t he erase operation by
using DQ7, DQ6, DQ2, or RY/BY#. (Refer to “Write Operation Status” for information on these
statu s bits.)
Figure 5, on page 36 illustrates the algorithm for the erase operation. Refer to Erase/Program
Operations on page 54 for paramet ers, and to Figur e 19, on page 56 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase opera tion and then
read d ata from, o r program da ta to, any sector not select ed for e rasure. This co mmand is valid
only during the sector erase operation, including the 50 µs time-out period during the sector erase
command sequence. The Er ase Suspend c ommand is i gnored i f wri tten dur ing t he chip er ase op -
eratio n or Embedded Progr am algo ri thm. W ri t ing th e Er ase Suspend c ommand duri ng th e Sector
Erase time-out immediately terminates the time-out period and suspends the erase operation.
Addresse s ar e don’t-cares when writing the Erase Suspen d command.
When the Eras e Suspend command is written du ring a sector erase operation, the devi ce requi res
a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command
is written during the sector erase time-out, the device immediately terminates the time-out pe-
riod and suspends t he erase operation.
After the erase operation has been suspended, the system can read array data from or program
data to any s ector not se lected for e rasu re. (The dev ice erase suspends all secto rs selecte d for
erasure.) Normal read and write timings and command definitions apply. R eading at any address
36 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
within er ase-sus pended sec tors produ ces status dat a on DQ7–DQ0. Th e system can u se DQ7, or
DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See
Write Operation Status on page 39 for information on these status bits.
After an erase-suspende d prog ram operation is complete, th e system can once ag ai n rea d array
data within non-suspended sect ors. The system can determi ne the status of the program opera-
tion using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write
Oper ation Sta tus on page 39 for more information.
The system may also write the autoselect command sequence when the device is in the Erase
Suspend mode. The device allows reading autoselect codes even at addresses within erasing sec-
tors, since the codes are not stored in the memory array. When the device exits the autoselect
mode, the device reverts to the Erase Suspend mode, and is ready for another va lid operation.
See Autoselect Command Sequence on page 32 for more information.
The system must write the Erase R esume command (address bits are don’t care) to exi t the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command
are ignored. Another Erase Suspend command can be written after the device has resumed
erasing.
Notes:
1. See Table 17 for erase command sequence.
2. See D Q3 : Sector Erase Timer on page 44 for more information.
Figure 5. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
June 13, 2005 S29AL032D_00_A3 S29AL032D 37
Advance Information
Command Definitions
Ta b l e 1 6 . S29AL032D Command Definitions — Model 00
Legend:
X = Don’t care, RA = Address of the memory location to be read, RD = Data read from location RA during read operation,
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE#
pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA = Address
of the sector to be erased or verified. Address bits A21–A16 uniquely select any sector.
Notes:
1. See Table 1 on page 11 for descriptions of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Address bits are don’t care for unlock and command cycles, except when PA or SA is required.
5. No unlock or command cycles required when device is in read mode.
6. The Reset co mmand is required to return to the read mode when the device is in the autoselect mod e or if D Q5 g oes high.
7. The fourth cy cle of the autoselect command sequence is a read cycle.
8. In the third and fourth cycles of the command sequence, set A21 to 0.
9. In the third cycle of the command sequence, address bit A21 must be set to 0 if verifying sectors 0–31, or to 1 if verifying
sectors 32–64. The data in the fourth cycle is 00h for an unprotected sector/sect or block and 01h for a protected sector/
sector block.
10.The Unlock Bypass command is required prior to the Unlock Bypass Program comma nd.
11.The Unlock Bypa ss Reset comm and is required to return to read ing array data when the devi ce is in the Unlock B ypass mode.
12.The system may read and program functions in non-erasing sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only during a se ctor erase operation.
13.The Erase Resume command is valid only during the Erase Suspend mode.
14.Command is valid when device is ready to read array data or when device is in autoselect mode.
15.The data is 85h for factory locked and 05h for not factory locked.
Command Sequence
(Not e 1 )
Cycles
Bus Cycles (Notes 2–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1RA RD
Reset (Note 7) 1 XXX F0
Autoselect
(Note 7)
Manufacturer ID (Note 8) 4 XXX AA XXX 55 0XXXXX 90 0XXX00 01
Device ID (Note 8) 4 XXX AA XXX 55 0XXXXX 90 0XXX01 A3
Secured Silicon Sector Factory
Protect (Note 15) 4 AAA AA 555 55 AAA 90 X06 85/05
Sector Protect Verify
(Not e 9) 4XXX AA XXX 55 0XXXXX
or
2XXXXX 90 SA
X02
00
XXX XXX 01
Enter Secured Silicon Sector Region 3 XXX AA XXX 55 XXX 88 XXX
Exit Secur ed Silico n Sect o r Re g ion 4 XXX AA XXX 55 XXX 90 XXX 00
Byte Prog ram 4 XXX AA XXX 55 XXX A0 PA PD
Unlock Bypass 3 XXX AA XXX 55 XXX 20
Unlock Bypass Program
(Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset
(Note 11) 2 XXX 90 XXX 00
Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 XXX 10
Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30
Erase Suspend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30
CFI Query (Note 14) 1 XXX 98
38 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Ta b l e 1 7 . S29AL032D Command Definitions — Models 03, 04
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location R A duri ng read op eration.
PA = Address of the memory location to be programmed. Addresses l atch on the falling edge of the WE# or C E# pulse, whicheve r
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1RA RD
Reset (No t e 7) 1XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID,
Model 03 Word 4555 AA 2AA 55 555 90 X01 22F6
Byte AAA 555 AAA X02 F6
Device ID,
Model 04 Word 4555 AA 2AA 55 555 90 X01 22F9
Byte AAA 555 AAA X02 F9
Secured Silicon Sector
F actory Protect
Model 03, (Note 9)
Word 4555 AA 2AA 55 555 90 X03 8D/0D
Byte AAA 555 AAA X06
Secured Silicon Sector
F actory Protect
Model 04, (Note 9)
Word 4555 AA 2AA 55 555 90 X03 9D/1D
Byte AAA 555 AAA X06
Sector Protect Verify
(Note 10)
Word 4555 AA 2AA 55 555 90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
Enter Secured Silicon Sector
Region Word 3555 AA 2AA 55 555 88
Byte AAA 555 AAA
Exit Secured Silico n Secto r
Region Word 4555 AA 2AA 55 555 90 XXX 00
Byte AAA 555 AAA
CFI Qu ery (Note 11) Word 155 98
Byte AA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 12) 2XXX A0 PA PD
Unlock Bypass Reset (Note 13) 2XXX 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Secto r Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 14) 1XXX B0
Erase Resume (Note 15) 1XXX 30
June 13, 2005 S29AL032D_00_A3 S29AL032D 39
Advance Information
Notes:
1. See Table 1 on page 11 for description of b us ope rations.
2. All values are in hexadecima l.
3. Except for t he read cy cle and th e fourth cycle of the auto select command sequence, all bus cycles are wr ite cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device
is prov iding status dat a).
8. The f o urth cycle of the a utoselect command seq ue nce is a read cycl e.
9. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory locked. For Model 04, the data is 9Dh for factory locked a nd 1Dh
for not factory locked.
10. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The U nlock Bypas s comm and is r eq uire d prior to t he Un lock Byp ass Program command.
13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also
acceptable.
14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Susp end comman d is valid o nly during a sector erase o p erati o n.
15. The Erase Resume command is valid only during the Erase Suspend mode.
Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5,
DQ6, DQ7, and RY/BY#. Table 18 on page 44 and the following subsections describe the functions
of these bi ts. DQ7, RY /BY#, and D Q6 eac h of fer a met hod f or det ermin ing whet her a program or
erase operation is complete or in progres s. T hes e th ree bits are discussed fi rst .
DQ7: Data# Polling
The D ata# Polling bit, DQ7, i ndicates to th e host syste m whether an Embedded Algo rithm is in
progress or c ompleted, or whether th e device is in Er ase Suspend. Data# P olling is v alid after t he
rising edge of the final WE# pulse in the progra m or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum progra mmed to DQ7. This DQ7 status als o applies to progr amming during E rase Suspend.
When the Embedded Progr a m algorithm is c omplete, the d evice ou tputs the dat um progr ammed
to DQ7. The system must provide the program address to read valid status informati on on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-
mately 1 µs, then the device returns to reading array data.
During the Embedded Er ase algor ithm, Data# P olling pr oduces a 0 on DQ7. When the Embedded
Erase al gorithm is complete, or if the device enters th e Erase Suspend mode, Data# Polling pro-
duces a 1 on DQ7. This is analogous to the complement/true datum output described for the
Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to
this, the device outputs the complement, or 0. The system must provide an address within any
of the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# P olling on DQ7 is activ e for appr oximately 100 µs, then the devi ce returns to reading arr ay
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.
When the syst e m d ete cts DQ7 has chan ge d fr om the co m p l e m ent to true d ata, it ca n r e ad vali d
data at DQ7 –DQ0 on th e following read cycles. This is because DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figu re 21, on page 57, D ata# Po lling
Timings (During Embedded Algorithms), in the AC Characteristics on page 50 section illustrates
this.
40 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Figure 18, on page 44 shows th e outputs fo r Data# Polling o n DQ7. Figure 7, on page 43 shows
the Da ta# P o lling algorithm.
Figure 6. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicate d, open-drain output pin th at indicate s whether an Embedded Al gorithm
is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse
in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be
tied together in parallel with a pull-up resistor to VCC.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operatio n, a valid address i s an address within
any se ctor se lect ed for e ra sure. Dur ing c hip er ase, a
valid addres s is any non- protecte d sector address.
2. DQ7 sho uld be rechecked even if DQ5 = 1 because
DQ7 may change simultaneously with DQ5.
June 13, 2005 S29AL032D_00_A3 S29AL032D 41
Advance Information
If the output is low (Busy), the device is actively er asing or progr amming. (This includes program-
ming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array
data (including durin g th e Erase Suspend mode), or is in the standby mode.
Table 18 on page 44 shows the ou tput s for R Y/BY# . Figures F igure 14, on page 50, Figure 15, on
page 51, Figure 18, on page 55 and Figure 19, on page 56 shows RY/BY# for read, reset, pro-
gram, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indica tes whet her an Embedded Progra m or Er ase algo rithm is in progre ss or
complete, or whet her the device has entered the Erase Suspend mode. Toggle Bit I may be read
at any addres s, and is vali d after the rising edge of the final WE# pulse in the c ommand seque nce
(prior to the pr ogram or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. (T he sy stem may use ei ther OE# or CE# to control the read cycles.)
When the oper ati on is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors tha t are protec ted.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ 7: Data# P olling on
page 39).
If a progr am address falls withi n a protecte d sector, DQ6 toggles for app roximately 1 µs after t he
progr am command sequence is written, then returns to reading array data.
DQ6 also toggles during the eras e-suspend-program mode, and stops toggling once the Embed-
ded Progr am algorithm is complete.
Table 18 on page 44 shows the ou tp u ts fo r Toggle Bit I o n DQ6. Figure 7, on page 43 shows th e
toggle bit algo rithm in flowchart form, and the sect ion Rea ding Toggle Bits DQ6/DQ2 on page 42
explains the algorithm. Figure 22, on page 57 shows the toggle bit timing diagra ms. Figure 2 3,
on page 58 shows t he diff ere nces between DQ2 and DQ6 i n gr aphi cal f orm. See also the subs ec -
tion on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected
for er asure. (The system may use eith er OE# or CE# to control t he read cycles .) But DQ2 ca nnot
distinguis h whether the sector is actively er asing or is er ase-suspended. DQ6 , by comparison, in -
dicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode
information. Ref e r to Table 18 on page 44 to compare outputs for DQ2 and DQ6.
Figure 7, on page 43 shows the toggle bit algorithm in flowchart form, and the section Reading
Toggle Bi ts DQ6/ DQ2 o n page 42 explains the algori thm. See also the DQ6: Togg le Bit I subsec-
42 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
tion. Figure 22, on page 57 shows the toggle bit timing diagram. Figure 23, on page 58 shows
the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refe r to Figure 7, on page 43 for the following discussion. Whenever the system initially begins
reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and st ore the value of the toggl e bit after
the first read. After the second read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has completed the program or erase
operation. The system can read array data on DQ7–DQ0 on the f ollowing read cycle.
However, if after th e initial two read c ycl es, the system deter mines that the t oggle bit i s still tog-
gling, the system also should note whether the value of DQ5 is h igh (see t he section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggl ing, sinc e the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successful ly completed the program or erase operati on. If it is still toggling , the device
did not complete the operation successfully, and the system must write the reset command to
retu rn to readi ng a r ray data .
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive r ead cy cles, deter mining the s tatus as described in the prev ious pa ragr aph. Alter natively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algori thm when it returns to determine the status of the operation (top of Figure 7, on page
43).
June 13, 2005 S29AL032D_00_A3 S29AL032D 43
Advance Information
Figure 7. Toggle Bit Algorithm
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Und er these condit ions DQ5 produces a 1. T his is a failure condit ion that indicat e s the pro-
gram or erase cycle w as not successful ly completed.
The DQ5 failure condi tion may appear if the system tries to pro gram a 1 to a location that is pre-
viously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twi ce to determine whether or not it
is toggling. See text.
2. Recheck toggle bit because it m ay stop toggling as
DQ5 changes to 1. See text.
(Note 1)
(Notes
1,2)
44 S29AL032D S29AL032D_00_A3 June 13, 2005
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condition, the devi ce halts the operation, and when the oper ation has exceeded the timing limits,
DQ5 produc e s a 1.
Under both these conditions, the system must issue the reset command to return the device to
reading array data.
DQ3: Sector Erase Timer
After writi ng a sector er ase command sequence, t he system may read D Q3 to determine whether
or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) If additional sectors a re se lected for erasure, the entire time-out also applies after
each additional sector erase command. W hen the time-out is complete, DQ3 switches from 0 to
1. The system may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 μs. See also the Sector Erase Command
Sequence on page 35 sect ion.
After the sector erase command sequence is written, the system should read the status on DQ7
(Data# Polli ng) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence,
and the n read DQ3. If DQ3 is 1, t he internally con trolled erase cycle h as begun; all fu rther com-
mands (other than Erase Suspend) are ig nored unti l the er ase oper ation i s complete. If D Q3 is 0,
the device will accept additional sector erase commands. To ensure the command has been ac-
cepted, the system software should check the status of DQ3 prior to and following each
subsequent sector er ase command. If DQ3 is h igh on t he second status check, the l ast command
might not have been accepted. Table 18 shows the outpu ts for DQ3.
Ta b l e 1 8 . Write Operation Status
Notes:
1. D Q5 swi tc h es to ‘ 1’ wh en an Embe dd ed Pro g ra m or E m bed d ed Er as e op eration has exceede d th e maxi mu m tim in g
limits. S ee DQ5: Exceeded Timing Limits on page 43 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
Operation DQ7
(No t e 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode
Embedded Program Algorithm
DQ7# Toggle 0N/A No toggle 0
Emb edded Erase Algorithm 0Toggle 0 1 Toggle 0
Erase
Suspend
Mode
R eading with in Er as e
Suspended Sector 1No toggle 0N/A Toggle 1
R eading within Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0N/A N/A 0
June 13, 2005 S29AL032D_00_A3 S29AL032D 45
Advance Information
Absolute Maximum Ratings
Storage Temper ature
Pla s tic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150 °C
Ambient Temperature
with Powe r Ap plied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .– 65°C to +125°C
Vo ltage wit h Respect to Ground
VCC (N o t e 1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0 . 5 V to +4.0 V
A9, OE#, and RESET # (N o te 2) . . . . . . . . . . . . . . . .– 0 .5 V to +12 .5 V
All ot h er pin s (N o te 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Outp u t Sh o rt Circu it Curren t (N o te 3). . . . . . . . . . . . . . . . . . . . . . . . 20 0 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 8, on page 45. Maximum DC voltage on input or I/O pins is VCC +0.5
V. During voltage transiti ons, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9,
on page 45.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 8, on page 45. Maximum DC input
voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to g round at a time. Duration of the short circuit should not be greater
than one sec ond.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the op-
erational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device re liability.
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . – 4 0°C to +85 ° C
VCC Supply Voltag es
VCC for standard volt a ge rang e . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3 .6 V
Operating ranges define those limits between which the functionality of the device is
guaranteed.
Figure 8. Maximum Negative
Overshoot Waveform
Figure 9. Maximum Positive Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
46 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
DC Characteristics
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep
mode current is 200 nA.
6. Not 100% tested.
7. On the ACC pin only, the maximum input load current when ACC = VIL is ±5.0 µA.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Cu rrent (Not e 7) VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Cu rrent VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Re ad Current
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode
10 MHz 15 30
mA
5 MHz 9 16
1 MHz 2 4
CE# = VIL, OE# = VIH,
Word Mod e
10 MHz 18 35
5 MHz 9 16
1 MHz 2 4
ICC2 VCC Active Write Current
(Notes 2, 3, 5) CE# = VIL, OE# = VIH 15 35 mA
ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±0.3 V 0.2 5 µA
ICC4 VCC Standby Current During Reset
(Notes 2, 4) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode
(Notes 2, 4, 6) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 0.2 5 µA
IACC ACC Acc elerated Program Current,
Wo rd or Byte CE# = VIL, OE# = VIH ACC pin 5 10 mA
VCC pi n 15 30 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VHH Voltage fo r WP#/ACC Sector Protect/
Unprote ct and Program Accele ration VCC = 3.0 V ± 10% 11.5 12.5 V
VID Voltage for Autoselect and Temporary
Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = V CC min 0.45 V
VOH1 Output High Voltage IOH = -2.0 mA, VCC = VCC min 2.4 V
VOH2 IOH = -100 µA, VCC = VCC min VCC–0.4 V
VLKO Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V
June 13, 2005 S29AL032D_00_A3 S29AL032D 47
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DC Characteristics
Zero Power Flash
Note: Addresses are switching at 1 MHz
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply C ur re nt in mA
Time in ns
10
8
2
0
12345
Frequency in MHz
Supply Cur rent in mA
Note: T = 25 °C
Figure 11. Typical ICC1 vs. Frequency
2.7 V
3.6 V
4
6
48 S29AL032D S29AL032D_00_A3 June 13, 2005
Advance Information
Test Conditions
Figure 12. Te s t S e t u p
Ta b l e 1 9 . Test Specifications
Speed Option 70 90 Unit
Output L oa d 1 TTL gate
Output L oa d Ca pa c ita nce, C
L
(including jig capa cita n ce) 30 100 pF
Input Ris e a nd Fall Times 5ns
Input Pulse L evels 0.0 or V
CC
V
Input tim ing me asurem e nt
reference levels 0.5 V
CC
V
Output timing meas urement
reference levels 0.5 V
CC
V
2.7 k
Ω
C
L
6.2 k
Ω
3.3 V
Device
Under
Test
Note: Diodes are IN3064 or equivalent
June 13, 2005 S29AL032D_00_A3 S29AL032D 49
Advance Information
Key to Switching Waveforms
Waveform Inputs Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care , A ny Change Permitted Changin g, State U nknown
Does Not Ap ply Cente r Line is H igh Impedance Sta te (Hi gh Z)
VCC
0.0 V
0.5 VCC OutputMeasurement LevelInput 0.5 VCC
Figure 13. Input Waveforms and Measurement Levels