LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization Check for Samples: LM5642, LM5642X FEATURES DESCRIPTION * * * * * The LM5642 series consists of two current mode synchronous buck regulator controllers operating 180 out of phase with each other at a normal switching frequency of 200kHz for the LM5642 and at 375kHz for the LM5642X. 1 2 * * * * * * * * * * * * * * Two Synchronous Buck Regulators 180 Out of Phase Operation 200 kHz Fixed Nominal Frequency: LM5642 375 kHz Fixed Nominal Frequency: LM5642X Synchronizable Switching Frequency from 150 kHz to 250 kHz for the LM5642 and 200 kHz to 500 kHz for the LM5642X 4.5V to 36V Input Range 50 A Shutdown Current Adjustable Output from 1.3V to 90% of Vin 0.04% (Typical) Line and Load Regulation Accuracy Current Mode Control with or without a Sense Resistor Independent Enable/Soft-start Pins Allow Simple Sequential Startup Configuration. Configurable for Single Output Parallel Operation. (See Figure 4) Adjustable Cycle-by-cycle Current Limit Input Under-voltage Lockout Output Over-voltage Latch Protection Output Under-voltage Protection with Delay Thermal Shutdown Self Discharge of Output Capacitors when the Regulator is OFF TSSOP and HTSSOP (Exposed PAD) Packages APPLICATIONS * * * * * * Embedded Computer Systems Navigation Systems Telecom Systems Set-Top Boxes WebPAD Point Of Load Power Architectures Out of phase operation reduces the input RMS ripple current, thereby significantly reducing the required input capacitance. The switching frequency can be synchronized to an external clock between 150 kHz and 250 kHz for the LM5642 and between 200 kHz and 500 kHz for the LM5642X. The two switching regulator outputs can also be paralleled to operate as a dual-phase, single output regulator. The output of each channel can be independently adjusted from 1.3V to 90% of Vin. An internal 5V rail is also available externally for driving bootstrap circuitry. Current-mode feedback control assures excellent line and load regulation and wide loop bandwidth for excellent response to fast load transients. Current is sensed across either the Vds of the top FET or across an external current-sense resistor connected in series with the drain of the top FET. The LM5642 features analog soft-start circuitry that is independent of the output load and output capacitance making the soft-start behavior more predictable and controllable than traditional soft-start circuits. Over-voltage protection is available for both outputs. A UV-Delay pin is also available to allow delayed shut off time for the IC during an output under-voltage event. Typical Application Circuit VIN 4.5V - 36V UV_Delay Vout1 1.3V-0.9VIN SYNC LM5642/LM5642X SS/ON1 SS/ON2 Vout2 1.3V-0.9VIN 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2013, Texas Instruments Incorporated LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com Connection Diagram KS1 1 28 RSNS1 ILIM1 2 27 SW1 COMP1 3 26 HDRV1 FB1 4 25 CBOOT1 SYNC 5 24 VDD1 UVDELAY 6 23 LDRV1 VLIN5 7 22 VIN SGND 8 21 PGND ON/SS1 9 20 ON/SS2 10 KS1 1 28 RSNS1 ILIM1 2 27 SW1 COMP1 3 26 HDRV1 FB1 4 25 CBOOT1 SYNC 5 24 VDD1 UVDELAY 6 23 LDRV1 VLIN5 7 22 VIN DAP SGND 8 21 PGND LDRV2 ON/SS1 9 20 LDRV2 19 VDD2 ON/SS2 10 19 VDD2 FB2 11 18 CBOOT2 COMP2 12 17 HDRV2 ILIM2 13 16 SW2 KS2 14 15 RSNS2 FB2 11 18 CBOOT2 COMP2 12 17 HDRV2 ILIM2 13 16 SW2 KS2 14 15 RSNS2 Figure 1. Top View Figure 2. Top View PIN DESCRIPTIONS KS1 (Pin 1) The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate trace to connect this pin to the current-sense point. It should be connected to VIN as close as possible to the currentsense resistor. When no current-sense resistor is used, connect as close as possible to the drain node of the upper MOSFET. ILIM1 (Pin 2) Current limit threshold setting for Channel 1. It sinks a constant current of 9.9 A, which is converted to a voltage across a resistor connected from this pin to VIN. The voltage across the resistor is compared with either the VDS of the top MOSFET or the voltage across the external current sense resistor to determine if an over-current condition has occurred in Channel 1. COMP1 (Pin 3) Compensation pin for Channel 1. This is the output of the internal transconductance error amplifier. The loop compensation network should be connected between this pin and the signal ground, SGND (Pin 8). FB1 (Pin 4) Feedback input for channel 1. Connect to VOUT through a voltage divider to set the Channel 1 output voltage. SYNC (Pin 5) The switching frequency of the LM5642 can be synchronized to an external clock. SYNC = LOW: Free running at 200 kHz for LM5642, and at 375kHz for LM5642X. Channels are 180 out of phase. SYNC = HIGH: Waiting for external clock SYNC = Falling Edge: Channel 1 HDRV pin goes high. Channel 2 HDRV pin goes high after 2.5 s delay. The maximum SYNC pulse width must be greater than 100 ns. For SYNC = Low operation, connect this pin to signal ground through a 220 k resistor. UV_DELAY (Pin 6) A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged from a 5 A current source. When UV_DELAY charges to 2.3V (typical), the system immediately latches off. Connecting this pin to ground will disable the output under-voltage protection. VLIN5 (Pin 7) The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the chip and powers the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of 4.7 F ceramic capacitor. SGND (Pin 8) The ground connection for the signal-level circuitry. It should be connected to the ground rail of the system. ON/SS1 (Pin 9) Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling this pin below 1.2V (open-collector type) turns off Channel 1. If both ON/SS1 and ON/SS2 pins are pulled below 1.2V, the whole chip goes into shut down mode. Adding a capacitor to this pin provides a soft-start feature that minimizes inrush current and output voltage overshoot. ON/SS2 (Pin 10) Channel 2 enable pin. See the description for Pin 9, ON/SS1. May be connected to ON/SS1 for simultaneous startup or for parallel operation. FB2 (Pin 11) Feedback input for channel 2. Connect to VOUT through a voltage divider to set the Channel 2 output voltage. 2 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 PIN DESCRIPTIONS (continued) COMP2 (Pin 12) Compensation pin for Channel 2. This is the output of the internal transconductance error amplifier. The loop compensation network should be connected between this pin and the signal ground SGND (Pin 8). ILIM2 (Pin 13) Current limit threshold setting for Channel 2. See ILIM1 (Pin 2). KS2 (Pin 14) The positive (+) Kelvin sense for the internal current sense amplifier of Channel 2. See KS1 (Pin 1). RSNS2 (Pin 15) The negative (-) Kelvin sense for the internal current sense amplifier of Channel 2. Connect this pin to the low side of the current sense resistor that is placed between VIN and the drain of the top MOSFET. When the Rds of the top MOSFET is used for current sensing, connect this pin to the source of the top MOSFET. Always use a separate trace to form a Kelvin connection to this pin. SW2 (Pin 16) Switch-node connection for Channel 2, which is connected to the source of the top MOSFET of Channel 2. It serves as the negative supply rail for the top-side gate driver, HDRV2. HDRV2 (Pin 17) Top-side gate-drive output for Channel 2. HDRV is a floating drive output that rides on the corresponding switching-node voltage. CBOOT2 (Pin 18) Bootstrap capacitor connection. It serves as the positive supply rail for the Channel 2 top-side gate drive. Connect this pin to VDD2 (Pin 19) through a diode, and connect the low side of the bootstrap capacitor to SW2 (Pin16). VDD2 (Pin 19) The supply rail for the Channel 2 low-side gate drive. Connected to VLIN5 (Pin 7) through a 4.7 resistor and bypassed to power ground with a ceramic capacitor of at least 1F. Tie this pin to VDD1 (Pin 24). LDRV2 (Pin 20) Low-side gate-drive output for Channel 2. PGND (Pin 21) The power ground connection for both channels. Connect to the ground rail of the system. VIN (Pin 22) The power input pin for the chip. Connect to the positive (+) input rail of the system. This pin must be connected to the same voltage rail as the top FET drain (or the current sense resistor when used). LDRV1 (Pin 23) Low-side gate-drive output for Channel 1. VDD1 (Pin 24) The supply rail for Channel 1 low-side gate drive. Tie this pin to VDD2 (Pin 19). CBOOT1 (Pin 25) Bootstrap capacitor connection. This pin serves as the positive supply rail for the Channel 1 top-side gate drive. See CBOOT2 (Pin 18). HDRV1 (Pin 26) Top-side gate-drive output for Channel 1. See HDRV2 (Pin 17). SW1 (Pin 27) Switch-node connection for Channel 1. See SW2 (Pin16). RSNS1 (Pin 28) The negative (-) Kelvin sense for the internal current sense amplifier of Channel 1. See RSNS2 (Pin 15). PGND (DAP) The power ground connection for both channels. Connect to the ground rail of the system. Use of multiple vias to internal ground plane or GND layer helps to dissipate heat generated by output power. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 3 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Voltages from the indicated pins to SGND/PGND: VIN, ILIM1, ILIM2, KS1, KS2 -0.3V to 38V SW1, SW2, RSNS1, RSNS2 -0.3 to (VIN + 0.3)V -0.3V to 6V FB1, FB2, VDD1, VDD2 -0.3V to (VLIN5 +0.3)V SYNC, COMP1, COMP2, UV Delay ON/SS1, ON/SS2 (3) -0.3V to (VLIN5 +0.6)V CBOOT1, CBOOT2 43V -0.3V to 7V CBOOT1 to SW1, CBOOT2 to SW2 -0.3V to (VDD+0.3)V LDRV1, LDRV2 HDRV1 to SW1, HDRV2 to SW2 -0.3V HDRV1 to CBOOT1, HDRV2 to CBOOT2 +0.3V Power Dissipation (TA = 25C) (4) TSSOP 1.1W HTSSOP 3.4W -65C to +150C Ambient Storage Temp. Range Soldering Dwell Time, Temp. (5) ESD Rating (1) (2) (3) (4) (5) (6) Wave 4 sec, 260C Infrared 10sec, 240C Vapor Phase 75sec, 219C (6) 2kV Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. ON/SS1 and ON/SS2 are internally pulled up to one diode drop above VLIN5. Do not apply an external pull-up voltage to these pins. It may cause damage to the IC. The maximum allowable power dissipation is calculated by using PDMAX = (TJMAX - TA)/JA, where TJMAX is the maximum junction temperature, TA is the ambient temperature and JA is the junction-to-ambient thermal resistance of the specified package. The power dissipation ratings results from using 125C, 25C, and 90.6C/W for TJMAX, TA, and JA respectively. A JA of 90.6C/W represents the worst-case condition of no heat sinking of the 28-pin TSSOP. The HTSSOP package has a JA of 29C/W. The HTSSOP package thermal ratings results from the IC being mounted on a 4 layer JEDEC standard board using the same temperature conditions as the TSSOP package above. A thermal shutdown will occur if the temperature exceeds the maximum junction temperature of the device. See http://www.ti.com for other methods of soldering plastic small-outline packages. For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5 k resistor. OPERATING RATINGS (1) VIN (VLIN5 tied to VIN) 4.5V to 5.5V VIN (VIN and VLIN5 separate) 5.5V to 36V -40C to +125C Junction Temperature (1) 4 Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Unless otherwise specified, VIN = 28V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply over the specified operating junction temperature range, (-40C to +125C, if not otherwise specified). Specifications appearing in plain type are measured using low duty cycle pulse testing with TA = 25C (1), (2). Min/Max limits are specified by design, test, or statistical analysis. Symbol Parameter Conditions Min Typ Max Units System VOUT/VOUT VFB1_FB2 IVIN Load Regulation VIN = 28V, Vcompx = 0.5V to 1.5V 0.04 % Line Regulation 5.5V VIN 36V, Vcompx =1.25V 0.04 % Feedback Voltage 5.5V VIN 36V 1.2154 -20C to 85C 1.2179 Input Supply Current 1.2364 1.2364 1.2574 1.2549 V VON_SSx > 2V 5.5V VIN 36V 1.1 2.0 mA Shutdown (3) VON_SS1 = VON_SS2= 0V 50 110 A 5 5.30 V 2 7.0 mV 8.4 9.9 11.4 A 0.5 2.4 5.0 A 2 5.5 10 A 0.7 1.12 1.4 V VLIN5 VLIN5 Output Voltage IVLIN5 = 0 to 25mA, 5.5V VIN 36V VCLos Current Limit Comparator Offset (VILIMX -VRSNSX) VIN = 6V ICL Current Limit Sink Current Iss_SC1, Iss_SC2 Soft-Start Source Current VON_ss1 = VON_ss2 = 1.5V (on) Iss_SK1, Iss_SK2 Soft-Start Sink Current VON_ss1 = VON_ss2 = 1.5V VON_SS1, VON_SS2 Soft-Start On Threshold VSSTO Soft-Start Timeout Threshold Isc_uvdelay UV_DELAY Source Current UV-DELAY = 2V Isk_uvdelay UV_DELAY Sink Current UV-DELAY = 0.4V VUVDelay UV_DELAY Threshold Voltage VUVP FB1, FB2, Under Voltage Protection Latch Threshold 4.70 (4) 3.4 V 2 5 9 A 0.2 0.48 1.2 mA 2.3 As a percentage of nominal output voltage (falling edge) 75 Hysteresis 80.7 V 86 3.7 % % VOVP VOUT Overvoltage Shutdown Latch Threshold As a percentage measured at VFB1, VFB2 107 114 122 % Swx_R SW1, SW2 ON-Resistance VSW1 = VSW2 = 0.4V 420 487 560 (1) (2) (3) (4) A typical is the center of characterization data measured with low duty cycle pulse tsting at TA = 25C. Typicals are not ensured. All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TA = TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Both switching controllers are off. The linear regulator VLIN5 remains on. When SS1 and SS2 pins are charged above this voltage and either of the output voltages at Vout1 or Vout2 is still below the regulation limit, the under voltage protection feature is initialized. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 5 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, VIN = 28V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply over the specified operating junction temperature range, (-40C to +125C, if not otherwise specified). Specifications appearing in plain type are measured using low duty cycle pulse testing with TA = 25C (1), (2). Min/Max limits are specified by design, test, or statistical analysis. Symbol Parameter Conditions Min Typ Max Units Gate Drive ICBOOT CBOOTx Leakage Current VCBOOT1 = VCBOOT2 = 7V 10 nA ISC_DRV HDRVx and LDRVx Source Current VCBOOT1 = VCBOOT2 = 5V, VSWx=0V, HDRVx=LDRVx=2.5V 0.5 A Isk_HDRV HDRVx Sink Current VCBOOTx = VDDx = 5V, VSWx = 0V, HDRVX = 2.5V 0.8 A Isk_LDRV LDRVx Sink Current VCBOOTx = VDDx = 5V, VSWx = 0V, LDRVX = 2.5V 1.1 A RHDRV HDRV1 & 2 Source OnResistance VCBOOT1 = VCBOOT2 = 5V, VSW1 = VSW2 = 0V 3.1 1.5 3.1 1.1 HDRV1 & 2 Sink OnResistance RLDRV LDRV1 & 2 Source OnResistance LDRV1 & 2 Sink OnResistance VCBOOT1 = VCBOOT2 = 5V, VSW1 = VSW2 = 0V VDD1 = VDD1 = 5V Oscillator and Sync Controls Fosc Oscillator Frequency Don_max Maximum On-Duty Cycle Ton_min Minimum On-Time SSOT_delta HDRV1 and HDRV2 Delta On Time VHS SYNC Pin Min High Input VLS SYNC Pin Max Low Input 5.5 VIN 36V, LM5642 166 200 226 5.5 VIN 36V, LM5642X 311 375 424 VFB1 = VFB2 = 1V, Measured at pins HDRV1 and HDRV2 96 98.9 % 166 ns ON/SS1 = ON/SS2 = 2V 20 2 250 1.52 kHz ns V 1.44 0.8 V 80 200 nA Error Amplifier IFB1, IFB2 Feedback Input Bias Current VFB1_FIX = 1.5V, VFB2_FIX = 1.5V Icomp1_SC, Icomp2_SC COMP Output Source Current VFB1_FIX = VFB2_FIX = 1V, VCOMP1 = VCOMP2 = 1V 6 -20C to 85C 18 VFB1_FIX = VFB2_FIX = 1.5V and VCOMP1 = VCOMP2 = 0.5V 6 -20C to 85C 18 Icomp1_SK, Icomp2_SK COMP Output Sink Current gm1, gm2 Transconductance GISNS1, GISNS2 Current Sense Amplifier (1&2) Gain 127 A 118 A 720 VCOMPx = 1.25V mho 4.2 5.2 7.5 3.6 4.0 4.4 Voltage References and Linear Voltage Regulators UVLO 6 VLIN5 Under-voltage Lockout Threshold Rising ON/SS1, ON/SS2 transition from low to high Submit Documentation Feedback V Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 C3 100 pF C2 10 nF Vin = 24V+10% 22 C1 ILIM1 VIN IC1 LM5642 1 PF KS1 RSNS1 6 C34 SYNC UV_DELAY 100 nF 5 HDRV1 CBOOT1 SW1 220 k: S1 C11 ON/SS1 LDRV1 PGND 10 nF FB1 10 S2 C12 VDD 19 VDD1 VDD2 R27 7 4.7 : C27 C26 3 C19 1 PF 4.7 PF R23 8.45 k: 8.2 nF 12 1 12 k: 28 25 27 R2 100: C6 R7 10 m: C4 100 pF R6 26 C7 Q1 100: D3A BAS40-06 VDD L1 4.2 PH 7 m: ILIM2 KS2 RSNS2 Q2 C13 10 nF C14 100 pF COMP2 HDRV2 CBOOT2 C20 15 nF SW2 R24 13.7 k: 8 LDRV2 SGND FB2 R15 10 m: C16 100 pF 17 18 16 C25 11 C9 + 330 PF 6.3V 10 m: VIN 6.8 k: 14 20 R10 2.26 k: R14 100: R13 13 15 Vo1 = 1.8V, 7A 4.99 k: 4 VLIN5 COMP1 R11 Si4840DY 21 10 PF 50V 2.8Arms Si4850EY 100 nF 23 ON/SS2 10 nF 24 R1 SYNC R28 9 2 VIN R16 Q4 100: D3B BAS40-06 VDD Si4850EY L2 100 nF Q5 C16 10 PF 50V 2.8Arms 10 P+ 12 m: Si4840DY R20 Vo2 = 3.3V, 4A R19 8.25 k: + C23 330 PF 6.3V 10 m: 4.99 k: Figure 3. Typical 2 Channel Application Circuit Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 7 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com C3 100 pF C2 10 nF Vin = 30Vr 10% 22 VIN C1 1 PF ILIM1 IC1 LM5642 1 KS1 28 R2 100: R1 2 16.9 k: C34 26 HDRV1 100 nF CBOOT1 5 SW1 SYNC R28 220 k: 9 S1 UV_DELAY C11 R6 ON/SS1 22 nF LDRV1 FB1 24 VDD 19 ON/SS2 VDD1 7 C27 C26 1 PF 4.7 PF 3 C19 FB2 ILIM2 VDD2 KS2 R27 4.7: VLIN5 RSNS2 Q2 23 27 nF HDRV2 CBOOT2 R23 SW2 8 SGND Si4850EY L1 Vo = 1.8V, 20A 2.7 PH 4.5 m: Q3 R10 2.26 k: R11 21 Si4470DY x 2 4 11 13 14 15 R13 20 1 PF C16 R15 10 m: R16 Q4 100: D3B BAS40-06 VDD 16 C25 C10 R14 100: C16 100 pF 18 C9 1000 PF 16V 22 m: VIN 16.9 k: 17 + 4.99 k: C13 10 nF C14 100 pF COMP1 12 COMP2 11.5 k: 27 Q1 100: D3A BAS40-06 VDD C7 100 nF SYNC PGND 10 25 C6 10 PF 50V 2.8Arms R7 10 m: C4 100 pF RSNS1 6 VIN 100 nF Q5 Q6 10 PF 50V 2.8Arms Si4850EY L2 2.7 PH 4.5 m: LDRV2 Si4470DY x 2 C23 + 1000 PF 16V 22 m: C24 1 PF Figure 4. Typical Single Channel Application Circuit 8 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 BLOCK DIAGRAM VIN Voltage and Current generator BG SD Disable BG reference Bias Generator Vref Current bias IREF Input Power Supply + + - 5V LDO (Allways ON) VLIN5 From another Ch. 10 PA COMPx ILIM Comp Ch1 and Ch2 are identical ILIMx + KSx + - CHx output ISENSE amp error amp FBx - PWM comp Normal: ON + BG 2 PA PWM logic control R Q HDRVx SS: ON S Q SWx Corrective ramp ON/OFF and S/S control ON/SSx CBOOTx Shifter and latch + - RSNSx 0.50V S/S level + Cycle Skip comp + - Shoot through protection sequencer CHx Output + VDDx LDRVx 7 PA PGNDx fault 5 PA UV_DELAY FAULT TSD UVLO Active discharge Rdson = 500: UVP R Q S Q R Q S Reset by POR or SD Q UV UVP OVP UVPG1 comparator OVP To Ch2 From another CH. 0 2.5 Ps delay OSC 200 kHz LM5642 or 375 kHz LM5642X SYNC SGND Figure 5. Block Diagram Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 9 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Softstart Waveforms (No-Load Both Channels) UVP Startup Waveform (VIN = 24V) ON/SS1, 2V/div Vo2, 2V/div Vo1, 1V/div Vo1, 2V/div ON/SS1 and 2, 5V/div, VIN = 36V Vo2, 2V/div Io1, 5A/div Vo1, 2V/div ON/SS1 and 2, 5V/div, VIN = 24V UV DELAY, 2V/div 20ms/DIV 4 ms/DIV Figure 6. Figure 7. Over-Current and UVP Shutdown (VIN = 24V, Io2 = 0A) Shutdown Waveforms (VIN = 24V, No-Load) Io1, 5A/div Vo2, 1V/div Vo1, 1V/div Vo2, 1V/div Vo1, 1V/div ON/SS1 and 2, 5V/div UV DELAY, 1V/div 100ms/DIV 20ms/DIV Figure 8. Figure 9. Ch.1 Load Transient Response (VIN = 24V, Vo1 = 1.8V) Ch.2 Load Transient Response (VIN = 24V, Vo2 = 3.3V) Io2, 2A/DIV Io1, 2A/DIV Vo2, 100mV/DIV Vo1, 100mV/DIV 100Ps/DIV 100Ps/DIV Figure 10. 10 Figure 11. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Ch. 2 Load Transient Response (VIN = 36V, Vo2 = 3.3V) Ch.1 Load Transient Response (VIN = 36V, Vo1 = 1.8V) Io2, 2A/DIV Io1, 2A/DIV Vo2, 100mV/DIV Vo1, 100mV/DIV 100Ps/DIV 100Ps/DIV Figure 12. Figure 13. Input Supply Current vs Temperature (Shutdown Mode VIN = 28V) Input Supply Current vs VIN Shutdown Mode (25C) 55 53.5 53 50 52 45 IQ (PA) IQ (PA) 52.5 40 51.5 51 50.5 35 50 30 -40 -20 0 25 50 75 100 49.5 5.5 125 8 12 16 20 24 28 32 36 32 36 TEMPERATURE (oC) VIN Figure 14. Figure 15. VLIN5 vs Temperature VLIN5 vs VIN (25C) 5.095 5.1 5.08 5.09 VIN = 36V 5.06 5.04 VLIN5 (V) VLIN5 (V) 5.085 VIN = 5.5V 5.02 5.08 5.075 5 5.07 4.98 4.96 -40 5.065 -20 0 25 50 75 100 125 5.5 TEMPERATURE (oC) 8 12 16 20 24 28 VIN (V) Figure 16. Figure 17. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 11 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Operating Frequency vs Temperature (VIN = 28V) FB Reference Voltage vs Temperature 204 1.2365 202 1.236 200 FREQUENCY (kHz) 1.237 1.2355 VREF (V) 1.235 1.2345 1.234 1.2335 198 196 194 192 190 1.233 188 1.2325 186 1.232 -40 -20 0 25 50 75 100 184 -40 125 -20 o 0 25 50 75 100 125 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 18. Figure 19. Error Amplifier Tranconductance Gain vs Temperature Efficiency vs Load Current Using Resistor Sense Ch.1 = 1.8V, Ch.2 = Off 750 100 700 90 650 80 EFFICIENCY (%) EA gm (Pmho) VIN = 24V 600 550 70 60 500 50 450 40 400 VIN = 36V 30 -40 -20 0 25 50 75 100 125 0 o TEMPERATURE ( C) 2 3 4 5 6 7 LOAD CURRENT (A) Figure 20. 12 1 Figure 21. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Efficiency vs Load Current Ch.2 = 3.3V, Ch.1 = Off Efficiency vs Load Current Using Vds Sense Ch.2 = 1.8V, Ch.2 = Off 100 100 VIN = 24V VIN = 24V 90 VIN = 36V 90 EFFICIENCY (%) EFFICIENCY (%) 80 80 70 VIN = 36V 70 60 50 60 40 50 30 0 1 2 3 4 5 0 1 2 3 4 5 6 7 LOAD CURRENT (A) LOAD CURRENT (A) Figure 22. Figure 23. Efficiency vs Load Current Using Vds Sense Ch.2 = 3.3V, Ch.1 = Off 100 VIN = 24V EFFICIENCY (%) 90 VIN = 36V 80 70 60 50 0 1 2 3 4 5 LOAD CURRENT (A) Figure 24. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 13 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com OPERATING DESCRIPTIONS SOFT START The ON/SS1 pin has dual functionality as both channel enable and soft start control. Referring to the soft start block diagram is shown in Figure 25, the LM5642 will remain in shutdown mode while both soft start pins are grounded. In a normal application (with a soft start capacitor connected between the ON/SS1 pin and SGND) soft start functions as follows: As the input voltage rises (note, Iss starts to flow when VIN 2.2V), the internal 5V LDO starts up, and an internal 2.4 A current charges the soft start capacitor. During soft start, the error amplifier output voltage at the COMPx pin is clamped at 0.55V and the duty cycle is controlled only by the soft start voltage. As the SSx pin voltage ramps up, the duty cycle increases proportional to the soft start ramp, causing the output voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft start capacitor. The higher the capacitance, the slower the output voltage ramps up. When the corresponding output voltage exceeds 98% (typical) of the set target voltage, the regulator switches from soft start to normal operating mode. At this time, the 0.55V clamp at the output of the error amplifier releases and peak current feedback control takes over. Once in peak current feedback control mode, the output voltage of the error amplifier will travel within a 0.5V and 2V window to achieve PWM control. See Figure 26. The amount of capacitance needed for a desired soft-start time can be approximated in the following equation: Iss x tss Css = Vss where * * Iss = 2.4 A for one channel and 4.8A if the channels are paralleled tss is the desired soft-start time (1) Finally, Vss = 1.5 * +1 (c) Vin Vo (2) During soft start, over-voltage protection and current limit remain in effect. The under voltage protection feature is activated when the ON/SS pin exceeds the timeout threshold (3.4V typical). If the ON/SSx capacitor is too small, the duty cycle may increase too rapidly, causing the device to latch off due to output voltage overshoot above the OVP threshold. This becomes more likely in applications with low output voltage, high input voltage and light load. A capacitance of 10 nF is recommended at each soft start pin to provide a smooth monotonic output ramp. + 2PA disable R Q S>R S Q fault ONx + - ON/SSx ON: 2.4PA source Fault: 5.5PA sink 7PA 1.2V/ 1.05V ON/OFF comparator + - S/S level S/S buffer Figure 25. Soft-Start and ON/OFF 14 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 low clamp + - 0.45V COMPx + high clamp SS:0.55V OP:2V Figure 26. Voltage Clamp at COMPx Pin FBx from other CH. OVP 1.13BG OVPx + shutdown latch OVP HDRV: off LDRV:on S Q OVP 1/2 R Q UVP in: 0.84BG out:0.80BG + 5u A UVPx UV_DELAY ONx SS Timeout from other CH. S SD power on reset Q R Q shutdown latch UVP HDRV: off LDRV:off TSD UVLO fault Figure 27. OVP and UVP OVER VOLTAGE PROTECTION (OVP) If the output voltage on either channel rises above 113% of nominal, over voltage protection activates. Both channels will latch off. When the OVP latch is set, the high side FET driver, HDRVx, is immediately turned off and the low side FET driver, LDRVx, is turned on to discharge the output capacitor through the inductor. To reset the OVP latch, either the input voltage must be cycled, or both channels must be switched off (both ON/SS pins pulled low). UNDER VOLTAGE PROTECTION (UVP) AND UV DELAY If the output voltage on either channel falls below 80% of nominal, under voltage protection activates. As shown in Figure 27, an under-voltage event will shut off the UV_DELAY MOSFET, which will allow the UV_DELAY capacitor to charge with 5A (typical). If the UV_DELAY pin voltage reaches the 2.3V threshold both channels will latch off. UV_DELAY will then be disabled and the UV_DELAY pin will return to 0V. During UVP, both the high side and low side FET drivers will be turned off. If no capacitor is connected to the UV_DELAY pin, the UVP latch will be activated immediately. To reset the UVP latch, either the input voltage must be cycled, or both ON/SS pins must be pulled low. The UVP function can be disabled by connecting the UV_DELAY pin to ground. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 15 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com THERMAL SHUTDOWN The LM5642 IC will enter thermal shutdown if the die temperature exceeds 160C. The top and bottom FETs of both channels will be turned off immediately. In addition, both soft start capacitors will begin to discharge through separate 5.5 A current sinks. The voltage on both capacitors will settle to approximately 1.1V, where it will remain until the thermal shutdown condition has cleared. The IC will return to normal operating mode when the die temperature has fallen to below 146C. At this point the two soft start capacitors will begin to charge with their normal 2.4 A current sources. This allows a controlled return to normal operation, similar to the soft start during turn-on. If the thermal shutdown condition clears before the voltage on the soft start capacitors has fallen to 1.1V, the capacitors will first be discharged to 1.1V, and then immediately begin charging back up. OUTPUT CAPACITOR DISCHARGE Each channel has an embedded 480 MOSFET with the drain connected to the SWx pin. This MOSFET will discharge the output capacitor of its channel if its channel is off, or the IC enters a fault state caused by one of the following conditions: 1. UVP 2. UVLO If an output over voltage event occurs, the HDRVx will be turned off and LDRVx will be turned on immediately to discharge the output capacitors of both channels through the inductors. BOOTSTRAP DIODE SELECTION The bootstrap diode and capacitor form a supply that floats above the switch node voltage. VLIN5 powers this supply, creating approximately 5V (minus the diode drop) which is used to power the high side FET drivers and driver logic. When selecting a bootstrap diode, Schottky diodes are preferred due to their low forward voltage drop, but care must be taken for circuits that operate at high ambient temperature. The reverse leakage of some Schottky diodes can increase by more than 1000x at high temperature, and this leakage path can deplete the charge on the bootstrap capacitor, starving the driver and logic. Standard PN junction diodes and fast rectifier diodes can also be used, and these types maintain tighter control over reverse leakage current across temperature. SWITCHING NOISE REDUCTION Power MOSFETs are very fast switching devices. In synchronous rectifier converters, the rapid increase of drain current in the top FET coupled with parasitic inductance will generate unwanted Ldi/dt noise spikes at the source node of the FET (SWx node) and also at the VIN node. The magnitude of this noise will increase as the output current increases. This parasitic spike noise may produce excessive electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, it must be suppressed using one of the following methods. When using resistor based current sensing, it is strongly recommended to add R-C filters to the current sense amplifier inputs as shown in Figure 29. This will reduce the susceptibility to switching noise, especially during heavy load transients and short on time conditions. The filter components should be connected as close as possible to the IC. As shown in Figure 28, adding a resistor in series with the HDRVx pin will slow down the gate drive, thus slowing the rise and fall time of the top FET, yielding a longer drain current transition time. Usually a 3.3 to 4.7 resistor is sufficient to suppress the noise. Top FET switching losses will increase with higher resistance values. Small resistors (1-5 ohms) can also be placed in series with the CBOOTx pin to effectively reduce switch node ringing. A CBOOT resistor will slow the rise time of the FET, whereas a resistor at HDRV will increase both rise and fall times. 16 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 CBOOTx HDRVx SWx Rsw 4R7 0.1 PF Figure 28. HDRV Series Resistor CURRENT SENSING AND LIMITING As shown in Figure 29, the KSx and RSNSx pins are the inputs of the current sense amplifier. Current sensing is accomplished either by sensing the Vds of the top FET or by sensing the voltage across a current sense resistor connected from VIN to the drain of the top FET. The advantages of sensing current across the top FET are reduced parts count, cost and power loss. The RDS-ON of the top FET is not as stable over temperature and voltage as a sense resistor, hence great care must be used in layout for VDS sensing circuits. At input voltages above 30V, the maximum recommended output current is 5A per channel. Keeping the differential current-sense voltage below 200mV ensures linear operation of the current sense amplifier. Therefore, the RDS-ON of the top FET or the current sense resistor must be small enough so that the current sense voltage does not exceed 200 mV when the top FET is on. There is a leading edge blanking circuit that forces the top FET on for at least 166ns. Beyond this minimum on time, the output of the PWM comparator is used to turn off the top FET. Additionally, a minimum voltage of at least 50 mV across Rsns is recommended to ensure a high SNR at the current sense amplifier. Assuming a maximum of 200 mV across Rsns, the current sense resistor can be calculated as follows: where * * Imax is the maximum expected load current, including overload multiplier (ie: 120%) Irip is the inductor ripple current (see Equation 17) (3) The above equation gives the maximum allowable value for Rsns. Conduction losses will increase with larger Rsns, thus lowering efficiency. The peak current limit is set by an external resistor connected between the ILIMx pin and the KSx pin. An internal 10 A current sink on the ILIMx pin produces a voltage across the resistor to set the current limit threshold which is then compared to the current sense voltage. A 10 nF capacitor across this resistor is required to filter unwanted noise that could improperly trip the current limit comparator. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 17 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com 10 PA LIMx comp LIMx 13k + - POWER SUPPLY KSx 10 nF 100 + ISENSE amp 20m RSNSx 100 100 pF 100 pF Figure 29. Current Sense and Current Limit Current limit is activated when the inductor current is high enough to cause the voltage at the RSNSx pin to be lower than that of the ILIMx pin. This toggles the Ilim comparator, thus turning off the top FET immediately. The comparator is disabled when the top FET is turned off and during the leading edge blanking time. The equation for current limit resistor, Rlim, is as follows: where * Ilim is the load current at which the current limit comparator will be tripped (4) When sensing current across the top FET, replace Rsns with the RDS-ON of the FET. This calculated Rlim value specifies that the minimum current limit will not be less than Imax. It is recommended that a 1% tolerance resistor be used. When sensing across the top FET (VDS sensing), RDS-ON will show more variation than a current-sense resistor, largely due to temperature variation. RDS-ON will increase proportional to temperature according to a specific temperature coefficient. Refer to the FET manufacturer's datasheet to determine the range of RDS-ON values over operating temperature or see the Component Selection section (Equation 27) for a calculation of maximum RDSON. This will prevent RDS-ON variations from prematurely tripping the current limit comparator as the operating temperature increases. To ensure accurate current sensing using VDS sensing, special attention in board layout is required. The KSx and RSNSx pins require separate traces to form a Kelvin connection at the corresponding current sense nodes. In addition, the filter components R14, R16, C14, C15 should be removed. INPUT UNDER VOLTAGE LOCKOUT (UVLO) The input under-voltage lock out threshold, which is sensed via the VLIN5 internal LDO output, is 4.0V (typical). Below this threshold, both HDRVx and LDRVx will be turned off and the internal 480 MOSFETs will be turned on to discharge the output capacitors through the SWx pins. When the input voltage is below the UVLO threshold, the ON/SS pins will sink 5mA to discharge the soft start capacitors and turn off both channels. As the input voltage increases again above 4.0V, UVLO will be de-activated, and the device will restart through a normal soft start phase. If the voltage at VLIN5 remains below 4.5V, but above the 4.0V UVLO threshold, the device cannot be ensured to operate within specification. If the input voltage is between 4.0V and 5.2V, the VLIN5 pin will not regulate, but will follow approximately 200 mV below the input voltage. 18 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 DUAL-PHASE PARALLEL OPERATION In applications with high output current demand, the two switching channels can be configured to operate as a two phase converter to provide a single output voltage with current sharing between the two switching channels. This approach greatly reduces the stress and heat on the output stage components while lowering input ripple current. The inductor ripple currents also cancel to a varying degree which results in lowered output ripple voltage. Figure 4 shows an example of a typical two-phase circuit. Because precision current sense is the primary design criteria to ensure accurate current sharing between the two channels, both channels must use external sense resistors for current sensing. To minimize the error between the error amplifiers of the two channels, tie the feedback pins FB1 and FB2 together and connect to a single voltage divider for output voltage sensing. Also, tie the COMP1 and COMP2 together and connect to the compensation network. ON/SS1 and ON/SS2 must be tied together to enable and disable both channels simultaneously. EXTERNAL FREQUENCY SYNC The LM5642 series has the ability to synchronize to external sources in order to set the switching frequency. This allows the LM5642 to use frequencies from 150 kHz to 250 kHz and the LM5642X to use frequencies from 200 kHz to 500 kHz. Lowering the switching frequency allows a smaller minimum duty cycle, DMIN, and hence a greater range between input and output voltage. Increasing switching frequency allows the use of smaller output inductors and output capacitors (see Component Selection). In general, synchronizing all the switching frequencies in multi-converter systems makes filtering of the switching noise easier. The sync input can be from a system clock, from another switching converter in the system, or from any other periodic signal with a logic low-level less than 1.4V and a logic high level greater than 2V. Both CMOS and TTL level inputs are acceptable. The LM5642 series uses a fixed delay between Channel 1 and Channel 2. The nominal switching frequency of 200kHz for the LM5642 corresponds to a switching period of 5s. Channel 2 always turns its high-side switch on 2.5s after Channel 1 Figure 30 (a). When the converter is synchronized to a frequency other than 200kHz, the switching period is reduced or increased, while the fixed delay between Channel 1 and Channel 2 remains constant. The phase difference between channels is therefore no longer 180. At the extremes of the sync range, the phase difference drops to 135 Figure 30 (b) and Figure 30 (c). The result of this lower phase difference is a reduction in the maximum duty cycle of one channel that will not overlap the duty cycle of the other. As shown in Input Capacitor Selection section, when the duty cycle D1 for Channel 1 overlaps the duty cycle D2 for Channel 2, the input rms current increases, requiring more input capacitors or input capacitors with higher ripple current ratings. The new, reduced maximum duty cycle can be calculated by multiplying the sync frequency (in Hz) by 2.5x10-6 (the fixed delay in seconds). The same logic applies to the LM5642X. However the LM5642X has a nominal switching frequency of 375kHz which corresponds to a period of 2.67s. Therefore channel 2 of the LM5642X always begins it's period after 1.33s. DMAX = FSYNC*2.5x10-6 (5) At a sync frequency of 150 kHz, for example, the maximum duty cycle for Channel 1 that will not overlap Channel 2 would be 37.5%. At 250 kHz, it is the duty cycle for Channel 2 that is reduced to a DMAX of 37.5%. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 19 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com FSW = 200 kHz D1 5 Ps 5 Ps D2 2.5 Ps (a) FSW = 150 kHz D1 6.67 Ps 6.67 Ps D2 2.5 Ps (b) FSW = 250 kHz D1 4 Ps 4 Ps D2 2.5 Ps (c) Figure 30. Period Fixed Delay Example Component Selection OUTPUT VOLTAGE SETTING The output voltage for each channel is set by the ratio of a voltage divider as shown in Figure 31. The resistor values can be determined by the following equation: where * Vfb = 1.238V (6) Although increasing the value of R1 and R2 will increase efficiency, this will also decrease accuracy. Therefore, a maximum value is recommended for R2 in order to keep the output within .3% of Vnom. This maximum R2 value should be calculated first with the following equation: where * 20 200nA is the maximum current drawn by FBx pin Submit Documentation Feedback (7) Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 Vout R2 FBx R1 GND Figure 31. Output Voltage Setting Example: Vnom = 5V, Vfb = 1.2364V, Ifbmax = 200nA. (8) Choose 60K (9) The Cycle Skip and Dropout modes of the LM5642 series regulate the minimum and maximum output voltage/duty cycle that the converter can deliver. Both modes check the voltage at the COMP pin. Minimum output voltage is determined by the Cycle Skip Comparator. This circuitry skips the high side FET ON pulse when the COMP pin voltage is below 0.5V at the beginning of a cycle. The converter will continue to skip every other pulse until the duty cycle (and COMP pin voltage) rise above 0.5V, effectively halving the switching frequency. Maximum output voltage is determined by the Dropout circuitry, which skips the low side FET ON pulse whenever the COMP pin voltage exceeds the ramp voltage derived from the current sense. Up to three low side pulses may be skipped in a row before a minimum on-time pulse must be applied to the low side FET. Figure 32 shows the range of ouput voltage (for Io = 3A) with respect to input voltage that will keep the converter from entering either Skip Cycle or Dropout mode. For input voltages below 5.5V, VLIN5 must be connected to Vin through a small resistor (approximately 4.7 ohm). This will ensure that VLIN5 does not fall below the UVLO threshold. 35 30 VOUT 25 20 15 Operating Region 10 5 0 4 8 12 16 20 24 28 32 36 VIN Figure 32. Output Voltage Range Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 21 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com Output Capacitor Selection In applications that exhibit large, fast load current swings, the slew rate of such a load current transient will likely be beyond the response speed of the regulator. Therefore, to meet voltage transient requirements during worstcase load transients, special consideration should be given to output capacitor selection. The total combined ESR of the output capacitors must be lower than a certain value, while the total capacitance must be greater than a certain value. Also, in applications where the specification of output voltage regulation is tight and ripple voltage must be low, starting from the required output voltage ripple will often result in fewer design iterations. ALLOWED TRANSIENT VOLTAGE EXCURSION The allowed output voltage excursion during a load transient (Vc_s) is: where * * % is the output voltage regulation window % is the output voltage initial accuracy (10) Example: Vnom = 5V, % = 7%, % = 3.4%, Vrip = 40mV peak to peak. (11) MAXIMUM ESR CALCULATION Unless the rise and fall times of a load transient are slower than the response speed of the control loop, if the total combined ESR (Re) is too high, the load transient requirement will not be met, no matter how large the capacitance. The maximum allowed total combined ESR is: (12) Since the ripple voltage is included in the calculation of Vc_s, the inductor ripple current should not be included in the worst-case load current excursion. Simply use the worst-case load current excursion for Ic_s. Example: Vc_s = 160 mV, Ic_s = 3A. Then Re_max = 53.3 m. Maximum ESR criterion can be used when the associated capacitance is high enough, otherwise more capacitors than the number determined by this criterion should be used in parallel. MINIMUM CAPACITANCE CALCULATION In a switch mode power supply, the minimum output capacitance is typically dictated by the load transient requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if the maximum ESR requirement is met. The worst-case load transient is an unloading transient that happens when the input voltage is the highest and when the current switching cycle has just finished. The corresponding minimum capacitance is calculated as follows: (13) Notice it is already assumed the total ESR, Re, is no greater than Re_max, otherwise the term under the square root will be a negative value. Also, it is assumed that L has already been selected, therefore the minimum L value should be calculated before Cmin and after Re (see Inductor Selection below). Example: Re = 20 m, Vnom = 5V, Vc_s = 160 mV, Ic_s = 3A, L = 8 H (14) Generally speaking, Cmin decreases with decreasing Re, Ic_s, and L, but with increasing Vnom and Vc_s. 22 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 Inductor Selection The size of the output inductor can be determined from the desired output ripple voltage, Vrip, and the impedance of the output capacitors at the switching frequency. The equation to determine the minimum inductance value is as follows: (15) In the above equation, Re is used in place of the impedance of the output capacitors. This is because in most cases, the impedance of the output capacitors at the switching frequency is very close to Re. In the case of ceramic capacitors, replace Re with the true impedance at the switching frequency. Example: Vin = 36V, Vo = 3.3V, VRIP = 60 mV, Re = 20 m, F = 200 kHz. Lmin = 3.3 x 0.02 36 - 3.3 x = 5PH 200kHz x 36 .060 (16) The actual selection process usually involves several iterations of all of the above steps, from ripple voltage selection, to capacitor selection, to inductance calculations. Both the highest and the lowest input and output voltages and load transient requirements should be considered. If an inductance value larger than Lmin is selected, make sure that the Cmin requirement is not violated. Priority should be given to parameters that are not flexible or more costly. For example, if there are very few types of capacitors to choose from, it may be a good idea to adjust the inductance value so that a requirement of 3.2 capacitors can be reduced to 3 capacitors. Since inductor ripple current is often the criterion for selecting an output inductor, it is a good idea to doublecheck this value. The equation is: (17) Also important is the ripple content, which is defined by Irip /Inom. Generally speaking, a ripple content of less than 50% is ok. Larger ripple content will cause too much power loss in the inductor. Example: Vin = 36V, Vo = 3.3V, F = 200 kHz, L = 5 H, 3A max IOUT Irip = 36 - 3.3 3.3 x = 3A 36 200kHz x 5x10-6 (18) 3A is 100% ripple which is too high. In this case, the inductor should be reselected on the basis of ripple current. Example: 40% ripple, 40% * 3A = 1.2A 1.2A = L= 36 - 3.3 3.3 x L x 200kHz 36 (19) 36 - 3.3 3.3 x = 12.5PH 200kHz x 1.2A 36 (20) When choosing the inductor, the saturation current should be higher than the maximum peak inductor current and the RMS current rating should be higher than the maximum load current. Input Capacitor Selection The fact that the two switching channels of the LM5642 are 180 out of phase will reduce the RMS value of the ripple current seen by the input capacitors. This will help extend input capacitor life span and result in a more efficient system. Input capacitors must be selected that can handle both the maximum ripple RMS current at highest ambient temperature as well as the maximum input voltage. In applications in which output voltages are less than half of the input voltage, the corresponding duty cycles will be less than 50%. This means there will be no overlap between the two channels' input current pulses. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 23 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com The equation for calculating the maximum total input ripple RMS current for duty cycles under 50% is: where * * * * I1 is maximum load current of Channel 1 I2 is the maximum load current of Channel 2 D1 is the duty cycle of Channel 1 D2 is the duty cycle of Channel 2 (21) Example: Imax_1 = 3.6A, Imax_2 = 3.6A, D1 = 0.42, and D2 = 0.275 (22) Choose input capacitors that can handle 1.66A ripple RMS current at highest ambient temperature. In applications where output voltages are greater than half the input voltage, the corresponding duty cycles will be greater than 50%, and there will be overlapping input current pulses. Input ripple current will be highest under these circumstances. The input RMS current in this case is given by: (23) Where, again, I1 and I2 are the maximum load currents of channel 1 and 2, and D1 and D2 are the duty cycles. This equation should be used when both duty cycles are expected to be higher than 50%. If the LM5642 is being used with an external clock frequency other than 200kHz, or 375 kHz for the LM5642X, the preceding equations for input rms current can still be used. The selection of the first equation or the second changes because overlap can now occur at duty cycles that are less than 50%. From the EXTERNAL FREQUENCY SYNC section, the maximum duty cycle that ensures no overlap between duty cycles (and hence input current pulses) is: DMAX = FSYNC* 2.5 x 10-6 (24) There are now three distinct possibilities which must be considered when selecting the equation for input rms current. The following applies for the LM5642, and also the LM5642X by replacing 200 kHz with 375 kHz: 1. Both duty cycles D1 and D2 are less than DMAX. In this case, the first, simple equation can always be used. 2. One duty cycle is greater than DMAX and the other duty cycle is less than DMAX. In this case, the system designer can take advantage of the fact that the sync feature reduces DMAX for one channel, but lengthens it for the other channel. For FSYNC < 200kHz, D1 is reduced to DMAX while D2 actually increases to (1-DMAX). For FSYNC > 200kHz, D2 is reduced to DMAX while D1 increases to (1-DMAX). By using the channel reduced to DMAX for the lower duty cycle, and the channel that has been increased for the higher duty cycle, the first, simple rms input current equation can be used. 3. Both duty cycles are greater than DMAX. This case is identical to a system at 200 kHz where either duty cycle is 50% or greater. Some overlap of duty cycles is specified, and hence the second, more complicated rms input current equation must be used. Input capacitors must meet the minimum requirements of voltage and ripple current capacity. The size of the capacitor should then be selected based on hold up time requirements. Bench testing for individual applications is still the best way to determine a reliable input capacitor value. Input capacitors should always be placed as close as possible to the current sense resistor or the drain of the top FET. When high ESR capacitors such as tantalum are used, a 1F ceramic capacitor should be added as closely as possible to the high-side FET drain and low-side FET source. 24 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 MOSFET Selection BOTTOM FET SELECTION During normal operation, the bottom FET is switching on and off at almost zero voltage. Therefore, only conduction losses are present in the bottom FET. The most important parameter when selecting the bottom FET is the on-resistance (RDS-ON). The lower the on-resistance, the lower the power loss. The bottom FET power loss peaks at maximum input voltage and load current. The equation for the maximum allowed on-resistance at room temperature for a given FET package, is: where * * * * Tj_max is the maximum allowed junction temperature in the FET Ta_max is the maximum ambient temperature Rja is the junction-to-ambient thermal resistance of the FET TC is the temperature coefficient of the on-resistance which is typically in the range of 4000ppm/C (25) If the calculated RDS-ON (MAX) is smaller than the lowest value available, multiple FETs can be used in parallel. This effectively reduces the Imax term in the above equation, thus reducing RDS-ON. When using two FETs in parallel, multiply the calculated RDS-ON (MAX) by 4 to obtain the RDS-ON (MAX) for each FET. In the case of three FETs, multiply by 9. (26) If the selected FET has an Rds value higher than 35.3, then two FETs with an RDS-ON less than 141 m (4 x 35.3 m) can be used in parallel. In this case, the temperature rise on each FET will not go to Tj_max because each FET is now dissipating only half of the total power. TOP FET SELECTION The top FET has two types of losses: switching loss and conduction loss. The switching losses mainly consist of crossover loss and losses related to the low-side FET body diode reverse recovery. Since it is rather difficult to estimate the switching loss, a general starting point is to allot 60% of the top FET thermal capacity to switching losses. The best way to precisely determine switching losses is through bench testing. The equation for calculating the on resistance of the top FET is thus: (27) Example: Tj_max = 100C, Ta_max = 60C, Rqja = 60C/W, Vin_min = 5.5V, Vnom = 5V, and Iload_max = 3.6A. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 25 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com (28) When using FETs in parallel, the same guidelines apply to the top FET as apply to the bottom FET. Loop Compensation The general purpose of loop compensation is to meet static and dynamic performance requirements while maintaining stability. Loop gain is what is usually checked to determine small-signal performance. Loop gain is equal to the product of control-output transfer function and the feedback transfer function (the compensation network transfer function). Generally speaking it is desirable to have a loop gain slope that is roughly -20dB /decade from a very low frequency to well beyond the crossover frequency. The crossover frequency should not exceed one-fifth of the switching frequency. The higher the bandwidth, the faster the load transient response speed will be. However, if the duty cycle saturates during a load transient, further increasing the small signal bandwidth will not help. Since the control-output transfer function usually has very limited low frequency gain, it is a good idea to place a pole in the compensation at zero frequency, so that the low frequency gain will be relatively large. A large DC gain means high DC regulation accuracy (i.e. DC voltage changes little with load or line variations). The rest of the compensation scheme depends highly on the shape of the control-output plot. 20 0 Asymptoti c GAIN (dB) PHASE () -45 0 -90 -20 Phas e -135 -40 Gain -60 10 100 -180 1M 1 10 100 k k k FREQUENCY (Hz) Figure 33. Control-Output Transfer Function GAIN (dB) As shown in Figure 33, the control-output transfer function consists of one pole (fp), one zero (fz), and a double pole at fn (half the switching frequency). The following can be done to create a -20dB /decade roll-off of the loop gain: Place the first pole at 0Hz, the first zero at fp, the second pole at fz, and the second zero at fn. The resulting feedback transfer function is shown in Figure 34. -20 dB/ dec (fp1 is at zero frequency) -20 dB/ dec B fz1 fp2 fz2 FREQUENCY Figure 34. Feedback Transfer Function 26 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 The control-output corner frequencies, and thus the desired compensation corner frequencies, can be determined approximately by the following equations: (29) fP = 1 1 - D - .5 + 2SRO CO 2SfLCO (30) Since fp is determined by the output network, it will shift with loading (Ro). It is best to use a minimum Iout value of approximately 100mA when determining the maximum Ro value. Example: Re = 20 m, Co = 100 uF, Romax = 5V/100 mA = 50: (31) (32) First determine the minimum frequency (fpmin) of the pole across the expected load range, then place the first compensation zero at or below that value. Once fpmin is determined, Rc1 should be calculated using: where * * * B is the desired gain in V/V at fp (fz1) gm is the transconductance of the error amplifier R1 and R2 are the feedback resistors (33) A gain value around 10dB (3.3v/v) is generally a good starting point. Example: B = 3.3v/v, gm = 650m, R1 = 20 kK, R2 = 60.4 k: (34) Bandwidth will vary proportional to the value of Rc1. Next, Cc1 can be determined with the following equation: (35) Example: fpmin = 995 Hz, Rc1 = 20 k: (36) The compensation network (Figure 35) will also introduce a low frequency pole which will be close to 0 Hz. A second pole should also be placed at fz. This pole can be created with a single capacitor Cc2 and a shorted Rc2 (see Figure 35). The minimum value for this capacitor can be calculated by: (37) Cc2 may not be necessary, however it does create a more stable control loop. This is especially important with high load currents and in current sharing mode. Example: fz = 80 kHz, Rc1 = 20 k: (38) Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 27 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com A second zero can also be added with a resistor in series with Cc2. If used, this zero should be placed at fn, where the control to output gain rolls off at -40dB/dec. Generally, fn will be well below the 0dB level and thus will have little effect on stability. Rc2 can be calculated with the following equation: (39) Vo Vc CC1 RC1 gm R2 CC2 RC2 compensation network R1 Figure 35. Compensation Network PCB Layout Considerations To produce an optimal power solution with the LM5642 series, good layout and design of the PCB are as important as the component selection. The following are several guidelines to aid in creating a good layout. KELVIN TRACES FOR SENSE LINES When using the current sense resistor to sense the load current connect the KS pin using a separate trace to VIN, as close as possible to the current-sense resistor. The RSNS pin should be connected using a separate trace to the low-side of the current sense resistor. The traces should be run parallel to each other to give common mode rejection. Although it can be difficult in a compact design, these traces should stay away from the output inductor and switch node if possible, to avoid coupling stray flux fields. When a current-sense resistor is not used the KS pin should be connected as close as possible to the drain node of the upper MOSFET and the RSNS pin should be connected as close as possible to the source of the upper MOSFET using Kelvin traces. To further help minimize noise pickup on the sense lines is to use RC filtering on the KS and RSNS pins. SEPARATE PGND AND SGND Good layout techniques include a dedicated ground plane, usually on an internal layer. Signal level components like the compensation and feedback resistors should be connected to a section of this internal SGND plane. The SGND section of the plane should be connected to the power ground at only one point. The best place to connect the SGND and PGND is right at the PGND pin.. MINIMIZE THE SWITCH NODE The plane that connects the power FETs and output inductor together radiates more EMI as it gets larger. Use just enough copper to give low impedance to the switching currents, preferably in the form of a wide, but short, trace run. LOW IMPEDANCE POWER PATH The power path includes the input capacitors, power FETs, output inductor, and output capacitors. Keep these components on the same side of the PCB and connect them with thick traces or copper planes (shapes) on the same layer. Vias add resistance and inductance to the power path, and have relatively high impedance connections to the internal planes. If high switching currents must be routed through vias and/or internal planes, use multiple vias in parallel to reduce their resistance and inductance. The power components should be kept close together. The longer the paths that connect them, the more they act as antennas, radiating unwanted EMI. Please see AN-1229 (literature number SNVA054) for further PCB layout considerations. 28 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 Table 1. Bill Of Materials for Figure 3 24V to 1.8, 3.3V LM5642 ID Part Number Type Size U1 LM5642 Dual Synchronous Controller TSSOP-28 Q1, Q4 Si4850EY N-MOSFET SO-8 Q2, Q5 Si4840DY N-MOSFET SO-8 D3 BAS40-06 Schottky Diode L1 RLF12560T-4R2N100 Inductor L2 RLF12545T-100M5R1 Inductor 12.5x12.5x 4.5mm Parameters Qty Vendor 1 TI 60V 2 Vishay 40V 2 Vishay SOT-23 40V 1 Vishay 12.5x12.5x 6mm 4.2H, 7m 10A 1 TDK 10H, 12m 5.1A 1 TDK C1 C3216X7R1H105K Capacitor 1206 1F, 50V 1 TDK C3, C4, C14, C15 VJ1206Y101KXXAT Capacitor 1206 100pF, 25V 3 Vishay C27 C2012X5R1C105K Capacitor 0805 1F, 16V 1 TDK C6, C16 C5750X5R1H106M Capacitor 2220 10F 50V, 2.8A 2 TDK C9, C23 6TPD330M Capacitor 7.3x4.3x 3.8mm 330F, 6.3V, 10m 2 Sanyo C2, C11, C12, C13 VJ1206Y103KXXAT Capacitor 1206 10nF, 25V 4 Vishay C7, C25, C34 VJ1206Y104KXXAT Capacitor 1206 100nF, 25V 3 Vishay C19 VJ1206Y822KXXAT Capacitor 1206 8.2nF 10% 1 Vishay C20 VJ1206Y153KXXAT Capacitor 1206 15nF 10% 1 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7F 25V 1 TDK R1 CRCW1206123J Resistor 1206 12k 5% 1 Vishay R2, R6, R14, R16 CRCW1206100J Resistor 1206 100 5% 1 Vishay R13 CRCW1206682J Resistor 1206 6.8k 12% 1 Vishay R7, R15 WSL-2512 .010 1% Resistor 2512 10m 1W 2 Vishay R8, R9, R12, R17, R18, R21, R31, R32 CRCW1206000Z Resistor 1206 0 8 Vishay R10 CRCW12062261F Resistor 1206 2.26k 1% 1 Vishay R23 CRCW12068451F Resistor 1206 8.45k 1% 1 Vishay R24 CRCW12061372F Resistor 1206 13.7k 1% 1 Vishay R11, R20 CRCW12064991F Resistor 1206 4.99k 1% 2 Vishay R19 CRCW12068251F Resistor 1206 8.25k 1% 1 Vishay R27 CRCW12064R7J Resistor 1206 4.7 5% 1 Vishay R28 CRCW1206224J Resistor 1206 220k 5% 1 Vishay Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 29 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com Table 2. Bill of Materials for Figure 4 30V to 1.8V, 20A LM5642 ID Part Number Type Size U1 LM5642 Dual Synchronou s Controller TSSOP-28 Parameters Qty Vendor 1 TI Q1, Q4 Si4850EY N-MOSFET SO-8 60V 2 Vishay Q2, Q3, Q5, Q6 Si4470DY N-MOSFET SO-8 60V 4 Vishay D3 BAS40-06 Schottky Diode SOT-23 40V 1 Vishay L1,L2 RLF12560T-2R7N110 Inductor 12.5x12.5x 6mm 2.7H,4.5m 11.5A 2 TDK C1 C3216X7R1H105K Capacitor 1206 1F, 50V 1 TDK C10, C24, C27 C2012X5R1C105K Capacitor 0805 1F, 16V 3 TDK C6, C16, C28, C30 C5750X5R1H106M Capacitor 2220 10F 50V, 2.8A 4 TDK C9, C23 16MV1000WX Capacitor 10mm D20mm H 1000F, 16V, 22m 2 Sanyo C2, C13 VJ1206Y103KXXAT Capacitor 1206 10nF, 25V 2 Vishay C11 VJ1206Y223KXXAT Capacitor 1206 22nF, 25V 1 Vishay C7,C25, C34 VJ1206Y104KXXAT Capacitor 1206 100nF, 25V 3 Vishay C19 VJ1206Y273KXXAT Capacitor 1206 27nF 10% 1 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7F 25V 1 TDK R1, R13 CRCW1206123J Resistor 1206 16.9k 1% 1 Vishay R2, R6, R14, R16 CRCW1206100J Resistor 1206 100 5% 1 Vishay R7, R15 WSL-2512 .010 1% Resistor 2512 10m 1W 2 Vishay R8, R9, R12, R17, R18, R21, R31, R32 CRCW1206000Z Resistor 1206 0 8 Vishay R10 CRCW12062261F Resistor 1206 2.26k 1% 1 Vishay R11 CRCW12064991F Resistor 1206 4.99k 1% 1 Vishay R23 CRCW12061152F Resistor 1206 11.5k 1% 1 Vishay R27 CRCW12064R7J Resistor 1206 4.7 5% 1 Vishay R28 CRCW1206224J Resistor 1206 220k 5% 1 Vishay 30 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 Table 3. Bill Of Materials Based on Figure 3 Vin= 9-16V, VO1,2=1.5V,1.8V, 5A LM5642X ID Part Number Type Size U1 LM5642X Dual Synchronous Controller TSSOP-28 Q1, Q4 Si4850EY N-MOSFET SO-8 Q2, Q5 Si4840DY N-MOSFET SO-8 Parameters Qty Vendor 1 TI 60V 2 Vishay 40V 2 Vishay D3 BA54A Schottky Diode SOT-23 30V 1 Vishay L1, L2 RLF12545T-4R2N100 Inductor 12.5x12.5x 4.5mm 4.2H, 7m 6.5A 2 TDK C1 C3216X7R1H105K Capacitor 1206 1F, 50V 1 TDK C3, C4, C14, C15 VJ1206Y101KXXAT Capacitor 1206 100pF, 25V 4 Vishay C27 C2012X5R1C105K Capacitor 0805 1F, 16V 1 TDK C6, C28 C5750X7R1H106M Capacitor 2220 10F 50V, 2.8A 2 TDK C9, C23 C4532X7R0J107M Capacitor 1812 100F, 6.3V, 1m 2 TDK C2, C11, C12, C13 VJ1206Y103KXXAT Capacitor 1206 10nF, 25V 4 Vishay C7, C25, C34 VJ1206Y104KXXAT Capacitor 1206 100nF, 25V 3 Vishay C18, C20 VJ1206Y473KXXAT Capacitor 1206 47nF 10% 2 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7F 25V 1 TDK R1, R13 CRCW12061912F Resistor 1206 19.1k 1% 2 Vishay R2, R6, R14, R16 CRCW1206100J Resistor 1206 100 5% 1 Vishay R7, R15 WSL-1206 .020 1% Resistor 1206 20m 1W 2 Vishay R8, R9, R12, R17, R18, R21, R31, R32 CRCW1206000Z Resistor 1206 0 8 Vishay R10, R19 CRCW12061001F Resistor 1206 1k 1% 2 Vishay R11 CRCW12062611F Resistor 1206 2.61k 1% 1 Vishay R20 CRCW12062321F Resistor 1206 2.32k 1% 1 Vishay R22, R24 CRCW12063011F Resistor 1206 3.01k 1% 2 Vishay R27 CRCW12064R7J Resistor 1206 4.7 5% 1 Vishay R28 CRCW1206224J Resistor 1206 220k 5% 1 Vishay Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 31 LM5642, LM5642X SNVS219K - JUNE 2003 - REVISED APRIL 2013 www.ti.com Table 4. Bill Of Materials Based on Figure 3 Vin= 9-16V, VO1,2=3.3V,5V, 5A LM5642X ID Part Number Type Size U1 LM5642X Dual Synchronous Controller TSSOP-28 Q1, Q4 Si4850EY N-MOSFET SO-8 Q2, Q5 Si4840DY N-MOSFET SO-8 Parameters Qty Vendor 1 TI 60V 2 Vishay 40V 2 Vishay D3 BA54A Schottky Diode SOT-23 30V 1 Vishay L1, L2 RLF12545T-5R6N6R1 Inductor 12.5x12.5x 4.5mm 5.6H, 9m 6.1A 2 TDK C1 C3216X7R1H105K Capacitor 1206 1F, 50V 1 TDK C3, C4, C14, C15 VJ1206Y101KXXAT Capacitor 1206 100pF, 25V 4 Vishay C27 C2012X5R1C105K Capacitor 0805 1F, 16V 1 TDK C6, C28 C5750X7R1H106M Capacitor 2220 10F 50V, 2.8A 2 TDK C9, C23 C4532X7R0J107M Capacitor 1812 100F, 6.3V, 1m 2 TDK C2, C11, C12, C13 VJ1206Y103KXXAT Capacitor 1206 10nF, 25V 4 Vishay C7, C25, C34 VJ1206Y104KXXAT Capacitor 1206 100nF, 25V 3 Vishay C18, C20 VJ1206Y393KXXAT Capacitor 1206 39nF 10% 2 Vishay C26 C3216X7R1C475K Capacitor 1206 4.7F 25V 1 TDK R1, R13 CRCW12061912F Resistor 1206 19.1k 1% 2 Vishay R2, R6, R14, R16 CRCW1206100J Resistor 1206 100 5% 1 Vishay R7, R15 WSL-1206 .020 1% Resistor 1206 20m 1W 2 Vishay R8, R9, R12, R17, R18, R21, R31, R32 CRCW1206000Z Resistor 1206 0 8 Vishay R10, R19 CRCW12061002F Resistor 1206 10k 1% 2 Vishay R11 CRCW12066191F Resistor 1206 6.19k 1% 1 Vishay R20 CRCW12063321F Resistor 1206 3.32k 1% 1 Vishay R22, R24 CRCW12063831F Resistor 1206 3.83k 1% 2 Vishay R27 CRCW12064R7J Resistor 1206 4.7 5% 1 Vishay R28 CRCW1206224J Resistor 1206 220k 5% 1 Vishay 32 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X LM5642, LM5642X www.ti.com SNVS219K - JUNE 2003 - REVISED APRIL 2013 REVISION HISTORY Changes from Revision J (April 2013) to Revision K * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 32 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM5642 LM5642X 33 PACKAGE OPTION ADDENDUM www.ti.com 1-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM5642MH/NOPB ACTIVE HTSSOP PWP 28 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM5642 MH LM5642MHX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM5642 MH LM5642MTC NRND TSSOP PW 28 48 TBD Call TI Call TI -40 to 125 LM5642 MTC LM5642MTC/NOPB ACTIVE TSSOP PW 28 48 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM5642 MTC LM5642MTCX NRND TSSOP PW 28 2500 TBD Call TI Call TI -40 to 125 LM5642 MTC LM5642MTCX/NOPB ACTIVE TSSOP PW 28 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM5642 MTC LM5642XMH/NOPB ACTIVE HTSSOP PWP 28 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5642 XMH LM5642XMHX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5642 XMH LM5642XMT/NOPB ACTIVE TSSOP PW 28 48 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM5642 XMT LM5642XMTX/NOPB ACTIVE TSSOP PW 28 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM5642 XMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Jun-2014 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Sep-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM5642MHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.8 10.2 1.6 8.0 16.0 Q1 LM5642MTCX TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642MTCX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642XMHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642XMTX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Sep-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5642MHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM5642MTCX TSSOP PW 28 2500 367.0 367.0 38.0 LM5642MTCX/NOPB TSSOP PW 28 2500 367.0 367.0 38.0 LM5642XMHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM5642XMTX/NOPB TSSOP PW 28 2500 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE OUTLINE PWP0028A PowerPAD TM - 1.1 mm max height SCALE 1.800 PLASTIC SMALL OUTLINE C 6.6 TYP 6.2 A SEATING PLANE PIN 1 ID AREA 28 1 9.8 9.6 NOTE 3 0.1 C 26X 0.65 2X 8.45 14 B 15 4.5 4.3 NOTE 4 0.30 0.19 0.1 C A 28X 1.1 MAX B 0.20 TYP 0.09 SEE DETAIL A 3.15 2.75 0.25 GAGE PLANE 5.65 5.25 THERMAL PAD 0 -8 0.10 0.02 0.7 0.5 (1) DETAIL A TYPICAL 4214870/A 10/2014 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MO-153, variation AET. www.ti.com EXAMPLE BOARD LAYOUT PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 (3) SOLDER MASK OPENING 28X (1.5) 28X (0.45) SOLDER MASK DEFINED PAD 1 28X (0.45) 28X (1.3) 28 26X (0.65) SYMM (5.5) (9.7) SOLDER MASK OPENING (1.3) TYP 14 15 ( 0.2) TYP VIA (1.3) SEE DETAILS SYMM (0.9) TYP METAL COVERED BY SOLDER MASK (0.65) TYP (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214870/A 10/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3) BASED ON 0.127 THICK STENCIL 28X (1.5) 28X (0.45) METAL COVERED BY SOLDER MASK 1 28X (1.3) 28 26X (0.65) 28X (0.45) (5.5) BASED ON 0.127 THICK STENCIL SYMM 14 15 SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SYMM (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE AREA SCALE:6X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.127 0.152 0.178 3.55 X 6.37 3.0 X 5.5 (SHOWN) 2.88 X 5.16 2.66 X 4.77 4214870/A 10/2014 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. 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