DS90UB949TRGCTQ1 - Texas Instruments

FPD-Link III

2 Lane

VDDIO

1.8V

IDx

DOUT0+

DOUT0-

1.1V

IN_CLK-/+

HDMI

HPD

DDC

CEC

DOUT1+

DOUT1-

RIN0+

RIN0-

RIN1+

RIN1-

CLK+/-

CLK2+/-

FPD-Link

(Open LDI)

D0+/-

D1+/-

D2+/-

D3+/-

D4+/-

D5+/-

D6+/-

D7+/-

DS90UB949-Q1

Serializer DS90UB948-Q1

Deserializer

IDx

D_GPIO

(SPI)

D_GPIO

(SPI)

LVDS

Display

1080p60

or Graphic

Processor

Graphics

Processor

IN_D0-/+

IN_D1-/+

IN_D2-/+

I2C

VDDIO

(3.3V / 1.8V)

3.3V

I2C

1.2V1.8V

HDMI ± High Definition Multimedia Interface

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

DS90UB949-Q1 1080p HDMI to FPD-Link III Bridge Serializer

1 Features 3 Description

The DS90UB949-Q1 is a HDMI to FPD-Link III bridge

1• Supports TMDS Clock up to 170 MHz for WUXGA device which, in conjunction with the FPD-Link III

(1920x1200) and 1080p60 Resolutions with 24-Bit DS90UB940-Q1/DS90UB948-Q1 deserializers,

Color Depth provides 1-lane or 2-lane high-speed serial streams

• Single and Dual FPD-Link III Outputs over cost-effective 50Ωsingle-ended coaxial or 100Ω

differential shielded twisted-pair (STP) cables. It

• High-Definition Multimedia (HDMI) v1.4b Inputs serializes a HDMI v1.4b input supporting video

• HDMI-Mode DisplayPort (DP++) Inputs resolutions up to WUXGA and 1080p60 with 24-bit

• HDMI Audio Extraction for up to 8 Channels color depth.

• High Speed Back Channel Supporting GPIO up to The FPD-Link III interface supports video and audio

2 Mbps data transmission and full duplex control, including

• Supports up to 15 Meters of Cable with Automatic I2C and SPI communication, over the same

Temperature and Aging Compensation differential link. Consolidation of video data and

control over two differential pairs reduces the

• Tracks Spread Spectrum Input Clock to Reduce interconnect size and weight and simplifies system

EMI design. EMI is minimized by the use of low voltage

• I2C (Master/Slave) with 1Mbps Fast-Mode Plus differential signaling, data scrambling, and

• SPI Pass-Through Interface randomization. In backward compatible mode, the

device supports up to WXGA and 720p resolutions

• Backward compatible with DS90UB926Q-Q1 and with 24-bit color depth over a single differential link.

DS90UB928Q-Q1 FPD-Link III Deserializers

• Automotive Grade Product: AEC-Q100 Grade 2 The DS90UB949-Q1 supports multi-channel audio

received through HDMI or an external I2S interface.

Qualified The device also supports an optional auxiliary audio

interface.

2 Applications

• Automotive Infotainment: Device Information(1)

– IVI Head Units and HMI Modules PART NUMBER PACKAGE BODY SIZE (NOM)

– Rear Seat Entertainment Systems DS90UB949-Q1 VQFN RGC (64) 9.00 mm X 9.00 mm

– Digital Instrument Clusters (1) For all available packages, see the orderable addendum at

the end of the datasheet.

• Security and Surveillance Camera

• Consumer Input HDMI Port

4 Applications Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

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Table of Contents

8.3 Feature Description................................................. 18

1 Features.................................................................. 18.4 Device Functional Modes........................................ 31

2 Applications ........................................................... 18.5 Programming........................................................... 33

3 Description............................................................. 18.6 Register Maps......................................................... 37

4 Applications Diagram............................................ 19 Application and Implementation ........................ 66

5 Revision History..................................................... 29.1 Applications Information.......................................... 66

6 Pin Configuration and Functions......................... 39.2 Typical Applications ................................................ 66

7 Specifications......................................................... 710 Power Supply Recommendations ..................... 71

7.1 Absolute Maximum Ratings ..................................... 710.1 Power Up Requirements And PDB Pin................. 71

7.2 Handling Ratings....................................................... 711 Layout................................................................... 72

7.3 Recommended Operating Conditions....................... 711.1 Layout Guidelines ................................................. 72

7.4 Thermal Information.................................................. 811.2 Layout Example .................................................... 73

7.5 DC Electrical Characteristics .................................... 912 Device and Documentation Support................. 74

7.6 AC Electrical Characteristics................................... 11 12.1 Documentation Support ....................................... 74

7.7 DC And AC Serial Control Bus Characteristics ...... 12 12.2 Trademarks........................................................... 74

7.8 Recommended Timing for the Serial Control Bus .. 13 12.3 Electrostatic Discharge Caution............................ 74

7.9 Typical Characteristics............................................ 16 12.4 Glossary................................................................ 74

8 Detailed Description............................................ 17 13 Mechanical, Packaging and Orderable

8.1 Overview................................................................. 17 Information........................................................... 74

8.2 Functional Block Diagram....................................... 17

5 Revision History

DATE REVISION NOTES

November 2014 * Initial release.

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VDD18

VDDIO

SDIN / GPIO0

RES0

IN_D0-

VTERM

IN_D0+

VDDHA11

IN_D1-

IN_D1+

SCL

VDDHS11

VDD18

RES2

PDB

VDDA11

D_GPIO0 / MOSI

DOUT0-

DOUT0+

MCLK

VDDS11

DOUT1-

DOUT1+

IN_D2-

VDDHA11

CEC

IN_D2+

VDD18

VDDHA11

I2S_DC / GPIO2

I2S_DD / GPIO3

VDDHA11

LFT

MODE_SEL0

IDx

RX_5V

IN_CLK-

IN_CLK+

VDDL11

REM_INTB

SCLK / I2CSEL

VDDL11

RES1

VDDHS11

DDC_SDA

NC1

DDC_SCL

NC0

SDA

INTB

D_GPIO3 / SS

D_GPIO2 / SPLK

I2S_WC / GPIO7_REG

I2S_DB / GPIO5_REG

I2S_CLK / GPIO8_REG

I2S_DA / GPIO6_REG

D_GPIO1 / MISO

MODE_SEL1

NC2

HPD

SWC / GPIO1

DS90UB949-Q1

DAP = GND

VDDP11

VDDIO

64 VQFN

Top View

DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

6 Pin Configuration and Functions

64 PINS

Top View

Pin Functions

PIN I/O, TYPE DESCRIPTION

NAME NO.

HDMI TMDS INPUT

IN_CLK- 49 I, TMDS TMDS Clock Differential Input

IN_CLK+ 50

IN_D0- 55 I, TMDS TMDS Data Channel 0 Differential Input

IN_D0+ 56

IN_D1- 59 I, TMDS TMDS Data Channel 1 Differential Input

IN_D1+ 60

IN_D2- 62 I, TMDS TMDS Data Channel 2 Differential Input

IN_D2+ 63

OTHER HDMI

HPD 42 O, Open- Hot Plug Detect Output. Pull up to RX_5V with a 1kΩresistor

Drain

RX_5V 43 I HDMI 5V Detect Input

DDC_SDA 44 IO, Open- DDC Slave Serial Data

Drain Pull up to RX_5V with a 47kΩresistor

DDC_SCL 45 I, Open-Drain DDC Slave Serial Clock

Pull up to RX_5V with a 47kΩresistor

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Pin Functions (continued)

PIN I/O, TYPE DESCRIPTION

NAME NO.

CEC 1 IO, Open- Consumer Electronic Control Channel Input/Output Interface.

Drain Pull-up with a 27kΩresistor to 3.3V

X1 39 I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be

connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level

1.8V. Leave it open if unused.

FPD-LINK III SERIAL

DOUT0- 26 O FPD-Link III Inverting Output 0

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

DOUT0+ 27 O FPD-Link III True Output 0

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

DOUT1- 22 O FPD-Link III Inverting Output 1

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

DOUT1+ 23 O FPD-Link III True Output 1

The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers

and 33nF capacitor for 94x deserializers

LFT 20 Analog FPD-Link III Loop Filter

Connect to a 10nF capacitor to GND

CONTROL

SDA 14 IO, Open- I2C Data Input / Output Interface

Drain Open drain. Must have an external pull-up to resistor to 1.8V or 3.3V. See I2CSEL pin. DO

NOT FLOAT.

Recommended pull-up: 4.7kΩ.

SCL 15 IO, Open- I2C Clock Input / Output Interface

Drain Open drain. Must have an external pull-up resistor to 1.8V or 3.3V. See I2CSEL pin. DO

NOT FLOAT.

Recommended pull-up: 4.7kΩ.

I2CSEL 6 I, LVCMOS I2C Voltage Level Strap Option

Tie to VDDIO with a 10kΩresistor for 1.8V I2C operation.

Leave floating for 3.3V I2C operation.

This pin is read as an input at power up.

IDx 19 Analog I2C Serial Control Bus Device ID Address Select

MODE_SEL0 18 Analog Mode Select 0. See Table 6.

MODE_SEL1 32 Analog Mode Select 1. See Table 6.

PDB 31 I, LVCMOS Power-Down Mode Input Pin

INTB 13 O, Open- Open Drain. Remote interrupt. Active LOW.

Drain Pull up to VDDIO with a 4.7kΩresistor.

REM_INTB 40 O, Open- Remote interrupt. Mirrors status of INTB_IN from the deserializer.

Drain Note: External pull-up to 1.8V required. Recommended pull-up: 4.7kΩ.

INTB = H, Normal Operation

INTB = L, Interrupt Request

SPI PINS (DUAL LINK MODE ONLY)

MOSI 8 IO, LVCMOS SPI Master Out Slave In. Shared with D_GPIO0

MISO 10 IO, LVCMOS SPI Master In Slave Out. Shared with D_GPIO1

SPLK 11 IO, LVCMOS SPI Clock. Shared with D_GPIO2

SS 12 IO, LVCMOS SPI Slave Select. Shared with D_GPIO3

HIGH SPEED (HS) BIDIRECTIONAL CONTROL CHANNEL GPIO PINS (DUAL LINK MODE ONLY)

D_GPIO0 8 IO, LVCMOS HS GPIO0. Shared with MOSI

D_GPIO1 10 IO, LVCMOS HS GPIO1. Shared with MISO

D_GPIO2 11 IO, LVCMOS HS GPIO2. Shared with SPLK

D_GPIO3 12 IO, LVCMOS HS GPIO3. Shared with SS

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Pin Functions (continued)

PIN I/O, TYPE DESCRIPTION

NAME NO.

BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS

GPIO0 4 IO, LVCMOS BCC GPIO0. Shared with SDIN

GPIO1 5 IO, LVCMOS BCC GPIO1. Shared with SWC

GPIO2 37 IO, LVCMOS BCC GPIO2. Shared with I2S_DC

GPIO3 38 IO, LVCMOS BCC GPIO3. Shared with I2S_DD

GPIO5_REG 36 IO, LVCMOS General Purpose Input/Output 5

Local register control only. Shared with I2S_DB

GPIO6_REG 35 IO, LVCMOS General Purpose Input/Output 6

Local register control only. Shared with I2S_DA

GPIO7_REG 33 IO, LVCMOS General Purpose Input/Output 7

Local register control only. Shared with I2S_WC

GPIO8_REG 34 IO, LVCMOS General Purpose Input/Output 8

Local register control only. Shared with I2S_CLK

SLAVE MODE LOCAL I2S CHANNEL PINS

I2S_WC 33 I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG

I2S_CLK 34 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG

I2S_DA 35 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG

I2S_DB 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG

I2S_DC 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2

I2S_DD 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3

AUXILIARY I2S CHANNEL PINS

SWC 5 O, LVCMOS Master Mode I2S Word Clock Ouput. Shared with GPIO1

SCLK 6 O, LVCMOS Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up

as I2CSEL, then it will switch to SCLK operation as an output.

SDIN 4 I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0

MCLK 16 IO, LVCMOS Master Mode I2S System Clock Input/Output

POWER and GROUND

VTERM 57 Power 3.3V (±5%) Supply for DC-coupled internal termination OR

1.8V (±5%) Supply for AC-coupled internal termination

Refer to Figure 25 or Figure 26.

VDD18 24 Power 1.8 (±5%) Analog supply. Refer to Figure 25 or Figure 26.

VDDA11 9 Power 1.1V(±5%) Analog supply. Refer to Figure 25 or Figure 26.

VDDHA11 52 Power 1.1V(±5%) TMDS supply. Refer to Figure 25 or Figure 26.

VDDHS11 21 Power 1.1V(±5%) supply. Refer to Figure 25 or Figure 26.

VDDL11 7 Power 1.1V(±5%) Digital supply. Refer to Figure 25 or Figure 26.

VDDP11 17 Power 1.1V(±5%) PLL supply. Refer to Figure 25 or Figure 26.

VDDS11 25 Power 1.1V(±5%) Serializer supply. Refer to Figure 25 or Figure 26.

VDDIO 3 Power 1.8V (±5%) IO supply. Refer to Figure 25 or Figure 26.

GND Thermal GND Ground. Connect to Ground plane with at least 9 vias.

Pad

OTHER

RES0 2 Reserved. Tie to GND.

RES1 29

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Pin Functions (continued)

PIN I/O, TYPE DESCRIPTION

NAME NO.

RES2 30 Reserved. Connect with 50Ωto GND.

NC0 47 No connect. Leave floating. Do not connect to VDD or GND.

NC1 48

NC2 53

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SNLS452 –NOVEMBER 2014

7 Specifications

7.1 Absolute Maximum Ratings MIN MAX UNIT

Supply Voltage – VDD11 −0.3 1.7 V

Supply Voltage – VDD18 -0.3 2.5 V

Supply Voltage – VDDIO −0.3 2.5 V

OpenLDI Inputs -0.3 2.75 V

LVCMOS I/O Voltage −0.3 (VDDIO + 0.3) V

1.8V Tolerant I/O -0.3 2.5 V

3.3V Tolerant I/O -0.3 4.0 V

5V Tolerant I/O -0.3 5.3 V

FPD-Link III Output Voltage −0.3 1.7 V

Junction Temperature 150 °C

For soldering specifications:

see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf

7.2 Handling Ratings MIN MAX UNIT

Tstg Storage temperature range 64 Lead VQFN Package -65 +150 °C

Human body model (HBM), per AEC Q100-002(1) -2 +2 kV

V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 -750 +750 V

Air Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -15 +15

ESD Rating (IEC 61000-4-2) kV

RD= 330Ω, CS= 150pF Contact Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -8 +8

ESD Rating (ISO10605) Air Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -15 +15

RD= 330Ω, CS= 150pF kV

Contact Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -8 +8

RD= 2KΩ, CS= 150pF or 330pF

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions MIN NOM MAX UNIT

Supply Voltage (VDD11) 1.045 1.1 1.155 V

Supply Voltage (VDD18) 1.71 1.8 1.89 V

LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V

VDDI2C, 1.8V Operation 1.71 1.8 1.89 V

VDDI2C, 3.3V Operation 3.135 3.3 3.465 V

HDMI Termination (VTERM), DC-coupled 3.135 3.3 3.465 V

HDMI Termination (VTERM), AC-coupled 1.71 1.8 1.89 V

Operating Free Air Temperature (TA)−40 +25 +105 °C

TMDS Frequency 25 170 MHz

Supply Noise(1) (DC-50MHz) 25 mVP-P

(1) Supply noise testing was done without any capacitors or ferrite beads connected. A sinusoidal signal is AC coupled to the VDD11 supply

of the serializer until the deserializer loses lock.

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7.4 Thermal Information VQFN

THERMAL METRIC(1) UNIT

64 PINS

RθJA Junction-to-ambient thermal resistance 25.8

RθJC(top) Junction-to-case (top) thermal resistance 11.4

RθJB Junction-to-board thermal resistance 5.1 °C/W

ψJT Junction-to-top characterization parameter 0.2

ψJB Junction-to-board characterization parameter 5.1

RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

1.8V LVCMOS I/O

High Level Input SCLK/I2CSEL,

VIH 0.65 * VDDIO V

Voltage PDB,

D_GPIO0/MOSI,

Low Level Input

VIL 0 0.35 * VDDIO V

D_GPIO1/MISO,

Voltage D_GPIO2/SPLK,

D_GPIO3/SS,

SDIN/GPIO0,

SWC/GPIO1,

MCLK

I2S_DC/GPIO2,

I2S_DD/GPIO3,

I2S_DB/GPIO5_RE

IIN Input Current VIN = 0V or 1.89V −10 10 μA

I2S_DA/GPIO6_RE

I2S_CLK/GPIO8_R

EG,

I2S_WC/GPIO7_R

High Level Output

VOH IOH =−4mA 0.7 * VDDIO VDDIO V

Voltage

Low Level Output

VOL IOL = +4mA GND 0.26 * VDDIO V

Voltage Same as above

Output Short Circuit

IOS VOUT = 0V -50 mA

Current

TRI-STATE™ Output

IOZ VOUT = 0V or VDDIO, PDB = L −10 10 μA

Current

TMDS INPUTS -- FROM HDMI v1.4b SECTION 4.2.5

Input Common-Mode IN_D[2:0]+,

VICM1 VTERM - 400 VTERM - 37.5 mV

Voltage IN_D[2:0]-

Input Common-Mode IN_CLK+, IN_CLK-

VICM2 IN_CLK ≤170MHz VTERM - 10 VTERM + 10 mV

Voltage VTERM = 1.8V (+,-

5%) or VTERM =

Input Differential

VIDIFF 150 1200 mVP-P

3.3V (+,- 5%)

Voltage Level IN_D[2:0]+,

Termination

RTMDS Differential IN_D[2:0]- 90 100 110 Ω

Resistance IN_CLK+, IN_CLK-

HDMI IO -- FROM HDMI v1.4b SECTION 4.2.7 to 4.2.9

4.8 5.3 V

VRX_5V +5V Power Signal RX_5V 50 mA

I5V_Sink +5V Input Current

High Level Output

VOH,HPD IOH = -4mA 2.4 5.3 V

Voltage, HPD HPD, RPU = 1 kΩ

Low Level Output

VOL,HPD IOL = +4mA GND 0.4 V

Voltage, HPD

Power-Down Input

IIZ,HPD PDB = L -10 10 uA

Current, HPD

Low Level Input

VIL,DDC 0.3*VDD,DDC V

Voltage, DDC

High Level Input DDC_SCL,

VIH,DDC 0.7*VDD,DDC V

Voltage, DDC DDC_SDA

Power-Down Input

IIZ,DDC PDB = L -10 10 µA

Current, DDC

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DC Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

High Level Input

VIH,CEC 2 V

Voltage, CEC

Low Level Input

VIL,CEC 0.8 V

Voltage, CEC

Input Hysteresis,

VHY,CEC 0.4 V

CEC CEC

Low Level Output

VOL,CEC GND 0.6 V

Voltage, CEC

High Level Output

VOH,CEC 2.5 3.63 V

Voltage, CEC

IOFF_CE Power-Down Input PDB = L -1.8 1.8 µA

CCurrent, CEC

FPD-LINK III DIFFERENTIAL DRIVER

Output Differential

VODp-p 900 1200 mVp-p

Voltage

Output Voltage

ΔVOD 1 50 mV

Unbalance

Output Differential

VOS 550 mV

Offset Voltage DOUT[1:0]+,

DOUT[1:0]-

Offset Voltage

ΔVOS 1 50 mV

Unbalance

Output Short Circuit

IOS FPD-Link III Outputs = 0V -50 mA

Current

Termination

RTSingle-ended 40 50 60 Ω

Resistance

SUPPLY CURRENT (1)

IDD11 330 mA

Supply Current, Colorbar Pattern

Normal Operation

IDD18 50 mA

IDD,VTER VTERM Current, Colorbar Pattern 60 mA

MNormal Operation

IDDZ11 15 mA

Supply Current, PDB = L

Power Down Mode

IDDZ18 5 mA

IDDZ,VTE VTERM Current, Colorbar Pattern 5 mA

RM Power Down Mode

(1) Specification is ensured by bench characterization.

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7.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

GPIO FREQUENCY(1)

Rb,FC Forward Channel GPIO Single-Lane, IN_CLK = 25MHz GPIO[3:0], 0.25 *

Frequency - 96MHz D_GPIO[3:0] IN_CLK MHz

Dual-Lane, IN_CLK/2 = 25MHz 0.125 *

- 85MHz IN_CLK

tGPIO,FC GPIO Pulse Width, Single-Lane, IN_CLK = 25MHz GPIO[3:0], >2 / IN_CLK

Forward Channel - 96MHz D_GPIO[3:0] s

Dual-Lane, IN_CLK/2 = 25MHz >2 /

- 85MHz (IN_CLK/2)

TMDS INPUT

Skew-Intra Maximum Intra-Pair IN_CLK±, 0.4 UITMDS(2)

Skew IN_D[2:0]±

Skew-Inter Maximum Inter-Pair 0.2*Tchar(3) ns

Skew + 1.78ns

ITJIT Input Total Jitter IN_CLK± 0.3 UITMDS(2)

Tolerance

FPD-LINK III OUTPUT

tLHT Low Voltage Differential

Low-to-High Transition 80 ps

Time

tHLT Low Voltage Differential

High-to-Low Transition 80 ps

Time

tXZD Output Active to OFF PDB = L 100 ns

Delay

tPLD Lock Time (HDMI Rx) 5 ms

tSD Delay — Latency IN_CLK± 145*T(2) s

Random Pattern Single-Lane:

High pass

filter

IN_CLK/20

Output Total

tDJIT 0.3 UIFPD3(4)

Jitter(Figure 5 )Dual-lane:

High pass

filter

IN_CLK/40

Jitter Transfer Function

λSTXBW 960 kHz

(-3dB Bandwidth)

Jitter Transfer Function

δSTX 0.1 dB

Peaking

(1) Back channel rates are available on the companion deserializer datasheet.

(2) One bit period of the TMDS input.

(3) Ten bit periods of the TMDS input.

(4) One bit period of the serializer output.

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7.7 DC And AC Serial Control Bus Characteristics

Over VDDI2C supply and temperature ranges unless otherwise specified. VDDI2C can be 1.8V (+,- 5%) or 3.3V (+,- 5%) (refer to

I2CSEL pin description for 1.8V or 3.3V operation).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH,I2C 0.7*

SDA and SCL, VDDI2C = 1.8V V

VDDI2C

Input High Level, I2C 0.7*

SDA and SCL, VDDI2C = 3.3V V

VDDI2C

VIL,I2C 0.3*

SDA and SCL, VDDI2C = 1.8V V

VDDI2C

Input Low Level Voltage, I2C 0.3*

SDA and SCL, VDDI2C = 3.3V V

VDDI2C

VHY Input Hysteresis, I2C SDA and SCL, VDDI2C = 1.8V or 3.3V >50 mV

VOL,I2C Output Low Level, I2C SDA and SCL, VDDI2C = 1.8V, Fast-Mode, 3mA Sink 0.2 *

GND V

Current VDDI2C

SDA and SCL, VDDI2C = 3.3V, 3mA Sink Current GND 0.4 V

IIN,I2C Input Current, I2C SDA and SCL, VDDI2C = 0V -800 -600 µA

SDA and SCL, VDDI2C = VDD18 or VDD33 -10 +10 µA

CIN,I2C Input Capacitance, I2C SDA and SCL 5 pF

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7.8 Recommended Timing for the Serial Control Bus

Over I2C supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fSCL SCL Clock Frequency Standard-Mode >0 100 kHz

Fast-Mode >0 400 kHz

Fast-Mode Plus >0 1 MHz

tLOW SCL Low Period Standard-Mode 4.7 µs

Fast-Mode 1.3 µs

Fast-Mode Plus 0.5 µs

tHIGH SCL High Period Standard-Mode 4.0 µs

Fast-Mode 0.6 µs

Fast-Mode Plus 0.26 µs

tHD;STA Hold time for a start or a Standard-Mode 4.0 µs

repeated start condition Fast-Mode 0.6 µs

Fast-Mode Plus 0.26 µs

tSU;STA Set Up time for a start or a Standard-Mode 4.7 µs

repeated start condition Fast-Mode 0.6 µs

Fast-Mode Plus 0.26 µs

tHD;DAT Data Hold Time Standard-Mode 0 µs

Fast-Mode 0 µs

Fast-Mode Plus 0 µs

tSU;DAT Data Set Up Time Standard-Mode 250 ns

Fast-Mode 100 ns

Fast-Mode Plus 50 ns

tSU;STO Set Up Time for STOP Standard-Mode 4.0 µs

Condition Fast-Mode 0.6 µs

Fast-Mode Plus 0.26 µs

tBUF Bus Free Time Standard-Mode 4.7 µs

Between STOP and START Fast-Mode 1.3 µs

Fast-Mode Plus 0.5 µs

trSCL & SDA Rise Time, Standard-Mode 1000 ns

Fast-Mode 300 ns

Fast-Mode Plus 120 ns

tfSCL & SDA Fall Time, Standard-Mode 300 ns

Fast-Mode 300 ns

Fast-Mode Plus 120 ns

tSP Input Filter Fast-Mode 50 ns

Fast-Mode Plus 50 ns

Product Folder Links: DS90UB949-Q1

RX_5V

IN_CLK

(Diff.)

DOUT

(Diff.) Driver OFF, VOD = 0V Driver On

VDD

VDDIO

tPLD

PDB

tHLT

tLHT

(DOUT+) - (DOUT-) 20%

80%

VOD

DOUT+

VOD/2

VOD

Single Ended

Differential

VOS

DOUT-

(DOUT+) - (DOUT-)

PARALLEL-TO-SERIAL

IN_CLK±

IN_D[2:0]±100:

DOUT-

DOUT+

100 nF

SCOPE

BW û 4GHz

Differential probe

Input Impedance û 100 k:

CL ú 0.5 pf

BW û 3.5 GHz

VOD/2

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

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Figure 1. Serializer VOD Output

Figure 2. Output Transition Times

Figure 3. Serializer Lock Time

Product Folder Links: DS90UB949-Q1

I2S_WC

I2S_D[A,B,C,D]

I2S_CLK VIH

VIL

tHC

tLC

tsr thr

SCL

SDA

tHD;STA

tLOW tr

tHD;DAT tHIGH

tSU;DAT

tSU;STA tSU;STO

START REPEATED

START STOP

tHD;STA

START

tSP

trBUF

DOUT

(Diff.)

tDJIT

tBIT (1 UI)

EYE OPENING 0V

tDJIT

210

START

BIT STOP

BIT

SYMBOL N

210

START

BIT STOP

BIT

SYMBOL N-1

210

START

BIT STOP

BIT

SYMBOL N-2

210

START

BIT STOP

BIT

SYMBOL N-3

210

STOP

BIT

SYMBOL N-4

DOUT

IN_CLK

tSD

NN-1 N+1 N+2

| |

IN_D[2:0]

DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

Figure 4. Latency Delay

Figure 5. Serializer Output Jitter

Figure 6. Serial Control Bus Timing Diagram

Figure 7. I2S Timing Diagram

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7.9 Typical Characteristics

Figure 8. Serializer Output at 2.975Gbps (85MHz TMDS Figure 9. Serializer Output at 3.36Gbps (96MHz TMDS

Clock) Clock)

Product Folder Links: DS90UB949-Q1

FPD-Link III Digital

HDMI Controller

Digital

HDMI RX

PHY

FPD-Link

III TX

Digital

FPD3 TX

Analog

Bridge Control

Digital

TMDS

DDC

HPA

FPD-Link III

Audio

PLL Audio

FIFO

Packet

FIFO

EDID/

Config

NVM

EDID

I/F

I2S Audio

Video

RX_5V

I2C Optional

Secondary

I2S

Digital

TMDS

Interface

FPD3 TX

Analog FPD-Link III

FPD-Link

III TX

Digital

PAT

GEN

DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

8 Detailed Description

8.1 Overview

The DS90UB949-Q1 converts an HDMI interface (3 TMDS data channels + 1 TMDS Clock) to an FPD-Link III

interface. This device transmits a 35-bit symbol over a single serial pair operating up to 3.36Gbps line rate, or

two serial pairs operating up to 2.975Gbps line rate. The serial stream contains an embedded clock, video

control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality and

support AC coupling.

The DS90UB949-Q1 serializer is intended for use with a DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB940-Q1,

DS90UB948-Q1 deserializer.

The DS90UB949-Q1 serializer and companion deserializer incorporate an I2C compatible interface. The I2C

compatible interface allows programming of serializer or deserializer devices from a local host controller. In

addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between

serializer/deserializer as well as remote I2C slave devices.

The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial

link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at

either side of the serial link.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 High-Definition Multimedia Interface (HDMI)

HDMI is a leading interface standard used to transmit digital video and audio from sources (such as a DVD

player) to sinks (such as an LCD display). The interface is capable of transmitting high-definition video and audio.

Other HDMI signals consist of various control and status data that travel bidirectionally.

8.3.1.1 HDMI Receive Controller

The HDMI Receiver is an HDMI version 1.4b compliant receiver. The HDMI receiver is capable of operation at

greater than 1080p resolutions. The configuration used in the DS90UB949-Q1does not include version 1.4b

features such as the ethernet channel (HEC) or Audio Return Channel (ARC).

8.3.2 Transition Minimized Differential Signaling

HDMI uses Transition Minimized Differential Signaling (TMDS) over four differential pairs (3 TMDS channels and

1 TMDS clock) to transmit video and audio data. TMDS is widely used to transmit high-speed serial data. The

technology incorporates a form of 8b/10b encoding and its differential signaling allows it to reduce

electromagnetic interference (EMI) and achieve high skew tolerance.

8.3.3 Enhanced Display Data Channel

The Display Data Channel or DDC is a collection of digital communication protocols between a computer display

and a graphics adapter that enables the display to communicate its supported display modes to the adapter and

allow the computer host to adjust monitor parameters, such as brightness and contrast.

8.3.4 Extended Display Identification Data (EDID)

EDID is a data structure provided by a digital display to describe its capabilities to a video source. By providing

this information, the video source can then send video data with proper timing and resolution that the display

supports. The DS90UB949-Q1 supports several options for delivering display identification (EDID) information to

the HDMI graphics source. The EDID information is accessible via the DDC interface and comply with the DDC

and EDID requirements given in the HDMI v1.4b specification.

The EDID configurations supported are as follows:

• External local EDID (EEPROM)

• Internal EDID loaded into device memory

• Remote EDID connected to I2C bus at deserializer side

• Internal pre-programmed EDID

The EDID mode selected should be configurable from the MODE_SEL pins, or from internal control registers. For

all modes, the EDID information should be accessible at the default address of 0xA0.

8.3.4.1 External Local EDID (EEPROM)

The DS90UB949-Q1 can be configured to allow a local EEPROM EDID device. The local EDID device may

implement any EDID configuration allowable by the HDMI v1.4b and DVI 1.0 standards, including multiple

extension blocks up to 32KB.

8.3.4.2 Internal EDID (SRAM)

The DS90UB949-Q1 also allows internal loading of an EDID profile up to 256 bytes. This SRAM storage is

volatile and requires loading from an external I2C master (local or remote). The internal EDID is reloadable and

readable (local/remote) from control registers during normal operation.

8.3.4.3 External Remote EDID

The serializer copies the remote EDID connected to the I2C bus of the remote deserializer into its internal

SRAM. The remote EDID device can be a standalone I2C EEPROM, or integrated into the digital display panel.

In this mode, the serializer automatically accesses the Bidirectional Control Channel to search for the EDID

information at the default address 0xA0. Once found, the serializer copies the remote EDID into local SRAM.

Product Folder Links: DS90UB949-Q1

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Feature Description (continued)

8.3.4.4 Internal Pre-Programmed EDID

The serializer also has an internal eFuse that is loaded into the internal SRAM with pre-programmed 256-byte

EDID data at startup. This EDID profile supports several generic video (480p, 720p) and audio (2-channel audio)

timing profiles within the single-link operating range of the device (25MHz-96MHz pixel clock). In this mode, the

internal EDID SRAM data is readable from the DDC interface. The EDID contents are below:

0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x53 0x0E 0x49 0x09 0x01 0x00 0x00 0x00

0x1C 0x18 0x01 0x03 0x80 0x34 0x20 0x78 0x0A 0xEC 0x18 0xA3 0x54 0x46 0x98 0x25

0x0F 0x48 0x4C 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01

0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x1D 0x00 0x72 0x51 0xD0 0x1E 0x20 0x6E 0x50

0x55 0x00 0x00 0x20 0x21 0x00 0x00 0x18 0x00 0x00 0x00 0xFD 0x00 0x3B 0x3D 0x62

0x64 0x08 0x00 0x0A 0x20 0x20 0x20 0x20 0x20 0x20 0x00 0x00 0x00 0xFC 0x00 0x54

0x49 0x2D 0x44 0x53 0x39 0x30 0x55 0x78 0x39 0x34 0x39 0x0A 0x00 0x00 0x00 0x10

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x57

0x02 0x03 0x15 0x40 0x41 0x84 0x23 0x09 0x7F 0x05 0x83 0x01 0x00 0x00 0x66 0x03

0x0C 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x28

8.3.5 Consumer Electronics Control (CEC)

Consumer Electronics Control (CEC) is designed to allow the system user to command and control up-to ten

CEC-enabled devices connected through HDMI, using only one of their remote controls (for example by

controlling a television set, set-top box, and DVD player using only the remote control of the TV). CEC also

allows for individual CEC-enabled devices to command and control each other without user intervention. CEC is

a one-wire open drain bus with an external 27kohm (+/-10%) resistor pull-up to 3.3V.

CEC protocol can be implemented using an external clock reference or the 25MHz internal oscillator inside the

DS90UB949-Q1.

8.3.6 +5V Power Signal

+5V is asserted by the HDMI source through the HDMI interface. The +5V signal propagates through the

connector and cable until it reaches the sink. The +5V supply is used for various HDMI functions, such as HPD

and DDC signals.

8.3.7 Hot Plug Detect (HPD)

The HPD pin is asserted by the sink to let the source know that it is ready to receive the HDMI signal. The

source initiates the connection by first providing the +5V power signal through the HDMI interface. The sink holds

HPD low until it is ready to receive signals from the source, at which point it will release HPD to be pulled up to

+5V.

8.3.8 High Speed Forward Channel Data Transfer

The High Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, I2C,

GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 10 illustrates the serial stream per clock

cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,

balanced and scrambled.

Figure 10. FPD-Link III Serial Stream

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Feature Description (continued)

The device supports TMDS clocks in the range of 25 MHz to 96 MHz over one lane, or 50MHz to 170MHz over

two lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) , or 2.975 Gbps

maximum per lane (875 Mbps minimum) when transmitting over both lanes.

8.3.9 Back Channel Data Transfer

The Backward Channel provides bidirectional communication between the display and host processor. The

information is carried from the deserializer to the serializer as serial frames. The back channel control data is

transferred over both serial links along with the high-speed forward data, DC balance coding and embedded

clock information. This architecture provides a backward path across the serial link together with a high speed

forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information with 5, 10, or

20 Mbps line rate (configured by the compatible deserializer).

8.3.10 FPD-Link III Port Register Access

Since the DS90UB949-Q1 contains two downstream ports, some registers need to be duplicated to allow control

and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two sets of

registers. Registers that are shared between ports (not duplicated) will be available independent of the settings in

the TX_PORT_SEL register.

Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both

bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing

simultaneous writes to both ports if both select bits are set.

Setting the PORT1_I2C_EN bit will enable a second I2C slave address, allowing access to the second port

registers through the second I2C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be

ignored.

8.3.11 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an

external device, or through VDDIO, where VDDIO = 1.71V to 1.89V. To save power, disable the link when the

display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before all power supplies have

reached final levels. When PDB is driven low, ensure that the pin is driven to 0V for at least 3ms before releasing

or driving high. In the case where PDB is pulled up to VDDIO directly, a 10kΩpull-up resistor and a >10µF

capacitor to ground are required (See Power Up Requirements And PDB Pin).

Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,

PDB must be held low for a minimum of 3ms before going high again.

8.3.12 Serial Link Fault Detect

The DS90UB949-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the

Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 10). The DS90UB949-Q1 will

detect any of the following conditions:

1. Cable open

2. “+” to “-” short

3. ”+” to GND short

4. ”-” to GND short

5. ”+” to battery short

6. ”-” to battery short

7. Cable is linked incorrectly (DOUT+/DOUT- connections reversed)

Note: The device will detect any of the above conditions, but does not report specifically which one has occurred.

Product Folder Links: DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

Feature Description (continued)

8.3.13 Interrupt Pin (INTB)

The INTB pin is an active low interrupt output pin that acts as an interrupt for various local and remote interrupt

conditions (see registers 0xC6 and 0xC7 of Register Maps). For the remote interrupt condition, the INTB pin

works in conjunction with the INTB_IN pin on the deserializer. This interrupt signal, when configured, will

propagate from the deserializer to the serializer.

1. On the Serializer, set register 0xC6[5] = 1 and 0xC6[0] = 1

2. Deserializer INTB_IN pin is set LOW by some downstream device.

3. Serializer pulls INTB pin LOW. The signal is active LOW, so a LOW indicates an interrupt condition.

4. External controller detects INTB = LOW; to determine interrupt source, read ISR register.

5. A read to ISR will clear the interrupt at the Serializer, releasing INTB.

6. The external controller typically must then access the remote device to determine downstream interrupt

source and clear the interrupt driving the Deserializer INTB_IN. This would be when the downstream device

releases the INTB_IN pin on the Deserializer. The system is now ready to return to step (2) at next falling

edge of INTB_IN.

8.3.14 Remote Interrupt Pin (REM_INTB)

REM_INTB will mirror the status of INTB_IN pin on the deserializer and does not need to be cleared. If the

serializer is not linked to the deserializer, REM_INTB will be high.

8.3.15 General-purpose I/O

8.3.15.1 GPIO[3:0] and D_GPIO[3:0] Configuration

In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back

channel (inputs) mode. GPIO and D_GPIO modes may be configured from the registers. The same registers

configure either GPIO or D_GPIO, depending on the status of PORT1_SEL and PORT0_SEL bits (0x1E[1:0]).

D_GPIO operation requires 2-lane FPD-Link III mode. See Table 1 for GPIO enable and configuration.

Table 1. GPIO Enable and Configuration

Description Device Forward Channel Back Channel

GPIO3 / D_GPIO3 Serializer 0x0F[3:0] = 0x3 0x0F[3:0] = 0x5

Deserializer 0x1F[3:0] = 0x5 0x1F[3:0] = 0x3

GPIO2 / D_GPIO2 Serializer 0x0E[7:4] = 0x3 0x0E[7:4] = 0x5

Deserializer 0x1E[7:4] = 0x5 0x1E[7:4] = 0x3

GPIO1 / D_GPIO1 Serializer 0x0E[3:0] = 0x3 0x0E[3:0] = 0x5

Deserializer 0x1E[3:0] = 0x5 0x1E[3:0] = 0x3

GPIO0 / D_GPIO0 Serializer 0x0D[3:0] = 0x3 0x0D[3:0] = 0x5

Deserializer 0x1D[3:0] = 0x5 0x1D[3:0] = 0x3

8.3.15.2 Back Channel Configuration

The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as

back channel frequency. These different modes are controlled by a compatible deserializer. Consult the

appropriate deserializer datasheet for details on how to configure the back channel frequency. See Table 2 for

details about D_GPIOs in various modes.

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Table 2. Back Channel D_GPIO Effective Frequency

D_GPIO Effective Frequency(1) (kHz)

HSCC_MODE Number of Samples per D_GPIOs

Mode

(on DES) D_GPIOs Frame Allowed

5 Mbps BC(2) 10 Mbps BC(3) 20 Mbps BC(4)

000 Normal 4 1 33 66 133 D_GPIO[3:0]

011 Fast 4 6 200 400 800 D_GPIO[3:0]

010 Fast 2 10 333 666 1333 D_GPIO[1:0]

001 Fast 1 15 500 1000 2000 D_GPIO0

(1) The effective frequency assumes the worst case back channel frequency (-20%) and a 4X sampling rate.

(2) 5 Mbps corresponds to BC FREQ SELECT = 0 & BC_HS_CTL = 0 on deserializer.

(3) 10 Mbps corresponds to BC FREQ SELECT = 1 & BC_HS_CTL = 0 on deserializer.

(4) 20 Mbps corresponds to BC FREQ SELECT = X & BC_HS_CTL = 1 on deserializer.

8.3.15.3 GPIO_REG[8:5] Configuration

GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local

GPIO_REG mode. See Table 3 for GPIO enable and configuration.

Note: Local GPIO value may be configured and read either through local register access, or remote register

access through the Bidirectional Control Channel. Configuration and state of these pins are not transported from

serializer to deserializer as is the case for GPIO[3:0].

Table 3. GPIO_REG and GPIO Local Enable and Configuration

Description Register Configuration Function

GPIO_REG8 0x11[7:4] = 0x01 Output, L

0x11[7:4] = 0x09 Output, H

0x11[7:4] = 0x03 Input, Read: 0x1D[0]

GPIO_REG7 0x11[3:0] = 0x1 Output, L

0x11[3:0] = 0x9 Output, H

0x11[3:0] = 0x3 Input, Read: 0x1C[7]

GPIO_REG6 0x10[7:4] = 0x1 Output, L

0x10[7:4] = 0x9 Output, H

0x10[7:4] = 0x3 Input, Read: 0x1C[6]

GPIO_REG5 0x10[3:0] = 0x1 Output, L

0x10[3:0] = 0x9 Output, H

0x10[3:0] = 0x3 Input, Read: 0x1C[5]

GPIO3 0x0F[3:0] = 0x1 Output, L

0x0F[3:0] = 0x9 Output, H

0x0F[3:0] = 0x3 Input, Read: 0x1C[3]

GPIO2 0x0E[7:4] = 0x1 Output, L

0x0E[7:4] = 0x9 Output, H

0x0E[7:4] = 0x3 Input, Read: 0x1C[2]

GPIO1 0x0E[3:0] = 0x1 Output, L

0x0E[3:0] = 0x9 Output, H

0x0E[3:0] = 0x3 Input, Read: 0x1C[1]

GPIO0 0x0D[3:0] = 0x1 Output, L

0x0D[3:0] = 0x9 Output, H

0x0D[3:0] = 0x3 Input, Read: 0x1C[0]

Product Folder Links: DS90UB949-Q1

D0 D1 D2 D3 DN

SPLK

MOSI

SPLK

MOSI

SERIALIZER

DESERIALIZER

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SNLS452 –NOVEMBER 2014

8.3.16 SPI Communication

The SPI Control Channel utilizes the secondary link in a 2-lane FPD-Link III implementation. Two possible

modes are available, Forward Channel and Reverse Channel modes. In Forward Channel mode, the SPI Master

is located at the Serializer, such that the direction of sending SPI data is in the same direction as the video data.

In Reverse Channel mode, the SPI Master is located at the Deserializer, such that the direction of sending SPI

data is in the opposite direction as the video data.

The SPI Control Channel can operate in a high speed mode when writing data, but must operate at lower

frequencies when reading data. During SPI reads, data is clocked from the slave to the master on the SPI clock

falling edge. Thus, the SPI read must operate with a clock period that is greater than the round trip data latency.

On the other hand, for SPI writes, data can be sent at much higher frequencies where the MISO pin can be

ignored by the master.

SPI data rates are not symmetrical for the two modes of operation. Data over the forward channel can be sent

much faster than data over the reverse channel.

Note: SPI cannot be used to access Serializer / Deserializer registers.

8.3.16.1 SPI Mode Configuration

SPI is configured over I2C using the High-Speed Control Channel Configuration (HSCC_CONTROL) register

0x43 on the deserializer. HSCC_MODE (0x43[2:0]) must be configured for either High-Speed, Forward Channel

SPI mode (110) or High-Speed, Reverse Channel SPI mode (111).

8.3.16.2 Forward Channel SPI Operation

In Forward Channel SPI operation, the SPI master located at the Serializer generates the SPI Clock (SPLK),

Master Out / Slave In data (MOSI), and active low Slave Select (SS). The Serializer oversamples the SPI

signals directly using the video pixel clock. The three sampled values for SPLK, MOSI, and SS are each sent on

data bits in the forward channel frame. At the Deserializer, the SPI signals are regenerated using the pixel

clock. In order to preserve setup and hold time, the Deserializer will hold MOSI data while the SPLK signal is

high. In addition, it delays SPLK by one pixel clock relative to the MOSI data, increasing setup by one pixel

clock.

Figure 11. Forward Channel SPI Write

Product Folder Links: DS90UB949-Q1

SPLK

MOSI

SPLK

MOSI

SERIALIZER

DESERIALIZER

RD0MISO

MISO RD0

RD1

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Figure 12. Forward Channel SPI Read

8.3.16.3 Reverse Channel SPI Operation

In Reverse Channel SPI operation, the Deserializer samples the Slave Select (SS), SPI clock (SCLK) into the

internal oscillator clock domain. In addition, upon detection of the active SPI clock edge, the Deserializer

samples the SPI data (MOSI). The SPI data samples are stored in a buffer to be passed to the Serializer over

the back channel. The Deserializer sends SPI information in a back channel frame to the Serializer. In each

back channel frame, the Deserializer sends an indication of the Slave Select value. The Slave Select should be

inactive (high) for at least one back-channel frame period to ensure propagation to the Serializer.

Because data is delivered in separate back channel frames and buffered, the data may be regenerated in

bursts. The following figure shows an example of the SPI data regeneration when the data arrives in three back

channel frames. The first frame delivered the SS active indication, the second frame delivered the first three

data bits, and the third frame delivers the additional data bits.

Product Folder Links: DS90UB949-Q1

SPLK

MOSI

SPLK

MOSI

DESERIALIZER

SERIALIZER

RD0MISO

MISO RD0

RD1

D0 D1 D2 D3 DN

SPLK

MOSI

SPLK

MOSI

DESERIALIZER

SERIALIZER

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Figure 13. Reverse Channel SPI Write

For Reverse Channel SPI reads, the SPI master must wait for a round-trip response before generating the

sampling edge of the SPI clock. This is similar to operation in Forward channel mode. Note that at most one

data/clock sample will be sent per back channel frame.

Figure 14. Reverse Channel SPI Read

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I2S_CLK

I2S_WC

I2S_Dx MSB LSB MSB LSB

Word Select

Serializer

Bit Clock I2S_CLK

I2S_WC

Data I2S_Dx

I2S

Transmitter

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For both Reverse Channel SPI writes and reads, the SPI_SS signal should be deasserted for at least one back

channel frame period.

Table 4. SPI SS Deassertion Requirement

Back Channel Frequency Deassertion Requirement

5 Mbps 7.5 µs

10 Mbps 3.75 µs

20 Mbps 1.875 µs

8.3.17 Backward Compatibility

This FPD-Link III serializer is backward compatible to the DS90UB926Q-Q1 and DS90UB928Q-Q1 for TMDS

clock frequencies ranging from 25MHz to 85MHz. Backward compatibility does not need to be enabled. When

paired with a backward compatible device, the serializer will auto-detect to 1-lane FPD-Link III on the primary

channel (DOUT0±).

8.3.18 Audio Modes

The DS90UB949-Q1 supports several audio modes and functions:

• HDMI Mode

• DVI Mode

• AUX Audio Channel

8.3.18.1 HDMI Audio

The DS90UB949-Q1 allows embedded audio in the HDMI interface to be transported over the FPD-Link III serial

link and output on the compatible deserializer. Depending on the number of channels, HDMI audio can be output

on several I2S pins on the deserializer, or it can be converted to TDM to output on one audio output pin on the

deserializer.

8.3.18.2 DVI I2S Audio Interface

The DS90UB949-Q1 serializer features six I2S input pins that, when paired with a compatible deserializer,

supports 7.1 High-Definition (HD) Surround Sound audio applications. The bit clock (I2S_CLK) supports

frequencies between 1MHz and the lesser of IN_CLK/2 or 13MHz. Four I2S data inputs transport two channels of

I2S-formatted digital audio each, with each channel delineated by the word select (I2S_WC) input. Refer to

Figure 15 and Figure 16 for I2S connection diagram and timing information.

Figure 15. I2S Connection Diagram

Figure 16. I2S Frame Timing Diagram

Table 5 covers several common I2S sample rates:

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SNLS452 –NOVEMBER 2014

Table 5. Audio Interface Frequencies

Sample Rate (kHz) I2S Data Word Size (bits) I2S CLK (MHz)

32 16 1.024

44.1 16 1.411

48 16 1.536

96 16 3.072

192 16 6.144

32 24 1.536

44.1 24 2.117

48 24 2.304

96 24 4.608

192 24 9.216

32 32 2.048

44.1 32 2.822

48 32 3.072

96 32 6.144

192 32 12.288

8.3.18.2.1 I2S Transport Modes

By default, audio is packetized and transmitted during video blanking periods in dedicated Data Island Transport

frames. Data Island frames may be disabled from control registers if Forward Channel Frame Transport of I2S

data is desired. In this mode, only I2S_DA is transmitted to a DS90UB928Q-Q1,DS90UB940-Q1, or

DS90UB948-Q1 deserializer. If connected to a DS90UB926Q-Q1 deserializer, I2S_DA and I2S_DB are

transmitted. Surround Sound Mode, which transmits all four I2S data inputs (I2S_D[A..D]), may only be operated

in Data Island Transport mode. This mode is only available when connected to a DS90UB928Q-Q1,DS90UB940-

Q1, or DS90UB948-Q1 deserializer.

8.3.18.2.2 I2S Repeater

I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via Data

Island Transport during the video blanking periods. If frame transport is desired, then the I2S pins should be

connected from the deserializer to all serializers. Activating surround sound at the top-level deserializer

automatically configures downstream serializers and deserializers for surround sound transport utilizing Data

Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be explicitly

set in each serializer and deserializer control register throughout the repeater tree (Table 10).

8.3.18.3 AUX Audio Channel

The AUX Audio Channel is a single separate I2S audio data channel that may be transported independently of

the main audio stream received in either HDMI Mode or DVI Mode. This channel is shared with the GPIO[1:0]

interface and is supported by DS90UB940-Q1and DS90UB948-Q1 deserializers.

8.3.18.4 TDM Audio Interface

In addition to the I2S audio interface, the DS90UB949-Q1 serializer also supports TDM format. Since a number

of specifications for TDM format are in common use, the DS90UB949-Q1 offers flexible support for word length,

bit clock, number of channels to be multiplexed, etc. For example, let’s assume that word clock signal (I2S_WC)

period = 256 * bit clock (I2S_CLK) time period. In this case, the DS90UB949-Q1 can multiplex 4 channels with

maximum word length of 64 bits each, or 8 channels with maximum word length of 32 bits each. Figure 17

illustrates the multiplexing of 8 channels with 24 bit word length, in a format similar to I2S.

Product Folder Links: DS90UB949-Q1

I2S_WC

I2S_CLK

I2S Mode

DIN1

(Single)

t1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)t

023 22 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22

Ch 2

t32 BCKstCh 3

t32 BCKstCh 4

t32 BCKstCh 5

t32 BCKstCh 6

t32 BCKstCh 7

t32 BCKstCh 8

t32 BCKst

Ch 1

t32 BCKst

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

www.ti.com

Figure 17. TDM Format

8.3.19 Built In Self Test (BIST)

An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and back

channel without external data connections. This is useful in the prototype stage, equipment production, in-system

test, and system diagnostics.

8.3.19.1 BIST Configuration And Status

The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may

select either an external TMDS clock or the internal Oscillator clock (OSC) frequency. In the absence of TMDS

clock, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST

configuration register.

When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back

Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test

pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received

containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel

frame.

The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a

half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS

output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low

on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width

applied to the deserializer BISTEN pin. LOCK is valid throughout the entire duration of BIST.

See Figure 18 for the BIST mode flow diagram.

Step 1: The Serializer is paired with another FPD-Link III Deserializer, BIST Mode is enabled via the BISTEN pin

or through register on the Deserializer. Right after BIST is enabled, part of the BIST sequence requires bit

0x04[5] be toggled locally on the Serializer (set 0x04[5]=1, then set 0x04[5]=0). The desired clock source is

selected through the deserializer BISTC pin, or through register on the Deserializer.

Step 2: An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to

the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock,

the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1

to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS

output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If

there one or more errors were detected, the PASS output will output constant LOW. The PASS output state is

held until a new BIST is run, the device is RESET, or the device is powered down. The BIST duration is user

controlled by the duration of the BISTEN signal.

Product Folder Links: DS90UB949-Q1

X XX

TxCLKOUT±

BISTEN

(DES)

PASS

DATA

(internal)

PASS

BIST Duration

Prior Result

BIST

Result

Held

PASS

FAIL

X = bit error(s)

TxOUT[3:0]±

DATA

(internal)

Case 1 - Pass Case 2 - Fail

Prior Result

Normal PRBS BIST Test Normal

DES Outputs

BIST

start

BIST

stop

BIST

Wait

Step 1: DES in BIST

Step 2: Wait, SER in BIST

Step 3: DES in Normal

Mode - check PASS

Step 4: DES/SER in Normal

Normal

DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

Step 4: The link returns to normal operation after the deserializer BISTEN pin is low. Figure 19 shows the

waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple

errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data

transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect

medium, or reducing signal condition enhancements (Rx Equalization).

Figure 18. BIST Mode Flow Diagram

8.3.19.2 Forward Channel And Back Channel Error Checking

While in BIST mode, the serializer stops sampling the FPD-Link input pins and switches over to an internal all

zeroes pattern. The internal all-zeroes pattern goes through scrambler, DC-balancing, etc. and is transmitted

over the serial link to the deserializer. The deserializer, on locking to the serial stream, compares the recovered

serial stream with all-zeroes and records any errors in status registers. Errors are also dynamically reported on

the PASS pin of the deserializer.

The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,

as indicated by link detect status (register bit 0x0C[0] - Table 10). CRC errors are recorded in an 8-bit register in

the deserializer. The register is cleared when the serializer enters BIST mode. As soon as the serializer enters

BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode

CRC error register is active in BIST mode only and keeps a record of the last BIST run until cleared or the

serializer enters BIST mode again.

Figure 19. BIST Waveforms, in Conjunction with Deserializer Signals

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8.3.20 Internal Pattern Generation

The DS90UB949-Q1 serializer provides an internal pattern generation feature. It allows basic testing and

debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual

verification of panel operation. As long as the device is not in power down mode, the test pattern will be

displayed even if no input is applied. If no clock is received, the test pattern can be configured to use a

programmed oscillator frequency. For detailed information, refer to Application Note AN-2198.

8.3.20.1 Pattern Options

The DS90UB949-Q1 serializer pattern generator is capable of generating 17 default patterns for use in basic

testing and debugging of panels. Each can be inverted using register bits (Table 10), shown below:

1. White/Black (default/inverted)

2. Black/White

3. Red/Cyan

4. Green/Magenta

5. Blue/Yellow

6. Horizontally Scaled Black to White/White to Black

7. Horizontally Scaled Black to Red/Cyan to White

8. Horizontally Scaled Black to Green/Magenta to White

9. Horizontally Scaled Black to Blue/Yellow to White

10. Vertically Scaled Black to White/White to Black

11. Vertically Scaled Black to Red/Cyan to White

12. Vertically Scaled Black to Green/Magenta to White

13. Vertically Scaled Black to Blue/Yellow to White

14. Custom Color (or its inversion) configured in PGRS

15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)

16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL

17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the auto-

scrolling feature

Additionally, the Pattern Generator incorporates one user-configurable full-screen 24-bit color, which is controlled

by the PGRS, PGGS, and PGBS registers. This is pattern #14. One of the pattern options is statically selected in

the PGCTL register when Auto-Scrolling is disabled. The PGTSC and PGTSO1-8 registers control the pattern

selection and order when Auto-Scrolling is enabled.

8.3.20.2 Color Modes

By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue

outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 10). In 18-bit

mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least

significant bits will be 0.

8.3.20.3 Video Timing Modes

The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern

Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not

present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel

clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator

uses custom video timing as configured in the control registers. The internal timing generation may also be

driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with

External Clock are enabled by the control registers (Table 10).

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8.3.20.4 External Timing

In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the

video control outputs after a two pixel clock delay. It extracts the active frame dimensions from the incoming

signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS

signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without

DE asserted.

8.3.20.5 Pattern Inversion

The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes

the output pattern to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and

the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.

8.3.20.6 Auto Scrolling

The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of

enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may

appear in any order in the sequence and may also appear more than once.

8.3.20.7 Additional Features

Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It

consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 10) and the Pattern Generator

Indirect Data (PGID reg_0x67 — Table 10). See Application Note AN-2198.

8.3.21 Spread Spectrum Clock Tolerance

The DS90UB949-Q1 (for DVI mode) tolerates a spread spectrum input clock to help reduce EMI. The following

triangular SSC profile is supported:

• Frequency deviation ≤2.5%

• Modulation rate ≤100kHz

Note: Maximum frequency deviation and maximum modulation rate are not supported simultaneously. Some

typical examples:

• Frequency deviation: 2.5%, modulation rate: 50kHz

• Frequency deviation: 1.25%, modulation rate: 100kHz

8.4 Device Functional Modes

8.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])

Configuration of the device may be done via the MODE_SEL[1:0] input pins, or via the configuration register bits.

A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the

MODE_SEL[1:0] inputs. See Table 7 and Table 8. These values will be latched into register location during

power-up:

Table 6. MODE_SEL[1:0] Settings

Mode Setting Function

Look for remote EDID, if none found, use internal SRAM EDID. Can be overridden

0from register. Remote EDID address may be overridden from default 0xA0.

EDID_SEL: Display ID Select 1 Use external local EDID.

0 Disable.

AUTO-SS: Auto Sleep-State 1 Enable.

0 HDMI audio.

AUX_I2S: AUX Audio Channel 1 HDMI + AUX audio channel.

0 Internal HDMI control.

EXT_CTL: External Controller

Override 1 External HDMI control from I2C interface pins.

Product Folder Links: DS90UB949-Q1

Serializer

MODE_SEL0

1.8V

VR4

1.8V

VR6

MODE_SEL1

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Device Functional Modes (continued)

Table 6. MODE_SEL[1:0] Settings (continued)

Mode Setting Function

0 Enable FPD-Link III for twisted pair cabling.

COAX: Cable Type 1 Enable FPD-Link III for coaxial cabling.

0 Use internal SRAM EDID.

REM_EDID_LOAD: Remote

EDID Load 1 If available, remote EDID is copied into internal SRAM EDID.

Figure 20. MODE_SEL[1:0] Connection Diagram

Table 7. Configuration Select (MODE_SEL0)

# Ratio Target VR4 Suggested Suggested EDID_SEL AUTO_SS AUX_I2S

VR4/VDD18 (V) Resistor Pull-Up Resistor Pull-

R3 kΩ(1% tol) Down R4 kΩ(1%

tol)

1 0 0 OPEN 40.2 0 0 0

2 0.208 0.374 118 30.9 0 0 1

3 0.323 0.582 107 51.1 0 1 0

4 0.440 0.792 113 88.7 0 1 1

5 0.553 0.995 82.5 102 1 0 0

6 0.668 1.202 68.1 137 1 0 1

7 0.789 1.420 56.2 210 1 1 0

8 1 1.8 13.3 OPEN 1 1 1

Table 8. Configuration Select (MODE_SEL1)

# Ratio Target VR6 Suggested Suggested EXT_CTL COAX REM_EDID_LOA

VR6/VDD18 (V) Resistor Pull-Up Resistor Pull- D

R5 kΩ(1% tol) Down R6 kΩ(1%

tol)

1 0 0 OPEN 40.2 0 0 0

2 0.208 0.374 118 30.9 0 0 1

3 0.323 0.582 107 51.1 0 1 0

4 0.440 0.792 113 88.7 0 1 1

5 0.553 0.995 82.5 102 1 0 0

6 0.668 1.202 68.1 137 1 0 1

7 0.789 1.420 56.2 210 1 1 0

8 1 1.8 13.3 OPEN 1 1 1

The strapped values can be viewed and/or modified in the following locations:

• EDID_SEL : Latched into BRIDGE_CTL[0], EDID_DISABLE (0x4F[0]).

• AUTO_SS : Latched into SOFT_SLEEP (0x01[7]).

• AUX_I2S : Latched into BRIDGE_CFG[1], AUDIO_MODE[1] (0x54[1]).

• EXT_CTL: Latched into BRIDGE_CFG[7], EXT_CONTROL (0x54[7]).

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• COAX : Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]).

• REM_EDID_LOAD : Latched into BRIDGE_CFG[5] (0x54[5]).

8.4.2 FPD-Link III Modes of Operation

The FPD-Link III transmit logic supports several modes of operation, dependent on the downstream receiver as

well as the video being delivered. The following modes are supported:

8.4.2.1 Single Link Operation

Single Link mode transmits the video over a single FPD-Link III to a single receiver. Single link mode supports

frequencies up to 96MHz for 24-bit video when paired with the DS90UB940-Q1/DS90UB948-Q1. This mode is

compatible with the DS90UB926Q-Q1/DS90UB928Q-Q1 when operating below 85MHz. If the downstream

device is capable, the secondary FPD-Link III link could be used for high-speed control.

In Forced Single mode (set via DUAL_CTL1 register), the secondary TX Phy and back channel are disabled.

8.4.2.2 Dual Link Operation

In Dual Link mode, the FPD-Link III TX splits a single video stream and sends alternating pixels on two

downstream links. The receiver must be a DS90UB948-Q1 or DS90UB940-Q1, capable of receiving the dual-

stream video. Dual link mode is capable of supporting an HDMI clock frequency of up to 170MHz, with each

FPD-Link III TX port running at one-half the frequency. This allows support for full 1080p video. The secondary

FPD-Link III link could be used for high-speed control.

Dual Link mode may be automatically configured when connected to a DS90UB948-Q1/DS90UB940-Q1, if the

video meets minimum frequency requirements. Dual Link mode may also be forced using the DUAL_CTL1

8.4.2.3 Replicate Mode

In this mode, the FPD-Link III TX operates as a 1:2 Repeater. The same video (up to 85MHz, 24-bit color) is

delivered to each receiver.

Replicate mode may be automatically configured when connected to two independent Deserializers.

8.4.2.4 Auto-Detection of FPD-Link III Modes

The DS90UB949-Q1 automatically detects the capabilities of downstream links and can resolve whether a single

device, dual-capable device, or multiple single link devices are connected.

In addition to the downstream device capabilities, the DS90UB949-Q1 will be able to detect the HDMI pixel clock

frequency to select the proper operating mode.

If the DS90UB949-Q1 detects two independent devices, it will operate in Replicate mode, sending the single

channel video on both connections. If the device detects a device on the secondary link, but not the first, it can

send the video only on the second link.

Auto-detection can be disabled to allow forced modes of operation using the Dual Link Control Register

(DUAL_CTL1).

8.5 Programming

8.5.1 Serial Control Bus

This serializer may also be configured by the use of a I2C compatible serial control bus. Multiple devices may

share the serial control bus (up to 8 device addresses supported). The device address is set via a resistor divider

(R1 and R2 — see Figure 21 below) connected to the IDx pin.

Product Folder Links: DS90UB949-Q1

SDA

SCL

S P

START condition, or

START repeat condition STOP condition

HOST SER

SCL

SDA

4.7k 4.7k R2

SCL

SDA

To other

Devices

IDx

VDD18

VDDI2C

VR2

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

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Programming (continued)

Figure 21. Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial

Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to VDD18 or VDD33.

For most applications, a 4.7kΩpull-up resistor is recommended. However, the pull-up resistor value may be

adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

The IDx pin configures the control interface to one of 8 possible device addresses. A pull-up resistor and a pull-

down resistor may be used to set the appropriate voltage on the IDx input pin See Table 10 below.

Table 9. Serial Control Bus Addresses For IDx

Ratio Ideal VR2 Suggested Resistor Suggested Resistor

# 7-Bit Address 8-Bit Address

VR2 / VDD18 (V) R1 kΩ(1% tol) R2 kΩ(1% tol)

1 0 0 OPEN 40.2 0x0C 0x18

2 0.208 0.374 118 30.9 0x0E 0x1C

3 0.323 0.582 107 51.1 0x10 0x20

4 0.440 0.792 113 88.7 0x12 0x24

5 0.553 0.995 82.5 102 0x14 0x28

6 0.668 1.202 68.1 137 0x16 0x2C

7 0.789 1.420 56.2 210 0x18 0x30

8 1 1.8 13.3 OPEN 0x1A 0x34

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when

SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See

Figure 22

Figure 22. Start And Stop Conditions

To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a

response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is

addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't

match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs

also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after

Product Folder Links: DS90UB949-Q1

Slave Address Register Address Data

S0a

Slave Address Register Address Slave Address Data

S01

S P

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SNLS452 –NOVEMBER 2014

every data byte is successfully received. When the master is reading data, the master ACKs after every data

byte is received to let the slave know it wants to receive another data byte. When the master wants to stop

reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus

begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop

condition. A READ is shown in Figure 25 and a WRITE is shown in Figure 26.

Figure 23. Serial Control Bus — Read

Figure 24. Serial Control Bus — Write

The I2C Master located at the serializer must support I2C clock stretching. For more information on I2C interface

requirements and throughput considerations, please refer to TI Application Note SNLA131.

8.5.2 Multi-Master Arbitration Support

The Bidirectional Control Channel in the FPD-Link III devices implements I2C compatible bus arbitration in the

proxy I2C master implementation. When sending a data bit, each I2C master senses the value on the SDA line.

If the master is sending a logic 1 but senses a logic 0, the master has lost arbitration. It will stop driving SDA,

retrying the transaction when the bus becomes idle. Thus, multiple I2C masters may be implemented in the

system.

If the system does require master-slave operation in both directions across the BCC, some method of

communication must be used to ensure only one direction of operation occurs at any time. The communication

method could include using available read/write registers in the deserializer to allow masters to communicate

with each other to pass control between the two masters. An example would be to use register 0x18 or 0x19 in

the deserializer as a mailbox register to pass control of the channel from one master to another.

8.5.3 I2C Restrictions on Multi-Master Operation

The I2C specification does not provide for arbitration between masters under certain conditions. The system

should make sure the following conditions cannot occur to prevent undefined conditions on the I2C bus:

• One master generates a repeated Start while another master is sending a data bit.

• One master generates a Stop while another master is sending a data bit.

• One master generates a repeated Start while another master sends a Stop.

Note that these restrictions mainly apply to accessing the same register offsets within a specific I2C slave.

8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices

When using the latest generation of FPD-Link III devices, DS90UB949-Q1 or DS90UB940-Q1/DS90UB948-Q1

registers may be accessed simultaneously from both local and remote I2C masters. These devices have internal

logic to properly arbitrate between sources to allow proper read and write access without risk of corruption.

Access to remote I2C slaves would still be allowed in only one direction at a time .

8.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices

When using older FPD-Link III devices, simultaneous access to serializer or deserializer registers from both local

and remote I2C masters may cause incorrect operation, thus restrictions should be imposed on accessing of

serializer and deserializer registers. The likelihood of an error occurrence is relatively small, but it is possible for

collision on reads and writes to occur, resulting in an errored read or write.

Two basic options are recommended. The first is to allow device register access only from one controller. This

would allow only the Host controller to access the serializer registers (local) and the deserializer registers

(remote). A controller at the deserializer would not be allowed to access the deserializer or serializer registers.

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The second basic option is to allow local register access only with no access to remote serializer or deserializer

registers. The Host controller would be allowed to access the serializer registers while a controller at the

deserializer could access those register only. Access to remote I2C slaves would still be allowed in one

direction .

In a very limited case, remote and local access could be allowed to the deserializer registers at the same time.

deserializer register. This allows a simple method of passing control of the Bidirectional Control Channel from

one master to another.

8.5.6 Restrictions on Control Channel Direction for Multi-Master Operation

Only one direction should be active at any time across the Bidirectional Control Channel. If both directions are

required, some method of transferring control between I2C masters should be implemented.

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8.6 Register Maps

Table 10. Serial Control Bus Registers

ADD ADD Register Default

(dec) (hex) Type (hex)

0 0x00 I2C Device ID 7:1 RW Strap DEVICE_ID 7-bit address of Serializer. Defaults to address configured by the IDx strap pin.

0 RW 0x00 ID Setting I2C ID setting.

0: Device I2C address is from IDx strap pin (default).

1: Device I2C address is from 0x00[7:1].

1 0x01 Reset 7 RW Strap Soft Sleep 0: Do not power down when no Bidirectional Control Channel link is detected.

1: Power down when no Bidirectional Control Channel link is detected.

This bit is strapped from MODE_SEL0 at power-up.

6:5 0x00 Reserved.

4 RW HDMI Reset HDMI Digital Reset.

Resets the HDMI digital block. This bit is self-clearing.

0: Normal operation.

1: Reset.

3:2 Reserved.

1 RW Digital Reset the entire digital block including registers. This bit is self-clearing.

RESET1 0: Normal operation (default).

1: Reset.

0 RW Digital Reset the entire digital block except registers. This bit is self-clearing.

RESET0 0: Normal operation (default).

1: Reset.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

3 0x03 General 7 RW 0xD2 Back channel Enable/disable back channel CRC Checker.

Configuration CRC Checker 0: Disable.

Enable 1: Enable (default).

6Reserved.

5 RW I2C Remote Automatically acknowledge I2C remote writes. When enabled, I2C writes to the

Write Auto Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately

Acknowledge acknowledged without waiting for the Deserializer to acknowledge the write. This allows

Port0/Port1 higher throughput on the I2C bus. Note: this mode will prevent any NACK from a remote

device from reaching the I2C master.

0: Disable (default).

1: Enable.

If PORT1_SEL is set, this register controls Port1 operation.

4 RW Filter Enable HS, VS, DE two-clock filter. When enabled, pulses less than two full TMDS clock cycles

on the DE, HS, and VS inputs will be rejected.

0: Filtering disable.

1: Filtering enable (default).

3 RW I2C Pass- I2C pass-through mode. Read/Write transactions matching any entry in the Slave Alias

through registers will be passed through to the remote Deserializer.

Port0/Port1 0: Pass-through disabled (default).

1: Pass-through enabled.

If PORT1_SEL is set, this register controls Port1 operation.

2Reserved.

1 RW TMDS Clock Switch over to internal oscillator in the absence of TMDS Clock.

Auto 0: Disable auto-switch.

1: Enable auto-switch (default).

0Reserved.

4 0x04 Mode Select 7 RW 0x80 Failsafe State Input failsafe state.

0: Failsafe to High.

1: Failsafe to Low (default).

6Reserved.

5 RW CRC Error Clear back channel CRC Error counters. This bit is NOT self-clearing.

Reset 0: Normal operation (default).

1: Clear counters.

4:0 Reserved.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

5 0x05 I2C Control 7:5 0x00 Reserved.

4:3 RW SDA Output Configures output delay on the SDA output. Setting this value will increase output delay

Delay in units of 40ns.

Nominal output delay values for SCL to SDA are:

00: 240ns (default).

01: 280ns.

10: 320ns.

11: 360ns.

2 RW Local Write Disable remote writes to local registers. Setting this bit to 1 will prevent remote writes to

Disable local device registers from across the control channel. This prevents writes to the

Serializer registers from an I2C master attached to the Deserializer. Setting this bit does

not affect remote access to I2C slaves at the Serializer.

0: Enable (default).

1: Disable.

1 RW I2C Bus Timer Speed up I2C bus Watchdog Timer.

Speedup 0: Watchdog Timer expires after approximately 1s (default).

1: Watchdog Timer expires after approximately 50µs.

0 RW I2C Bus Timer Disable I2C bus Watchdog Timer. The I2C Watchdog Timer may be used to detect when

Disable the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is

high and no signaling occurs for approximately 1s, the I2C bus will be assumed to be

free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by

driving 9 clocks on SCL.

0: Enable (default).

1: Disable.

6 0x06 DES ID 7:1 RW 0x00 DES Device ID 7-bit I2C address of the remote Deserializer. A value of 0 in this field disables I2C access

Port0/Port1 to the remote Deserializer. This field is automatically configured by the Bidirectional

Control Channel once RX Lock has been detected. Software may overwrite this value,

but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the

Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates the Deserializer Device ID for the

Deserializer attached to Port1.

0 RW Freeze Device Freeze Deserializer Device ID.

ID 1: Prevents auto-loading of the Deserializer Device ID by the Bidirectional Control

Port0/Port1 Channel. The ID will be frozen at the value written.

0: Allows auto-loading of the Deserializer Device ID from the Bidirectional Control

Channel.

If PORT1_SEL is set, this register is with reference to Port1.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

7 0x07 Slave ID[0] 7:1 RW 0x00 Slave ID 0 7-bit I2C address of the remote Slave 0 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 0, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 0.

If PORT1_SEL is set, this register is with reference to Port1.

0Reserved.

8 0x08 Slave Alias[0] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 0 attached to the remote Deserializer. The

0 transaction will be remapped to the address specified in the Slave ID 0 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 0.

If PORT1_SEL is set, this register is with reference to Port1.

0Reserved.

10 0x0A CRC Errors 7:0 R 0x00 CRC Error Number of back channel CRC errors – 8 least significant bits. Cleared by 0x04[5].

LSB If PORT1_SEL is set, this register is with reference to Port1.

Port0/Port1

11 0x0B 7:0 R 0x00 CRC Error Number of back channel CRC errors – 8 most significant bits. Cleared by 0x04[5].

MSB If PORT1_SEL is set, this register is with reference to Port1.

Port0/Port1

12 0x0C General Status 7:5 Reserved.

4 0x00 Link Lost Link lost flag for selected port:

Port0/Port1 This bit indicates that loss of link has been detected. This register bit will stay high until

cleared using the CRC Error Reset in register 0x04.

If PORT1_SEL is set, this register is with reference to Port1.

3 R BIST CRC Back channel CRC error(s) during BIST communication with Deserializer. This bit is

Error cleared upon loss of link, restart of BIST, or assertion of CRC Error Reset bit in 0x04[5].

Port0/Port1 0: No CRC errors detected during BIST.

1: CRC error(s) detected during BIST.

If PORT1_SEL is set, this register is with reference to Port1.

2 R TMDS Clock Pixel clock status:

Detect 0: Valid clock not detected at HDMI input.

1: Valid clock detected at HDMI input.

1 R DES Error CRC error(s) during normal communication with Deserializer. This bit is cleared upon

Port0/Port1 loss of link or assertion of 0x04[5].

0: No CRC errors detected.

1: CRC error(s) detected.

If PORT1_SEL is set, this register is with reference to Port1.

0 R Link Detect Link detect status:

Port0/Port1 0: Cable link not detected.

1: Cable link detected.

If PORT1_SEL is set, this register is with reference to Port1.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

13 0x0D GPIO0 7:4 R Revision ID Revision ID.

Configuration 3 RW 0x00 GPIO0 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

Value is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

D_GPIO0 0: Output LOW (default).

Output Value 1: Output HIGH.

If PORT1_SEL is set, this register controls the D_GPIO0 pin.

2:0 RW GPIO0 Determines operating mode for the GPIO pin:

ModeD_GPIO0 xx0: TRI-STATE™.

Mode 001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO0 pin.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

14 0x0E GPIO1 and 7 RW 0x00 GPIO2 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

GPIO2 ValueD_GPIO is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

ConfigurationD_ 2 Output Value 0: Output LOW (default).

GPIO1 and 1: Output HIGH.

D_GPIO2 If PORT1_SEL is set, this register controls the D_GPIO2 pin.

Configuration 6:4 RW GPIO2 Determines operating mode for the GPIO pin:

ModeD_GPIO2 x00: Functional input mode.

Mode x10: TRI-STATE™.

001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO2 pin.

3 RW GPIO1 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

ValueD_GPIO is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

1 Output Value 0: Output LOW (default).

1: Output HIGH.

If PORT1_SEL is set, this register controls the D_GPIO1 pin.

2:0 RW GPIO1 Determines operating mode for the GPIO pin:

ModeD_GPIO1 xx0: TRI-STATE™.

Mode 001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO1 pin.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

15 0x0F GPIO3 7:4 0x00 Reserved.

ConfigurationD_ 3 RW GPIO3 Output Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

GPIO3 ValueD_GPIO is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.

Configuration 3 Output Value 0: Output LOW (default).

1: Output HIGH.

If PORT1_SEL is set, this register controls the D_GPIO3 pin.

2:0 RW GPIO3 Determines operating mode for the GPIO pin:

ModeD_GPIO3 x00: Functional input mode.

Mode x10: TRI-STATE™.

001: GPIO mode, output.

011: GPIO mode, input.

101: Remote-hold mode. The GPIO pin will be an output, and the value is received from

the remote Deserializer. In remote-hold mode, data is maintained on link loss.

111: Remote-default mode. The GPIO pin will be an output, and the value is received

from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output

on link loss.

If PORT1_SEL is set, this register controls the D_GPIO3 pin.

16 0x10 GPIO5_REG 7 RW 0x00 GPIO6_REG Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

and Output Value is enabled and the local GPIO direction is set to output.

GPIO6_REG 0: Output LOW (default).

Configuration 1: Output HIGH.

6Reserved.

5:4 RW GPIO6_REG Determines operating mode for the GPIO pin:

Mode 00: Functional input mode.

10: TRI-STATE™.

01: GPIO mode, output.

11: GPIO mode; input.

3 RW GPIO5_REG Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

Output Value is enabled and the local GPIO direction is set to output.

0: Output LOW (default).

1: Output HIGH.

2Reserved.

1:0 RW GPIO5_REG Determines operating mode for the GPIO pin:

Mode 00: Functional input mode.

10: TRI-STATE™.

01: GPIO mode, output.

11: GPIO mode; input.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

17 0x11 GPIO7_REG 7 RW 0x00 GPIO8_REG Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

and Output Value is enabled and the local GPIO direction is set to output.

GPIO8_REG 0: Output LOW (default).

Configuration 1: Output HIGH.

6Reserved.

5:4 RW GPIO8_REG Determines operating mode for the GPIO pin:

Mode 00: Functional input mode.

10: TRI-STATE.

01: GPIO mode, output.

11: GPIO mode; input.

3 RW GPIO7_REG Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function

Output Value is enabled and the local GPIO direction is set to output.

0: Output LOW (default).

1: Output HIGH.

2Reserved.

1:0 RW GPIO7_REG Determines operating mode for the GPIO pin:

Mode 00: Functional input mode.

10: TRI-STATE.

01: GPIO mode, output.

11: GPIO mode; input.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

18 0x12 Data Path 7 0x00 Reserved.

Control 6 RW Pass RGB Setting this bit causes RGB data to be sent independent of DE. However, setting this bit

blocks packetized audio. This bit does not need to be set in UB serializers.

0: Normal operation.

1: Pass RGB independent of DE.

5 RW DE Polarity This bit indicates the polarity of the DE (Data Enable) signal.

0: DE is positive (active high, idle low).

1: DE is inverted (active low, idle high).

4 RW I2S Repeater Regenerate I2S data from Repeater I2S pins.

Regen 0: Repeater pass through I2S from video pins (default).

1: Repeater regenerate I2S from I2S pins.

3 RW I2S Channel B I2S Channel B Enable Override.

Enable 0: Disable I2S Channel B override.

Override 1: Set I2S Channel B Enable from 0x12[0].

2 RW 18-Bit Video 0: Select 24-bit video mode.

Select 1: Select 18-bit video mode.

1 RW I2S Transport Select I2S transport mode:

Select 0: Enable I2S Data Island transport (default).

1: Enable I2S Data Forward Channel Frame transport.

0 RW I2S Channel B I2S Channel B Enable.

Enable 0: I2S Channel B disabled.

1: Enable I2S Channel B on B1 input.

Note that in a repeater, this bit may be overridden by the in-band I2S mode detection.

19 0x13 General Purpose 7 R 0x88 MODE_SEL1 Indicates MODE_SEL1 value has stabilized and has been latched.

Control Done

6:4 R MODE_SEL1 Returns the 3-bit decode of the MODE_SEL1 pin.

Decode

3 R MODE_SEL0 Indicates MODE_SEL0 value has stabilized and has been latched.

Done

2:0 R MODE_SEL0 Returns the 3-bit decode of the MODE_SEL0 pin.

Decode

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

20 0x14 BIST Control 7:3 0x00 Reserved.

2:1 RW OSC Clock Allows choosing different OSC clock frequencies for forward channel frame.

Source OSC clock frequency in functional mode when TMDS clock is not present and 0x03[2]=1:

00: 50 MHz oscillator.

01: 50 MHz oscillator.

10: 100 MHz oscillator.

11: 25 MHz oscillator.

Clock source in BIST mode i.e. when 0x14[0]=1:

00: External pixel clock.

01: 33 MHz oscillator.

1x: 100 MHz oscillator.

0 RW BIST Enable BIST control:

0: Disabled (default).

1: Enabled.

21 0x15 I2C Voltage 7:0 RW 0x01 I2C Voltage Selects 1.8 or 3.3V for the I2C_SDA and I2C_SCL pins. This register is loaded from the

Select Select I2C_VSEL strap option from the SCLK pin at power-up. At power-up, a logic LOW will

select 3.3V operation, while a logic HIGH (pull-up resistor attached) will select 1.8V

signaling.

Reads of this register return the status of the I2C_VSEL control:

0: Select 1.8V signaling.

1: Select 3.3V signaling.

This bit may be overwritten via register access or via eFuse program by writing an 8-bit

value to this register:

Write 0xb5 to set I2C_VSEL.

Write 0xb6 to clear I2C_VSEL.

22 0x16 BCC Watchdog 7:1 RW 0xFE Timer Value The watchdog timer allows termination of a control channel transaction if it fails to

Control complete within a programmed amount of time. This field sets the Bidirectional Control

Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set

to 0.

0 RW Timer Control Disable Bidirectional Control Channel (BCC) Watchdog Timer:

0: Enable BCC Watchdog Timer operation (default).

1: Disable BCC Watchdog Timer operation.

23 0x17 I2C Control 7 RW 0x1E I2C Pass All 0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs

Port0/Port1 matching either the remote Deserializer Slave ID or the remote Slave ID (default).

1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs

that do not match the Serializer I2C Slave ID.

If PORT1_SEL is set, this bit controls Port1 operation.

6:4 RW SDA Hold Internal SDA hold time:

Time Configures the amount of internal hold time provided for the SDA input relative to the

SCL input. Units are 40 nanoseconds.

3:0 RW I2C Filter Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be

Depth rejected. Units are 5 nanoseconds.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

24 0x18 SCL High Time 7:0 RW 0x7F TX_SCL_HIGH I2C Master SCL high time:

This field configures the high pulse width of the SCL output when the Serializer is the

Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency.

The default value is set to provide a minimum 5us SCL high time with the internal

oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5

additional oscillator clock periods.

Min_delay = 38.0952ns * (TX_SCL_HIGH + 5).

25 0x19 SCL Low Time 7:0 RW 0x7F TX_SCL_LOW I2C Master SCL low time:

This field configures the low pulse width of the SCL output when the Serializer is the

Master on the local I2C bus. This value is also used as the SDA setup time by the I2C

Slave for providing data prior to releasing SCL during accesses over the Bidirectional

Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default

value is set to provide a minimum 5us SCL low time with the internal oscillator clock

running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional clock

periods.

Min_delay = 38.0952ns * (TX_SCL_LOW + 5).

26 0x1A Data Path 7:4 Reserved.

Control 2 3 R Strap SECONDARY Enable Secondary Audio.

_AUDIO This register indicates that the AUX audio channel is enabled. The control for this

function is via the AUX_AUDIO bit in the BRIDGE_CFG register register offset 0x54).

The AUX_AUDIO control is strapped from the MODE_SEL0 pin at power-up.

2 0x01 Reserved.

1 RW MODE_28B Enable 28-bit Serializer Mode.

0: 24-bit high-speed data + 3 low-speed control (DE, HS, VS).

1: 28-bit high-speed data mode.

0 RW I2S Surround Enable 5.1- or 7.1-channel I2S audio transport:

0: 2-channel or 4-channel I2S audio is enabled as configured in register 0x12 bits 3 and 0

(default).

1: 5.1- or 7.1-channel audio is enabled.

Note that I2S Data Island Transport is the only option for surround audio. Also note that

in a repeater, this bit may be overridden by the in-band I2S mode detection.

27 0x1B BIST BC Error 7:0 R 0x00 BIST BC Error BIST back channel CRC error counter.

Count Port0/Port1 This register stores the back channel CRC error count during BIST Mode (saturates at

255 errors). Clears when a new BIST is initiated or by 0x04[5].

If PORT1_SEL is set, this register indicates Port1 status.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

28 0x1C GPIO Pin Status 7 R 0x00 GPIO7_REG GPIO7_REG input pin status.

1 Pin Status Note: status valid only if pin is set to GPI (input) mode.

6 R GPIO6_REG GPIO6_REG input pin status.

Pin Status Note: status valid only if pin is set to GPI (input) mode.

5 R GPIO5_REG GPIO5_REG input pin status.

Pin Status Note: status valid only if pin is set to GPI (input) mode.

4Reserved.

3 R GPIO3 Pin GPIO3 input pin status.

Status Note: status valid only if pin is set to GPI (input) mode.

D_GPIO3 Pin If PORT1_SEL is set, this register indicates D_GPIO3 input pin status.

Status

2 R GPIO2 Pin GPIO2 input pin status.

Status Note: status valid only if pin is set to GPI (input) mode.

D_GPIO2 Pin If PORT1_SEL is set, this register indicates D_GPIO2 input pin status.

Status

1 R GPIO1 Pin GPIO1 input pin status.

Status Note: status valid only if pin is set to GPI (input) mode.

D_GPIO1 Pin If PORT1_SEL is set, this register indicates D_GPIO1 input pin status.

Status

0 R GPIO0 Pin GPIO0 input pin status.

Status Note: status valid only if pin is set to GPI (input) mode.

D_GPIO0 Pin If PORT1_SEL is set, this register indicates D_GPIO0 input pin status.

Status

29 0x1D GPIO Pin Status 7:1 0x00 Reserved

20 R GPIO8_REG GPIO8_REG input pin status.

Pin Status Note: status valid only if pin is set to GPI (input) mode.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

30 0x1E Transmitter Port 7:3 Reserved.

Select 2 RW 0x01 PORT1_I2C_E Port1 I2C Enable.

N Enables secondary I2C address. The second I2C address provides access to Port1

registers as well as registers that are shared between Port0 and Port1. The second I2C

address value will be set to DeviceID + 1 (7-bit format). The PORT1_I2C_EN bit must

also be set to allow accessing remote devices over the second link when the device is in

Replicate mode.

1 RW PORT1_SEL Selects Port1 for register access from primary I2C address.

For writes, Port1 registers and shared registers will both be written.

For reads, Port1 registers and shared registers will be read. This bit must be cleared to

read Port0 registers.

This bit is ignored if PORT1_I2C_EN is set.

0 RW PORT0_SEL Selects Port0 for register access from primary I2C address.

For writes, Port0 registers and shared registers will both be written.

For reads, Port0 registers and shared registers will be read. Note that if PORT1_SEL is

also set, then Port1 registers will be read.

This bit is ignored if PORT1_I2C_EN is set.

31 0x1F Frequency 7:0 RW 0x00 Frequency Frequency counter control.

Counter Count A write to this register will enable a frequency counter to count the number of pixel clock

during a specified time interval. The time interval is equal to the value written multiplied

by the oscillator clock period (nominally 40ns). A read of the register returns the number

of pixel clock edges seen during the enabled interval. The frequency counter will freeze

at 0xff if it reaches the maximum value. The frequency counter will provide a rough

estimate of the pixel clock period. If the pixel clock frequency is known, the frequency

counter may be used to determine the actual oscillator clock frequency.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

32 0x20 Deserializer 7 RW 0x00 FREEZE_DES Freeze Deserializer Capabilities.

Capabilities 1 _CAP Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel.

Port0/Port1 The Capabilities will be frozen at the values written in registers 0x20 and 0x21.

If PORT1_SEL is set, this register indicates Port1 capabilities.

6 RW 0x00 HSCC_MODE[ High-Speed Control Channel bit 0.

0] Lowest bit of the 3-bit HSCC indication. The other 2 bits are contained in Deserializer

Port0/Port1 Capabilities 2. This field is automatically configured by the Bidirectional Control Channel

once RX Lock has been detected. Software may overwrite this value, but must also set

the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

5 SEND_FREQ Send Frequency Training Pattern.

Port0/Port1 Indicates the DS90UB949-Q1 should send the Frequency Training Pattern. This field is

automatically configured by the Bidirectional Control Channel once RX Lock has been

detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit

to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

4 RW 0x00 SEND_EQ Send Equalization Training Pattern.

Port0/Port1 Indicates the DS90UB949-Q1 should send the Equalization Training Pattern. This field is

automatically configured by the Bidirectional Control Channel once RX Lock has been

detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit

to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

3 RW DUAL_LINK_C Dual link Capabilities.

AP Indicates if the Deserializer is capable of dual link operation. This field is automatically

Port0/Port1 configured by the Bidirectional Control Channel once RX Lock has been detected.

Software may overwrite this value, but must also set the FREEZE DES CAP bit to

prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

2 RW DUAL_CHANN Dual Channel 0/1 Indication.

EL In a dual-link capable device, indicates if this is the primary or secondary channel.

Port0/Port1 0: Primary channel (channel 0).

1: Secondary channel (channel 1).

This field is automatically configured by the Bidirectional Control Channel once RX Lock

has been detected. Software may overwrite this value, but must also set the FREEZE

DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

32 0x20 Deserializer 1 RW 0x00 VID_24B_HD_ Deserializer supports 24-bit video concurrently with HD audio.

Capabilities 1 AUD This field is automatically configured by the Bidirectional Control Channel once RX Lock

Port0/Port1 has been detected. Software may overwrite this value, but must also set the FREEZE

DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

0 RW DES_CAP_FC Deserializer supports GPIO in the Forward Channel Frame.

_GPIO This field is automatically configured by the Bidirectional Control Channel once RX Lock

Port0/Port1 has been detected. Software may overwrite this value, but must also set the FREEZE

DES CAP bit to prevent overwriting by the Bidirectional Control Channel.

If PORT1_SEL is set, this register indicates Port1 capabilities.

33 0x21 Deserializer 7:2 Reserved.

Capabilities 2 1:0 RW 0x00 HSCC_MODE[ High-Speed Control Channel bits [2:1].

2:1] Upper bits of the 3-bit HSCC indication. The lowest bit is contained in Deserializer

Port0/Port1 Capabilities 1.

000: Normal back channel frame, GPIO mode.

001: High Speed GPIO mode, 1 GPIO.

010: High Speed GPIO mode, 2 GPIOs.

011: High Speed GPIO mode: 4 GPIOs.

100: Reserved.

101: Reserved.

110: High Speed, Forward Channel SPI mode.

111: High Speed, Reverse Channel SPI mode. In Single Link devices, only Normal back

channel frame modes are supported.

If PORT1_SEL is set, this register indicates Port1 capabilities.

38 0x26 Link Detect 7:3 Reserved.

Control 2:0 RW 0x00 LINK DETECT Bidirectional Control Channel Link Detect Timer.

TIMER This field configures the link detection timeout period. If the timer expires without valid

communication over the reverse channel, link detect will be deasserted.

000: 162 microseconds.

001: 325 microseconds.

010: 650 microseconds.

011: 1.3 milliseconds.

100: 10.25 microseconds.

101: 20.5 microseconds.

110: 41 microseconds.

111: 82 microseconds.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

48 0x30 SCLK_CTRL 7 RW 0x00 SCLK/WS SCLK to Word Select Ratio.

0 : 64.

1 : 32.

6:5 RW MCLK/SCLK MCLK to SCLK Select Ratio.

00 : 4.

01 : 2.

10 : 1.

11 : 8.

4:3 RW CLEAN Clock Cleaner divider.

CLOCK_DIV 00 : FPD_VCO_CLOCK/8.

01 : FPD_VCO_CLOCK/4.

10 : FPD_VCO_CLOCK/2.

11 : AON_OSC.

2:1 RW CLEAN Mode If non-zero, the SCLK Input or HDMI N/CTS generated Audio Clock is cleaned digitally

before being used.

00 : Off.

01 : ratio of 1.

10 : ratio of 2.

11 : ratio of 4.

0 RW MASTER If set, the SCLK I/O and the WS_IO are used as an output and the Clock Generation

Circuits are enabled, otherwise they are inputs.

49 0x31 AUDIO_CTS0 7:0 RW 0x00 CTS[7:0] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

50 0x32 AUDIO_CTS1 7:0 RW 0x00 CTS[15:8] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

51 0x33 AUDIO_CTS2 7:0 RW 0x00 CTS[23:16] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

52 0x34 AUDIO_N0 7:0 RW 0x00 N[7:0] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

53 0x35 AUDIO_N1 7:0 RW 0x00 N[15:8] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

54 0x36 AUDIO_N2_CO 7:4 RW 0x00 COEFF[3:0] Selects the LPF_COEFF in the Clock Cleaner (Feedback is divided by 2^COEFF).

EFF 3:0 RW 0x00 N[19:16] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO.

55 0x37 CLK_CLEAN_ST 7:6 Reserved.

S5:3 R 0x00 IN_FIFO_LVL Clock Cleaner Input FIFO Level.

2:0 R 0x00 OUT_FIFO_LV Clock Cleaner Output FIFO Level.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

72 0x48 APB_CTL 7:5 Reserved.

4:3 RW 0x00 APB_SELECT APB Select: Selects target for register access.

00 : HDMI APB interface.

01 : EDID SRAM.

10 : Configuration Data (read only).

11 : Die ID (read only).

2 RW APB_AUTO_I APB Auto Increment: Enables auto-increment mode. Upon completion of an APB read or

NC write, the APB address will automatically be incremented by 0x4 for HDMI registers or by

0x1 for others.

1 RW APB_READ Start APB Read: Setting this bit to a 1 will begin an APB read. Read data will be available

in the APB_DATAx registers. The APB_ADRx registers should be programmed prior to

setting this bit. This bit will be cleared when the read is complete.

0 RW APB_ENABLE APB Interface Enable: Set to a 1 to enable the APB interface. The APB_SELECT bits

indicate what device is selected.

73 0x49 APB_ADR0 7:0 RW 0x00 APB_ADR0 APB Address byte 0 (LSB).

74 0x4A APB_ADR1 7:0 RW 0x00 APB_ADR1 APB Address byte 1 (MSB).

75 0x4B APB_DATA0 7:0 RW 0x00 APB_DATA0 Byte 0 (LSB) of the APB Interface Data.

76 0x4C APB_DATA1 7:0 RW 0x00 APB_DATA1 Byte 1 of the APB Interface Data.

77 0x4D APB_DATA2 7:0 RW 0x00 APB_DATA2 Byte 2 of the APB Interface Data.

78 0x4E APB_DATA3 7:0 RW 0x00 APB_DATA3 Byte 3 (MSB) of the APB Interface Data.

79 0x4F BRIDGE_CTL 7:5 Reserved.

4 RW 0x00 CEC_CLK_SR CEC Clock Source Select: Selects clock source for generating the 32.768kHz clock for

C CEC operations in the HDMI Receive Controller.

0 : Selects internal generated clock.

1 : Selects external 25MHz oscillator clock.

3 RW CEC_CLK_EN CEC Clock Enable: Enable CEC clock generation. Enables generation of the 32.768kHz

clock for the HDMI Receive controller. This bit should be set prior to enabling CEC

operation via the HDMI controller registers.

2 RW EDID_CLEAR Clear EDID SRAM: Set to 1 to enable clearing the EDID SRAM. The EDID_INIT bit must

be set at the same time for the clear to occur. This bit will be cleared when the

initialization is complete.

1 RW EDID_INIT Initialize EDID SRAM from EEPROM: Causes a reload of the EDID SRAM from the non-

volatile EDID EEPROM. This bit will be cleared when the initialization is complete.

0 R Strap EDID_DISABL Disable EDID access via DDC/I2C: Disables access to the EDID SRAM via the HDMI

E DDC interface. This value is loaded from the MODE_SEL0 pin at power-up.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

80 0x50 BRIDGE_STS 7 R 0x03 RX5V_DETEC RX +5V detect: Indicates status of the RX_5V pin. When asserted, indicates the HDMI

T interface has detected valid voltage on the RX_5V input.

6 R HDMI_INT HDMI Interrupt Status: Indicates an HDMI Interrupt is pending. HDMI interrupts are

serviced through the HDMI Registers via the APB Interface.

5 Reserved.

4 R INIT_DONE Initialization Done: Initialization sequence has completed. This step will complete after

configuration complete (CFG_DONE).

3 R REM_EDID_L Remote EDID Loaded: Indicates EDID SRAM has been loaded from a remote EDID

OAD EEPROM device over the Bidirectional Control Channel. The EDID_CKSUM value

indicates if the EDID load was successful.

2 R CFG_DONE Configuration Complete: Indicates automatic configuration has completed. This step will

complete prior to initialization complete (INIT_DONE).

1 R CFG_CKSUM Configuration checksum status: Indicates result of Configuration checksum during

initialization. The device verifies the 2’s complement checksum in the last 128 bytes of

the EEPROM. A value of 1 indicates the checksum passed.

0 R EDID_CKSUM EDID checksum Status: Indicates result of EDID checksum during EDID initialization. The

device verifies the 2’s complement checksum in the first 256 bytes of the EEPROM. A

value of 1 indicates the checksum passed.

81 0x51 EDID_ID 7:1 RW 0x50 EDID_ID EDID I2C Slave Address: I2C address used for accessing the EDID information. These

are the upper 7 bits in 8-bit format addressing, where the lowest bit is the Read/Write

control.

0 RW 0 EDID_RDONL EDID Read Only: Set to a 1 puts the EDID SRAM memory in read-only mode for access

Y via the HDMI DDC interface. Setting to a 0 allows writes to the EDID SRAM memory.

82 0x52 EDID_CFG0 7 Reserved.

6:4 RW 0x01 EDID_SDA_H Internal SDA Hold Time: This field configures the amount of internal hold time provided

OLD for the DDC_SDA input relative to the DDC_SCL input. Units are 40 nanoseconds. The

hold time is used to qualify the start detection to avoid false detection of Start or Stop

conditions.

3:0 RW 0x0E EDID_FLTR_D I2C Glitch Filter Depth: This field configures the maximum width of glitch pulses on the

PTH DDC_SCL and DDC_SDA inputs that will be rejected. Units are 5 nanoseconds.

83 0x53 EDID_CFG1 7:2 Reserved.

1:0 RW 0x00 EDID_SDA_DL SDA Output Delay: This field configures output delay on the DDC_SDA output when the

Y EDID memory is accessed. Setting this value will increase output delay in units of 40ns.

Nominal output delay values for DDC_SCL to DDC_SDA are:

00 : 240ns.

01 : 280ns.

10 : 320ns.

11 : 360ns.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

84 0x54 BRIDGE_CFG 7 RW Strap EXT_CTL External Control: When this bit Is set, the internal bridge control function is disabled. This

disables initialization of the HDMI Receiver. These operations must be controlled by an

external controller attached to the I2C interface. This value is loaded from the

MODE_SEL1 pin at power-up.

6 RW 0x00 HDMI_INT_EN HDMI Interrupt Enable: When this bit is set, Interrupts from the HDMI Receive controller

will be reported on the INTB pin. Software may check the BRIDGE_STS register to

determine if the interrupt is from the HDMI Receiver.

5 RW Strap DIS_REM_EDI Disable Remote EDID load: Disables automatic load of EDID SRAM from a remote EDID

D EEPROM. By default, the device will check the remote I2C bus for an EEPROM with a

valid EDID, and load the EDID data to local EDID SRAM. If this bit is set to a 1, the

remote EDID load will be bypassed. This value is loaded from the MODE_SEL1 pin at

power-up.

4 RW 0x00 AUTO_INIT_DI Disable Automatic initialization: The Bridge control will automatically initialize the HDMI

S Receiver for operation. Setting this bit to a 1 will disable automatic initialization of the

HDMI Receiver. In this mode, initialization of the HDMI Receiver must be done through

EEPROM configuration or via external control.

3 Reserved.

2 RW 0x00 AUDIO_TDM Enable TDM Audio: Setting this bit to a 1 will enable TDM audio for the HDMI audio.

1 RW AUDIO_MODE Audio Mode: Selects source for audio to be sent over the FPD-Link III downstream link.

0 : HDMI audio.

1 : Local/DVI audio.

Local audio is sourced from the device I2S pins rather than from HDMI, and is useful in

modes such as DVI that do not include audio.

0 RW Strap AUX_AUDIO_ AUX Audio Channel Enable: Setting this bit to a 1 will enable the AUX audio channel.

EN This allows sending additional 2-channel audio in addition to the HDMI or DVI audio. This

bit is loaded from the MODE_SEL0 pin at power-up.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

85 0x55 AUDIO_CFG 7 RW 0x00 TDM_2_PARA Enable I2S TDM to parallel audio conversion: When this bit is set, the i2s tdm to parallel

LLEL conversion module is enabled. The clock output from the i2s tdm to parallel conversion

module is them used to send data to the deserializer.

6 RW HDMI_I2S_OU HDMI Audio Output Enable: When this bit is set, the HDMI I2S audio data will be output

T on the I2S audio interface pins. This control is ignored if the

BRIDGE_CFG:AUDIO_MODE is not set to 00 (HDMI audio only).

5:4 Reserved.

3 RW 0x0C RST_ON_TYP Reset Audio FIFO on Type Change: When this bit is set, the internal bridge control

E function will reset the HDMI Audio FIFO on a change in the Audio type.

2 RW RST_ON_AIF Reset Audio FIFO on Audio Infoframe: When this bit is set, the internal bridge control

function will reset the HDMI Audio FIFO on a change in the Audio Infoframe checksum.

1 RW RST_ON_AVI Reset Audio FIFO on Audio Video Information Infoframe: When this bit is set, the internal

bridge control function will reset the HDMI Audio FIFO on a change in the Audio Video

Information Infoframe checksum.

0 RW RST_ON_ACR Reset Audio FIFO on Audio Control Frame: When this bit is set, the internal bridge

control function will reset the HDMI Audio FIFO on a change in the Audio Control Frame

N or CTS fields.

90 0x5A DUAL_STS 7 R 0x00 FPD3_LINK_R This bit indicates that the FPD-Link III has detected a valid downstream connection and

DY determined capabilities for the downstream link.

6 R FPD3_TX_ST FPD-Link III transmit status:

S This bit indicates that the FPD-Link III transmitter is active and the receiver is LOCKED to

the transmit clock. It is only asserted once a valid input has been detected, and the FPD-

Link III transmit connection has entered the correct mode (Single vs. Dual mode).

5:4 R FPD3_PORT_ FPD3 Port Status: If FPD3_TX_STS is set to a 1, this field indicates the port mode status

STS as follows:

00: Dual FPD-Link III Transmitter mode.

01: Single FPD-Link III Transmit on port 0.

10: Single FPD-Link III Transmit on port 1.

11: Replicate FPD-Link III Transmit on both ports.

3 R TMDS_VALID HDMI TMDS Valid: This bit indicates the TMDS interface is recovering valid TMDS data

from HDMI. In revA1 silicon, this bit will always return 1.

2 R HDMI_PLL_LO HDMI PLL lock status: Indicates the HDMI PLL has locked to the incoming HDMI clock.

1 R NO_HDMI_CL No HDMI Clock Detected: This bit indicates the Frequency Detect circuit did not detect an

K HDMI clock greater than the value specified in the FREQ_LOW register.

0 R FREQ_STABL HDMI Frequency is Stable: Indicates the Frequency Detection circuit has detected a

E stable HDMI clock frequency.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

91 0x5B DUAL_CTL1 7 RW Strap FPD3_COAX_ FPD3 Coax Mode: Enables configuration for the FPD3 Interface cabling type.

MODE 0 : Twisted Pair.

1 : Coax This bit is loaded from the MODE_SEL1 pin at power-up.

6 RW 0 DUAL_SWAP Dual Swap Control: Indicates current status of the Dual Swap control. If automatic

correction of Dual Swap is disabled via the DISABLE_DUAL_SWAP control, this bit may

be modified by software.

5 RW 1 RST_PLL_FR Reset FPD3 PLL on Frequency Change: When set to a 1, frequency changes detected

EQ by the Frequency Detect circuit will result in a reset of the FPD3 PLL.

4 RW 0 FREQ_DET_P Frequency Detect Select PLL Clock: Determines the clock source for the Frequency

LL detection circuit:

0 : HDMI clock (prior to PLL).

1: HDMI PLL clock.

3 RW 0 DUAL_ALIGN_ Dual align on DE (valid in dual-link mode):

DE 0: Data will be sent on alternating links without regard to odd/even pixel position.

1: Odd/Even data will be sent on the primary/secondary links, respectively, based on the

assertion of DE.

2 RW 0 DISABLE_DU Disable Dual Mode: During Auto-detect operation, setting this bit to a 1 will disable Dual

AL FPD-Link III operation.

0: Normal Auto-detect operation.

1: Only Single or Replicate operation supported.

This bit will have no effect if FORCE_LINK is set.

1 RW 0 FORCE_DUAL Force dual mode:

When FORCE_LINK bit is set, the value on this bit controls single versus dual operation:

0: Single FPD-Link III Transmitter mode.

1: Dual FPD-Link III Transmitter mode.

0 RW 0 FORCE_LINK Force Link Mode: Forces link to dual or single mode, based on the FORCE_DUAL control

setting. If this bit is 0, mode setting will be automatically set based on downstream device

capabilities as well as the incoming data frequency.

0 : Auto-Detect FPD-Link III mode.

1 : Forced Single or Dual FPD-Link III mode.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

92 0x5C DUAL_CTL2 7 RW 0 DISABLE_DU Disable Dual Swap: Prevents automatic correction of swapped Dual link connection.

AL_SWAP Setting this bit allows writes to the DUAL_SWAP control in the DUAL_CTL1 register.

6 RW 0x00 FORCE_LINK_ Force Link Ready: Forces link ready indication, bypassing back channel link detection.

RDY

5 RW FORCE_CLK_ Force Clock Detect: Forces the HDMI/OpenLDI clock detect circuit to indicate presence

DET of a valid input clock. This bypasses the clock detect circuit, allowing operation with an

input clock that does not meet frequency or stability requirements.

4:3 RW FREQ_STBL_ Frequency Stability Threshold: The Frequency detect circuit can be used to detect a

THR stable clock frequency. The Stability Threshold determines the amount of time required

for the clock frequency to stay within the FREQ_HYST range to be considered stable:

00 : 160us.

01 : 640us.

10 : 1.28ms.

11 : 2.55ms.

2:0 RW 0x02 FREQ_HYST Frequency Detect Hysteresis: The Frequency detect hysteresis setting allows ignoring

minor fluctuations in frequency. A new frequency measurement will be captured only if

the measured frequency differs from the current measured frequency by more than the

FREQ_HYST setting. The FREQ_HYST setting is in MHz.

93 0x5D FREQ_LOW 7 Reserved.

6 RW 0 HDMI_RST_M HDMI Phy Reset Mode:

ODE 0 : Reset HDMI Phy on change in mode or frequency.

1 : Don't reset HDMI Phy on change in mode or frequency if +5V is asserted.

5:0 RW 6 FREQ_LO_TH Frequency Low Threshold: Sets the low threshold for the HDMI Clock frequency detect

R circuit in MHz. This value is used to determine if the HDMI clock frequency is too low for

proper operation.

94 0x5E FREQ_HIGH 7 Reserved.

6:0 RW 44 FREQ_HI_TH Frequency High Threshold: Sets the high threshold for the HDMI Clock frequency detect

R circuit in MHz.

95 0x5F HDMI Frequency 7:0 R 0x00 HDMI_FREQ HDMI frequency:

Returns the value of the HDMI frequency in MHz. A value of 0 indicates the HDMI

receiver is not detecting a valid signal.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

96 0x60 SPI_TIMING1 7:4 RW 0x02 SPI_HOLD SPI Data Hold from SPI clock: These bits set the minimum hold time for SPI data

following the SPI clock sampling edge. In addition, this also sets the minimum active

pulse width for the SPI output clock.

0: Do not use.

0x1-0xF: Hold = (SPI_HOLD + 1) * 40ns.

For example, default setting of 2 will result in 120ns data hold time.

3:0 RW 0x02 SPI_SETUP SPI Data Setup to SPI Clock: These bits set the minimum setup time for SPI data to the

SPI clock active edge. In addition, this also sets the minimum inactive width for the SPI

output clock.

0: Do not use.

0x1-0xF: Hold = (SPI_SETUP + 1) * 40ns.

For example, default setting of 2 will result in 120ns data setup time.

97 0x61 SPI_TIMING2 7:4 Reserved.

3:0 RW 0x00 SPI_SS_SETU SPI Slave Select Setup: This field controls the delay from assertion of the Slave Select

P low to initial data timing. Delays are in units of 40ns.

Delay = (SPI_SS_SETUP + 1) * 40ns.

98 0x62 SPI_CONFIG 7:2 Reserved.

1 R 0x00 SPI_CPHA SPI Clock Phase setting: Determines which phase of the SPI clock is used for sampling

data.

0: Data sampled on leading (first) clock edge.

1: Data sampled on trailing (second) clock edge.

This bit is read-only, with a value of 0. There is no support for CPHA of 1.

0 RW SPI_CPOL SPI Clock Polarity setting: Determines the base (inactive) value of the SPI clock.

0: base value of the clock is 0.

1: base value of the clock is 1.

This bit affects both capture and propagation of SPI signals.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

100 0x64 Pattern 7:4 RW 0x10 Pattern Fixed Pattern Select

Generator Generator Selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly

Control Select distributed across the horizontal or vertical active regions. This field is ignored when

Auto-Scrolling Mode is enabled.

xxxx: normal/inverted.

0000: Checkerboard.

0001: White/Black (default).

0010: Black/White.

0011: Red/Cyan.

0100: Green/Magenta.

0101: Blue/Yellow.

0110: Horizontal Black-White/White-Black.

0111: Horizontal Black-Red/White-Cyan.

1000: Horizontal Black-Green/White-Magenta.

1001: Horizontal Black-Blue/White-Yellow.

1010: Vertical Black-White/White-Black.

1011: Vertical Black-Red/White-Cyan.

1100: Vertical Black-Green/White-Magenta.

1101: Vertical Black-Blue/White-Yellow.

1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers.

1111: VCOM.

See TI App Note AN-2198.

3Reserved.

2 RW Color Bars Enable color bars:

Pattern 0: Color Bars disabled (default).

1: Color Bars enabled.

Overrides the selection from reg_0x64[7:4].

1 RW VCOM Pattern Reverse order of color bands in VCOM pattern:

Reverse 0: Color sequence from top left is (YCBR) (default).

1: Color sequence from top left is (RBCY).

0 RW Pattern Pattern Generator enable:

Generator 0: Disable Pattern Generator (default).

Enable 1: Enable Pattern Generator.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

101 0x65 Pattern 7 0x00 Reserved.

Generator 6 RW Checkerboard Scale Checkered Patterns:

Configuration Scale 0: Normal operation (each square is 1x1 pixel) (default).

1: Scale checkered patterns (VCOM and checkerboard) by 8 (each square is 8x8 pixels).

Setting this bit gives better visibility of the checkered patterns.

5 RW Custom Use Custom Checkerboard Color:

Checkerboard 0: Use white and black in the Checkerboard pattern (default).

1: Use the Custom Color and black in the Checkerboard pattern.

4 RW PG 18–bit 18-bit Mode Select:

Mode 0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness

(default).

1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of

brightness and the R, G, and B outputs use the six most significant color bits.

3 RW External Clock Select External Clock Source:

0: Selects the internal divided clock when using internal timing (default).

1: Selects the external pixel clock when using internal timing.

This bit has no effect in external timing mode (PATGEN_TSEL = 0).

2 RW Timing Select Timing Select Control:

0: The Pattern Generator uses external video timing from the pixel clock, Data Enable,

Horizontal Sync, and Vertical Sync signals (default).

1: The Pattern Generator creates its own video timing as configured in the Pattern

Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync

Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.

See TI App Note AN-2198.

1 RW Color Invert Enable Inverted Color Patterns:

0: Do not invert the color output (default).

1: Invert the color output.

See TI App Note AN-2198.

0 RW Auto Scroll Auto Scroll Enable:

0: The Pattern Generator retains the current pattern (default).

1: The Pattern Generator will automatically move to the next enabled pattern after the

number of frames specified in the Pattern Generator Frame Time (PGFT) register.

See TI App Note AN-2198.

102 0x66 PGIA 7:0 RW 0x00 PG Indirect This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It

Address should be written prior to reading or writing the Pattern Generator Indirect Data register.

See TI App Note AN-2198

103 0x67 PGID 7:0 RW 0x00 PG Indirect When writing to indirect registers, this register contains the data to be written. When

Data reading from indirect registers, this register contains the read back value.

See TI App Note AN-2198

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

112 0x70 Slave ID[1] 7:1 RW 0x00 Slave ID 1 7-bit I2C address of the remote Slave 1 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 1, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 1.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

0Reserved.

113 0x71 Slave ID[2] 7:1 RW 0x00 Slave ID 2 7-bit I2C address of the remote Slave 2 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 2, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 2.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

0Reserved.

114 0x72 Slave ID[3] 7:1 RW 0x00 Slave ID 3 7-bit I2C address of the remote Slave 3 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 3, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 3.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

0Reserved.

115 0x73 Slave ID[4] 7:1 RW 0x00 Slave ID 4 7-bit I2C address of the remote Slave 4 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 4, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 4.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

0Reserved.

116 0x74 Slave ID[5] 7:1 RW 0x00 Slave ID 5 7-bit I2C address of the remote Slave 5 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 5, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 5.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

0Reserved.

117 0x75 Slave ID[6] 7:1 RW 0x00 Slave ID 6 7-bit I2C address of the remote Slave 6 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 6, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 6.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

0Reserved.

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SNLS452 –NOVEMBER 2014

Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

118 0x76 Slave ID[7] 7:1 RW 0x00 Slave ID 7 7-bit I2C address of the remote Slave 7 attached to the remote Deserializer. If an I2C

Port0/Port1 transaction is addressed to Slave Alias ID 7, the transaction will be remapped to this

address before passing the transaction across the Bidirectional Control Channel to the

Deserializer. A value of 0 in this field disables access to the remote Slave 7.

If PORT1_SEL is set, this register controls Port 1 Slave ID.

0Reserved.

119 0x77 Slave Alias[1] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 1 attached to the remote Deserializer. The

1 transaction will be remapped to the address specified in the Slave ID 1 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 1.

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

0Reserved.

120 0x78 Slave Alias[2] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 2 attached to the remote Deserializer. The

2 transaction will be remapped to the address specified in the Slave ID 2 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 2.

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

0Reserved.

121 0x79 Slave Alias[3] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 3 attached to the remote Deserializer. The

3 transaction will be remapped to the address specified in the Slave ID 3 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 3.

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

0Reserved.

122 0x7A Slave Alias[4] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 4 attached to the remote Deserializer. The

4 transaction will be remapped to the address specified in the Slave ID 4 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 4.

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

0Reserved.

123 0x7B Slave Alias[5] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 5 attached to the remote Deserializer. The

5 transaction will be remapped to the address specified in the Slave ID 5 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 5.

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

0Reserved.

124 0x7C Slave Alias[6] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 6 attached to the remote Deserializer. The

6 transaction will be remapped to the address specified in the Slave ID 6 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 6.

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

0Reserved.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

125 0x7D Slave Alias[7] 7:1 RW 0x00 Slave Alias ID 7-bit Slave Alias ID of the remote Slave 7 attached to the remote Deserializer. The

7 transaction will be remapped to the address specified in the Slave ID 7 register. A value

Port0/Port1 of 0 in this field disables access to the remote Slave 7.

If PORT1_SEL is set, this register controls Port 1 Slave Alias.

0Reserved.

198 0xC6 ICR 7 RW 0x00 IE_IND_ACC Interrupt on Indirect Access Complete: Enables interrupt on completion of Indirect

6 RW IE_RXDET_IN Interrupt on Receiver Detect: Enables interrupt on detection of a downstream Receiver.

5 RW IE_RX_INT Interrupt on Receiver interrupt: Enables interrupt on indication from the Receiver. Allows

propagation of interrupts from downstream devices.

4 RW IE_LIST_RDY Interrupt on KSV List Ready: Enables interrupt on KSV List Ready.

3 RW IE_KSV_RDY Interrupt on KSV Ready: Enables interrupt on KSV Ready.

2 RW IE_AUTH_FAI Interrupt on Authentication Failure: Enables interrupt on authentication failure or loss of

L authentication.

1 RW IE_AUTH_PAS Interrupt on Authentication Pass: Enables interrupt on successful completion of

S authentication.

0 RW INT_EN Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller.

199 0xC7 ISR 7 R 0x00 IS_IND_ACC Interrupt on Indirect Access Complete: Indirect Register Access has completed.

6 R IS_RXDET_IN Interrupt on Receiver Detect interrupt: A downstream receiver has been detected.

5 R IS_RX_INT Interrupt on Receiver interrupt: Receiver has indicated an interrupt request from down-

stream device.

4 R IS_LIST_RDY Interrupt on KSV List Ready: The KSV list is ready for reading by the controller.

3 R IS_KSV_RDY Interrupt on KSV Ready: The Receiver KSV is ready for reading by the controller.

2 R IS_AUTH_FAI Interrupt on Authentication Failure: Authentication failure or loss of authentication has

L occurred.

1 R IS_AUTH_PAS Interrupt on Authentication Pass: Authentication has completed successfully.

0 R INT Global Interrupt: Set if any enabled interrupt is indicated.

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Table 10. Serial Control Bus Registers (continued)

ADD ADD Register Default

(dec) (hex) Type (hex)

240 0xF0 TX ID 7:0 R 0x5F ID0 First byte ID code: "_".

241 0xF1 7:0 R 0x55 ID1 Second byte of ID code: "U".

242 0xF2 7:0 R 0x42 ID2 Third byte of ID code: "B".

243 0xF3 7:0 R 0x39 ID3 Fourth byte of ID code: "9".

244 0xF4 7:0 R 0x34 ID4 Fifth byte of ID code: "4".

245 0xF5 7:0 R 0x39 ID5 Sixth byte of ID code: “9”.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Applications Information

The DS90UB949-Q1, in conjunction with the DS90UB940-Q1/DS90UB948-Q1 deserializer, is intended to

interface between a host (graphics processor) and a display, supporting 24-bit color depth (RGB888) and high

definition (1080p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 170 MHz

together with four I2S audio streams when paired with the DS90UB940-Q1/DS90UB948-Q1 deserializer.

9.2 Typical Applications

Bypass capacitors should be placed near the power supply pins. A capacitor and resistor are placed on the PDB

pin to delay the enabling of the device until power is stable. See below for typical STP and coax connection

diagrams.

Product Folder Links: DS90UB949-Q1

VDD18

VDDIO

VDDHS11

VDDS11VDDL11

VDDHA11

VDDHS11

IN_CLK+

IN_CLK-

IN_D0+

IN_D0-

IN_D1+

IN_D1-

IN_D2+

IN_D2-

RX_5V

HPD

DDC_SDA

DDC_SCL

CEC

I2S_WC

I2S_CLK

I2S_DA

I2S_DB

I2S_DC

I2S_DD

PDB

NC0

NC1

VDDL11

DAP

1.1V1.8V

1.1V

1.8V

TMDS

(DC coupled)

HDMI Control

I2S Audio

Hot Plug Detect

FB1

FB2

FB3

FB4

>10µF

10k

27k 47k 47k

3.3V

VTERM

3.3V (DC coupled)/1.8V (AC coupled)

FB5

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

1µF

DOUT0+

DOUT0-

DOUT1+

DOUT1-

LFT

RES2

MODE_SEL0

IDx

MODE_SEL1

SDA

SCL

MOSI

MISO

SPLK

SCLK

SWC

SDIN

MCLK

INTB

1.8V

Aux Audio

I2C

SPI

FPD-Link III

VDD18

(Filtered 1.8V)

10nF

R2 R3

R4 R5

4.7k 4.7k 4.7k

VDDA11

VDDP11

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

NOTE:

FB1,FB5: DCR<=0.3Ohm; Z=1Kohm@100MHz

FB2-FB4: DCR<=25mOhm; Z=120ohm@100MHz

C1-C4 = 0.1µF (50 WV; 0402) with DS90UB926/928

C1-C4 = 0.033µF (50 WV; 0402) with DS90UB940/948

R1 ± R2 (see IDx Resistor Values Table)

R3 ± R6 (see MODE_SEL Resistor Values Table)

VDDI2C = Pull up voltage of I2C bus. Refer to I2CSEL pin

description for 1.8V or 3.3V operation.

10µF 1µF

float

0.1µF

Controller (Optional)

10µF 1µF 0.1µF

0.1µF

1µF 10µF0.1µF

DS90UB949-Q1

RES1

Interrupts

REF CLKIN

VDD18

(Filtered 1.8V)

RES0

VDDI2C

NC2float

REM_INTB

4.7k

DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

Typical Applications (continued)

Figure 25. Typical Application Connection -- STP

Product Folder Links: DS90UB949-Q1

VDD18

VDDIO

VDDHS11

VDDS11VDDL11

VDDHA11

VDDHS11

IN_CLK+

IN_CLK-

IN_D0+

IN_D0-

IN_D1+

IN_D1-

IN_D2+

IN_D2-

RX_5V

HPD

DDC_SDA

DDC_SCL

CEC

I2S_WC

I2S_CLK

I2S_DA

I2S_DB

I2S_DC

I2S_DD

PDB

NC0

NC1

VDDL11

DAP

1.1V1.8V

1.1V

1.8V

TMDS

(DC coupled)

HDMI Control

I2S Audio

Hot Plug Detect

FB1

FB2

FB3

FB4

>10µF

10k

27k 47k 47k

3.3V

VTERM

3.3V (DC coupled)/1.8V (AC coupled)

FB5

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

1µF

DOUT0+

DOUT0-

DOUT1+

DOUT1-

LFT

RES2

MODE_SEL0

IDx

MODE_SEL1

SDA

SCL

MOSI

MISO

SPLK

SCLK

SWC

SDIN

MCLK

INTB

1.8V

Aux Audio

I2C

SPI

FPD-Link III

VDD18

(Filtered 1.8V)

10nF

R2 R3

R4 R5

4.7k 4.7k 4.7k

VDDA11

VDDP11

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

0.01µF

- 0.1µF

NOTE:

FB1,FB5: DCR<=0.3Ohm; Z=1Kohm@100MHz

FB2-FB4: DCR<=25mOhm; Z=120ohm@100MHz

C1,C3 = 0.033µF (50 WV; 0402)

C2,C4 = 0.015µF (50 WV; 0402)

R1 ± R2 (see IDx Resistor Values Table)

R3 ± R6 (see MODE_SEL Resistor Values Table)

VDDI2C = Pull up voltage of I2C bus. Refer to I2CSEL pin

description for 1.8V or 3.3V operation.

10µF 1µF

float

0.1µF

Controller (Optional)

10µF 1µF 0.1µF

0.1µF

1µF 10µF0.1µF

DS90UB949-Q1

RES1

Interrupts

REF CLKIN

VDD18

(Filtered 1.8V)

RES0

VDDI2C

NC2float

REM_INTB

4.7k

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

www.ti.com

Typical Applications (continued)

Figure 26. Typical Application Connection -- Coax

Product Folder Links: DS90UB949-Q1

DOUT-

DOUT+

SER

RIN-

RIN+

DES

50Q50Q

DOUT-

DOUT+

SER

RIN-

RIN+

DES

FPD-Link III

2 Lane

VDDIO

1.8V

IDx

DOUT0+

DOUT0-

1.1V

IN_CLK-/+

HDMI

HPD

DDC

CEC

DOUT1+

DOUT1-

RIN0+

RIN0-

RIN1+

RIN1-

CLK+/-

CLK2+/-

FPD-Link

(Open LDI)

D0+/-

D1+/-

D2+/-

D3+/-

D4+/-

D5+/-

D6+/-

D7+/-

DS90UB949-Q1

Serializer DS90UB948-Q1

Deserializer

IDx

D_GPIO

(SPI)

D_GPIO

(SPI)

LVDS

Display

1080p60

or Graphic

Processor

Graphics

Processor

IN_D0-/+

IN_D1-/+

IN_D2-/+

I2C

VDDIO

(3.3V / 1.8V)

3.3V

I2C

1.2V1.8V

HDMI ± High Definition Multimedia Interface

DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

Typical Applications (continued)

Figure 27. Typical System Diagram

9.2.1 Design Requirements

The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.

External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in

Figure 28.

Table 11. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

VDDIO 1.8V

AC Coupling Capacitor for DOUT0± and DOUT1± with 92x 100nF

deserializers

AC Coupling Capacitor for DOUT0± and DOUT1± with 94x 33nF

deserializers

For applications utilizing single-ended 50Ωcoaxial cable, the unused data pins (DOUT0-, DOUT1-) should utilize

a 15nF capacitor and should be terminated with a 50Ωresistor.

Figure 28. AC-Coupled Connection (STP)

Figure 29. AC-Coupled Connection (Coaxial)

For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling

capacitor. This will help minimize degradation of signal quality due to package parasitics.

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9.2.2 Detailed Design Procedure

9.2.2.1 High Speed Interconnect Guidelines

See AN-1108 and AN-905 for full details.

• Use 100Ωcoupled differential pairs

• Use the S/2S/3S rule in spacings

– S = space between the pair

– 2S = space between pairs

– 3S = space to LVCMOS signal

• Minimize the number of Vias

• Use differential connectors when operating above 500Mbps line speed

• Maintain balance of the traces

• Minimize skew within the pair

• Terminate as close to the TX outputs and RX inputs as possible

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas

Instruments web site at: LVDS Owner's Manual.

9.2.3 Application Curves

9.2.3.1 Application Performance Plots

Figure 30 corresponds to 1080p60 video application with 2-lane FPD-Link III output. Figure 31 corresponds to

3.36Gbps single-lane output from 96MHz input TMDS clock.

Figure 30. 1080p60 Video at 2.6 Gbps Serial Line Rate Figure 31. Serializer Output at 3.36Gbps (96MHz TMDS

(One of Two Lanes) Clock)

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SNLS452 –NOVEMBER 2014

10 Power Supply Recommendations

This device provides separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. The Pin Functions table provides guidance on which circuit blocks are connected to which power pins.

In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.

10.1 Power Up Requirements And PDB Pin

The power supply ramp should be faster than 1.5ms with a monotonic rise. A large capacitor on the PDB pin is

needed to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage.

When PDB pin is pulled up to VDDIO, a 10kΩpull-up and a >10μF capacitor to GND are required to delay the

PDB input signal rise. All inputs must not be driven until all power supplies have reached steady state.

The recommended power up sequence is as follows: VTERM, VDD18, VDD11, wait until all supplies have settled,

activate PDB, then apply HDMI input.

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11 Layout

11.1 Layout Guidelines

Circuit board layout and stack-up for the LVDS serializer and deserializer devices should be designed to provide

low-noise power to the device. Good layout practice will also separate high frequency or high-level inputs and

outputs to minimize unwanted stray noise, feedback and interference. Power system performance may be greatly

improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes the plane

capacitance for the PCB power system and has low-inductance, which has proven effectiveness especially at

high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass

capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the

range of 0.01μF to 10μF. Tantalum capacitors may be in the 2.2μF to 10μF range. The voltage rating of the

tantalum capacitors should be at least 5X the power supply voltage being used.

MLCC surface mount capacitors are recommended due to their smaller parasitic properties. When using multiple

capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at

the point of power entry. This is typically in the 50μF to 100μF range and will smooth low frequency switching

noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass

capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an

external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as

0603 or 0805, is recommended for external bypass. A small body sized capacitor has less inductance. The user

must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of

20MHz-30MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance

between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use

two vias from power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate

switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not

required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power

pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as

PLLs. For DS90UB949-Q1, only one common ground plane is required to connect all device related ground pins.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS

lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100Ωare

typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will

appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.

At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device

ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB

ground plane. More information on the LLP style package, including PCB design and manufacturing

requirements, is provided in TI Application Note: AN-1187.

Product Folder Links: DS90UB949-Q1

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SNLS452 –NOVEMBER 2014

11.2 Layout Example

Figure 32 is derived from a layout design of the DS90UB949-Q1. This graphic is used to demonstrate proper

high-speed routing when designing in the Serializer.

Figure 32. DS90UB949-Q1 Serializer Layout Example

Product Folder Links: DS90UB949-Q1

DS90UB949-Q1

SNLS452 –NOVEMBER 2014

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•Soldering Specifications Application Report, SNOA549

•IC Package Thermal Metrics Application Report, SPRA953

•Channel-Link PCB and Interconnect Design-In Guidelines, SNLA008

•Transmission Line RAPIDESIGNER Operation and Application Guide, SNLA035

•Leadless Leadframe Package (LLP) Application Report, SNOA401

•LVDS Owner's Manual, SNLA187

•I2C Communication Over FPD-Link III with Bidirectional Control Channel, SNLA131A

•Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices, SNLA221

•Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices, SNLA132

12.2 Trademarks

TRI-STATE is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: DS90UB949-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 5-Jan-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90UB949TRGCRQ1 ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 UB949Q

DS90UB949TRGCTQ1 ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 UB949Q

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 5-Jan-2015

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90UB949TRGCRQ1 VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

DS90UB949TRGCTQ1 VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 9-May-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90UB949TRGCRQ1 VQFN RGC 64 2000 367.0 367.0 38.0

DS90UB949TRGCTQ1 VQFN RGC 64 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 9-May-2018

Pack Materials-Page 2

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DS90UB949TRGCRQ1 DS90UB949TRGCTQ1