1
Data sheet acquired from Harris Semiconductor
SCHS154D
The CD54HCT161 is obsolete
and no longer is supplied.
Features
• ’HC161, ’HCT161 4-Bit Binary Counter,
Asynchronous Reset
• ’HC163, ’HCT163 4-Bit Binary Counter,
Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC161, ’HCT161, ’HC163, and ’HCT163 are
presettable synchronous counters that feature look-ahead
carry logic for use in high-speed counting applications. The
’HC161 and ’HCT161 are asynchronous reset decade and
binary counters, respectively; the ’HC163 and ’HCT163
devices are decade and binary counters, respectively, that
are reset synchronously with the clock. Counting and
parallel presetting are both accomplished synchronously
with the negative-to-positive transition of the clock.
A low level on the synchronous parallel enable input, SPE,
disables counting operation and allows data at the P0 to P3
inputs to be loaded into the counter (provided that the
setup and hold requirements for SPE are met).
All counters are reset with a low level on the Master Reset
input, MR. In the ’HC163 and ’HCT163 counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
Two count enables, PE and TE, in each counter are
provided for n-bit cascading. In all counters reset action
occurs regardless of the level of the SPE, PE and TE inputs
(and the clock input, CP, in the ’HC161 and ’HCT161
types).
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC161F3A -55 to 125 16 Ld CERDIP
CD54HC163F3A -55 to 125 16 Ld CERDIP
CD54HCT163F3A -55 to 125 16 Ld CERDIP
CD74HC161E -55 to 125 16 Ld PDIP
CD74HC161M -55 to 125 16 Ld SOIC
CD74HC161MT -55 to 125 16 Ld SOIC
CD74HC161M96 -55 to 125 16 Ld SOIC
CD74HC163E -55 to 125 16 Ld PDIP
CD74HC163M -55 to 125 16 Ld SOIC
CD74HC163MT -55 to 125 16 Ld SOIC
CD74HC163M96 -55 to 125 16 Ld SOIC
CD74HCT161E -55 to 125 16 Ld PDIP
CD74HCT161M -55 to 125 16 Ld SOIC
CD74HCT161MT -55 to 125 16 Ld SOIC
CD74HCT161M96 -55 to 125 16 Ld SOIC
CD74HCT163E -55 to 125 16 Ld PDIP
CD74HCT163M -55 to 125 16 Ld SOIC
CD74HCT163MT -55 to 125 16 Ld SOIC
CD74HCT163M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54/74HC161, CD54/74HCT161,
CD54/74HC163, CD54/74HCT163
High-Speed CMOS Logic
Presettable Counters
[ /Title
(CD74
HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs,
High
Speed
2
Pinout
CD54HC161, CD54HCT161, CD54HC163, CD54HCT163
(CERDIP)
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
(PDIP, SOIC)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
MR
CP
P0
P1
P2
P3
GND
PE
VCC
Q0
Q1
Q2
Q3
TE
SPE
TC
SPE
CP
MR
PE
TE
9
2
1
7
10
3456
14
13
12
11
15
Q0
Q1
Q2
Q3
TC
P0 P1 P2 P3
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
3
MODE SELECT - FUNCTION TABLE FOR ’HC161 AND ’HCT161
OPERATING MODE
INPUTS OUTPUTS
MR CP PE TE SPE PnQnTC
Reset (Clear) L XXXXXLL
Parallel Load H ↑XX l l LL
H↑X X l h H (Note 1)
Count H ↑h h h (Note 3) X Count (Note 1)
Inhibit H X I (Note 2) X h (Note 3) X qn(Note 1)
H X X I (Note 2) h (Note 3) X qnL
MODE SELECT - FUNCTION TABLE FOR ’HC163 AND ’HCT163
OPERATING MODE
INPUTS OUTPUTS
MR CP PE TE SPE PnQnTC
Reset (Clear) l ↑XXXXLL
Parallel Load h (Note 3) ↑XX l l LL
h (Note 3) ↑X X l h H (Note 1)
Count h (Note 3) ↑h h h (Note 3) X Count (Note 1)
Inhibit h (Note 3) X I (Note 2) X h (Note 3) X qn(Note 1)
h (Note 3) X X I (Note 2) h (Note 3) X qnL
H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock
transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate the
state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and ’HC/HCT163).
2. The High-to-Low transition of PE or TE on the ’HC/HCT161 and the ’HC/HCT163 should only occur while CP is HIGH for conventional
operation.
3. The Low-to-High transition of SPE on the ’HC/HCT161 and SPE or MR on the ’HC/HCT163 should only occur while CP is HIGH for
conventional operation.
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 4) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
4. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
5
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 5) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
5. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
P0 - P3 0.25
PE 0.65
CP 1.05
MR 0.8
SPE 0.5
TE 1.05
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
6
Prerequisite For Switching Specifications
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Maximum CP Frequency
(Note 6) fMAX - 2 6 - - 5 - 4 - MHz
4.5 30 - - 24 - 20 - MHz
6 35 - - 28 - 24 - MHz
CP Width (Low) tW(L) - 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
MR Pulse Width (161) tW- 2 100 - - 125 - 150 - ns
4.5 20 - - 25 - 30 - ns
6 17 - - 21 - 26 - ns
Setup Time, Pn to CP tSU - 2 60 - - 75 - 90 - ns
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns
Setup Time, PE or TE to CP tSU - 2 50 - - 65 - 75 - ns
4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns
Setup Time, SPE to CP tSU - 2 60 - - 75 - 90 - ns
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns
Setup Time, MR to CP (163) tSU - 2 65 - - 80 - 100 - ns
4.5 13 - - 16 - 20 - ns
6 11 - - 14 - 17 - ns
Hold Time, PN to CP tH-23--3-3-ns
4.5 3 - - 3 - 3 - ns
63--3-3-ns
Hold Time, TE or PE to CP tH-20--0-0-ns
4.5 0 - - 0 - 0 - ns
60--0-0-ns
Hold Time, SPE to CP tH-20--0-0-ns
4.5 0 - - 0 - 0 - ns
60--0-0-ns
Recovery Time, MR to CP (161) tREC - 2 75 - - 95 - 110 - ns
4.5 15 - - 19 - 22 - ns
6 13 - - 16 - 19 - ns
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
7
HCT TYPES
Maximum CP Frequency fMAX - 4.5 30 - - 24 - 20 - MHz
CP Width (Low) (Note 6) tW(L) - 4.5 16 - - 20 - 24 - ns
MR Pulse Width (161) tW- 4.5 20 - - 25 - 30 - ns
Setup Time, Pn to CP tSU - 4.5 10 - - 13 - 15 - ns
Setup Time, PE or TE to CP tSU - 4.5 13 - - 16 - 20 - ns
Setup Time, SPE to CP tSU - 4.5 12 - - 15 - 18 - ns
Setup Time, MR to CP (163) tSU - 4.5 13 - - 16 - 20 - ns
Hold Time, PN to CP tH- 4.5 5 - - 5 - 5 - ns
Hold Time, TE or PE to CP tH- 4.5 3 - - 3 - 3 - ns
Hold Time, SPE to CP tH- 4.5 3 - - 3 - 3 - ns
Recovery Time, MR to CP (161) tREC - 4.5 15 - - 19 - 22 - ns
NOTE:
6. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)-
to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC
devices:
Switching Specifications CL = 50pF, Input tr, tf= 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPHL, tPLH CL = 50pF
CP to TC 2 - - 185 - 230 - 280 ns
4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 15 - - - - - ns
CL = 50pF 6 - - 31 - 39 - 48 ns
CP to Qn tPHL, tPLH CL = 50pF 2 - - 185 - 230 - 280 ns
4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 15 - - - - - ns
CL = 50pF 6 - - 31 - 39 - 48 ns
TE to TC tPHL, tPLH CL = 50pF 2 - - 120 - 150 - 180 ns
4.5 - - 24 - 30 - 36 ns
CL = 15pF 5 - 9 - - - - - ns
CL = 50pF 6 - - 20 - 26 - 31 ns
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
fMAX (CP)
1
CP-to-TC prop. delay TE-to-CP setup TE-to-CP Hold++
-----------------------------------------------------------------------------------------------------------------------------------------------------
1
37 10 0++
-----------------------------21MHz min()≈==
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
8
MR to Qn (161) tPHL CL = 50pF 2 - - 210 - 265 - 315 ns
4.5 - - 42 - 53 - 63 ns
CL = 15pF 5 - 18 - - - - - ns
CL = 50pF 6 - - 36 - 45 - 54 ns
MR to TC (161) tPHL CL = 50pF 2 - - 210 - 265 - 315 ns
4.5 - - 42 - 53 - 63 ns
CL = 50pF 6 - - 36 - 45 - 54 ns
Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Power Dissipation Capacitance
(Notes 7, 8) CPD -5-60-----pF
Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF
HCT TYPES
Propagation Delay
CP to TC tPHL, tPLH CL = 50pF 4.5 - - 42 - 53 - 63 ns
CL = 15pF 5 - 18 - - - - - ns
CP to Qn tPHL, tPLH CL = 50pF 4.5 - - 39 - 49 - 59 ns
CL = 15pF 5 - 16 - - - - - ns
TE to TC tPHL, tPLH CL = 50pF 4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - - - - - ns
MR to Qn (161) tPHL CL = 50pF 4.5 - - 50 - 63 - 75 ns
CL = 15pF 5 - 21 - - - - - ns
MR to TC (161) tPHL CL = 50pF 4.5 - - 50 - 63 - 75 ns
Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns
Power Dissipation Capacitance
(Notes 7, 8) CPD -5-63-----pF
Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF
NOTES:
7. CPD is used to determine the dynamic power consumption, per package.
8. PD=C
PD VCC2fi+∑(CLVCC2fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
9
Timing Diagram
Sequence illustrated on waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
MASTER RESET (161)
MASTER RESET (163)
SPE
P0
P1
P2
P3
PRESET
DATA
CP (161)
CP (163)
PE
TE
COUNT
ENABLES
Q0
Q1
Q2
Q3
OUTPUTS
TC
RESET PRESET COUNT INHIBIT
(ASYNCHRONOUS)
(SYNCHRONOUS)
12 13 14 15 0 1 2
INPUTS
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
10
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54HC161F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC161F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC163F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HCT161F3A OBSOLETE CDIP J 16 TBD Call TI Call TI
CD54HCT163F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HCT163F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74HC161E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC161EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC161M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC161MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC163EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC163M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC163MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD74HC163MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT161EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT161M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT161MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT163EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT163M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT163MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC161M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC163M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT161M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT163M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC161M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC163M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT161M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT163M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
