1. General description
The 74AHC125-Q100; 74AHCT125-Q100 is a high-speed Si-gate CMOS de vice and is
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard JESD7-A.
The 74AHC125-Q100; 74AHCT125-Q100 provides four non-inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input
(nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125-Q100; 74AHCT125-Q100 is identical to the 74AHC126-Q100;
74AHCT126- Q1 0 0 but ha s active LOW enable inpu ts.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt trigger action
Inputs accept voltages higher tha n VCC
For 74AHC125-Q100: CMOS input levels
For 74AHCT125-Q100: TTL input levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Multiple package options
74AHC125-Q100;
74AHCT125-Q100
Quad buffer/line driver; 3-state
Rev. 1 — 5 June 2012 Product data sheet
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 2 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Tempe rature range Name Description Version
74AHC125D-Q100 40 Cto+125C S O14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74AHCT125D-Q100
74AHC125PW-Q100 40 Cto+125C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74AHCT125PW-Q100
74AHC125BQ-Q100 40 Cto+125C DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 30.85 mm
SOT762-1
74AHCT125BQ-Q100
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer)
mna228
1A 1Y
2
1
3
1OE
2A 2Y
5
4
6
2OE
3A 3Y
9
10
8
3OE
4A 4Y
12
13
11
4OE
mna229
1EN1
13
2
46
5
10 8
9
13 11
12
mna227
nOE
nA nY
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 3 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14
74AHC125-Q100
74AHCT125-Q100
1OE V
CC
1A 4OE
1Y 4A
2OE 4Y
2A 3OE
2Y 3A
GND 3Y
aaa-003138
1
2
3
4
5
6
78
10
9
12
11
14
13
aaa-003139
74AHC125-Q100
74AHCT125-Q100
Transparent top view
2Y 3A
2A 3OE
2OE 4Y
1Y 4A
1A 4OE
GND
3Y
1OE
VCC
6 9
510
411
312
213
7
8
1
14
terminal 1
index area
GND(1)
Table 2. Pin description
Symbol Pin Description
1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 output enable input (active LOW)
1A, 2A, 3A, 4A 2, 5, 9, 12 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage
Table 3. Function table[1]
Control Input Output
nOE nA nY
LLL
HH
HXZ
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 4 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
[4] Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V [1] 20 - mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput curren t VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - 75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO14 package [2] - 500 mW
TSSOP14 package [3] - 500 mW
DHVQFN14 package [4] - 500 mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74AHC125-Q100 74AHCT125-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 0 - 5.5 V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate VCC = 3.3 V 0.3 V - - 100 - - - ns/V
VCC = 5.0 V 0.5 V - - 20 - - 20 ns/V
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 5 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
9. Static characteristics
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74AHC125-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1 .5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0 .5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0 .9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO= 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO= 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO= 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO= 8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
IOZ OFF-state
output current VI =V
IH or VIL;
VO=V
CC or GND;
VCC =5.5V
--0.25 - 2.5 - 10.0 A
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC =5.5V --2.0- 20 - 40A
CIinput
capacitance - 3.0 10 - 10 - 10 pF
COoutput
capacitance -4.0- - - - - pF
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 6 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
74AHCT125-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A 4.4 4.5 - 4.4 - 4.4 - V
IO= 8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IOZ OFF-state
output current per input pin; VI =V
IH or VIL;
VCC =5.5V; I
O=0 A
VO=V
CC or GND;
other pins at VCC or GND
--0.25 - 2.5 - 10.0 A
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC =5.5V --2.0- 20 - 40A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; IO=0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
--1.35- 1.5 - 1.5mA
CIinput
capacitance - 3.0 10 - 10 - 10 pF
COoutput
capacitance -4.0- - - - - pF
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 7 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
10. Dynamic characteristics
Table 7. Dynam ic characteristics
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74AHC125-Q100
tpd propagation
delay nA to nY; see Figure 6 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 4.4 8.0 1.0 9.5 1.0 11.5 ns
CL= 50 pF - 6.2 11.5 1.0 13.0 1.0 14.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.0 5.5 1.0 6.5 1.0 7.0 ns
CL= 50 pF - 4.3 7.5 1.0 8.5 1.0 9.5 ns
ten enable time nOE to nY; see Figure 7 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 4.7 8.0 1.0 9.5 1.0 11.5 ns
CL= 50 pF - 6.8 11.5 1.0 13.0 1.0 14.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.3 5.1 1.0 6.0 1.0 6.5 ns
CL= 50 pF - 4.7 7.1 1.0 8.0 1.0 9.0 ns
tdis disable time nOE to nY; see Figure 7 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 6.7 9.7 1.0 11.5 1.0 12.5 ns
CL= 50 pF - 9.6 13.2 1.0 15.0 1.0 16.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.8 6.8 1.0 8.0 1.0 8.5 ns
CL= 50 pF - 6.8 8.8 1.0 10.0 1.0 11.0 ns
CPD power
dissipation
capacitance
CL=50pF; f
i = 1 MHz;
VI=GNDtoV
CC
[3] -10- - - - -pF
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 8 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz, fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs.
11. Waveforms
74AHCT125-Q100
tpd propagation
delay nA to nY; see Figure 6 [2]
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.0 5.5 1.0 6.5 1.0 7.0 ns
CL= 50 pF - 4.3 7.5 1.0 8.5 1.0 9.5 ns
ten enable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.4 5.1 1.0 6.0 1.0 6.5 ns
CL= 50 pF - 4.9 7.3 1.0 8.3 1.0 9.5 ns
tdis disable time nOE to nY; see Figure 7 [2]
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.5 6.8 1.0 8.0 1.0 8.5 ns
CL= 50 pF - 6.5 8.8 1.0 10.0 1.0 11.0 ns
CPD power
dissipation
capacitance
CL=50pF; f
i = 1 MHz;
VI=GNDtoV
CC
[3] -12- - - - -pF
Table 7. Dynam ic characteristics …continued
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay input (nA) to output (nY)
mna230
t
PHL
t
PLH
V
M
V
M
nA input
nY output
GND
V
I
V
OH
V
OL
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 9 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Enable an d disable times
mna362
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Type Input Output
VMVMVXVY
74AHC125-Q100 0.5VCC 0.5VCC VOL + 0.3 V VOL 0.3 V
74AHCT125-Q100 1.5 V 0.5VCC VOL + 0.3 V VOL 0.3 V
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 10 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74AHC125-Q100 VCC 3.0 ns 15 pF, 50 pF 1 kopen GND VCC
74AHCT125-Q100 3.0 V 3.0 ns 15 pF, 50 pF 1 kopen GND VCC
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 11 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
12. Package outline
Fig 9. Package outline SOT108-1 (SO14)
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 12 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
Fig 10. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 13 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
Fig 11. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
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Product data sheet Rev. 1 — 5 June 2012 14 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
LSTTL Low-power Schottky Transistor-Transistor Logic
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
CDM Charge-Device Model
TTL Transistor-Transistor Logic
MIL Military
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT125_Q100 v.1 20120605 Product data sheet - -
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 15 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, t he product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe propert y or environment al
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specifica tion.
74AHC_AHCT125_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 5 June 2012 16 of 17
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AHC125-Q100; 74AHCT125-Q100
Quad buffer/line driver; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 June 2012
Document identifier: 74 AHC_AHCT125_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16 Contact information. . . . . . . . . . . . . . . . . . . . . 16
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17