© Semiconductor Components Industries, LLC, 2019
January, 2020 − Rev. 1 1Publication Order Number:
FAN65004C/D
PWM Buck Regulator, High
Performance, Synchronous
Voltage Mode, 65 V, 6 A
FAN65004C
Description
FAN65004C is a wide VIN highly efficient synchronous buck
regulator, with integrated high side and low side power MOSFETs.
The device incorporates a fixed frequency voltage mode PWM
controller supporting a wide voltage range from 4.5 V to 65 V and can
handle continuous currents up to 6 A.
FAN65004C includes a 0.67% accurate reference voltage to achieve
tight regulation. The switching frequency can be programmed from
100 kHz to 1 MHz. To improve efficiency at light load condition, the
device can be set to discontinuous conduction mode with pulse
skipping operation.
FAN65004C has dual LDOs to minimize power loss and integrated
current sense circuit that provides cycle−by−cycle current limiting.
This single phase buck regulator offers complete protection features
including Over current protection, Thermal shutdown, Under−voltage
lockout, Over voltage protection, Under voltage protection and
Short−circuit protection.
FAN65004C uses ON Semiconductor’s high performance
PowerTrench® MOSFETs that reduces ringing in switching
applications. FAN65004C integrates the controller, driver, and power
MOSFETs into a thermally enhanced, compact 6 x 6 mm PQFN
package. With an integrated approach, the complete DC/DC converter
is optimized from the controller and driver to MOSFET switching
performance, delivering a high power density solution.
Features
•Wide Input Voltage Range: 4.5 V to 65 V
•Continuous Output Current: 6 A
•Fixed Frequency Voltage Mode PWM Control with Input Voltage
Feed−forward
•0.6 V Reference Voltage with 0.67% Accuracy
•Adjustable Switching Frequency: 100 kHz to 1 MHz
•Dual LDOs for Single Supply Operation and to Reduce
Power Loss
•Selectable CCM PWM Mode or PFM Mode for Light
Loads
•External Compensation for Wide Operation Range
•Adjustable Soft−Start & Pre−Bias Startup
•Enable Function with Adjustable Input Voltage
Under−Voltage−Lock−Out (UVLO)
•Power Good Indicator
•Over Current Protection, Thermal Shutdown, Over
Voltage Protection, Under Voltage Protection and
Short−circuit Protection
•High Performance Low Profile 6 mm x 6 mm PQFN
Package
•This Device is Pb−Free and RoHS Compliant
Applications
•High Voltage POL Module
•Telecommunications: Base Station Power Supplies
•Networking: Computing, Battery Management
Systems, USB−PD
•Industrial Equipment: Automation, Power Tools, Slot
Machines
PQFN35 6x6
CASE 483BE
MARKING DIAGRAM
www.onsemi.com
See detailed ordering and shipping information on page 23 o
f
this data sheet.
ORDERING INFORMATION
FAN
65004C
AWLYYWWG
1
FAN65004C = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
FAN65004C
www.onsemi.com
2
TYPICAL APPLICATION
Figure 1. Typical Application
L
R6
PWM Controller with Driver
C2 C3 C1
SW
VIN
EN /
UVLO
VIN
4.5 V~65 V
PH
BOOT
HVBIAS
C10
PGND
PVCC
R4
VCC
MODE
SS
RT
EXTBIAS
R10
R7
ILIM
AGND
R11
R9
C9
C8
C7
COMP
FB
VO
SYNC
PGOOD
R8
C6
R5
VCC
R3
C4
C5
R2 RBOOT
Table 1. APPLICATION DESIGN EXAMPLE
V
IN
(V)
V
O
(V)
L (
m
H)
L to be
used (mH
)
C
O
from
VO_RIPPLE
(mF)
C
O
from
VOS (mF
)
C
O
from
VUS (mF
)
C
O
to be
used
R10 (
W
)
R11
(W)
(W)
(W)
(F)
(F)
(F)
f
CO
(Hz)
Phase
margin
(⁰)
RT
(=R6) (W
)
35
24
16.762
22.00
2.6
30.9
65.2
75.2 28010
718.2
365 1.0k 2.7n 220n 470p
18.0k
69.4
3.75E+04
35
28
12.444
2.2
22.7
83.5
613.4
22.6k
67.5
35
30
9.524
2.1
19.8
103.6
571.6
22.6k
67.5
48
24
26.667
2.6
30.9
30.9
718.2
48
28
25.926
2.2
22.7
31.4
613.4
48
30
25.000
2.1
19.8
32.3
571.6
60
24
32.000
2.6
30.9
20.8
718.2
60
28
33.185
2.2
22.7
19.9
613.4
60
30
33.333
2.1
19.8
19.8
571.6
NOTE: *Iout = 6 A, Fsw = 300 KHz
FAN65004C
www.onsemi.com
3
BLOCK DIAGRAM
Figure 2. Block Diagram
PVCC
Peak Current
Limiting (PCL)
PCL
Sleep Mode/
UVLO/POR
VCC
FB
VREF
Deadtime
Control
Fault / Power
Good
Control
Fault
Soft
Start
LDO2
Level Shift
PWM
Control
Over Temp
Protection
PCL
PWM Operation
and Frequency
Sync Control
LDO1
UVLO
VCC
Ramp Generator VIN Feed−forward
Ramp
PCL
PVCC
E/A
ISEN
SW
Comparator
High−side
ISEN
VREF
ILIM SYNC RT VCC HVBIAS PVCC EXTBIAS BOOT VIN
SW
PH
PGND
LGPGOODCOMPMODE
FB
SS
EN/
UVLO
15
12
29
22
20
19 24 26
13
27
17
16
2114 23 1−3, 31−35
7−10
4−6
Pre−bias
Startup
GND GND
VINMO
N
28
30
18 25
Low−side
I
FAN65004C
www.onsemi.com
4
PIN CONFIGURATION
Figure 3. Pin Assignment (Bottom View)
1
2
3
4
5
6
27 28 29 30 31 32 33 34 35
15 14 13
12
11 10 9 8 716
17
18
19
20
21
22
23
24
25
26
PH
BOOT
VINMON
HVBIAS
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
EXTBIAS
GND
PVCC
VCC
EN/UVLO
SYNC
PGOOD
GND
RT
SS
COMP
FB
ILIM
MODE
LG
NC
SW
SW
SW
SW
Table 2. PIN DESCRIPTION
Name
Pin/Pad
Description
VIN
1−3, 31−35,
VIN Pad
Input voltage to power stage
PGND
4−6, PGND Pad
Power ground for power stage and PVCC
SW
7−10
Switching node, junction of high- and low-side MOSFETs
NC
11
No Connection
LG
12
Gate of low side MOSFET
MODE
13
Configures pulse modulation/frequency synchronization modes. See MODE description for details
ILIM
14
Connect a resistor to GND to set the high-side MOSFET peak current limit
FB
15
Feedback Voltage Input
COMP
16
Output of internal error amplifier for external compensation
SS
17
Set up soft-start time. Connect a capacitor between SS and PGND to set the soft start time. If left
floating, part enters hiccup mode
GND
18, 25
Analog ground for VCC, RT, SYNC, MODE, etc.
RT
19
Connect a resistor to GND to set switching frequency. If left floating, part enters hiccup mode
PGOOD
20
Power good indicator, open-drain output. Level HIGH indicates V
OUT
is within set limits
SYNC
21
The pin is used to synchronize frequency in when in Non-Master mode or out when in master mode
EN/UVLO
22
Enable/VIN Under-Voltage-Lockout set pin. When used as enable function in-dependent of input
voltage, connect this pin to a voltage > 1.22 V to enable or PGND to disable. When used as enable func
-
tion at specific input voltage level, connect a resistor divider between input voltage and PGND to this pin
VCC
23
Bias power for internal analog circuits
PVCC
24
LDO output and the bias supply for gate driver circuit
EXTBIAS
26
Input voltage to the secondary LDO. Typically connect to V
O
when V
O
≥
5V
FAN65004C
www.onsemi.com
5
Table 2. PIN DESCRIPTION (continued)
Name DescriptionPin/Pad
HVBIAS
27
Input voltage to the primary LDO. Also used for the feed-forward function. Connect it to power stage
input with a small RC filter
VINMON
28
Current sense positive pin. Do NOT connect anything
BOOT
29
Bootstrap supply for high-side driver. Connect a low impedance capacitor between this pin and PH pin
PH
30
High-side source connection (SW node) for the bootstrap capacitor
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
V
IN
VIN Pin Voltage (System Supply) with regard to PGND
−0.3
70
V
V
HVBIAS
HVBIAS Pin Voltage with regard to PGND
−0.3
70
V
EXTBIAS
EXTBIAS Pin Voltage with regard to PGND
−0.3
70
V
EN/UVLO
EN/UVLO Pin Voltage with regard to PGND
−0.3
8.4
V
PH
PH Pin Voltage with regard to PGND
−0.3
70
VSW
SW Pin Voltage with regard to PGND
−0.3
70
SW Pin Voltage with regard to PGND (Pulse, 100 ns)
−5.0
75
SW Pin Voltage with regard to PGND (Pulse, 30 ns)
−7.5
75
VBOOT
BOOT Pin Voltage with regard to PGND
−0.3
75
BOOT Pin Voltage with regard to PH Pin
−0.3
6.5
V
ILIM
ILIM Pin Voltage with regard to GND
−0.3
6.5
V
PVCC
PVCC Pin Voltage with regard to PGND
−0.3
6.5
V
VCC
VCC Pin Voltage with regard to PGND
−0.3
6.5
V
FB
FB Pin Voltage with regard to GND
−0.3
V
CC
+ 0.3
V
COMP
COMP Pin Voltage with regard to GND
−0.3
V
CC
+ 0.3
V
PGOOD
PGOOD Pin Voltage with regard to GND
−0.3
V
CC
+ 0.3
V
LG
LG Pin Voltage with regard to PGND
−0.3
V
PVCC
+ 0.3
V
MODE
MODE Pin Voltage with regard to GND
−0.3
V
CC
+ 0.3
V
RT
RT Pin Voltage with regard to GND
−0.3
V
CC
+ 0.3
V
SS
SS Pin Voltage with regard to PGND
−0.3
V
CC
+ 0.3
V
SYNC
SYNC Pin Voltage with regard to GND
−0.3
V
CC
+ 0.3
V
GND
GND Pin Voltage with regard to PGND
−0.3
0.3
ESD
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012
−
1000
Charged Device Model, JESD22−C101
−
500
R
qJA
(Note 1)
Junction−to−Ambient Thermal Resistance
−
21.1
°
C/W
R
qJC
(Note 1)
Junction−to−Case (Top) Thermal Resistance
−
7.3
°
C/W
R
qJB
(Note 1)
Junction−to−Board Thermal Resistance
−
3.4
°
C/W
T
J
Junction Operating Temperature
−55
150
°C
T
STG
Device Storage Temperature
−55
150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. Measured on 6−layer applications board with 0 LFM at TA = 25°C.
FAN65004C
www.onsemi.com
6
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
IN
VIN Pin Voltage (System Supply) with regard to PGND
4.5
−
65
V
V
HVBIAS
HVBIAS Pin Voltage with regard to PGND
4.5
−
65
V
SW
SW Pin Voltage with regard to PGND (DC)
−0.3
−
V
IN
V
EXTBIAS
EXTBIAS Pin Voltage with regard to PGND
4.5
−
65
V
EN/UVLO
EN/UVLO Pin Voltage with regard to PGND
−
−
7.5
V
PG_SPLY
PGOOD Pin Voltage with regard to GND
−
−
5.4
T
A
Operating Ambient Temperature
−40
−
125
°
C
T
J
Junction Operating Temperature
−40
−
125
°
C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. ELECTRICAL CHARACTERISTICS
(Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C.
TA = TJ = +25°C for typical values.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY
I
HVBIAS_Q_PWM
Forced CCM Quiescent Cur-
rent
V
EN
= 2.0 V, MODE = 5 V through a
100 kW resistor, VFB = 0.64 V −
1.2
−
mA
I
HVBIAS_Q_PSM
DCM with Pulse Skipping Qui-
escent Current
V
EN
= 2.0 V, MODE = 0 V through a
100 kW resistor, VFB = 0.64 V
−
1.4
−
I
HVBIAS_SDN
Shutdown Current
V
EN
= 0 V
−
5
9
m
A
V
HVBIAS_TH
HVBIAS UVLO Threshold
HVBIAS Rising
−
3.92
−
V
V
HVBIAS_HYS
HVBIAS UVLO Hysteresis
HVBIAS Falling
−
1.0
−
LDOs
VPVCC LDO Output Voltage
I
PVCC
= 1 mA and EXTBIAS pin is
open
4.75
5.00
5.25
V
V
EXTBIAS
= 12 V, I
PVCC
= 1 mA
4.75
5.00
5.25
V
HVBIAS_D
LDO1 Dropout Voltage
V
HVBIAS
= 5.0 V, LDO Output
Current = 150 mA
−
1.0
2.0
V
EXTBIAS_D
LDO2 Dropout Voltage
V
EXTBIAS
= 5.0 V, LDO Output
Current = 150 mA
−
0.33
0.66
V
LDOSWO
Switchover Voltage above
which LDO1 is Disabled and
LDO2 is Enabled
V
EXTBIAS
is rising
−
4.7
−
V
LDOSWO_HYS
Switchover Voltage Hysteresis
V
EXTBIAS
is falling
−
100
−
mV
V
SWTOLDO
Threshold Voltage above
which the LDO is in LDO mode
V
HVBIAS
or V
EXTBIAS
is rising
−
5.5
−
V
V
LDOTOSW
Threshold Voltage below which
the LDO is in switch mode
V
HVBIAS
or V
EXTBIAS
is falling
−
5.4
−
VCC SUPPLY
V
CC_ON
V
CC
Start Voltage
V
CC
Rising
3.8
4.0
4.4
V
V
CC_UVLO
V
CC
UVLO Threshold
V
CC
Falling
3.6
3.8
4.1
V
CC_UVLO_HYS
V
CC
UVLO Hysteresis
−
0.2
−
FAN65004C
www.onsemi.com
7
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C.
TA = TJ = +25°C for typical values.)
Symbol UnitMaxTypMinConditionsParameter
REFERENCE VOLTAGE
VREF Reference Voltage
T
J
= 25
°
C, V
IN
= 4.5 V to 65 V
0.596
0.600
0.604
V
T
J
= −40
°
C to 125
°
C (Note 2)
0.594
−
0.606
ENABLE AND UNDER VOLTAGE LOCK OUT
V
EN_TH
EN/UVLO Threshold
EN/UVLO Rising
1.141
1.22
1.296
V
V
EN_HYS
EN/UVLO Hysteresis
EN/UVLO Falling
−
115
−
mV
R
EN_PD
EN/UVLO Internal Pull down
Resistance
−
500
−
k
W
V
EN_CLP
EN/UVLO Clamp Voltage
TBD
−
2.5
−
V
R
EN_CLP
EN/UVLO Clamp Resistance
−
200
−
k
W
I
EN_CLP
EN/UVLO Clamp Current
V
EN
= 2.5 V
−
22
−
m
A
MODE
R
MASTER
Resistor Connected to Mode
Pin for Master Synchronization
Mode
70
100
130
k
W
R
NON_MASTER
Resistor Connected to Mode
Pin for Non-Master Synchro-
nization Mode
1
−
5
k
W
OSCILLATOR
f
SW
Frequency Range
100
−
1000
kHz
f
SW1 Switching Frequency Set by
RT
R
T
= 199 k
W
85
100
125
f
SW2
R
T
= 8.0 k
W
900
1000
1200
f
SW3
RT Pin is Short-Circuited to VCC Pin
215
250
280
f
SW4
RT Pin is Short-Circuited to GND Pin
425
500
581
FREQUENCY SYNCHRONIZATION
V
SYNC_IN_H
SYNC Input Logic HIGH
2
−
−
V
V
SYNC_IN_L
SYNC Input Logic LOW
−
−
0.8
t
HIGH_IN_MIN
Input HIGH Level Pulse Width
150
−
−
ns
t
LOW_IN_MIN
Input LOW Level Pulse Width
150
−
−
f
SYNC
Synchronizable Frequency
Percentage of frequency set by RT
70
−
130
%
t
RT_SYNC_DL
Transition Delay from RT Set
Frequency to Sync Frequency
In Number of External Clock Cycles
in 2 ms time period
−
64
−
Cycles
R
SYNC_PD
SYNC Pin Pull down Resis-
tance
−
100
−
k
W
R
SYNC_DR_PU
SYNC output Driver Pull-up
Resistance
−
10
−
W
R
SYNC_DR _PD
SYNC output Driver Pull-down
Resistance
−
13
−
D
SYNC_OUT
SYNC Output Frequency Duty
Cycle
−
50
−
%
C
L_SYNC
SYNC Pin Lead Capacitance
−
−
200
pF
FAN65004C
www.onsemi.com
8
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C.
TA = TJ = +25°C for typical values.)
Symbol UnitMaxTypMinConditionsParameter
RAMP AND PWM MODULATOR
k
PWM
PWM Modulator Gain,
VIN/DVRAMP
V
IN
= V
HVBIAS
= 4.5 to 65 V
−
25
−
V/V
T
ON_MIN
PWM Minimum ON time
−
150
200
ns
T
OFF_MIN
PWM Minimum OFF time
−
150
200
ERROR AMPLIFIER
GBW
Unit Gain Bandwidth
−
10
−
MHz
G
DC Gain
−
80
−
dB
I
FB
FB Bias Current
V
FB
= 0.6 V
−50
5
50
nA
I
COMP_SOURCE
COMP Source Current
2
7
−
mA
I
COMP_SINK
COMP Sink Current
2
8.5
−
mA
SOFT START
t
SS_DL
Enable High to Soft Start
Ramp Start Delay
−
1
3
ms
I
SS
Charging Current to SS
Capacitor
4.3
5
5.9
m
A
BOOT
V
BT_SWITCH
Bootstrap Switch Voltage Drop
BOOT Current, I
BOOT
= 50 mA
−
0.1
−
V
V
BT_UVLO_TH
BOOT UVLO Voltage with re-
gard to PH
BOOT Falling
−
3.20
−
V
BT_UVLO_HYS
BOOT UVLO Hysteresis with
regard to PH
BOOT Rising
−
0.35
−
CURRENT PROTECTION
I
LIM_S
Current Source Creating
Current Limit Reference
Voltage on R_ILIM
−
30
−
m
A
k
ILIM_HS
High-side MOSFET current
limit scale factor
(ILIM_HS = kILIM_HS × RILIM)
−
206
−
mA/W
k
ILIM_LS
Low-side MOSFET current
limit scale factor
(ILIM_LS = kILIM_LS × RILIM)
−
71
−
n
CYCLE_OCP Number of Switching Cycle(s)
before Entering Hiccup Mode
I
LIM_HS
≤
I
SEN_PEAK
< 130% I
LIM_HS
−
1024
−
Cycle
n
CYCLE_SCP
I
SEN_PEAK
≥
130%I
LIM_HS
−
1
−
POWER GOOD
VFB_NPG_TH
FB Pin Voltage for PGOOD to
Be De-asserted When Down
from Regulation
FB Falling
88
92
96
%VREF
FB Pin Voltage for PGOOD to
Be De-asserted When up into
OVP1
FB Rising
110
115
120
VFB_PG_TH
FB Pin Voltage for PGOOD to
Be Asserted When Down from
OVP1
FB Falling
−
110
−
FB Pin Voltage for PGOOD to
Be Asserted When up
into Regulation
FB Rising
−
94
−
FAN65004C
www.onsemi.com
9
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(Typical application circuit shown in Figure 1 is used. VIN = VHVBIAS = 48 V, VOUT = 5 V, VPVCC = VCC = 5 V, −40°C < TJ = TA < +125°C.
TA = TJ = +25°C for typical values.)
Symbol UnitMaxTypMinConditionsParameter
POWER GOOD
t
PG_DL
PGOOD Delay
Time from when FB Reaches
VFB_PG_TH to when PGOOD
becomes HIGH
−
500
−
m
s
t
PG_FLT
PGOOD De-glitch Filter
Duration
−
5
−
m
s
V
PG_L
PGOOD Output LOW Voltage
V
FB
= 70%V
REF
, I
PGOOD
= −1 mA
−
6
10
mV
VOLTAGE PROTECTION
V
FB_OVP1
FB Pin Voltage for Level 1
Over Voltage Detection FB Voltage Rising
110
115
120
%VREF
V
FB_OVP2
FB Pin Voltage for Level 2
Over Voltage Detection
124
130
136
V
FB_UVP_TH
FB Pin Voltage for Under
Voltage Detection
FB Voltage Falling
−
35
−
HICCUP
tHICCUP
Hiccup Time
−
1
−
s
THERMAL SHUTDOWN
T
J_SD
Thermal Shutdown Threshold
Temperature Rising
−
150
−
°C
T
J_SD_HYS
Thermal Shutdown Hysteresis
Temperature Falling
−
20
−
V
IN
VOLTAGE PROTECTION
V
IN_OV_Rising
V
IN
Voltage for Over Voltage
Detection
V
IN
Rising
66.7
68.5
69.3
V
V
IN_OV_Falling
V
IN
Voltage for Over Voltage
Detection
V
IN
Falling
64.9
67
68.1
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design
Table 6. FAULT TABLE
Name
Condition
Action
Recovery
Over−Current Protection OCP
100% ILIM_HS
≤
IDS_HS < 130% ILIM_HS
Hiccup after 1024 OC
events
ISEN_PEAK
≤
ILIM_HS
Short−Circuit Protection SCP
IDS_HS
≥
130% ILIM_HS.
Hiccup
ISEN_PEAK
≤
ILIM_HS
Over−Voltage Protection OVP1
115% VREF < VFB < 130% VREF
Switching resumes
when OVP1 is cleared
VFB
≤
VREF
Over−Voltage Protection OVP2
VFB > 130% VREF
HS MOSFET off
LS MOSFET On
VFB
≤
VREF
Under−Voltage Protection UVP
VFB
≥
35% VREF
Hiccup
VFB > 35% VREF
Input Over−Voltage Protection
OV rising threshold
(min/max) = 66.7/69.3V
Switching resumes
when Input OV is
cleared
OV falling threshold
(min/max) = 64.9/68.1V
Power Good
VFB
≤
92% VREF
PGOOD low
VFB
≥
94% VREF
VFB
≥
115% VREF
VFB
≤
110% VREF
Thermal Shutdown
TJ
≥
150
°
C
Switching resumes
when thermal shutdown
is cleared
TJ
≤
130
°
C
FAN65004C
www.onsemi.com
10
TYPICAL PERFORMANCE CHARACTERISTICS
(Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified)
Figure 4. Line Regulation vs. Temperature Figure 5. VIN Quiescent Current vs. Temperature
Figure 6. Shutdown Current vs. T at VHVBIAS = 48 V Figure 7. HVBIAS Rising Threshold vs. T
Figure 8. HVBIAS Falling Threshold vs. T Figure 9. VREF vs T at VHVBIAS =48V
TEMPERATURE (°C)
100806040200−20−40
3.0
3.2
3.4
3.6
3.8
4.0
4.4
4.6
TEMPERATURE (°C)
TEMPERATURE (°C)
100806040200−20−40
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
100806040200−20−40
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
IHVBIAS_SDN (mA)
VHVBIAS_TH_P (V)
VHVBIAS_TH_N (V)
120
4.2
120
120
TEMPERATURE (°C)
0.000
0.010
LINE REGULATION (%)
0.005
TEMPERATURE (°C)
100806040200−20−40
12
13
15
QUIESCENT CURRENT (mA)
120
14
−0.005
−0.010
14.5
13.5
12.5
TEMPERATURE (°C)
100806040200−20−40
0.5970
0.5975
0.5985
0.5990
0.5995
0.5960
0.5965
VREF (V)
120
0.5980
100806040200−20−40 120
4.8
5.0
FSW − 300 kHz
FAN65004C
www.onsemi.com
11
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified)
Figure 10. EN/UVLO Threshold Voltage vs. T
at VHVBIAS =48V Figure 11. EN/UVLO Hysteresis Voltage vs. T
at VHVBIAS =48V
TEMPERATURE (°C)
100806040200−20−40
1.2430
1.2435
1.2445
1.2455
1.2460
Figure 12. Switching Frequency vs. RT at
VHVBIAS = 48 V and T = 255CFigure 13. Switching Frequency vs. T at
VHVBIAS = 48 V and RT = 8.06 kW
TEMPERATURE (°C)
RT (kW)
100806040200−20−40
120
130
140
150
160
180
190
200
200150100500
200
400
600
800
1000
700
900
Figure 14. Switching Frequency vs. T at
VHVBIAS = 48 V and RT shorted to VCC
Figure 15. Switching Frequency vs. T at
VHVBIAS = 48 V and RT shorted to GND
TEMPERATURE (°C)
TEMPERATURE (°C)
100806040200−20−40
1004
1005
1006
1007
1008
1010
100806040200−20−40
242
244
246
248
250
VEN_TH (V)
VEN_HYS (mV)
FSW (kHz)
FSW2 (kHz)
FSW3 (kHz)
120
1.2440
1.2450
120
170
120
120
TEMPERATURE (°C)
100806040200−20−40
502
504
508
510
514
516
500
FSW (kHz)
120
506
512
500
300
100
1009
FAN65004C
www.onsemi.com
12
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified)
Figure 16. PWM Modulator Gain, VIN / DVRAMP,
vs. T at VHVBIAS =48V Figure 17. TON_MIN vs. T at VHVBIAS =48V
TEMPERATURE (°C)
100806040200−20−40
24.2
24.3
24.5
24.7
24.8
24.9
Figure 18. TOFF_MIN vs. T at VHVBIAS =48V Figure 19. 30 mA Current Source for Current
Limit Purpose vs. T at VHVBIAS =48V
TEMPERATURE (°C)
TEMPERATURE (°C)
100806040200−20−40
155
155.5
156
156.5
157
155
155.5
156
156.5
157.5
158
TEMPERATURE (°C)
100806040200−20−40
15
20
30
40
45
55
KPWM (V/V)
TON_MIN (ns)
TOFF_MIN (ns)
ILIM_S (mA)
120
24.4
24.6
120
157.5
120
100806040200−20−40 120
158
157
25
35
50
FAN65004C
www.onsemi.com
13
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified)
Figure 20. System Startup with No Load
Figure 21. System Startup with No Load Figure 22. System Startup with 25% Pre-bias
CH1 = EN (0.5V/div), CH2 = SS (0.5V/div), CH3 = Vcc (2V/div),
CH4 = Vo (5V/div), T = 2mS/Div
CH1 = EN (0.5V/div), CH2 = SW (20V/div), CH3 = LG (2V/div),
CH4 = Vo (5V/div), T = 2mS/Div CH1 = Vin (10V/div), CH2 = SW (20V/div), CH3 = Vo (5V/div),
CH4 = SS (0.5V/div), T = 2mS/Div
FAN65004C
www.onsemi.com
14
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified)
Figure 23. System Startup with 75% Pre-bias Figure 24. Transition from Native Frequency to
Sync Frequency in Non-Master Mode
Figure 25. SYNC Output Frequency Duty Cycle in
Master Mode Figure 26. Over-current Protection with 280 kHz
Switching Frequency
Figure 27. Power Good at Startup with No Load Figure 28. Power Good at Startup with No Load
CH1 = Vin (10V/div), CH2 = SW (20V/div), CH3 = Vo (5V/div),
CH4 = SS (0.5V/div), T = 2mS/Div CH1 = Comp (0.5V/div), CH2 = SW (20V/div), CH3 = SYNC
(2V/div), CH4 = Vo (5V/div), T = 50uS/Div
CH1 = Vcc (2V/div), CH2 = SW (20V/div), CH3 = SYNC
(2V/div), CH4 = Vo (5V/div), T = 2uS/Div CH1 = LG (5V/div), CH2 = SW (20V/div), CH3 = Vo (5V/div),
CH4 = IL (1A/div), T = 500uS/Div
CH1 = PGOOD (2V/div), CH2 = SW (20V/div), CH3 = FB
(0.1V/div), CH4 = Vo (5V/div), T = 1mS/Div CH1 = PGOOD (2V/div), CH2 = SW (20V/div), CH3 = FB
(0.1V/div), CH4 = Vo (5V/div), T = 10uS/Div
FAN65004C
www.onsemi.com
15
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified)
Figure 29. OVP1 at VFB . 115% VREF Figure 30. OVP1 Release at VFB 3 110% VREF
Figure 31. UVP due to Deep Over-current Figure 32. Switching and Voltage Ripple
CH1 = PGOOD (2V/div), CH2 = SW (20V/div), CH3 = FB
(0.1V/div), CH4 = Vo (4V/div), T = 500uS/Div CH1 = PGOOD (2V/div), CH2 = SW (20V/div), CH3 = FB
(0.1V/div), CH4 = Vo (4V/div), T = 500uS/Div
CH1 = FB (0.2V/div), CH2 = SW (20V/div), CH3 = Vo (5V/div),
CH4 = IL (2A/div), T = 100uS/Div CH1 = LG (4V/div), CH2 = SW (50V/div), CH3 = Vo (20mV/div),
CH4 = IL (1A/div), T = 1uS/Div
FAN65004C
www.onsemi.com
16
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at TA = 25°C, VHVBIAS = VIN = 48 V and VO = 28 V unless otherwise specified)
Figure 33. Load Step between 2.5 A and 5 A Load Figure 34. Load Regulation
Figure 35. System Efficiency Figure 36. System Power Loss
CH3 = Vo (0.4V/div), CH4 = Iout (2A/div), T = 50uS/Div
Figure 37. Over Current vs. Temperature Figure 38. Thermal De−rating Curve
LOAD CURRENT (A)
6543210
90
92
94
98
EFFICIENCY (%)
96
100
TEMPERATURE (°C)
100806040200−20−40
5.5
5.8
6.0
6.3
6.5
6.8
OVER CURRENT (%)
7.0
LOAD CURRENT (A)
LOAD REGULATION (%)
6
543210
−0.40%
−0.30%
−0.20%
0.00%
−0.10%
0.20%
0.10%
FSW − 300 kHz
FSW − 300 kHz
35 V 48 V
60 V
35 V
48 V
60 V
LOAD CURRENT (A)
6
543210
0
1
2
4
SYSTEM POWER LOSS (W)
3
5FSW − 300 kHz
35 V
48 V
60 V
FSW − 300 kHz
RILIM − 34.7 kW
35 V 48 V
60 V
TEMPERATURE (°C)
85654525
5
7
9
11
13
10
5
FSW − 300 kHz
35 V 48 V
60 V
OUTPUT CURRENT (A)
6
8
10
12
7.3
7.5
FAN65004C
www.onsemi.com
17
Functional Description
FAN65004C is a high-efficiency synchronous buck
converter with integrated controller, driver and two power
MOSFETs. It can operate over a 4.5 V to 6 5 V input voltage
range, and delivers 6 A load current. The internal reference
voltage is 0.6 V ±1% over −40°C to 125°C temperature
range.
FAN65004C uses voltage mode PWM control scheme
with input voltage feed-forward feature for the wide input
voltage range. The high bandwidth error amplifier monitors
the output voltage and generates the control signal for the
pulse width modulation block. By adjusting the external
compensation network, the system performance can be
optimized based on the application parameters.
The switching frequency is set by an external resistor and
can be synchronized to an external clock signal. To improve
light load efficiency (low IQ mode), either low-side
MOSFET is turned off when the inductor current drops to
zero or pulse skipping is implemented when load current
further decreases. The high-side MOSFET current sense
circuit is adopted for the peak current limiting function and
the output voltage will be reduced in current limiting
condition. Other protection functions include over
temperature shut-down and over-voltage protection.
At the beginning of each switching cycle, the clock signal
initiates a PWM signal to turn on high-side MOSFET, and
at the same time, the ramp signal starts to rise up. A reset
pulse is generated by the comparator when the ramp signal
intercepts the COMP signal. This reset pulse turns off
high-side MOSFET and turns on low-side MOSFET until
next clock cycle comes. In the case that current limit is hit,
a peak current limiting (PCL) signal is generated to turn off
the high-side MOSFET until the next PWM signal. This is
cycle by cycle current limit protection. When certain faulty
condition is met, the device enters hiccup mode to further
protect itself.
LDOs
Two LDOs are included in FAN65004C to provide
internal supply and to balance power loss from them. The
LDO block diagram is shown below.
Figure 39. LDO Block Diagram
VIN:
4.5 V~65 V
R1
VEXT
C2
LDO1
LDO2
Sync
Control
Internal Bias and
Feed-forward Feature
PVCC BOOT
EXTBIAS
HVBIAS
REG
Since LDO1 input, HVBIAS, is also used for initial
internal bias and for input voltage feed-forward
compensation, system input voltage, VIN, should always be
connected to HVBIAS pin and an RC filter is recommended
between VIN and HVBIAS to filter any noise from high
frequency switching. During power up, LDO1 is always
selected. After the system finishes soft start, which LDO
block is selected depends on voltages appearing on both
HVBIAS and EXTBIAS pins. If there is a voltage at
EXTBIAS pin and it is above 4.7 V, LDO2 will be selected,
otherwise LDO1 will continue to supply power to the
device. EXTBIAS can be left open for single LDO operation
all the time. In the case that EXTBIAS is connected to a
voltage, V EXT, and VEXT > 4. 7 V and also VEXT > VHVBIAS,
LDO2 will be selected. This makes power loss on LDO2
greater than that on LDO1 if LDO1 were selected. So it’s the
designer’s responsibility to make sure VEXT < VHVBIAS
while V EXT > 4 .7 V. Both LDOs work in switch mode when
their input voltages are lower than 5.4 V. This allows very
low voltage drop on both LDOs and ensures high enough
voltage level on PVCC for internal bias and MOSFET drive.
Assuming V EXT < VHVBIAS while VEXT > 4 . 7 V, Table 7
shows which LDO will be selected and the LDO work status.
(• indicates which LDO and mode are selected and × means
disabled)
Table 7. LDO SELECTION AND WORK MODE
Input
Work Mode
LDO1
LDO2
HVBIAS
(V)
EXTBIAS
(V)
Switch
LDO
Switch
LDO
4.5−4.7
4.5−4.7
• × × ×
4.7−5.5
4.5−4.7
• × × ×
4.7−5.5
× × • ×
5.5−65
4.5−4.7
× • × ×
4.7−5.5
× × • ×
5.5−65
× × × •
Both LDOs are designed to deliver up to 150 mA current.
A 4.7 mF ceramic capacitor between PVCC and PGND
placed as close as possible to PVCC pin is recommended to
decouple any noise from high frequency driver currents.
A1W resistor can be used between PVCC and VCC
together with a ceramic capacitor between VCC and GND
to form a filter for the VCC bias supply for the internal
control circuits. When VCC voltage drops below its UVLO,
the regulator control circuit blocks are disabled.
Enable and Under Voltage Lock-Out
EN/UVLO signal is used for device enable/disable when
its voltage is higher/lower than the threshold, VEN_TH,
which is typical 1.22 V. The precision threshold voltage of
this signal can also be used to set a system input voltage
level, above which FAN65004C will be enabled and below
which disabled. Figure 40 shows the EN/UVLO block
diagram and application configuration.
FAN65004C
www.onsemi.com
18
A resistor divider (R2 and R3 as shown in Figure 1) can
be used to set the level of input voltage, VIN_UVLO, which
enables the device. Selection of R3 is determined by
Equation 1.
R3 +
VEN_TH R2 REN_PD1
VIN_UVLO REN_PD1 *VEN_TH R2 *VEN_TH REN_PD1
(eq. 1)
R2 and R3 are both in kW.
Assuming i, in mA, is the current flowing through R2
when working input voltage is VIN, then R2 is determined by
Equation 2.
R2 +
VIN_UVLO *VEN_TH
VIN_UVLO VIN
i(eq. 2)
Figure 40. EN/UVLO Block Diagram
V
IN
= 4.5 V~65 V
EN/UVLO
PGND
R2
R3
i
EN/UVLO
Threshold
1.22 V
VCC
2.5 V
REN_CLP = 200 kW
REN_PD1 =
150 kW
REN_PD2 =
500 kW
VEN < 1 V VEN > 1 V
For example, a converter has nominal input voltage of
VIN = 48 V. It’s desired that the device is enabled when input
voltage is above 35 V, which makes VIN_UVLO = 35 V. If
50 mA is chosen, then Equations 1 and 2 yield R2 and R3 in
Equations 3 and 4 respectively:
R2 +48 (35 *1.22)
35 50 10*6 103+926.5 kW(eq. 3)
R3 +1.22 926.5 150
35 150 *1.22 926.5 *1.22 150 (eq. 4)
+43.1 kW
Choose the closest standard 1% resistor values of
R1 = 931 kW and R2 = 43.2kW. What value is chosen for i
is a power loss matter. The greater the i is, the greater the
power loss will be, and vice versa. But if the current is too
low, the EN/UVLO signal will be vulnerable to noise.
Choose the highest possible current that only creates
negligible power loss to the system. In the example shown
above, the power loss in this EN/UVLO branch is P = VIN ×
i = 48 V ×50 mA = 2.4 mW.
When the device is disabled, only a few micro-ampere
current is required to support essential blocks like bandgap.
Only after the device is enabled, major functions like, LDO,
oscillator, soft start, driver, logic control, start to run. The
device is disabled if the EN/UVLO pin is floating.
Soft Start
The soft start block diagram is shown in Figure 41.
Figure 41. Soft Start Block Diagram
_
+
+
VCC
EA
VREF
5 mA
FB
SS
C6
The soft start function is enabled with a delay of maximum
3 ms after EN is high. During the delay, the SS capacitor is
discharged if there is any residual voltage. If SS voltage is
still not 0 after this delay, a fault condition is created and the
device enters hiccup mode, otherwise soft start process is
initiated. A typical 5 mA constant current flows out of SS pin
to charge the capacitor at SS pin. The error amplifier
regulates the converter output voltage according to the lower
value of SS pin voltage and the fixed 0.6 V reference
voltage. Wit h the constant current, SS voltage linearly ramps
up from 0, and the regulator output voltage follows the SS
voltage to ramp up. SS voltage continues to rise after it
exceeds the 0.6 V reference voltage, at which point, the SS
voltage is out of the loop and the converter output voltage is
regulated to the reference voltage of 0.6 V. When SS
capacitor i s char ged to 1.5 V, the SS timer stops counting and
the device checks if FB has reached 94% VREF. If not, the
device enters hiccup mode, otherwise, the device considers
the soft start successful and continues to charge SS capacitor
until it reaches VCC.
If the SS pin is floating, device enters hiccup.
Pre-bias Startup
A pre-biased regulator is one that, before the regulator is
powered, has output voltage above 0, and so for the FB pin.
FAN65004C is able to start in such a case. When soft start
is initiated, both high- and low-side MOSFETs are forced off
until the SS pin is charged up to the pre-biased FB voltage.
The following startup process will be a normal soft start
process as stated in “Soft Start” section.
Switching Frequency
The internal clock generator can be programmed from
100 kHz to 1 MHz by a resistor connected between the RT
FAN65004C
www.onsemi.com
19
pin and the GND pin. To set the desired switching frequency,
the resistor can be calculated by Equation 5 as shown below:
fSW +min ƪ104
RT )2.5 )50, 1000ƫ(eq. 5)
where fSW is in kHz and RT is in kW.
The switching frequency vs. the external resistor curve is
shown below.
Figure 42. Relationship between RT and fSW
RT (kW)
Switching Frequency, fSW (kHz)
Switching Frequency, fSW vs. RT
0 20 100 200
0
200
400
600
800
1000
1200
120 140 160 18040 60 80
As soon as the device is enabled, it will go through a set
of routine to check the RT pin configuration to determine the
switching frequency or if there is any fault. If RT is tied to
VCC, the switching frequency is 250 kHz, and 500 kHz if
short-circuited to GND. If RT pin is floating initially or
becomes open from any non-open state, the device enters
hiccup mode.
Frequency Synchronization
FAN65004C can be set to work in either master mode or
non-master mode. When in master mode, it sends out clock
signal through SYNC pin; when in non-master mode, it
either takes in clock signal from an external source on SYNC
pin in ±30% of RT set frequency or uses RT to set its clock.
Both modes are configured via MODE pin.
1. Master mode: A 100 kW resistor connected
between MODE pin and either VCC or GND will
enable master mode. In this mode, FAN65004C
generates its ramp and PWM signal by its own and
sends out PWM clock through SYNC pin with
180 degree phase shift and 50% duty cycle. If an
external clock is detected on SYNC pin that is in
conflict with the internal one, FAN65004C makes
SYNC pin high impedance until fault is cleared.
2. Non-master mode: The MODE pin connected to
either VCC or GND through a 1 kW~5 kW resistor
or left floating enables this mode. In this mode, the
device keeps checking the SYNC pin for incoming
clocks every 2 ms. If 64 cycles of clock are
detected and the clock frequency is in ±30% of RT
set frequency, the device is in sync with the clock
appearing on SYNC pin. If no clocks are detected,
the number of clocks in 2 ms does not reach 64, or
the clock frequency is not within ±30% of RT set
frequency, the device uses RT to set the clock.
The synchronization block diagram is shown
below.
Figure 43. Frequency Synchronization
Block Diagram
10 W
VCC
SYNC
AGND
10 W
100 kWRX
HiZ
SCLK_IN
SCLK_Presen
t
SCLK
Master Mode
CLK_PWM
LOGIC
CONTROL
FAN65004C implements fault protection in case SYNC
pin is short-circuited to either GND or VCC. The logic
checks voltage levels of both internal driving clock and
SYNC pin except for a 100 ns time period at every clock
transition, which is used to mask the transition glitches due
to propagation delay. These 2 logic levels are expected to be
the same when there is no pin fault. When SYNC pin fault
is detected, the driver is disabled by using high impedance
for 8 clock cycles, which makes worst case duty cycle of
~1.67% with 1 MHz frequency.
SYNC pin fault is only a local fault and doesn’t trigger
global hiccup or stop device operation. Figure 43 shows the
frequency synchronization block diagram.
Operation Modes
The MODE pin controls 2 functions: pulse modulation
and frequency synchronization.
Pulse modulation refers to continuous conduction fixed
frequency pulse width modulation (short-formed Forced
CCM) and discontinuous conduction with pulse skipping
modulation (Short-formed DCM with Pulse Skipping).
When in DCM with Pulse Skipping, device works in
discontinuous conduction mode when inductor current hit 0
and may skip pulses when load becomes even lighter; device
transits to fixed frequency operation and works in
continuous conduction mode when inductor current valley
is higher than 0. Frequency synchronization refers to master
or non-master mode.
If low output voltage ripple is desired, Forced CCM PWM
operation can be selected. In this mode, continuous
conduction fixed switching frequency applies regardless of
light load or heavy load and negative current appears at light
load condition. This results in greater power loss at light
load.
FAN65004C
www.onsemi.com
20
To reduce the power loss at light load, DCM with Pulse
Skipping can be chosen. When at light load, the device
works in discontinuous conduction mode and skips pulses,
so that the power loss is reduced.
The relationship between the MODE configuration and
the actual mode is illustrated in the following table:
Table 8. OPERATION MODES WITH MODE
CONFIGURATION
MODE Pin
Configuration
Operation Mode
Pulse Modulation
Freq Sync
VCC
←
R=1kW~5 kW →
MODE
Forced CCM
Non-master
VCC
←
R = 100 kW±30%
→ MODE
Forced CCM
Master
GND
←
R=1kW~5 kW →
MODE
DCM with Pulse
Skipping
Non-master
GND
←
R = 100 kW±30%
→ MODE
DCM with Pulse
Skipping
Master
Floating
Forced CCM
Non-master
Power Good
A comparator monitors the FB voltage and controls an
open drain MOSFET. The PGOOD pin is connected to the
Drain of this MOSFET. To correctly use the PGOOD signal,
a pull-up resistor connected to an external voltage source is
required. When FB voltage exceeds 94% of VREF (typical
0.6 V), PGOOD signal is asserted after a delay, tPG_DL, and
when it’s below 92% of VREF it is de-asserted. PGOOD
signal is valid only after device is enabled and soft start is
completed (SS ramps above 0.6 V). When OVP1 is
detected, PGOOD is de-asserted. PGOOD is re-asserted
with 5% hysteresis. Figure 44 shows the internal circuitry
connected to PGOOD pin.
Figure 44. PGOOD Block Diagram
RPG
VCC
NOT
Power
Good
PGOOD
External
Voltage
Setting Current Limit
A 1% tolerance or better resistor with a low temperature
coefficient o f resistance, R_ILIM, connected between ILIM
pin and GND is used to set the current limit for both high-
and low-side MOSFETs. An 30 mA internal current source
flows through R_ILIM, creating a reference voltage, and t h e
voltage drops on RDSON of both high- and low-side
MOSFETs are used to compare with this reference voltage.
This comparison generates an over current event. The
high-side MOSFET current is monitored in forward
direction, i.e. current flows from drain to source, while
low-side MOSFET current is monitored in a reverse
direction. When low-side MOSFET turns on in a normal
condition, its current flows from ground to switching node.
Current is NOT monitored in this case. If current flows from
switching node to ground, it is considered abnormal and is
monitored. The current limit for both high- and low-side
MOSFETs is calculated the same way, ILIM = kILIM × RILIM,
and k ILIM parameters for both high- and low-side MOSFETs
are shown in the Electrical Characteristic Table. If ILIM is
tied to VCC, system is in standby mode, enabling all blocks
except driver.
R_ILIM below 22 kW is defined as short-circuit, above
80 kW is considered to be open.
Over Current Protection (OCP) and Short Circuit
Protection (SCP)
FAN65004C implements over current protection for
high-side and low-side MOSFETs differently.
For high-side MOSFET, FAN65004C sets two levels of
over load protection according to the current limit setting:
over current protection (OCP) and short circuit protection
(SCP). OCP happens when the high-side MOSFET current,
iDS_HS, is in the range of; 100% ILIM_HS ≤ iDS_HS <
130% ILIM_HS, and SCP occurs when iDS_HS ≥
130% ILIM_HS. FAN65004C monitors MOSFET current
constantly and provides cycle by cycle peak current limit.
The high-side MOSFET is turned off whenever its current
exceeds the limit.
Once the current limit is hit, FAN65004C counts. If 1024
consecutive OC events have reached, regardless of the FB
voltage, the system enters hiccup mode.
The worst case of over current is such conditions as
short-circuited output or saturated inductor, in which the
current exceeds 130% of current limit. In this case, device
initiates short circuit protection and enters hiccup mode
immediately.
For low-side MOSFET, FAN65004C performs cycle by
cycle protection if its current limit is hit. At each cycle of
low-side MOSFET turn-on, its current is checked. If the
current exceeds its current limit, ILIM_LS, the low-side
MOSFET will be turned off immediately and remains off
until next switching cycle. This process repeats until
the over current event is released (low-side MOSFET
current becomes less than ILIM_LS). Low-side MOSFET
over current protection doesn’t affect high-side MOSFET
switching, i.e. high-side MOSFET remains normal
switching if high-side MOSFET over current event does not
occur.
FAN65004C
www.onsemi.com
21
Hiccup Mode
Hiccup mode is described as follows. When a fault
condition is met, both high- and low-side MOSFETs turn off
for a period of time, tHICCUP (typical 1 s), and soft start
capacitor is discharged. Then device enters soft start. After
soft start, if the fault condition is met again, both high- and
low-side MOSFETs turn off for tHICCUP again and soft start
capacitor is discharged…System returns to normal
operation after the fault event is released.
Over Voltage Protection (OVP)
There are 2 levels of over voltage protection: over voltage
protection 1 (OVP1) and over voltage protection 2 (OVP2),
which are defined below respectively.
1. OVP1 is protection when FB voltage is above
115% but below 130% of VREF. When OVP1 is
triggered, both high- and low-side MOSFETs are
turned off immediately. When FB falls to or below
VREF, the system returns to normal operation and
initiates a new PWM signal at the next clock cycle.
2. OVP2 is protection when FB voltage is above
130% of VREF. When OVP2 is triggered, the
high-side MOSFET is turned off immediately
while the low-side MOSFET is turned ON. If over
current event occurs during the low-side
MOSFET ON time, cycle by cycle protection will
be performed as described in “Over Current
Protection (OCP) and Short Circuit Protection
(SCP)” section. As soon as over current event is
released, the low-side MOSFET will be kept on
again until FB voltage drops to or below VREF.
One hiccup cycle is initiated once FB voltage
reaches 100%VREF. After the hiccup, the part will
go into a soft start sequence and try to regulate.
If OVP2 happens during the hiccup timing period,
nothing will happen.
In the case of OVP, power good signal is de-asserted and
re-asserted after VFB comes down to 110%VREF.
Under Voltage Protection (UVP)
Under voltage is a condition when output voltage is below
35% of its regulated level (checked on FB pin). If VFB ≤ 35%
is met, then under voltage protection (UVP) is initiated,
where IC enters hiccup mode.
Over Temperature Protection (OTP)
The device keeps monitoring the junction temperature.
When the sensed temperature is above the protection point,
TJ_SD, over temperature protection (OTP) event occurred
and the system shuts down. OTP is released when the sensed
temperature i s 2 0 ° lower than the trip point, TJ_SD, where the
system resets through soft-start.
Output Inductor Selection
The output inductor is selected to meet the output ripple
requirements. The inductor value determines the converter’ s
ripple current DIL. Largest ripple current occurs at highest
Vin voltage.
DIL +ǒVIN *VOUTǓǒVOUTǓ
FSW @L@VIN (eq. 6)
Lower ripple current reduced core losses in the inductor
and output voltage ripple. Highest efficiency is obtained at
low frequency with small ripple current, however with a
disadvantage o f using a lar ge inductor. Inductor value can be
chosen based on the equation below in order to not exceed
a max ripple current (usually 30% to 70% of max inductor
current)
LwǒVIN *VOUTǓ
FSW @DIL@D(eq. 7)
Output Capacitor Selection
In general, the output capacitors should be selected to
meet the dynamic regulation requirements including ripple
voltage and load transients.
1. For ripple voltage considerations; the output bulk
maintains the DC output voltage. The use of
ceramic capacitors is recommended to sustain a
low output voltage ripple. At switching frequency
the ceramic capacitors are capacitance dominante
use the following equation for calculating Cout
where the ripple output voltage is within 1% of
Vout.
DOUT +VOUT @(1*D)
8@FSW2@L@COUT (eq. 8)
And the RMS current through it is
ICOUT(RMS) +IOUT @DIL(pp)
12
Ǹ(eq. 9)
2. The maximum capacitor value required to provide
the full, rising step, transient load current during
the response time of the inductor is shown
CMIN +L@IPK2
ǒVOV )VOUTǓ2*VOUT2(eq. 10)
where IPK is defined as:
IPEAK +IOUT,MAX *DIL
2(eq. 11)
Where CMIN is the minimum value of output capacitor
required, L is the output inductor, IPK is the peak load
current, VOV is the increase in output voltage during a load
release, VOUT is output voltage.
Input Capacitor Selection
Voltage and RMS current rating of the input capacitors are
critical factors. Typically input capacitor is designed based
on input voltage ripple of 2%. Capacitor voltage rating must
be at least 1.25x greater than max input voltage . Maximum
RMS current supplied by the input capacitance occurs at
50% duty cycle and when Vin =2 x Vout.
FAN65004C
www.onsemi.com
22
RMS current varies with load as shown below:
ICIN(RMS) +IOUT @D@ǒ1*D)DIL(pp)2
12 Ǔ
Ǹ(eq. 12)
Ceramic capacitors are best known for low ESR and are
highly recommended.
Loop Compensation
Selecting External Compensation:
The FAN65004C is a voltage mode buck regulator with an
error amplifier compensated by external components to
achieve accurate output voltage regulation and to respond to
fast transient events. The goal of the compensation network
is to provide a loop gain function with the highest cross−over
frequency at adequate phase and gain margins.
The output stage (LC) of the buck regulator is a double
pole system. The resonance frequency of this lowpass filter
is shown below:
ƒp0 +1
2p@LCOUT
Ǹ(eq. 13)
The output filter has a zero that is calculated from the
output capacitance and output capacitor ESR:
ƒz0 +1
2p@ESR @COUT (eq. 14)
The bode plot of the power stage, error amplifier and the
desired loop gain are drawn in the figure below. The first
zero ( f z1) compensates the phase lag of the pole located at the
origin followed by a second zero (fz2) to compensate for one
of the poles of the LC filter in order to crossover (fc) at
−20 dB slope. The second pole (fp2) is aimed to cancel the
ESR zero and finally the third pole (fp3) is to provide
attenuation for frequencies above fsw/2.
Figure 45. Power Stage, Loop Gain and Compensator
Bode Plots
For ease of calculation, with C1 >> C3:
ƒz1 +1
2p@(R10 )R9)@C9
ƒz2 +1
2p@R8 @C7
ƒp2 +1
2p@R9 @C9
ƒp3 +1
2p@R8 @C8
ƒc+VIN
2p@VRamp @R10 @C7
Thermal Considerations
The temperature gradients on the FAN65004C are shown
below. While measuring the thermal performance, place the
thermocouple at the hottest spot of the IC (not at the center
of the part).
FAN65004C
www.onsemi.com
23
Layout Guidelines
1. Place RT resistor and SS capacitor close to RT and
SS pins.
2. Use a low impedance source such as a logic gate to
drive the SYNC pin and keep the PCB trace as
short as possible.
3. Components of digital signals like EN/UVLO,
PGOOD and SYNC can be placed far away from
device.
4. Place BOOT capacitor right next to BOOT and PH
pins. If flexibility of high−side MOSFET driving
strength is desired, place a resistor in series with
this BOOT capacitor. For Vin > 40 V, use Rboot
= 2 ohm.
5. Place inductor on top layer. Restrict the SW trace
to only cover the inductor pin but keep its trace as
wide as possible for thermal relief.
6. Avoid all the compensation components from
passing through, above or underneath switching
trace.
7. Keep the switching nodes away from sensitive
small signal nodes (FB). Ideally the switch nodes
printed circuit traces should be routed away and
separated from the IC and especially the quiet side
of the IC. Separate the high dv/dt traces from
sensitive small−signal nodes with ground traces or
ground planes.
8. Place decoupling caps right next to PVCC, VCC ,
HVBIAS and EXTBIAS.
9. The output capacitors should be placed as close to
the load as possible. Use short wide copper regions
to connect output capacitors to load to avoid
inductance and resistances.
Table 9. ORDERING INFORMATION
Part Number
Current Rating (A)
Input Voltage Max. (V)
Frequency Max. (kHz)
Package
FAN65004C
6
65
1000
PQFN 6.0
×
6.0 mm
PowerTrench is a registered trademark of of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
PQFN35 6X6, 0.5P
CASE 483BE
ISSUE O
DATE 30 SEP 2016
SCALE 2:1
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13684G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
PQFN35 6X6, 0.5P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
PQFN35 6X6, 0.5P
CASE 483BE
ISSUE O
DATE 30 SEP 2016
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13684G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
PQFN35 6X6, 0.5P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊