PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
Preliminary Information
www.fairchildsemi.com
Features
• 10-bit or 20-bit Parallel YCbCr input
• 24-bit RGB input
• D1, Genlock and Master mode operation
• Composite, S-video and component analog outputs
• Digital Composite output
• Fairchild demo board compatibility
Applications
• Evaluation of TMC2193 DENC
• Evaluation of TMC2072 Genlock interface
• Output for TMC2068P7C Decoder demo board
• System Breadboarding
Description
The TMB2193MS100 demonstration board provides a flexi-
ble base for evaluating the performance of the TMC2193
Digital Video Encoder (DENC). The demonstration board
can be driven by either a D1 or Genlock signal, or it can sup-
ply the synchronization signals needed to drive a framestore
or any MPEG Decoder. Both YCbCr, in either 4:2:2, D1, or
4:4:4 formats, and RGB inputs are supported. The board
provides high quality analog composite video, analog
S-video, analog component video and digital composite
video outputs.
Block Diagram
96 W ay
Edge
Connector
(female)
RBUS
Connector
1
32
65-B2193-01
Digital Inputs:
10 bit D1
24 bit RGB
20 bit YCbCr
PXCK
Analog Outputs:
Composite
S-Video
RGB
YPbPr
Sync
Digital Outputs (Optional):
10 bit DCVBS
HSYNC
VSYNC
PXCK
Digital Outputs:
HSYNC
VSYNC
MPXCK
TMC2193
FPGA TMC2072
MCU
+5V 0V -5V
Analog
LPF
TMB2193MS100
Demonstration Board for the TMC2193
Rev. 0.9.0
TMB2193MS100 PRODUCT SPECIFICATION
2
Preliminary Information
Functional Description
The TMB2193MS100 is designed to demonstrate the perfor-
mance of the TMC2193 Digital Video Encoder (DENC). For
a complete description of the TMC2193, please refer to the
TMC2193 data sheet. The TMB2193MS100 is compatible
with other Fairchild Demo boards. Typical configurations
are the TMC2067P7C, the TMC2068P7C, and the
TMB2193MS100 or the TMB0001MS100 and the
TMB2193MS100. The first configuration requires an analog
composite or S-video input and supplies a re-encoded analog
composite or S-video output. The later requires a parallel
D1 input and supplies an encoded analog composite or
S-video output.
The TMC2193 can be operated in D1, Genlock or Master
mode. In the D1 mode the synchronization is derived from
the TRS codes embedded in the D1 data stream. The
TMB2193MS100 has the TMC2072 Genlock front end,
which supplies the HSYNC, VSYNC and subcarrier infor-
mation to the TMC2193 for the Genlock operation of the
encoder. In Master mode the synchronization is driven by
the TMC2193, supplying the line (HSYNC) and field
(VSYNC or BnT) synchronization signals. With the
TMC2193 running in Master mode the TMB2193MS100
demo board interfaces directly to either a MPEG decoder or
a video framestore with no additional glue logic.
The TMB2193MS100 has an onboard microcontroller
(MCU) to program the TMC2193, the TMC2072, and to
configure the FPGA. All the default register maps are held
within the MCU. Table 1 provides a description of each of
the default register maps. A control register map is written to
the TMC2193, the TMC2072, and to Port 2 of the MCU each
time the MRST\ button is pressed. The MCU determines
which map to load from the PROG[3-0] (Px) dip switches.
The TMC2193, 2072 and the MCU can also be dri v en by the
Raydemo software. The interface is provided by the RBUS
connector on the TMB2193MS100 and the TMC2070P7C
R-Bus interface board. With this setup the user can config-
ure the TMC2193, the TMC2072 and the MCU with any
IBM compatible PC.
Table 1. Default Control Register Maps
P3 P2 P1 P0 Format Mode Source Output Mode
0 0 0 0 NTSC MASTER Mod. Ramp Composite, S-Video
0 0 0 1 NTSC MASTER 75% CB Composite, YPBPR
0 0 1 0 NTSC MASTER 100% CB Composite, RGB
0 0 1 1 NTSC D1 D1 Composite, YPBPR
0 1 0 0 NTSC D1 D1 Composite, RGB
0 1 0 1 NTSC D1 D1 DCVBS
0 1 1 0 NTSC Genlock 601 Composite, YPBPR
0 1 1 1 NTSC Genlock 601 Composite, RGB
1 0 0 0 PAL MASTER Mod. Ramp Composite, S-Video
1 0 0 1 PAL MASTER 75% CB Composite, YPBPR
1 0 1 0 PAL MASTER 100% CB Composite, RGB
1 0 1 1 PAL D1 D1 Composite, YPBPR
1 1 0 0 PAL D1 D1 Composite, RGB
1 1 0 1 PAL D1 D1 DCVBS
1 1 1 0 PAL Genlock 601 Composite, YPBPR
1 1 1 1 PAL Genlock 601 Composite, RGB
PRODUCT SPECIFICATION TMB2193MS100
3
Preliminary Information
CPLD Description
The Altera 10K20 CLPD functions as the central matrix for
routing the buses to the TMC2193. Eight (8) control pins are
connected from port 2 of the MCU to the CLPD. These pins
are used to configure the CPLD and are broken up into 2
buses: FPGA control1 is on pins P2[7:4] and FPGA control2
is on pins P2[3:0]. The 10K20 default configuration routes
the 3 buses from the input edge connector and the bus from
the framestore header to the pixel data (PD[23:0]) port of the
TMC2193. This enables the various input formats of the
TMC2193 to be supported. In addition, the PD input can be
delayed in respect to the HSIN and VSIN for proper data
alignment. Table 2 describes the function of the pixel data
formatting.
The FPGA Control 2 bus selects which subcarrier reference
signal to be used; either the GRS from the TMC2072 or the
xRS signal from bus B of the input edge connector. FGPA
Control 2 also selects which set of synchronization signals
are to used; either the IXHSYNC and IXVSYNC from the
input edge connector or the TMC2072 GHSYNC and
GVSYNC.
FPGA Controls 1 and 2 can be accessed by the Raydemo
software. The dialog box exists in the MCU icon of the
TMB2193MS100 window. The functions of these controls
are purposely left generic to allow for the reconfiguration of
the CPLD.
The 10K20 utilization is approximately 20% of the av ailable
logic cells. This allows for additional functions to be
implemented in the 10K20 such as notch filters, interpolation
filters for 4:2:2 to 4:4:4 conversion, simple comb filtering
and ancillary data insertion. These are just some of the
possibilities.
Table 2. FPGA Control 1
FGPA
Control1 bit# Function Description
3-2 PDMODE PD Input
00 10-bit format, A bus
01 20-bit format, C and
B buses
10 24-bit format, C, A,
and B buses
11 10-bit format, A bus
delayed
1-0 PDDEL PD delay
00 0 pxck’s of delay
01 1 pxck’s of delay
10 2 pxck’s of delay
11 3 pxck’s of delay
Table 3. FPGA Control 2
FGPA
Control2 bit# Function Description
3-2 No Modes
1 REFSEL CVBS Input
0 B[5:2] bus
1 GENLOCK
0 SYNCSEL HSIN, VSIN Input
0 IXH and IXV
1 GH and GV
Table 4. Switch, Button, and Jumper Description
Button Description
MRST Resets the AT89C55. When the GLOBAL RESET jumper is in place, the reset line on all
boards connected to the TMB2193MS100 are driven by MRST.
Jumpers Description
GLOBAL RESET When GLOBAL RESET is open, only the TMC2193, the TMC2072, the framestore header
and the AT89C55 receive the reset pulse from MRST. When GLOBAL RESET is closed,
the reset line on all boards connected to the TMB2193MS100 are driven by MRST.
CASC INT Cascade Programming Enable.
When CASC INT is open, the AT89C55 automatically initializes the devices after reset.
When CASC INT is closed, the AT89C55 will wait for a LOW pulse on the PGM_IN pin
before initializing the devices on the TMB2193MS100.
RBUSEN When RBUSEN is open, the RBUS port is disabled.
When RBUSEN is closed, the RBUS port is enabled.
TMB2193MS100 PRODUCT SPECIFICATION
4
Preliminary Information
Setup Procedure
Set E1 to MPXCK and E2 to PASS, enable the onboard TTL
clock oscillator as the clock source.
1. Set ESA1-0 to ON (down).
2. Set P3-0 to 0h, P3 is ON (down), P2 is ON (do wn), P1 is
ON (down), and P0 is ON (down).
3. Plug in power supply connector and apply power. The
LED’s corresponding to +5 Volts and -5 Volts should be
illuminated.
4. Reset board by pressing the MRST button.
5. Connect a scope probe to TP25 and adjust R39 until the
sync to blank amplitude is 286 mV.
6. Connect a scope probe to TP19 and adjust R36 until the
sync to blank amplitude is 286 mV.
7. Connect a scope probe to TP21 and adjust R37 until the
sync to blank amplitude is 286 mV.
8. Connect a scope probe to TP23 and adjust R38 until the
burst amplitude is 286 mV.
Power Supply Requirements
The TMB2193MS100 board requires 1.5 Amps from the +5
Volt power supply and 0.5 Amps from the -5 Volt power sup-
ply. Both the +5 Volt and -5 Volt supplies are connected to
the input connector to supply the power requirements of any
upstream board. The +5 Volt power supply not only drives
TTL logic devices but it also provides the power and v oltage
references to the D/A’s in the TMC2193. Therefore, it is rec-
ommended that a bench power supply be used with the cable
lengths kept to a minimum.
JP20, JP21, JP22,
JP23 When JPx is open, the output video is a single 75Ohm termination.
When JPx is closed, the output video is a double 75Ohm termination.
Switches Description
E1 Onboard Clock Selection.
Selects either the PXCK from the TMC2072 or the onboard TTL clock oscillator.
E2 Master Clock Selection.
When Pass is selected the clock source for the entire board is either the TMC2072 PXCK
or the TTL clock oscillator. When IXPCK is selected the clock source for the entire board
is the PXCK from the input header.
E3 Output Header Clock Selection.
Selects either PXCK or PXCK for the output header.
Dip Switches Description
SA1-0 Configures the bits 2 and 1 of the TMC2193 RBUS chip address. When SAx is ON
(down), ESAx is in a LOW state. When SAx is OFF (up), ESAx is in a HIGH state.
CAS Configures the bit 2 of the TMC2072 RBUS chip address. When CAS is ON (down),
GSA1 is in a LOW state. When CAS is OFF (up), GSA1 is in a HIGH state.
ERS Configures the bit 1 of the TMC2072 RBUS chip address. When ERS is ON (down),
GSA0 is in a LOW state. When ERS is OFF (up), GSA0 is in a HIGH state.
P3-0 Control Register Programming.
P3-0 selects which control register map to configure the devices with. Refer to Table 1
Default Control Register Maps for a description.
Table 4. Switch, Button, and Jumper Description (continued)
Button Description
PRODUCT SPECIFICATION TMB2193MS100
5
Preliminary Information
Figure 1.
TMB2193 0.9.0
TOP
Raytheon Electronics - Semiconductor Division
5580 Morehouse Dr.
San Diego, CA 92121
B
112Thursday, September 04, 1997
Title
Size Document Number Rev
Date: Sheet of
CKDRIVE
CKDRIVE
MPXCK
EPXCK
FPXCK
OPXCK
GPXCK
IXPXCK
675MCLK
135MCLK
HEADERIN
HEADERIN
IXHSYNC
IXVSYNC
IXPXCK
MPXCK
SDA
SCL
HSOUT
VSOUT PGM_IN
A_DEL[0..9]
B[0..9]
C[0..9]
RESET
FRESET
A[0..9]
FPGA
FPGA
A_DEL[0..9]
B[0..9]
C[0..9]
CVBS[0..7]
GHSYNC
GVSYNC
IXHSYNC
IXVSYNC
PD[0..23]
ECVBS[0..9]
HSIN
VSIN
OLENG[0..5]
FMCU[0..7]
IXPXCK
FPXCK
675MCLK
A[0..9]
GENLOCK
GENLOCK
CVBS[0..7]
SDA
SCL
GHSYNC
GVSYNC
GPXCK
GMCU[0..6]
MCU
MCU
EMCU[0..3]
GMCU[0..6]
SDA
PGM_OUT
FMCU[0..7]
PGM_IN
SCL FRESET
135MCLK RESET
VSOUT
HEADEROUT
HEADEROUT
HSOUT
VSOUT
DCVBS[0..9]
SDA
SCL
RESET
OPXCK
PGM_OUT
TMC2193
TMC2193
PD[0..23]
ECVBS[0..9]
EPXCK
HSIN
VSIN
DCVBS[0..9]
HSOUT
VSOUT
SDA
SCL
OLENGI[0..5]
EMCU[0..3]
POWER
{Schematic}
A_DEL[0..9]
B[0..9]
C[0..9]
CVBS[0..7]
IXHSYNC\
IXVSYNC\
GHSYNC
GVSYNC
GPXCK
IXPXCK
IXPXCK
FPXCK
MPXCK
PD[0..23]
ECVBS[0..9]
OLENG[0..5]
DCVBS[0..9]
HSIN OPXCK
GMCU[0..6]
FMCU[0..7]
PGM_IN
RESET\
PGM_OUT
FRESET\
VSIN
HSOUT
SDA
VSOUT
EMCU[0..3]
EPXCK
SCL
A[0..9]
675MCLK
135MCLK
65-B2193-02
TMB2193MS100 PRODUCT SPECIFICATION
6
Preliminary Information
Figure 2.
Friday, February 07, 1997
TMB2193 0.9.0
CKDRIVE.SCH
Raytheon Electronics - Semiconductor Division
5580 Morehouse Drive
San Diego, CA 92121
(619) 457-1000
B
912
Title
Size Document Number Rev
Date: Sheet of
VCC
VCC
VCC
PLACE COMPONENTS ON THIS
PAGE CLOSE TO THE
GENLOCK.
GPXCK
MPXCK
IXPXCK PASS MPXCK
FPCXK
EPXCK
OPXCK
C1
0.1µF
U2A
74F14
12
U1A
74F240
A1
2
A2
4
A3
6
A4
8
G
1
Y1 18
Y2 16
Y3 14
Y4 12
U1B
74F240
A1
11
A2
13
A3
15
A4
17
G
19
Y1 9
Y2 7
Y3 5
Y4 3
E2
SELECT
Y1
27MHz
OUT 5
E1
SELECT
U10A
74F74
D
2
CLK
3Q5
Q6
PR 4
CL
1
U10B
74F74
D
12
CLK
11 Q9
Q8
PR 10
CL
13
MPXCK
EPXCK
FPXCK
OPXCK
GPXCK
IXPXCK
135MCLK
675MCLK
VCC
C2
0.1µF
C3
0.1µF
65-B2193-03
PRODUCT SPECIFICATION TMB2193MS100
7
Preliminary Information
Figure 3.
TMB2193 0.9.0
FPGA.SCH
Raytheon Electronics - Semiconductor Division
65-B2193-04
5580 Morehouse Dr.
San Diego, CA 92121
B
312Thursday, September 04, 1997
Title
Size Document Number Rev
Date: Sheet of
VCC
VCC
BYTE
BLASTER
GHSYNC
GVSYNC
IXHSYNC\
IXVSYNC\
VSIN
HSIN
IXPXCK
FPXCK
CVBS5
CVBS3
CVBS6
PD22
PD20
B8
B0
B1
PD21
PD4
PD2
OLENG5 PD20
PD12
PD7
PD18
CVBS7
B5
B7
B6
B4
ECVBS2
A6
A_DEL6
A8
OLENG4
A_DEL7
C9
PD19
PD14
FMCU7
C7
C6
C5
C4
PD9
PD8
FMCU0
C8
GHSYNC
PD9
PD23
FMCU1
C3
C2
C1
C0
PD6
PD5
PD23
PD7
PD4
VSIN
ECVBS6
C4
A9
IXHSYNC\
GVSYNC
PD16
PD22
PD21
PD3
PD1
FMCU1
PD2
ECVBS7
ECVBS8
ECVBS9
ECVBS4
HSIN
IXVSYNC\
OLENG3
A_DEL4
B3
FMCU2
CVBS7
ECVBS5
FPXCK
C7
OLENG1
OLENG2
CVBS6
CVBS0
FMCU5
B2
C9 PD10
OLENG0
CVBS1
FMCU3
C8
PD0
B8
B9
A5
B0
A0
PD11
PD17
CVBS4
PD10
B7
A_DEL9
A_DEL5
A_DEL3
A3 C1
B4
A_DEL8
A_DEL0
A_DEL1
FMCU3 B5
B6A7
B1
CVBS2
CVBS0
FMCU4
CVBS1
FMCU6
B3
C0
C6
FMCU5
C3
B2
FMCU2
CVBS2
FMCU7
PD19
A2
A4
CVBS5
PD16
PD17
PD15
PD18
PD8
FMCU4
FMCU6
PD13
FMCU0
B9 PD14
PD11
PD12
C2
ECVBS3
PD1
PD5
PD15
CVBS3
CVBS4
C5
A1
PD3
PD0
PD13
PD6
OLENG1
OLENG5
OLENG2
OLENG0
OLENG4
OLENG3
A_DEL5
A8
A4
A9
A_DEL7
A_DEL9
A_DEL0
A_DEL4
A_DEL1
A3
A_DEL8
A2
A6
A7
A1
A_DEL3
A5
A_DEL2
A0
A_DEL6
ECVBS9
ECVBS5
ECVBS4
ECVBS7
ECVBS0
ECVBS2
ECVBS6
ECVBS3
ECVBS8
ECVBS1
A_DEL2
U4
EPC1PC8
DATA 1
DCLK
2
OE
3
nCS
4nCASC 6
C10
0.1µF
R5
1K
U11
EPF10K10TC144
MSEL0
77
MSEL1
76
nSTATUS
35
nCONFIG
74
DCLK
107
CONF_DONE
2
INIT_DONE
14
nCE
106
nCEO
3
nWS
142
nRS
141
nCS
144
CS
143
RDYnBSY
11
CLKUSR
7
DATA7
116
DATA6
114
DATA0
108 DATA1
109 DATA2
110 DATA3
111 DATA4
112 DATA5
113
TDI
105
TDO
4
TCLK
1
TMS
34
DEDIN
54
DEDIN
56
DEDIN
124
DEDIN
126
GCLK0
125
GCLK1
55
DEV_CLRn
122
DEV_OE
128
8
8
9
9
10
10
12
12
13
13
18
18
19
19
20
20
21
21
22
22
23
23
26
26
27
27
28
28
29
29
30
30
31
31
32
32 33 33
36 36
37 37
38 38
39 39
41 41
42 42
43 43
44 44
46 46
47 47
48 48
49 49
51 51
59 59
60 60
62 62
63 63
64 64
65 65
67 67
68 68
69 69
70 70
72 72
73 73
78 78
79 79
80 80
81 81
82 82
83 83
86 86
87 87
88 88
89 89
90 90
91 91
92 92
95 95
96 96
97 97
98 98
99 99
100 100
101 101
102 102
117 117
118 118
119 119
120 120
121 121
130 130
131 131
132 132
133 133
135 135
136 136
137 137
138 138
140 140
17
17
JP1
HEADER 5X2
12 34 56 78 910
B[0..9]
C[0..9]
CVBS[0..7]
GHSYNC
GVSYNC
IXHSYNC\
IXVSYNC\
PD[0..23]
ECVBS[0..9]
HSIN
VSIN
FMCU[0..7]
IXPXCK
FPXCK
OLENG[0..5]
A_DEL[0..9]
A[0..9]
675MCLK
VCC
C19
0.1µF
R4
1K
R3
1K
R2
1K
R1
1K
C11
0.1µFC12
0.1µFC13
0.1µFC14
0.1µF
C4
0.1µFC5
0.1µFC6
0.1µFC7
0.1µFC8
0.1µFC9
0.1µF
TMB2193MS100 PRODUCT SPECIFICATION
8
Preliminary Information
Figure 4.
Monday, January 20, 1997
TMB2193 0.9.0
GENLOCK.SCH
Raytheon Electronics - Semiconductor Division
5580 Morehouse Drive
San Diego, CA 92121
(619) 457-1000
B
212
Title
Size Document Number Rev
65-B2193-05
Date: Sheet of
VCC
VCC
VCC
VCC VCC
STUFF EITHER
C36 OR CR1
STUFF: A for TMC2072
B for TMC22071A
SDA
GD0
GCS
GSA0
GRW\
GVSYNC
GSA1
GRESET\
GHSYNC
GHSYNC
GVSYNC
GPXCK
GPXCK
CVBS6
CVBS3
CVBS7
CVBS[0..7]
DGND
CVBS0
GND
CVBS4
CVBS1
CVBS5
AGND
CVBS2
GSA1GMCU5 GD0GMCU4 GRW\GMCU3
GSA0GMCU6
GA0GMCU2 GCSGMCU1 GRESET\GMCU0
GA0
20MCLK
+
C29
22µF/6.3V
+
C30
22µF/6.3V
R16
33
R10
33
R8
220
U5
TMC22071AKHC(2072KHC)_2
VIN1
65
VIN2
61
VIN3
58
D0
9
NC
12
(SA2)
3
CS (SCL)
5
EXT PXCK
94
LDV 40
NC 85
NC
19
NC
20
CVBS0 21
CVBS1 22
CVBS5 28
CVBS7 30
GHSYNC 32
GVSYNC 33
VALID 34
NC
13
NC
76
VREF 70
COMP 88
RT 68
RB 57
NC 83
CBYP 75
PFD IN 77
NC
10
NC
14
CVBS4 25
NC
66
NC
43
CLK IN
91
CVBS2 23
PXCK 45
CLK OUT
93
NC 99
A0 (SA0)
1
(SA1)
2
RESET
7
NC
11
NC
15
INT 17
CVBS3 24
CVBS6 29
(BURL) 31
NC
71
NC
53
NC
54 NC 56
NC 59
NC 62
(FID2) 37
(FID1) 36
(FID0) 35
NC 78
NC 79
NC 80
DDS OUT 82
NC 84
PXCK SEL
86
R/W (SDA)
4
R6
75
R15
33
R7
75
R9
75
L1
10µH
H1
1
TP1
VID_IN
R11
3.3K
R14
4.75K
R13
4.75K
R12
4.75K
H3 1C33
6.8pF
C40
390pF
C36
0.1uF
C39
150pF
C37
0.1µF
C35
0.1uF
C34
0.1uF
C38
0.1µF
C31
0.1uF
C23
0.1µF
C24
0.1µF
C25
0.1µF
C26
0.1µF
C27
0.1µF
C28
0.1µF
C22
0.1µF
C21
0.1µF
C20
0.1µF
JP3
A
JP4
A
JP5
A
JP6
B
JP7
B
JP8
B
H2
1
TP2
GH TP3
GV TP4
GPXCK
J1
BNC 1
2
CR1
1.235V
2 1
Y2
20MHz
OUT 5
H5
PTH
1
H6
PTH
1
H7
PTH
1
H8
PTH
1
CVBS[0..7]
SDA
SCL
GHSYNC
GVSYNC
GPXCK
GMCU[0..6]
VCC
C32
0.1µF
PRODUCT SPECIFICATION TMB2193MS100
9
Preliminary Information
Figure 5.
TMB2193 0.9.0
65-B2193-06
B
412Thursday, September 04, 1997
Title
Size Document Number Rev
Date: Sheet of
VCC
10 BIT FRAMESTORE
A7
A8
A0
A2
A[0..9]
A9
A1
A3
A5
A4
A6
A_DEL[0..9]
A_DEL9
A_DEL5
A_DEL4
A_DEL2
A_DEL8
A_DEL0
A_DEL6
A_DEL7
A_DEL1
A_DEL3
P1
SIMM72
22
33
44
55
66
77
88
99
GND
1
VDD 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
GND
19
28 28
29 29
VDD 30
31 31
32 32
33 33
34 34
35 35
36 36
37 37
38 38
GND
39 40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
VDD 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
VDD 59
60 60
61 61
62 62
63 63
64 64
65 65
66 66
67 67
68 68
69 69
70 70
71 71
GND
72
IXHSYNC\
IXVSYNC\
A[0..9]
SCL
IXPXCK
FRESET\
VSOUT
HSOUT
MPXCK
SDA A_DEL[0..9]
TMB2193MS100 PRODUCT SPECIFICATION
10
Preliminary Information
Figure 6.
TMB2193 0.9.0
65-B2193-07
HEADERIN.SCH
Raytheon Semiconductor - La Jolla
San Diego, CA92121
(619) 457-1000
B
10 12Thursday, September 04, 1997
5580 Morehouse Drive
Title
Size Document Number Rev
Date: Sheet of
FS_CONN
{Value}
IXHSYNC
IXVSYNC
A[0..9]
SCL
IXPXCK
FRESET
VSOUT
HSOUT
MPXCK
SDA
A_DEL[0..9]
+12V
VCC
-12V
-5V -5V
MPXCK
VSOUT
HSOUT
IMASTER/SLAVE
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
IXVSYNC\
IXHSYNC\
RESET\
SCL
SDA
PGM_IN
IXPXCK
IXVSYNC\
IXHSYNC\
IXPXCK
MPXCK
RESET\
SCL
SDA
HSOUT
VSOUT
PGM_IN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
B0
B6
B8
B7
B3
B4
B5
B1
B9
B2
A[0..9]
A0
A6
A8
A7
A3
A4
A5
A1
A9
A2
SCL
SDA
IXHSYNC\
IXVSYNC\
IXPXCK
HSOUT
VSOUT
MPXCK
P2A
EURO96F
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
31 31
32 32 P2B
EURO96F
133
234
335
436
537
638
739
840
941
10 42
11 43
12 44
13 45
14 46
15 47
16 48
17 49
18 50
19 51
20 52
21 53
22 54
23 55
24 56
25 57
26 58
27 59
28 60
29 61
30 62
31 63
32 64 P2C
EURO96F
165
266
367
468
569
670
771
872
973
10 74
11 75
12 76
13 77
14 78
15 79
16 80
17 81
18 82
19 83
20 84
21 85
22 86
23 87
24 88
25 89
26 90
27 91
28 92
29 93
30 94
31 95
32 96
R17
10K
IXHSYNC\
IXVSYNC\
IXPXCK
MPXCK
SDA
SCL
HSOUT
VSOUT
PGM_IN
A_DEL[0..9]
B[0..9]
C[0..9]
RESET\
FRESET\
A[0..9]
PRODUCT SPECIFICATION TMB2193MS100
11
Preliminary Information
Figure 7.
Wednesday, January 22, 1997
TMB2193 0.9.0
65-B2193-08
HEADEROUT.SCH
Raytheon Electronics - Semiconductor Division
5580 Morehouse Drive
San Diego, CA92121
(619) 457-1000
B
612
Title
Size Document Number Rev
Date: Sheet of
+12V
VCC -5V -12V
96 WAY EDGE CONNECTIONS FROM THE TMC2193 BOARD
PXCK\
PXCK
HSOUT
VSOUT
SDA
SCL
RESET\
PXCK4
PXCK4
VSOUT
HSOUT
SCL
SDA
DCVBS0
DCVBS1
DCVBS2
DCVBS3
DCVBS4
DCVBS5
DCVBS6
DCVBS7
DCVBS8
DCVBS9
DCVS[0..9]
PGM_OUT
PGM_OUT RESET\
P3A
EURO96M
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
P3B
EURO96M
1
33
2
34
3
35
4
36
5
37
6
38
7
39
8
40
9
41
10
42
11
43
12
44
13
45
14
46
15
47
16
48
17
49
18
50
19
51
20
52
21
53
22
54
23
55
24
56
25
57
26
58
27
59
28
60
29
61
30
62
31
63
32
64
P3C
EURO96M
1
65
2
66
3
67
4
68
5
69
6
70
7
71
8
72
9
73
10
74
11
75
12
76
13
77
14
78
15
79
16
80
17
81
18
82
19
83
20
84
21
85
22
86
23
87
24
88
25
89
26
90
27
91
28
92
29
93
30
94
31
95
32
96
U2B
74F14
3 4
E3
SELECT
HSOUT
VSOUT
DCVBS[0..9]
SDA
SCL
RESET\
OPXCK
PGM_OUT
TMB2193MS100 PRODUCT SPECIFICATION
12
Preliminary Information
Figure 8.
TMB2193 0.9.0
65-B2193-09
LPF.SCH
Raytheon Electronics - Semiconductor Division
5580 Morehouse Dr.
San Diego, CA 92121
A
11 12Thursday, September 04, 1997
Title
Size Document Number Rev
Date: Sheet of
VDD
R18
75 Ohm
D1
DIODE SCHOTTKY
D2
DIODE SCHOTTKY
A_IN A_OUT
PRODUCT SPECIFICATION TMB2193MS100
13
Preliminary Information
Figure 9.
TMB2193 0.9.0
65-B2193-10
MCU.SCH
Raytheon Electronics - Semiconductor Division
5580 Morehouse Dr.
San Diego, CA 92121
B
812Friday, September 19, 1997
Title
Size Document Number Rev
Date: Sheet of
VCC VCC VCC
VCC
VCC
VCC
VCC
VCC
VCC
UART
PLACE NEAR
STANDOFF
SA1
SA0
CAS
ERS
P0
P1
P2
P3
EMCU0 ERESET\
EMCU1 EDCVBSEN\
EMCU2 ESA1
EMCU3 ESA0
RESET\
MRESET\
MRESET\
RXD
TXD
RXD
TXD
SCL
SDA
GD0
GRW\
GAO
GCS
FMCU0
FMCU1
FMCU2
FMCU3
FMCU4
FMCU5
FMCU6
FMCU7
FMCU[0..7]
SCL
SDA
SCL
SDA
PROG0
PROG1
PROG2
PROG3
PGM_OUT PGM_OUT
PGM_IN
ERESET\
EDCVBSEN\
GRESET\
FRESET\ PGM_IN
CAS_PROGEN
CAS_PROGEN
FRESET\
135MCLK
135MCLK
RESET\
ESA0
ESA1
PROG1
PROG3
VSOUT
VSOUT
GSA1
GCSGMCU1
GSA1GMCU5
GRW\GMCU3 GA0GMCU2
GD0GMCU4
GSA0
PROG0
GRESET\GMCU0
GSA0GMCU6
PROG2
R21
10K
R20
4K7
S1
MRST
JP10
UART
1
2
3
4R23
10K R24
10K
U7
AT89C55 44 PIN PLCC
P0.0
43
P0.1
42
P0.2
41
P0.3
40
P0.4
39
P0.5
38
P0.6
37
P0.7
36
P1.0
2
P1.1
3
P1.2
4
P1.3
5
P1.4
6
P1.5
7
P1.6
8
P1.7
9
P2.0 24
P2.1 25
P2.2 26
P2.3 27
P2.4 28
P2.5 29
P2.6 30
P2.7 31
P3.0 11
P3.1 13
P3.2 14
P3.3 15
P3.4 16
P3.5 17
P3.6 18
P3.7 19
XTAL2
20
XTAL1
21
RST
10
EA/VPP 35
ALE/PROG 33
PSEN 32
NC 1
NC 12
NC 23
NC 34
C41
10.0µF/16V
R22
4K7
R19
1OHM, 1/4W C
JP11
CASCADE INIT
JP9
RBUSEN
C42
0.1µF
U2C
74F14
5 6
U2D
74F14
9 8
SCL
+5V
SDA
GND
P4
15-83-0064
4
3
2
1
D3
GREEN
21
H4
135MCLK
1
R49
10K
S2
SW DIP-8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R50
10K R51
10K R52
10K R53
10K R54
10K R55
10K R56
10K
FB3
F BEAD
H9 1
H10 1
H11
1H12
1
C43
0.1µF
EMCU[0..3]
GMCU[0..6]
SDA
PGM_OUT
FMCU[0..7]
PGM_IN
FRESET\
135MCLK
SCL
RESET\
VSOUT
TMB2193MS100 PRODUCT SPECIFICATION
14
Preliminary Information
Figure 10.
Thursday, January 23, 1997
TMB2193 0.9.0
POWER.SCH
Raytheon Electronics - Semiconductor Division
5580 Morehouse Drive
San Diego, CA92121
(619) 457-1000
B
12 12
Title
Size Document Number Rev
Date: Sheet of
VDD VDDA VCC +5V
-5V
DGND AGND
VEE
Ground T est Points
P5V
GND
N5V
C47
0.01µF
50V
C46
0.1µF
50V
C50
0.1µF
50V
C51
0.01µF
50V
TP11
GND TP12
GND TP13
GND TP14
GND TP15
GND
FB1
F BEAD
FB2
F BEAD
+C44
22µF
35V
+C45
0.47µF
35V
+C48
22µF
35V
+C49
0.47µF
35V
TP9
+5V
TP10
-5V
CR3
1N4004
2 1
CR4
1N4004
2 1
CR2
RED
LED
21
CR5
ORANGE
LED
21
JP12
POWER3
1
2
3
PRODUCT SPECIFICATION TMB2193MS100
15
Preliminary Information
Figure 11.
TMB2193 0.9.0
65-B2193-12
MMC
A
712Thursday, September 04, 1997
Title
Size Document Number Rev
Date: Sheet of
VCC
D IS150 OHM (1%)
DO NOT STUFF
A2XEN
B2XEN
C2XEN
D2XEN
NC1EN
NC2EN
ALL 1%
R41
DR42
DR43
DR44
D
JP14
JUMPER
JP15
JUMPER
JP16
JUMPER
JP17
JUMPER
JP18
JUMPER
JP19
JUMPER
JP20
JUMPER
R45
75 R46
75 R47
75 R48
75
JP21
JUMPER JP22
JUMPER JP23
JUMPER
U9
ST-163E
AIN
1
BIN
12 CIN
13 DIN
24
A2X
4
C2X
16 B2X
9
D2X
21
AOUT 5
BOUT 8
COUT 17
DOUT 20
NC1
7
NC2
18
R57
10K R58
10K R59
10K R60
10K R61
10K R62
10K
AOUT
AIN
CIN COUT
BOUT
DOUT
BIN
DIN
TMB2193MS100 PRODUCT SPECIFICATION
16
Preliminary Information
Figure 12.
TMB2193 0.9.0
65-B2193-13
TMC2193.SCH
Raytheon Electronics - Semiconductor Division
5580 Morehouse Dr.
San Diego, CA 92121
B
512Thursday, September 04, 1997
Title
Size Document Number Rev
Date: Sheet of
LPF {Schematic}
A_IN A_OUT
MMC
{Schematic}
AOUT
DOUT
BOUT
COUTCIN
BIN
DIN
AIN
VDD
VCC
VCC
VDD
VDD
CONNECT Cx TO VDDA PIN
AND CBYPy PIN DIRECTLY
STUFF EITHER C54 OR D4
PD[0..23]
OLENG[0..5]
DCVBS3
PD2
PD14
PD18
DCVBS1
DCVBS4
DCVBS6
HSOUT
ECVBS1
PD19
OLENG3
ECVBS9
PD22
PD23
DCVBS5
PD20
PD11
ECVBS[0..9]
PD13
ECVBS0
PD4
PD12
DCVBS2
SCL
PD7
PD8
PD3
PD5
PD16
OLENG2
VSOUT
ECVBS4
ECVBS3
ECVBS2
DCVBS9
PD21
ECVBS8
SDA
PD6
OLENG4
DCVBS0
DCVBS7
ECVBS6
ECVBS5
DCVBS[0..9]
PD0
PD9
DCVBS8
ECVBS7
PD17
PD1
PD15
OLENG0
OLENG1
OLENG5
PD10
EMCU[0..3]
ESA0EMCU3
EDCVBSEN\EMCU1
ESA1EMCU2
EMCU0 ERESET\
R32
8.25K Ohm
R33
8.25K Ohm R35
8.25K Ohm
R31
10K Ohm
R28
10K Ohm
R29
10K Ohm
R40
4K7
TP27
VSOUT TP28
HSOUT
TP26
PXCK TP29
HSIN TP30
VSIN
JP13
1
2
3
4
5
6
7
8
C58
0.1uF
C57
0.1uF
C56
0.1uF
TP16
RDA
TP18
DA1
TP20
DA2
TP22
DA3
TP24
DA4
TP17
ORDA
TP19
ODA1
TP21
ODA2
TP23
ODA3
TP25
ODA4
J2
RDAC
1
2
J3
DAC1
1
2
J4
DAC2
1
2
J5
DAC3
1
2
J6
DAC4
1
2
C55
0.1uF
C67
0.1uF
C63
0.1uF
C62
0.1uF C66
0.1uF
C65
0.1uF
C61
0.1uF C64
0.1uF C68
0.1uF
U8
TMC2193KHC
V_REF 98
VDDA 1
COMP2 2
C_BYB4 3
AGND
4
CH/R/P_R 5
C_BYB3 6
VDDA 7
R_REF3 8
AGND
9
Y/B/P_B 10
C_BYB2 11
VDDA 12
R_REF2 13
AGND
14
COMP/G/Y 15
C_BYB1 16
VDDA 17
R_REF1 18
REFDAC 19
KEY
20 OL4
21 OL3
22 OL2
23 OL1
24 OL0
25
DGND
26
PD23
27 PD22
28 PD21
29 PD20
30 PD19
31 PD18
32 PD17
33 PD16
34 PD15
35 PD14
36 PD13
37 PD12
38
VDD 39
DGND
40
PD11
41 PD10
42 PD9
43 PD8
44 PD7
45 PD6
46 PD5
47 PD4
48 PD3
49 PD2
50 PD0
52
PD1
51
VDD 54
VSIN
55 HSIN
56
SER
58
CS/SCL
59
R/W/SDA
60
A1/SA1
61
A0/SA0
62 D7 63
CVBS0
93
CVBS1
92
CVBS2
91
CVBS3
90
CVBS4
89
CVBS5
88
CVBS6
87
CVBS7
86
CVBS8
85
CVBS9
84
PXCK
95
PDC
73
HSOUT
74
VSOUT
75
DCVEN
57
RESET
94
D0 70
DGND
71
VDD 72
LINE4 76
LINE3 77
D6 64
D5 65
D4 66
D3 67
D2 68
D1 69
FLD0 83
FLD1 82
FLD2 81
LINE0 80
LINE1 79
LINE2 78
R_REF4 99
AGND
100
VDD 96
DGND
53
DGND
97
R37
10K Pot
13
2
R36
10K Pot
1
3
2
R39
10K Pot
1
3
2
R34
8.25K Ohm
R30
10K Ohm
R38
10K Pot
1
3
2
C54
0.1uF D4
1.235V
2 1
R27
3.3K Ohm
PD[0..23]
ECVBS[0..9]
EPXCK
HSIN
VSIN
DCVBS[0..9]
HSOUT
VSOUT
SDA
SCL
OLENGI[0..5]
EMCU[0..3]
PRODUCT SPECIFICATION TMB2193MS100
17
Preliminary Information
Table 5. TMB2193MS100 Parts List
Item Quantity Reference Part
Number Manufacturer Description
1 48 C1 C2 C3 C4 C5 C6 C7 C8
C9 C10 C11 C12 C13 C14
C19 C20 C21 C22 C23
C24C25 C26 C27 C28 C31
C32 C34 C35 C36 C37 C38
C42 C43 C46 C50 C54 C55
C56 C57 C58 C61 C62 C63
C64 C65 C66 C67 C68
MiniReel: 605-611 0.1mF (0805 FP)
2 2 C29 C30 Minireel 22mF/6.3v (D FP)
3 1 C33 MiniReel: 605-168 6.8pF (0805 FP)
4 1 C39 MiniReel: 605-315 150pF (0805 FP)
5 1 C40 MiniReel: 605-339 390pF (0805 FP)
6 1 C41 MiniReel: 642-810 10.0mF/16V (B FP)
7 2 C44 C48 MiniReel: 645-823 22mF/25v (D FP)
8 2 C45 C49 MiniReel: 641-647 0.47mF/25v (A FP)
9 2 C47 C51 MiniReel: 605-510 0.01mF (0805 FP)
10 5 R1 R2 R3 R4 R5 MiniReel: 615-410 1K (0805 FP)
11 7 R6 R7 R9 R45 R46 R47
R48 MiniReel: 615-275 75 (0805 FP)
12 1 R8 MiniReel: 615-822 220 (0805 FP)
13 3 R10 R15 R16 MiniReel: 615-844 33 (0805 FP)
14 1 R11 MiniReel: 615-844 3.3K (0805 FP)
15 3 R12 R13 R14 MiniReel: 615-447 4.75K (0805 FP)
16 18 R17 R21 R23 R24 R49 R50
R51 R52 R53 R54 R55 R56
R57 R58 R59 R60 R61 R62
MiniReel: 615-510 10K (0805 FP)
17 1 R18 MiniReel: 615-275 75 (0805 FP)
18 1 R19 ROHM 1 OHM, 1/4W Carbon
19 3 R20 R22 R40 MiniReel: 615-848 4.7k (0805 FP)
20 1 R27 MiniReel: 615-844 3.3K Ohm (0805 FP)
21 4 R28 R29 R30 R31 MiniReel: 615-849 10K Ohm (0805 FP)
22 4 R32 R33 R34 R35 MiniReel: 615-415 8.25K Ohm (0805 FP)
23 4 R36 R37 R38 R39 Bourns 10K Pot (SMT)
24 4 R41 R42 R43 R44 150 (0805 FP)
25 1 L1 MiniReel 10uH (3225M FP)
26 3 FB1 FB2 FB3 Ferrite Ferrite Bead
27 2 CR1 D4 Linear Technology 1.235V Reference
28 2 D1 D2 Motorola Diode Schottky
29 2 CR3 CR4 MiniReel: 76-4004 Diode Rectifier
30 1 CR2 Hewlett Packard Red LED
31 1 CR5 Hewlett Packard Orange LED
32 1 D3 Hewlett Packard Green LED
35 1 JP1 Amp Header 5X2
TMB2193MS100 PRODUCT SPECIFICATION
18
Preliminary Information
36 6 JP9 JP11 JP20 JP21 JP22
JP23 Amp 2 Pin Header
37 1 JP10 Amp 4 Pin Header
38 1 JP13 Amp 8 Pin Header
39 1 P1 Amp 72 Pin Header
40 1 JP12 Beau Power, Plug Power,
Socket
41 6 J1 J2 J3 J4 J5 J6 Amphenol BNC
42 1 P2 Amp 96 Pin Euro Connector
(Female)
43 1 P3 Amp 96 Pin Euro Connector
(Male)
44 1 P4 Molex Rbus Connector
45 3 E1 E2 E3 Secma SPDT Switch
46 1 S1 ITT Canon SMT Push Button
Switch
47 1 S2 Alco 8 Position DIP Switch
48 21 TP1 TP2 TP3 TP4 TP9
TP10 TP16 TP17 TP18
TP19 TP20 TP21 TP22
TP23 TP24 TP25 TP26
TP27 TP28 TP29 TP30
Mouser Test Point
49 5 TP11 TP12 TP13 TP14
TP15 Bare Wire Ground Point
50 1 U1 Motorola 74F240
51 1 U2 Motorola 74F14
52 1 U4 Atmel Serial Eprom
53 1 U5 Fairchild Genlock
54 1 U7 Atmel Microprocessor
55 1 U8 Fairchild Encoder
56 1 U9 MMC Video Filter
ST-163E
57 1 U10 Motorola 74F74
58 1 U11 Altera FPGA
59 1 Y1 Ecliptec 27MHz
60 1 Y2 Ecliptec 20MHz
Table 5. TMB2193MS100 Parts List (continued)
Item Quantity Reference Part
Number Manufacturer Description
PRODUCT SPECIFICATION TMB2193MS100
19
Preliminary Information
Table 6. INPUT 96 Way Connector (Female)
row A row B row C
32 +5V 32 GND 32 +5V
31 D1 or R/V [bit 0] 31 +5V 31 GND
30 D1 or R/V [bit 1] 30 +5V 30 PXCK
29 D1 or R/V [bit 2] 29 +5V 29 GND
28 D1 or R/V [bit 3] 28 GND 28 PCK
27 D1 or R/V [bit 4] 27
Analog Composite/luma
27 GND
26 D1 or R/V [bit 5] 26 GND 26 CREF
25 D1 or R/V [bit 6] 25
Analog chroma
25 GND
24 D1 or R/V [bit 7] 24 XEN 24 VSYNC
23 D1 or R/V [bit 8] 23 GND 23 HSYNC
22 D1 or R/V [bit 9] 22 XDIR 22 HREF
21 Comp, G/Y, or Luma [bit 0] 21 XHSYNC 21 VREF
20 Comp, G/Y, or Luma [bit 1] 20 XVSYNC 20 ODD IN
19 Comp, G/Y, or Luma [bit 2] 19 XPXCK 19 GND
18 Comp, G/Y, or Luma [bit 3] 18 XRS [bit 3] 18 NTSC/PAL
17 Comp, G/Y, or Luma [bit 4] 17 XRS [bit 2] 17 CLAMP pulse
16 Comp, G/Y, or Luma [bit 5] 16 XRS [bit 1] 16 RGB
15 Comp, G/Y, or Luma [bit 6] 15 XRS [bit 0] 15
14 Comp, G/Y, or Luma [bit 7] 14 GND 14
13 Comp, G/Y, or Luma [bit 8] 13 -5V 13
12 Comp, G/Y, or Luma [bit 9] 12 -5V 12 LOCK
11 Chroma or B/U [bit 0] 11 -5V 11 D1
10 Chroma or B/U [bit 1] 10 GND 10 RESET
9 Chroma or B/U [bit 2] 9 PGM_IN 9 SCL
8 Chroma or B/U [bit 3] 8 -12V 8 GND
7 Chroma or B/U [bit 4] 7 -12V 7 SDA
6 Chroma or B/U [bit 5] 6 IE (input enable) 6 OE (output enable)
5 Chroma or B/U [bit 6] 5 GND 5 BLANK (DAC)
4 Chroma or B/U [bit 7] 4 4
3 Chroma or B/U [bit 8] 3 3
2 Chroma or B/U [bit 9] 2 +12V 2+12V
1GND 1GND 1GND
TMB2193MS100 PRODUCT SPECIFICATION
20
Preliminary Information
Input Edge Connector Design Notes
1. Boards with different revision letters may not be
compatible. Damage may occur if they are con-
nected together!
2. XPXCK is a two times pixel clock fed BACKWARD.
3. XHSYNC and XVSYNC are timing reference signals
fed BACKWARD.
4. The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed
FORWARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc.
5. XDIR is fed FOR WARD and controls in which direction
the XRS[3:0] data flows.
6. PGM_IN is a negative going pulse, logically ANDed
with the onboard program start pulse, for initiating the
programming sequence for components on that board.
Care must be taken to ensure that multiple devices do
not try to drive the RBUS at any given time. Minimum
width of PGM_IN is 1uS.
7. The RESET pin on the input edge connector should be
connected directly to the RESET pin on the output con-
nector . A link should be used to connect any pulse to the
RESET line.
8. The MASTER/SLAVE, XDIR, PGM_IN and RESET
pins on the input edge connector should be connected to
+5V through a 10k pull up resistor.
9. The CLAMP signal is fed BACKWARD from a
MASTER to a SLAVE board. The CLAMP signal
should not be fed FORWARD.
Y/Composite
LPF and
Clamp Circuit
Chrominance
BPF and
Clamp Circuit
TMC1185 TMC1185
SW1 SW1 +5V 0V -5V
2:1 MUX
65-B2193-14
10 bit
ADCs Digital
LPFs
TMC2242
EPROM FPGA
Signal Flow FORWARD
TMC2072
TMC3003
Low Quality
LPF
Low Quality
LPF
Low Quality
LPF
High Quality
LPF
High Quality
LPF
High Quality
LPF
TMC22153
DC Supply
Decoder
Input Logic
TMC2242
1
32
1
32
1
32
1
32
SW2
Signal Flow BACKWARD
PRODUCT SPECIFICATION TMB2193MS100
21
Preliminary Information
Table 7. OUTPUT 96 Way Connector (Male)
row A row B row C
1+5V 1GND 1+5v
2 D1 or R/V [bit 0] 2 +5V 2GND
3 D1 or R/V [bit 1] 3 +5V 3 PXCK
4 D1 or R/V [bit 2] 4 +5V 4GND
5 D1 or R/V [bit 3] 5 GND 5 PCK
6 D1 or R/V [bit 4] 6
Analog Composite/luma
6GND
7 D1 or R/V [bit 5] 7 GND 7 CREF
8 D1 or R/V [bit 6] 8
Analog chroma
8GND
9 D1 or R/V [bit 7] 9 XEN 9 VSYNC
10 D1 or R/V [bit 8] 10 GND 10 HSYNC
11 D1 or R/V [bit 9] 11 XDIR 11 HREF
12 Comp, G/Y, or Luma [bit 0] 12 XHSYNC 12 VREF
13 Comp, G/Y, or Luma [bit 1] 13 XVSYNC 13 ODD IN
14 Comp, G/Y, or Luma [bit 2] 14 XPXCK 14 GND
15 Comp, G/Y, or Luma [bit 3] 15 XRS [bit 3] 15 NTSC/PAL
16 Comp, G/Y, or Luma [bit 4] 16 XRS [bit 2] 16 CLAMP pulse
17 Comp, G/Y, or Luma [bit 5] 17 XRS [bit 1] 17 RGB
18 Comp, G/Y, or Luma [bit 6] 18 XRS [bit 0] 18
19 Comp, G/Y, or Luma [bit 7] 19 GND 19
20 Comp, G/Y, or Luma [bit 8] 20 -5V 20
21 Comp, G/Y, or Luma [bit 9] 21 -5V 21 LOCK
22 Chroma or B/U [bit 0] 22 -5V 22 D1
23 Chroma or B/U [bit 1] 23 GND 23 RESET
24 Chroma or B/U [bit 2] 24 PGM_OUT 24 SCL
25 Chroma or B/U [bit 3] 25 -12V 25 GND
26 Chroma or B/U [bit 4] 26 -12V 26 SDA
27 Chroma or B/U [bit 5] 27 IE (input enable) 27 OE (output enable)
28 Chroma or B/U [bit 6] 28 GND 28 BLANK (DAC)
29 Chroma or B/U [bit 7] 29 29
30 Chroma or B/U [bit 8] 30 30
31 Chroma or B/U [bit 9] 31 +12V 31 +12V
32 GND 32 GND 32 GND
TMB2193MS100 PRODUCT SPECIFICATION
22
Preliminary Information
Output Edge Connector Design Notes
1. Boards with different revision letters may not be com-
patible; damage may occur if they are connected
together.
2. XPXCK is a two times pixel clock fed BACKWARD.
3. XHSYNC and XVSYNC are timing reference signals
fed BACKWARD.
4. The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed FOR-
WARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc.
5. XDIR is fed FOR WARD and controls in which direction
the XRS[3:0] data flows.
6. PGM_OUT negative going signal pulse for initiating
programming of down stream boards, generated once
the devices on the board have been programmed. Care
must be taken to ensure that multiple devices do not try
to drive the RBUS at any given time. The Minimum
width of PGM_OUT is 1uS.
7. The RESET pin on the output edge connector should be
connected directly to the RESET pin on the input con-
nector . A link should be used to connect any pulse to the
RESET line.
8. The MASTER/SLAVE, XDIR, PGM_OUT and RESET
pins on the output edge connector should be connected
to +5V through a 10k pull up resistor.
9. The CLAMP signal is fed BACKWARD from a MAS-
TER to a SLAVE board. The CLAMP signal should not
be fed FORWARD.
Related Products
• TMB22153MS101 Decoder demonstration board
• TMB1185MS102 ADC demonstration board
• TMB0000UG100 RBUS Interface
• TMB0001MS100 Parallel D1 interface board
• Raydemo software
Y/Composite
LPF and
Clamp Circuit
Chrominance
BPF and
Clamp Circuit
TMC1185 TMC1185
SW1 SW1 +5V 0V -5V
2:1 MUX
65-B2193-14
10 bit
ADCs Digital
LPFs
TMC2242
EPROM FPGA
Signal Flow FORWARD
TMC2072
TMC3003
Low Quality
LPF
Low Quality
LPF
Low Quality
LPF
High Quality
LPF
High Quality
LPF
High Quality
LPF
TMC22153
DC Supply
Decoder
Input Logic
TMC2242
1
32
1
32
1
32
1
32
SW2
Signal Flow BACKWARD
PRODUCT SPECIFICATION TMB2193MS100
23
Preliminary Information
Notes:
TMB2193MS100 PRODUCT SPECIFICATION
Preliminary Information
6/3/98 0.0m 002
Stock# DS7TMB2193
Ó 1998 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Ordering Information
A schematic database is available in OrCAD™ format. Contact the factory.
The TMB2193MS100 Demonstration Board, design documentation, and software are provided as a design example for the
customers of Fairchild. F airchild makes no w arranties, e xpress, statutory, or implied regarding merchantability or fitness for a
particular purpose.
FCC Compliance
This device has not been approved by the Federal Communications Commission (FCC). This board is intended for the evalu-
ation of Fairchild products only. This device is not and may not be offered for sale or lease or sold or leased until the approval
of the FCC has been obtained.
Product Number Temperature
Range Speed
Grade Screening Package Package
Marking
TMB2193MS100 25°C 27 MHz Commercial 4" by 5" Printed Circuit Board TMB2193MS100