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FEATURES
SN54LVC86A . . . J OR W PACKAGE
SN74LVC86A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A V
4B
2Y
GND
NC
SN54LVC86A . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
SN74LVC86A . . . RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
4B
4A
4Y
3B
3A
1B
1Y
2A
2B
2Y
1A
3Y V
GND
CC
DESCRIPTION/ORDERING INFORMATION
SN54LVC86A, SN74LVC86AQUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288P – JANUARY 1993 – REVISED APRIL 2005
•Typical V
OHV
(Output V
OH
Undershoot)>2 V at V
CC
= 3.3 V, T
A
= 25 °C•Operate From 1.65 V to 3.6 V
•Latch-Up Performance Exceeds 250 mA Per•Specified From –40 °C to 85 °C,
JESD 17–40 °C to 125 °C, and –55 °C to 125 °C
•ESD Protection Exceeds JESD 22•Inputs Accept Voltages to 5.5 V
– 2000-V Human-Body Model (A114-A)•Max t
pd
of 4.6 ns at 3.3 V
– 200-V Machine Model (A115-A)•Typical V
OLP
(Output Ground Bounce)<0.8 V at V
CC
= 3.3 V, T
A
= 25 °C – 1000-V Charged-Device Model (C101)
The SN54LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V V
CC
operation, and theSN74LVC86A quadruple 2-input exclusive-OR gate is designed for 1.65-V to 3.6-V V
CC
operation.
The 'LVC86A devices perform the Boolean function Y = A ⊕B or Y = AB + A B in positive logic.
ORDERING INFORMATION
ORDERABLE TOP-SIDET
A
PACKAGE
(1)
PART NUMBER MARKING
–40 °C to 85 °C QFN – RGY Reel of 1000 SN74LVC86ARGYR LC86ATube of 50 SN74LVC86ADSOIC – D Reel of 2500 SN74LVC86ADR LVC86AReel of 250 SN74LVC86ADTSOP – NS Reel of 2000 SN74LVC86ANSR LVC86A–40 °C to 125 °C
SSOP – DB Reel of 2000 SN74LVC86ADBR LC86ATube of 90 SN74LVC86APWTSSOP – PW Reel of 2000 SN74LVC86APWR LC86AReel of 250 SN74LVC86APWTCDIP – J Tube of 25 SNJ54LVC86AJ SNJ54LVC86AJ–55 °C to 125 °C CFP – W Tube of 150 SNJ54LVC86AW SNJ54LVC86AWLCCC – FK Tube of 55 SNJ54LVC86AFK SNJ54LVC86AFK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters areInstruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, productionnecessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
EXCLUSIVE-OR LOGIC
= 1
EXCLUSIVE OR
These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports.
= 2k 2k + 1
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
SN54LVC86A, SN74LVC86AQUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288P – JANUARY 1993 – REVISED APRIL 2005
A common application is as a true/complement element. If one of the inputs is low, the other input is reproducedin true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at theoutput.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translatorsin a mixed 3.3-V/5-V system environment.
FUNCTION TABLE(EACH GATE)
INPUTS
OUTPUT
YA B
L L LL H HH L HH H L
An exclusive-OR gate has many applications, some of which can be represented better by alternative logicsymbols.
2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN54LVC86A, SN74LVC86AQUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288P – JANUARY 1993 – REVISED APRIL 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Output voltage range
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mAD package
(4)
86DB package
(4)
96θ
JA
Package thermal impedance NS package
(4)
76 °C/WPW package
(4)
113RGY package
(4)
47T
stg
Storage temperature range –65 150 °CP
tot
Power dissipation T
A
= –40 °C to 125 °C
(5) (6)
500 mW
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.(5) For the D package: above 70 °C, the value of P
tot
derates linearly with 8 mW/K.(6) For the DB, DGV, NS, and PW packages: above 60 °C, the value of P
tot
derates linearly with 5.5 mW/K.
SN54LVC86A
–55 TO 125 °C UNIT
MIN MAX
Operating 2 3.6V
CC
Supply voltage VData retention only 1.5V
IH
High-level input voltage V
CC
= 2.7 V to 3.6 V 2 VV
IL
Low-level input voltage V
CC
= 2.7 V to 3.6 V 0.8 VV
I
Input voltage 0 5.5 VV
O
Output voltage 0 V
CC
VV
CC
= 2.7 V –12I
OH
High-level output current mAV
CC
= 3 V –24V
CC
= 2.7 V 12I
OL
Low-level output current mAV
CC
= 3 V 24∆t/ ∆v Input transition rise or fall rate 9 ns/V
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Recommended Operating Conditions
(1)
Electrical Characteristics
SN54LVC86A, SN74LVC86AQUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288P – JANUARY 1993 – REVISED APRIL 2005
SN74LVC86A
T
A
= 25°C –40 TO 85°C –40 TO 125°C UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6V
CC
Supply voltage VData retention only 1.5 1.5 1.5V
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
0.65 ×V
CC
0.65 ×V
CCHigh-level inputV
IH
V
CC
= 2.3 V to 2.7 V 1.7 1.7 1.7 Vvoltage
V
CC
= 2.7 V to 3.6 V 2 2 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
0.35 ×V
CC
0.35 ×V
CCLow-level inputV
IL
V
CC
= 2.3 V to 2.7 V 0.7 0.7 0.7 Vvoltage
V
CC
= 2.7 V to 3.6 V 0.8 0.8 0.8V
I
Input voltage 0 5.5 0 5.5 0 5.5 VV
O
Output voltage 0 V
CC
0 V
CC
0 V
CC
VV
CC
= 1.65 V –4 –4 –4V
CC
= 2.3 V –8 –8 –8High-levelI
OH
mAoutput current
V
CC
= 2.7 V –12 –12 –12V
CC
= 3 V –24 –24 –24V
CC
= 1.65 V 4 4 4V
CC
= 2.3 V 8 8 8Low-level outputI
OL
mAcurrent
V
CC
= 2.7 V 12 12 12V
CC
= 3 V 24 24 24∆t/ ∆v Input transition rise or fall rate 9 9 9 ns/V
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over operating free-air temperature range (unless otherwise noted)
SN54LVC86A
PARAMETER TEST CONDITIONS V
CC
–55 TO 125 °C UNIT
MIN TYP MAX
I
OH
= –100 µA 2.7 V to 3.6 V V
CC
– 0.22.7 V 2.2V
OH
I
OH
= –12 mA V3 V 2.4I
OH
= –24 mA 3 V 2.2I
OL
= 100 µA 2.7 V to 3.6 V 0.2V
OL
I
OL
= 12 mA 2.7 V 0.4 VI
OL
= 24 mA 3 V 0.55I
I
V
I
= 5.5 V or GND 3.6 V ±5µAI
CC
V
I
= V
CC
or GND I
O
= 0 3.6 V 10 µAOne input at V
CC
– 0.6 V,∆I
CC
2.7 V to 3.6 V 500 µAOther inputs at V
CC
or GNDC
i
V
I
= V
CC
or GND 3.3 V 5
(1)
pF
(1) T
A
= 25 °C
4
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Electrical Characteristics
Switching Characteristics
Switching Characteristics
Operating Characteristics
SN54LVC86A, SN74LVC86AQUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288P – JANUARY 1993 – REVISED APRIL 2005
over operating free-air temperature range (unless otherwise noted)
SN74LVC86A
PARAMETER TEST CONDITIONS V
CC
T
A
= 25 °C –40 TO 85 °C –40 TO 125 °C UNIT
MIN TYP MAX MIN MAX MIN MAX
I
OH
= –100 µA 1.65 V to 3.6 V V
CC
– 0.2 V
CC
– 0.2 V
CC
– 0.3I
OH
= –4 mA 1.65 V 1.29 1.2 1.05I
OH
= –8 mA 2.3 V 1.9 1.7 1.55V
OH
V2.7 V 2.2 2.2 2.05I
OH
= –12 mA
3 V 2.4 2.4 2.25I
OH
= –24 mA 3 V 2.3 2.2 2I
OL
= 100 µA 1.65 V to 3.6 V 0.1 0.2 0.3I
OL
= 4 mA 1.65 V 0.24 0.45 0.6V
OL
I
OL
= 8 mA 2.3 V 0.3 0.7 0.75 VI
OL
= 12 mA 2.7 V 0.4 0.4 0.6I
OL
= 24 mA 3 V 0.55 0.55 0.8I
I
V
I
= 5.5 V or GND 3.6 V ±1±5±20 µAI
CC
V
I
= V
CC
or GND I
O
= 0 3.6 V 1 10 40 µAOne input at V
CC
– 0.6 V,∆I
CC
2.7 V to 3.6 V 500 500 5000 µAOther inputs at V
CC
or GNDC
i
V
I
= V
CC
or GND 3.3 V 5 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC86AFROM TOPARAMETER V
CC
–55 TO 125 °C UNIT(INPUT) (OUTPUT)
MIN MAX
2.7 V 5.6t
pd
A Y ns3.3 V ±0.3 V 1 4.6
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC86AFROM TOPARAMETER V
CC
T
A
= 25 °C –40 TO 85 °C –40 TO 125 °C UNIT(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
1.8 V ±0.15 V 1 4.1 9.4 1 9.9 1 11.42.5 V ±0.2 V 1 2.9 7.1 1 7.6 1 9.7t
pd
A Y ns2.7 V 1 2.8 5.4 1 5.6 1 7.13.3 V ±0.3 V 1 2.5 4.4 1 4.6 1 5.8t
sk(o)
3.3 V ±0.3 V 1 1.5 ns
T
A
= 25 °C
TESTPARAMETER V
CC
TYP UNITCONDITIONS
1.8 V 6.5C
pd
Power dissipation capacitance per gate f = 10 MHz 2.5 V 7.5 pF3.3 V 8.5
5
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE W AVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH - V∆≈0 V
VI
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN54LVC86A, SN74LVC86AQUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288P – JANUARY 1993 – REVISED APRIL 2005
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-9761901Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9761901QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
5962-9761901QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN74LVC86AD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74LVC86ADBR ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADT ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADTE4 ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ADTG4 ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ANSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74LVC86APWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APWT ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LVC86APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC86ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVC86ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SNJ54LVC86AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LVC86AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SNJ54LVC86AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC86A, SN74LVC86A :
•Automotive: SN74LVC86A-Q1
•Enhanced Product: SN74LVC86A-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC86ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVC86ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC86ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC86APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LVC86ARGYR VQFN RGY 14 3000 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC86ADBR SSOP DB 14 2000 346.0 346.0 33.0
SN74LVC86ADR SOIC D 14 2500 346.0 346.0 33.0
SN74LVC86ANSR SO NS 14 2000 346.0 346.0 33.0
SN74LVC86APWR TSSOP PW 14 2000 346.0 346.0 29.0
SN74LVC86ARGYR VQFN RGY 14 3000 190.5 212.7 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Dec-2009
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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