PGA2505
Burr-BrownAudio
™ Digitally-Controlled
1
FEATURES APPLICATIONS
DESCRIPTION
PGA2505
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......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
MICROPHONE PREAMPLIFIER
•MICROPHONE PREAMPLIFIERS AND MIXERS234
•FULLY DIFFERENTIAL lNPUT-TO-OUTPUTARCHITECTURE
•DIGITAL MIXERS AND RECORDERS•DIGITAL AUDIO EDITING SYSTEMS•DIGITALLY-CONTROLLED GAIN USING SPI™:
•BROADCAST EQUIPMENT– Gain Range: 9dB through 60dB,
•INTERCOMS3dB per Step– Unity (0dB) Gain Setting via Serial Port•DYNAMIC PERFORMANCE:
The PGA2505 is a digitally-controlled, analog– Equivalent Input Noise with Z
S
= 150 Ω
microphone preamplifier designed for use as aand Gain = 30dB: – 123dBu
front-end for high-performance audio analog-to-digital– Total Harmonic Distortion plus Noise
converters (ADCs). The PGA2505 features include(THD+N) with Gain = 30dB: 0.0006%
low noise, wide dynamic range, and a differentialsignal path. An on-chip dc servo loop is employed to•ZERO CROSSING DETECTION MINIMIZES
minimize dc offset, while a common-mode servoAUDIBLE ARTIFACTS WHEN GAIN
function may be used to enhance common-modeSWITCHING
rejection.SoundPlus™•INTEGRATED DC SERVO MINIMIZES
The PGA2505 features a gain range of 9dB throughOUTPUT OFFSET VOLTAGE
60dB (3dB/step), along with a unity gain setting. The•COMMON-MODE SERVO IMPROVES CMRR
wide gain range allows the PGA2505 to be used with•FOUR-WIRE SERIAL CONTROL PORT
a variety of microphones. Gain settings and internalINTERFACE:
functions are programmed using a 16-bit controlword, which is loaded using a simple serial port– Simple Interface to Microprocessor
interface. A serial data output pin provides support foror DSP Serial Ports
daisy-chained connection of multiple PGA2505– Supports Daisy-Chaining of Multiple
devices. Four programmable digital outputs arePGA2505 Devices
provided for controlling the external switching of input•OVER-RANGE OUTPUT PIN PROVIDES
pads, phantom power, and high-pass filters. TheCLIPPING INDICATION
PGA2505 requires both +5V and – 5V power suppliesand is available in a small SSOP-24 package.•FOUR GENERAL-PURPOSE
DIGITAL OUTPUT PINS•± 5V POWER SUPPLIES•AVAILABLE IN AN SSOP-24 PACKAGE
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SoundPlus is a trademark of Texas Instruments Incorporated.3SPI is a trademark of Motorola, Inc..4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 .........................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Over operating free-air temperature range, unless otherwise noted.
PGA2505 UNIT
Supply Voltage, AGND or DGND to VA+ – 0.3 to +5.5 VSupply Voltage, AGND or DGND to VA – +0.3 to – 5.5 VSupply Voltage, AGND or DGND to VD – +0.3 to – 5.5 VVoltage Difference, VA – to VD – ± 0.3 VGround Difference, AGND to DGND ± 0.3 VAnalog Input Voltage (VA – ) – 0.3 to (VA+) +0.3 VDigital Input Voltage (DGND) – 0.3 to (VA+) + 0.3 VInput Current of All Pins Except Supply ± 10 mASee Electrical Characteristics,Power Dissipation
Thermal Resistance parameterJunction Temperature Range, T
J
– 40 to +150 ° COperating Free-Air Temperature Range, T
A
– 40 to +85 ° CStorage Temperature Range, T
STG
– 60 to +150 ° CHuman Body Model (HBM) 2000 VESD Ratings Charged Device Model (CDM) 1000 VMachine Model (MM) 150 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.
ORDERING INFORMATION
(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
PGA2505 SSOP-24 DB PGA2505I
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
2Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA2505
ELECTRICAL CHARACTERISTICS
PGA2505
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......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
At T
A
= +25 ° C, VA+ = +5V, VA – = – 5V, VD – = – 5V, and V
COM
IN = 0V, unless otherwise noted.
PGA2505
PARAMETERS CONDITIONS MIN TYP MAX UNIT
DC CHARACTERISTICS
Step Size Gain = 9dB through 60dB 3 dB
Gain Error All gain settings ± 0.5 dB
AC CHARACTERISTICS
f
IN
= 1kHz, Gain = 0dB, V
OUT
= 3.5V
RMS
– 110 – 100 dBTHD+N
f
IN
= 1kHz, Gain = 30dB, V
OUT
= 3.5V
RMS
– 105 – 95 dB
ANALOG INPUT
Maximum Input Voltage Gain = 0dB VA – +1.5 VA+ – 2.0 V
Input Resistance
Per Input Pin 4600 Ω
Differential 9200 Ω
ANALOG OUTPUT
Output Voltage Range V
COM
IN = 0V, R
L
= 600 ΩVA – +0.9 VA+ – 0.9 V
Output Offset Voltage DC servo on, any gain ± 0.08 ± 1 mV
Input-Referred Offset DC servo off, gain = 30dB ± 1 mV
Output Resistive Loading 600 Ω
Load Capacitance Stability 100 pF
Short Circuit Current 10-second duration 100 mA
DIGITAL CHARACTERISTICS
High-Level Input Voltage V
IH
+2.0 VA+ V
Low-Level Input Voltage V
IL
– 0.3 0.8 V
High-Level Output Voltage V
OH
I
O
= 200 µA (VA+) – 1.0 V
Low-Level Output Voltage V
OL
I
O
= – 3.2mA 0.4 V
Input Leakage Current I
IN
2 10 µA
POWER SUPPLY
Operating Voltage
VA+ +4.75 +5 +5.25 V
VA – – 4.75 – 5 – 5.25 V
VD – – 4.75 – 5 – 5.25 V
Quiescent Current
IA+ VA+ = +5V 30 40 mA
IA – VA – = – 5V 30 40 mA
ID – VD – = – 5V 1 2 mA
TEMPERATURE RANGE
Operating Free-Air Temperature
T
A
– 40 ÷ 85 ° CRange
Thermal Resistance
θ
JA
High-K board 72 ° C/WSSOP-24
θ
JC
High-K board 42 ° C/W
Copyright © 2009, Texas Instruments Incorporated 3
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SWITCHING CHARACTERISTICS
TIMING REQUIREMENTS
SCLK
SDI
SDO
tCSO
MSB
MSB
tCFDO
tCSCR
tSDS
tSDH
tCFCS
tCSZ
CS
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 .........................................................................................................................................................
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Over operating free-air temperature range (unless otherwise noted).
PGA2505
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLK
Serial clock (SCLK) frequency 0 6.25 MHzt
PH
Serial clock (SCLK) pulse width low 80 nst
PL
Serial clock (SCLK) pulse width high 80 ns
Over operating free-air temperature range (unless otherwise noted).
PGA2505
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT TIMING
t
SDS
SDI setup time 20 nst
SDH
SDI hold time 20 nst
CSCR
CS falling to SCLK rising 90 nst
CFCS
SCLK falling to CS rising 35 ns
OUTPUT TIMING
t
CSO
CS low to SDO active 35 nst
CFDO
SCLK falling to SDO data valid 60 nst
CSZ
CS high to SDO high impedance 100 ns
SERIAL PORT TIMING DIAGRAM
4Copyright © 2009, Texas Instruments Incorporated
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PIN CONFIGURATION
PGA2505
1
2
3
4
5
24
23
22
21
20
V +
IN
V-
IN
V IN
COM
CS11
CS12
CS21
CS22
VA-
VA+
V +
OUT
V-
OUT
VA-
AGND
GPO1
GPO2
GPO3
OVR
DGND
SDI
CS
SCLK
SDO
VD-
6
7
8
9
10
11
12
19
18
17
16
15
14
13
GPO4
PIN ASSIGNMENTS
PGA2505
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......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
DB PACKAGE
SSOP-24
(TOP VIEW)
TERMINAL
NAME PIN# DESCRIPTION
AGND 1 Analog GroundGPO1 2 General-Purpose CMOS Logic OutputGPO2 3 General-Purpose CMOS Logic OutputGPO3 4 General-Purpose CMOS Logic OutputGPO4 5 General-Purpose CMOS Logic OutputOVR 6 Over Range Output (Active High)DGND 7 Digital GroundSDI 8 Serial Data InputCS 9 Chip Select Input (Active Low)SCLK 10 Serial Data Clock InputSDO 11 Serial Data OutputVD – 12 – 5V Digital SupplyVA – 13 – 5V Analog SupplyV
OUT
– 14 Inverting Analog OutputV
OUT
+ 15 Noninverting Analog OutputVA+ 16 +5V Analog SupplyVA – 17 – 5V Analog SupplyC
S22
18 External DC Servo Capacitor #2, Terminal 2C
S21
19 External DC Servo Capacitor #2, Terminal 1C
S12
20 External DC Servo Capacitor #1, Terminal 2C
S11
21 External DC Servo Capacitor #1, Terminal 1V
COM
IN 22 Common Mode Voltage Input, 0V to +2.5VV
IN
– 23 Inverting Analog InputV
IN
+ 24 Noninverting Analog Input
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TYPICAL CHARACTERISTICS
-
-
110
112
114
116
118
120
122
124
126
-
-
-
-
-
-
-
EIN(dBu)
9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60
Gain(dB)
-
-
110
112
114
116
118
120
122
124
126
-
-
-
-
-
-
-
EIN(dBu)
9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60
Gain(dB)
0.01
0.001
0.0001
TotalHarmonicDistortion+Noise(%)
9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60
Gain(dB)
V =4.0V
Z =40W
OUT RMS
S
-60
70
80
90
100
110
120
130
-
-
-
-
-
-
-
THD+NandNoise(dB)
9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60
Gain(dB)
THD+N
withZ =40
SW
V =4.0V
OUT RMS
Noise
with 0
Reference0dB
Z =
SW
=4.0VRMS
0.1
0.01
0.001
0.0001
THD+NRatio(%)
20 100 1k 10k 20k
Frequency(Hz)
V =4.0V DifferentialforGains=
12dB,24dB,30dB,36dB,48dB,and60dB
OUT RMS
V =3.5V DifferentialforGain=0dB
OUT RMS 60dB
48dB
36dB
24dB
0dB 12dB
30dB
0.1
0.01
0.001
0.0001
THD+NRatio(%)
20 100 1k 10k 20k
Frequency(Hz)
V =2.0V DifferentialforGains=12dB,
24dB,30dB,36dB,48dB,and60dB
OUT RMS
60dB
48dB
36dB
30dB
24dB
12dB
0dB
V =1V DifferentialforGain=0dB
OUT RMS
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 .........................................................................................................................................................
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At T
A
= +25 ° C, VA+ = +5V, VA – = – 5V, VD – = – 5V, and V
COM
IN = 0V, unless otherwise noted.
EQUIVALENT INPUT NOISE AS A FUNCTION OF GAIN EQUIVALENT INPUT NOISE AS A FUNCTION OF GAINWITH Z
S
= 0 ΩWITH Z
S
= 150 Ω
Figure 1. Figure 2.
THD+N vs GAIN THD+N vs GAIN AND NOISE vs GAIN
Figure 3. Figure 4.
THD + N vs FREQUENCY THD + N vs FREQUENCY(Z
S
= 40 Ω, R
L
= 600 Ω, V
COM
IN = 0V, BW = 22Hz to 22kHz) (Z
S
= 40 Ω, R
L
= 600 Ω, V
COM
IN = +2.5V, BW = 22Hz to 22kHz)
Figure 5. Figure 6.
6Copyright © 2009, Texas Instruments Incorporated
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0.1
0.01
0.001
0.0001
0.03 0.3 3 6
OutputAmplitude(V )
RMS
THD+N(%)
Gain=30dB
f=1kHz
0.1
0.01
0.001
0.0001
THD+NRatio(%)
20 100 1k 10k 20k
Frequency(Hz)
V =1.0V DifferentialforAllGainSettings
OUT RMS
60dB
48dB
36dB
30dB
24dB
0dB
12dB
PGA2505
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......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, VA+ = +5V, VA – = – 5V, VD – = – 5V, and V
COM
IN = 0V, unless otherwise noted.
THD + N vs FREQUENCY THD + N vs OUTPUT SWING(Z
S
= 40 Ω, R
L
= 600 Ω, V
COM
IN = +2.5V, BW = 22Hz to 22kHz) (Z
S
= 40 Ω, R
L
= 600 Ω, V
COM
IN = 0V, BW = 22Hz to 22kHz)
Figure 7. Figure 8.
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APPLICATION INFORMATION
OVERVIEW
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 .........................................................................................................................................................
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space
The differential analog output of the PGA2505 isconstantly monitored by a dc servo amplifier loop.The PGA2505 is a digitally-controlled microphone
The purpose of the servo loop is to minimize the dcpreamplifier integrated circuit designed to amplify the
offset voltage present at the analog outputs byoutput of dynamic and condenser microphones and
feeding back an error signal to the input stage of thedrive high-performance audio analog-to-digital
programmable gain amplifier. The error signal is thenconverters (ADCs). A functional block diagram of the
used to correct the offset. The DC servo may bePGA2505 is shown in Figure 9 .
disabled by setting the dc bit in the serial control wordThe analog input to the preamplifier is provided
to '1'.differentially at the V
IN
+ and V
IN
– inputs (pins 24 and
Two external capacitors are required for the dc servo23, respectively). The programmable gain amplifier
function, with one capacitor connected between C
S11can be programmed to either pass through the signal
and C
S12
(pins 21 and 20), and the second capacitorat unity gain, or apply 9dB to 60dB of gain to the
connected between C
S21
and C
S22
(pins 19 and 18).input signal. The gain of the amplifier is adjustable
A capacitor value of 1 µF is recommended for use inover the full 9dB to 60dB range in 3dB steps. The
most microphone preamplifier applications. Capacitordifferential output of the PGA2505 is made available
values up to 4.7 µF may be used. However, largerat V
OUT
+ and V
OUT
– (pins 15 and 14, respectively).
valued capacitors result in longer settling times forGain is controlled using a serial port interface.
the dc servo loop. Smaller capacitors under 0.22 µFThe four-wire serial port interface is used to program
may result in additional distortion in the low frequencythe PGA2505 gain and support functions. A 16-bit
audio bandwidth.control word is utilized to program these functions(see Figure 10 ). A serial data output pin providessupport for daisy-chaining multiple PGA2505 deviceson a single serial interface bus (see Figure 11 ).
(1) Gain Range: 0dB, or +9dB to +60dB (3dB/step).(2) C
S1
and C
S2
are external dc servo integrator capacitors, and are connected across the C
S11
/C
S12
and C
S21
/C
S22
pins,respectively.
Figure 9. PGA2505 Functional Block Diagram
8Copyright © 2009, Texas Instruments Incorporated
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ANALOG INPUTS AND OUTPUTS
PGA2505
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......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
The PGA2505 includes a common-mode servo An over-range indicator output, OVR, is provided atfunction. This function is enabled and disabled using pin 6. The OVR pin is an active high,the CM bit in the serial control word; see Figure 10 . CMOS-logic-level output. The over-range output isWhen enabled, the servo provides common-mode forced high when the preamplifier output voltagenegative feedback at the input differential pair, exceeds one of two preset thresholds. The thresholdresulting in very low common-mode input impedance. is programmed through the serial port interface usingThe differential input impedance is not affected by the OR bit. If OR = '0', then the output threshold is setthis feedback. This function is useful when the source to 5.1V
RMS
differential, which is approximately 1dBis floating, or has a high common-mode output below the specified output voltage range. If OR = '1',impedance. then the output threshold is set to 4.0V
RMSdifferential, which is approximately 3dB below theWhen the source is floating, the only connection
specified output voltage range.between the source and the ground is through thePGA2505 preamplifier input resistance. The input The PGA2505 includes four programmable digitalcommon-mode parasitic current is determined by high outputs, named GPO1, GPO2, GPO3, and GPO4output impedance of the source, not by input (pins 2, 3, 4, and 5 respectively), that are controlledimpedance of the amplifier. Therefore, input via the serial port interface. These pins arecommon-mode interference can be reduced by CMOS-logic-level outputs. These pins may be usedlowering the common-mode input impedance while at to control relay drivers or switches used for externalthe same time not increasing the input common-mode preamplifier functions, including input pads, filtering,current. Increasing common-mode current degrades polarity reversal, or phantom power.common-mode rejection. Using the common-modeservo, overall common-mode rejection can beimproved by suppressing low and medium frequency
An analog signal is input differentially across the V
IN
+common-mode interference.
(pin 24) and V
IN
– (pin 23) inputs. The input voltageThe common-mode servo function is designed to
range and input impedance are provided in theoperate with a total common-mode input capacitance
Electrical Characteristics table. The Applications(including the microphone cable capacitance) of up to
Information section of this data sheet provides10nF. Beyond this limit, stable servo operation is not
additional details regarding typical input circuitassured.
considerations when interfacing the PGA2505 to amicrophone input.The common-mode voltage control input, namedV
COM
IN (pin 22), allows the PGA2505 output and
Both V
IN
+ and V
IN
– are biased at approximatelyinput to be dc-biased to a common-mode voltage
0.65V below the common-mode input voltage,between 0V and +2.5V and should not be left floating.
supplied at V
COM
IN (pin 22). The use of ac-couplingThis configuration allows for a dc-coupled interface
capacitors (see Figure 10 ) is highly recommended forbetween the PGA2505 preamplifier output and the
the analog inputs of the PGA2505. If dc-coupling isinputs of common single-supply audio ADCs.
required for a given application, the user must takethis offset into account.The zero crossing control input is provided forenabling and disabling the internal zero crossing
It is recommended that a small capacitor bedetector function. This function is enabled and
connected from each analog input pin to analogdisabled using the ZC bit in the serial control word;
ground. Values of at least 50pF are recommended.see Figure 10 . Zero crossing detection is used to
See Figure 10 for larger capacitors used for EMIforce gain changes on zero crossings of the analog
filtering, which satisfies this requirement.input signal. This configuration limits the glitch energy
The analog output is presented differentially acrossassociated with switching gain, thereby minimizing
V
OUT
+ (pin 15) and V
OUT
– (pin 14). The outputaudible artifacts at the preamplifier output. Because
voltage range is provided in the Electricalzero crossing detection can add some delay when
Characteristics table. The analog output is designedperforming gain changes (up to 16ms maximum for a
to drive a 600 Ωdifferential load while meeting thedetector timeout event), there may be cases where
published THD+N specifications and typicalthe user may wish to disable the function. Setting the
performance graphs.ZC bit high enables zero crossing detection, with gainchanges occurring immediately when programmed.
Note that because the zero crossing detector requiressetup, the user should set the ZC bit as a firstoperation. Subsequent changes in gain occur on thezero crossings provided that the ZC bit setting ismaintained.
Copyright © 2009, Texas Instruments Incorporated 9
Product Folder Link(s): PGA2505
SERIAL PORT OPERATION
SCLK
DC CM ZC OR D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0 DataIgnored
DataIgnored
DC CM ZC OR D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0 HighImpedance
HighImpedance
CS
SDI
SDO
DCServoEnable
(ActiveLow)
CMServoEnable
(ActiveHigh)
Over-RangeIndicatorBit
(0=5.1V ,1=4.0V )
RMS RMS
DataforGPO4
DataforGPO2
DataforGPO1
PreamplifierGain
whereN=G[5:0]DEC
ForN=0
Gain=0dB
ForN=1to17
Gain(dB)=6+3N
ForN=18to31
Gain=60dB
DataforGPO3
ZeroCrossingDetect
(ActiveHigh)
PGA2505
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The SCLK input is used to clock serial data into theSDI pin and out of the SDO pin. The SDI pinThe serial port interface for the PGA2505 is
functions as the serial data input, and is used to writecomprised of four wires: CS (pin 9), SCLK (pin 10),
the serial port register. The SDO pin is the shiftSDI (pin 8), and SDO (pin 11). Figure 10 illustrates
register serial output, and is used for either registerthe serial port protocol.
read-back or for daisy-chaining multiple PGA2505devices. Data on SDI are sampled on the rising edgeThe CS input functions as the chip select and word
of SCLK, while data are clocked out of SDO on thelatch clock for the serial port. The CS input must be
falling edge of SCLK.low in order to clock data into and out of the serialport. The control word is latched on a low-to-hightransition of the CS input.
The serial port ignores the SCLK and SDI inputswhen CS is high, and the SDO output is set to a highimpedance state while CS is high.
Figure 10. Serial Port Protocol
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DAISY-CHAINING MULTIPLE PGA2505
CS
SCLK
SDI
SDO
VOUT+
VOUT-
VIN+
VIN-
PGA2505
#1
CS
SCLK
SDI
SDO
VOUT+
VOUT-
VIN+
VIN-
PGA2505
#2
CS
SCLK
SDI
SDO
VOUT+
VOUT-
VIN+
VIN-
PGA2505
#N
CS
DATACLK
DOUT
DIN
Microprocessor
orDSP
SCLK
CS
SDI DC G0
DC G0
DC
Device#1
Device#2
Device#N
G0
PGA2505
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......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
PREAMPLIFIERS
Because the serial port interface may be viewed as a To program all of the devices, simply force CS low forserial in, serial out shift register, multiple PGA2505 16 x Nserial clock periods and clock in 16 x Nbits ofpreamplifiers may be connected in a cascaded or control data. The CS input is then forced high to latchdaisy-chained fashion, as shown in Figure 11 . The in the new settings.daisy-chained PGA2505 devices behave as a 16 x
A timing diagram for the daisy-chain application isN-bit shift register, where Nis the number of
shown in Figure 12 .cascaded PGA2505 devices.
Figure 11. Daisy-Chain Configuration for Multiple PGA2505 Preamplifiers
Figure 12. Serial Port Operation for Daisy-Chain Operation
Copyright © 2009, Texas Instruments Incorporated 11
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APPLICATION INFORMATION
BASIC CIRCUIT CONFIGURATION
AGND
GPO2
GPO3
OVR
1
3
4
6
PGA2505
ToRelayDrivers
and Switches
DGND
7
To/From
MPU,MCU,
DSP,orLogic
SDI
CS
SCLK
SDO
11
13
12 VD-
VA-15
14
V +
IN
V-
IN
0W
24
23
8
9
10
CS21
CS22
19
18
10W
0.1 Fm
VA-
0.1 Fm
+
4.7 Fm
+
4.7 Fm
V +
OUT
17 0.1 Fm
1 Fm
CS11
CS12
21
20
1 Fm
V-
OUT
VA-
VA+
VA-
+
4.7 Fm
VA+
V IN
COM
22
16 0.1 Fm
+
4.7 Fm
0.1 Fm
GPO1
2
GPO4
5
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 .........................................................................................................................................................
www.ti.com
with analog and digital pins separated basically downthe center of the package. (Note that AGND is on theThis section provides practical information for
opposite side.) However, there must be a lowdesigning the PGA2505 into end applications.
impedance connection between the analog and digitalgrounds at a common return point.
The dc common-mode input, V
COM
IN (pin 22), can beA typical application configuration, without the input
connected to analog ground or a dc voltage (such asand output circuitry, is shown in Figure 13 .
the reference or common voltage output of an audioPower-supply bypass and dc servo capacitors are
ADC). When biasing this input to a dc voltage, keepshown with recommended values. All capacitors
in mind that both the analog output and input pins willshould be placed as close as possible to the
be level-shifted by the value of the bias voltage.PGA2505 package to limit inductive noise coupling.Surface-mount capacitors are recommended (X7Rceramic for the 0.1 µF and 1 µF capacitors, and lowESR tantalum for the 4.7 µF capacitors).
The PGA2505 can be placed on a split ground plane,
Figure 13. Basic Circuit Configuration for the PGA2505
12 Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA2505
INPUT CIRCUIT CONSIDERATIONS
(3)
6.81kW
0.25W
(4) (4)
(4) (4)
(3)
10 F 47m m- F
63WV
+
+
10 F 47m - mF
63WV
1
MicInput
2
3
1000pF
1000pF
1000pF
6.81kW
0.25W
Phantom
Power
Switch
+48V
(1)
(2)
(2)
VA+ VA-
V +
IN
V-
IN
NOTES:
PGA2505
www.ti.com
......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
The blocking capacitors, along with the PGA2505input resistance, form a high-pass filter circuit. WithFor proper operation, the input circuit for the
the typical input resistance of the PGA2505 specifiedPGA2505 must include several items that are
in the Electrical Characteristics table, the value of thecommon to most microphone preamplifiers. Figure 14
capacitor can be chosen to meet the desired lowshows a typical input circuit configuration. Other
frequency response for the end application. At thefunctions, such as input attenuation (pads), filters,
same time, the value should be no greater thanand polarity reversal switches are commonly found in
required, because larger capacitors store morepreamplifier circuits, but are not shown here in order
charge and increase the surge current seen at theto focus on the basic input circuit requirements.
preamplifier when a short circuit occurs on themicrophone input connector.The microphone input is typically taken from abalanced XLR or TRS input connection (XLR shown).
To protect the PGA2505 from large surge currents,Three 1000pF capacitors provide simple EMI filtering
power Schottky diodes are placed on the input pins tofor the circuit. Additional filtering for low- or
both the VA+ and VA – power supplies. Schottkyhigh-frequency noise may be added, depending on
diodes are used because of the lower turn-on voltagethe end application environment. A bridging resistor is
compared to standard rectifier diodes. Power devicesshown and may be selected to provide the desired
are required because the surge currents from a largeoverall input impedance required for a given
valued blocking capacitor (47 µF) can exceed 4.5A formicrophone. This resistance is in parallel with the
a very short duration of time. It is recommended thatphantom power bias resistors and the PGA2505 input
the Schottky diode chosen for this application beresistance to set the actual impedance seen by the
specified for at least a 10A surge current.microphone.
The use of a series current-limiting resistor before theConnections for +48V phantom power, required for
protection diodes aids in handling surge currents,condenser microphones, are shown in Figure 14 . The
although the resistor adds noise to the circuit. Selectphantom power requires an On/Off switch, because
a current-liming resistor value that is as high asdynamic microphones do not require phantom power
tolerable for the desired noise performance of theand may be damaged if power is applied.
preamplifier circuit.DC-blocking capacitors are required between thephantom power connections and the PGA2505inputs. The blocking capacitors are selected to havea high working voltage rating, with 50V being theminimum and 63V recommended for long-termreliability.
(1) Bridging resistor; used to set the impedance seen by the microphone.(2) The blocking capacitor value is selected based upon the desired low frequency response.(3) Current-limiting resistor. Select the highest value tolerable based upon input noise requirements.(4) Schottky diode; selected for fast turn-on and rated for a minimum of a 10A surge current. Recommended device is theMBRA120LT3 from ON Semiconductor.
Figure 14. Typical Input Circuit for the PGA2505
Copyright © 2009, Texas Instruments Incorporated 13
Product Folder Link(s): PGA2505
OPERATION WITH V
COM
IN = +2.5V
R
R
2R C
PGA
PGA2505
CC1
CC2
V+
OUT
V-
OUT
V IN
COM
ADC
A/DConverter(1)
+
+
SerialDataOutput
PCMorDSD
Coupling
Capacitors
Attenuationand
AntialiasingFilter
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 .........................................................................................................................................................
www.ti.com
As a suggested alternative, the PGA2505 analogoutputs may be ac-coupled to the ADC inputs,When interfacing the analog outputs of the PGA2505
allowing the PGA2505 to operate with V
COM
IN = 0V inwith audio ADC inputs, the converter may frequently
order to achieve best performance. The ac-couplinghave a common-mode dc output pin. This pin may be
capacitors affect the overall low-frequency responseconnected to the V
COM
IN pin of the PGA2505 in order
of the preamplifier and converter combination, andto facilitate a dc-coupled interface between the two
the user is advised to choose a value that best suitsdevices. The common-mode dc voltage level is
the application requirements.typically +2.5V, although some converters may havea slightly lower value, usually between +2.1V and Figure 15 illustrates a typical PGA2505 to audio ADC+2.5V. There are several issues that must be interface using ac-coupling. In addition to the couplingconsidered when operating the PGA2505 in this capacitors, a passive RC filter is required as anfashion. antialiasing filter for the converter. The vast majorityof audio ADCs are of the oversampling delta-sigmaBoth the analog input and output pins of the
variety, with a simple single-pole filter meeting thePGA2505 are level-shifted by the V
COM
IN voltage.
anti-aliasing requirements for this type of converter.The analog outputs are shifted to the V
COM
IN level,
Providing at least 6dB of attenuation also allows thewhile the analog inputs are shifted to approximately
PGA2505 to operate near full signal swing withoutV
COM
IN – 0.65V, as a result of the offset that normally
overdriving the ADC inputs.exists on the input pins. The level-shifting limits theinput and output swing of the PGA2505, reducing the Figure 16 illustrates an application where the V
COM
INoverall signal-to-noise ratio and degrading the pin of the PGA2505 is connected to theTHD+N performance. common-mode dc output of the audio ADC, with adc-coupled interface between the PGA2505 analogGiven V
COM
IN = +2.5V and gains of 0dB through
outputs and the ADC analog inputs.60dB, the output swing is limited to less than one-halfthat specified in the Electrical Characteristics table. To ensure optimal performance, an output buffer toThe output hard-clips at approximately a diode drop the PGA2505 is recommended. Figure 17 illustratesbelow the VA+ supply rail and a diode drop above the use of an OPA1632 as the buffer. Additionally,analog ground. the feedback circuitry functions as the antialiasingfilter shown in Figure 15 and Figure 16 . Having aGiven V
COM
IN = +2.5V and a gain of 0dB, the
differential buffer with attenuation of 6dB or greaterpractical maximum input or output voltage swing is
also allows for the PGA2505 to maximize the outputapproximately 1.0V
RMS
differential. Increasing the
signal swing, while ensuring that the input swing doessignal level much beyond this point results in a
not exceed the full-scale input range of the ADC. Ansubstantial increase in distortion.
OPA227 is used to drive the output common-mode ofthe OPA1632.Plots of THD+N vs Frequency are shown in theTypical Characteristics section of this data sheet forboth V
COM
IN = 0V and +2.5V. The performancedifference can be seen when comparing the plots.The user must consider whether the difference isacceptable for the end application.
(1) Recommended devices are the PCM1804 ,PCM4202 ,PCM4204 ,PCM4220 , or PCM4222 .
Figure 15. PGA2505 Analog Output to ADC Analog Input Interface, AC-Coupled
14 Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA2505
R
R
C
0.1 Fm
PGA
PGA2505
V+
OUT
V-
OUT
V IN
COM V Output
COM
ADC
A/DConverter(1)
SerialDataOutput
PCMorDSD
AntialiasingFilter
40.2W
40.2W
2.7nF
0.1 Fm
A/DConverter(1)
VIN+
VCOM
VIN-
OPA1632
1nF
470W
1nF
1kW
1kW
1kW
470W
8
1
6
375
24
PGA2505
OPA227
17
16
15
22 14
-
+
23
3
24
2
6
+5V
-5V
PGA2505
www.ti.com
......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
(1) Recommended devices are the PCM1804 ,PCM4202 ,PCM4204 ,PCM4220 , or PCM4222 .
Figure 16. PGA2505 Analog Output to ADC Analog Input Interface, DC-Coupled
(1) Recommended devices are the PCM1804 ,PCM4202 ,PCM4204 ,PCM4220 , or PCM4222 .
Figure 17. PGA2505 Using OPA1632 as an Output Buffer
REVISION HISTORYNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May, 2009) to Revision B ..................................................................................................... Page
•Changed logo on document .................................................................................................................................................. 1
Copyright © 2009, Texas Instruments Incorporated 15
Product Folder Link(s): PGA2505
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PGA2505IDB ACTIVE SSOP DB 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PGA2505IDBR ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Jun-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PGA2505IDBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Jun-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PGA2505IDBR SSOP DB 24 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Jun-2009
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2009, Texas Instruments Incorporated