LP5990TM-2.8/NOPB - NATIONAL SEMICONDUCTOR

1.0 µF VOUT

GND

VIN

VEN

CIN COUT

VIN

VOUT

VEN

GND

1.0 µF

LP5990

Capacitor Case

Size = 0402

LP5990

www.ti.com

SNVS438B –APRIL 2007–REVISED DECEMBER 2007

LP5990 Micropower 200mA CMOS Low Dropout Voltage Regulator

Check for Samples: LP5990

1FEATURES DESCRIPTION

The LP5990 regulator is designed to meet the

2• Operation from 2.2V to 5.5V Input requirements of portable, battery-powered systems

• ±1% Accuracy Over Temp Range providing an accurate output voltage, low noise and

• Output Voltage from 0.8V to 3.6V in 50mV low quiescent current.

Increments The LP5990 will provide a 1.8V output from a low

• 30 μA Quiescent Current (Enabled) input voltage of 2.2V and can provide 200mA to an

external load.

• 10nA Quiescent Current (Disabled)

• 160mV Dropout at 200mA Load When switched into shutdown mode via a logic signal

at the enable pin, the power consumption is reduced

• 60 μVRMSOutput Voltage Noise to virtually

• 60 μs Start-Up Time zero.

• 500μs Shut-Down Time

• PSRR 55 dB at 10 kHz Fast shut-down is achieved by the push pull

architecture.

• Stable with 0402 1.0µF Ceramic Capacitors The LP5990 is designed to be stable with space

• Logic Controlled Enable saving 0402 ceramic capacitors as small as 1µF, this

• Thermal–Overload and Short–Circuit gives an overall solution size of < 2.5mm 2.

Protection Performance is specified for a -40°C to 125°C

junction temperature range.

APPLICATIONS

• Cellular Phones The device is available in DSBGA Package (0.4mm

pitch) and is available with

• Hand–Held Information Appliances 1.2V,1.3V,1.8V,2.8V,3.0V,3.3V and 3.6V outputs.

Lower voltage options down to 0.8V are available on

PACKAGE request. For all other output voltage options please

• 4-Bump DSBGA, 0.4 mm Pitch 866 µm x 917 contact your local TI sales office.

µm (Lead Free)

TYPICAL APPLICATION CIRCUIT

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Bottom View Top View

B1A1

B2A2

VIN

VOUT

VEN

GND

B1 A1

B2 A2

VIN

VOUT

VEN

GND

LP5990

SNVS438B –APRIL 2007–REVISED DECEMBER 2007

www.ti.com

CONNECTION DIAGRAMS

Figure 1. 4-Bump Thin DSBGA Package, 0.4mm pitch

Package Number YFQ0004CEA

The actual physical placement of the package marking will vary from part to part.

PIN DESCRIPTIONS

Pin No. Symbol Name and Function

DSBGA

A2 VEN Enable input; disables the regulator when ≤0.35V. Enables the regulator when ≥1.0V.

A1 GND Common ground.

B1 VOUT Output voltage. A 1.0 μF Low ESR capacitor should be connected to this Pin. Connect

this output to the load circuit.

B2 VIN Input voltage supply. A 1.0 µF capacitor should be connected at this input.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS (1)(2)(3)

VIN Pin: Input Voltage -0.3 to 6.0V

VOUT Pin: Output Voltage -0.3 to (VIN + 0.3V) to 6.0V (max)

VEN Pin: Enable Input Voltage -0.3 to 6.0V (max)

Continuous Power Dissipation (4) Internally Limited

Junction Temperature (TJMAX) 150°C

Storage Temperature Range -65 to 150°C

Maximum Lead Temperature (Soldering, 10 sec.) 260°C

ESD Rating (5) Human Body Model 2 kV

Machine Model 200V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) Internal thermal shutdown circuitry protects the device from permanent damage.

(5) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. The machine model is a 200 pF

capacitor discharged directly into each pin. MIL-STD-883 3015.7

Product Folder Links: LP5990

LP5990

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SNVS438B –APRIL 2007–REVISED DECEMBER 2007

OPERATING RATINGS (1),(2)

VIN: Input Voltage Range 2.2V to 5.5V

VEN: Enable Voltage Range 0 to 5.5V (max)

Recommended Load Current (3) 0 to 200 mA

Junction Temperature Range (TJ) -40°C to +125°C

Ambient Temperature Range (TA)(3) -40°C to +85°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See applications section.

THERMAL PROPERTIES

Junction to Ambient Thermal Resistance θJA(1) JEDEC Board (DSBGA) (2) 100.6°C/W

4L Cellphone Board (DSBGA) 174.8°C/W

(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(2) Detailed description of the board can be found in JESD51-7

ELECTRICAL CHARACTERISTICS

Limits in standard typeface are for TA= 25°C. Limits in boldface type apply over the full operating junction temperature range

(-40°C ≤TJ≤+125°C). Unless otherwise noted, specifications apply to the LP5990 Typical Application Circuit (pg. 1) with: VIN

= VOUT (NOM) + 1.0V, or 2.2V, whichever is higher. VEN = 1.0V, CIN = COUT = 1.0 μF, IOUT = 1.0 mA. (1),(2)

Symbol Parameter Conditions Min Typ Max Units

VIN Input Voltage 2.2 5.5 V

ΔVOUT Output Voltage Tolerance VIN = (VOUT(NOM) + 1.0V) to 5.5V −1 1 %

Line Regulation VIN = (VOUT(NOM) + 1.0V) to 5.5V, IOUT = 1 1 mV

Load Regulation IOUT = 1 mA to 200 mA 5 15 mV

ILOAD Load Current See(3) 0mA

Maximum Output Current 200

IQQuiescent Current (4) VEN = 1.0V, IOUT = 0 mA 30 75

VEN = 1.0V, IOUT = 200 mA 35 µA

VEN = <0.35V (Disabled) 0.01

VDO Dropout Voltage(5) IOUT = 200 mA 160 250 mV

ISC Short Circuit Current Limit See(6) 600 mA

PSRR Power Supply Rejection Ratio (7) f = 10 kHz, IOUT = 200 mA 55 dB

enOutput Noise Voltage (7) BW = 10 Hz to 100 V OUT = 1.8V 60 μVRMS

kHz, VIN = 4.2V, IOUT =VOUT = 2.8V 85

1 mA

TSHUTDOWN Thermal Shutdown Temperature 160 °C

Hysteresis 20

Enable Input Thresholds

VIL Low Input Threshold (VEN) VIN = 2.2V to 5.5V 0.35 V

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most

likely norm.

(3) The device maintains a stable, regulated output voltage without a load current.

(4) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value. This parameter only applies to output voltages above 2.8V.

(6) Short Circuit Current is measured with VOUT pulled to 0V.

(7) This specification is ensured by design.

Product Folder Links: LP5990

LP5990

SNVS438B –APRIL 2007–REVISED DECEMBER 2007

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ELECTRICAL CHARACTERISTICS (continued)

Limits in standard typeface are for TA= 25°C. Limits in boldface type apply over the full operating junction temperature range

(-40°C ≤TJ≤+125°C). Unless otherwise noted, specifications apply to the LP5990 Typical Application Circuit (pg. 1) with: VIN

= VOUT (NOM) + 1.0V, or 2.2V, whichever is higher. VEN = 1.0V, CIN = COUT = 1.0 μF, IOUT = 1.0 mA. (1),(2)

Symbol Parameter Conditions Min Typ Max Units

VIH High Input Threshold (VEN) VIN = 2.2V to 5.5V 1.0 V

IEN Input Current at VEN Pin (8) VEN = 5.5V and VIN = 5.5V 2 5μA

VEN = 0.0V and VIN = 5.5V 0.001

Transient Characteristics

ΔVOUT Line Transient (7) Trise = Tfall = 30μs. ΔVIN = 600 mV 4 mV

Load Transient (7) IOUT = 1 mA to 200 mA in 1 μs –50 mV

IOUT = 200 mA to 1 mA in 1 μs 50

TON Turn on Time To 98% of VOUT(NOM) 60 μs

TOFF Turn off Time from Enable 100mV of V OUT(NOM)IOUT= 0mA 500 μs

(8) There is a 3 MΩresistor between VEN and ground on the device.

OUTPUT & INPUT CAPACITOR, RECOMMENDED SPECIFICATIONS(1)

Symbol Parameter Conditions Min Nom Max Units

CIN Input Capacitance Capacitance for stability 0.3 1.0 µF

COUT Output Capacitance 0.3 1.0 10

ESR Output/Input Capacitance 5 500 mΩ

(1) The minimum capacitance should be greater than 0.3 µF over the full range of operating conditions. The capacitor tolerance should be

30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be

considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however

capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions.

Product Folder Links: LP5990

LP5990

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SNVS438B –APRIL 2007–REVISED DECEMBER 2007

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise specified,CIN = COUT = 1.0µF, VIN = VOUT(NOM) + 1.0V, VEN = 1.0V, IOUT = 1mA , T A= 25°C.

Output Voltage Change vs Temperature Ground Current vs Load Current

Figure 2. Figure 3.

Ground Current vs V IN.ILOAD= 1mA Ground Current vs VIN. ILOAD = 200mA

Figure 4. Figure 5.

Dropout Voltage Load Transient Response VOUT = 2.8V

Figure 6. Figure 7.

Product Folder Links: LP5990

LP5990

SNVS438B –APRIL 2007–REVISED DECEMBER 2007

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified,CIN = COUT = 1.0µF, VIN = VOUT(NOM) + 1.0V, VEN = 1.0V, IOUT = 1mA , T A= 25°C.

Load Transient Response. VOUT = 2.8V Short Circuit Current

Figure 8. Figure 9.

Line Transient Response Line Transient Response

Figure 10. Figure 11.

Start-up Time Shutdown Characteristics

Figure 12. Figure 13.

Product Folder Links: LP5990

LP5990

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SNVS438B –APRIL 2007–REVISED DECEMBER 2007

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified,CIN = COUT = 1.0µF, VIN = VOUT(NOM) + 1.0V, VEN = 1.0V, IOUT = 1mA , T A= 25°C.

Power Supply Rejection ratio Output Noise Density

Figure 14. Figure 15.

Product Folder Links: LP5990

PD =(TJMAX - TA)

TJA

LP5990

SNVS438B –APRIL 2007–REVISED DECEMBER 2007

www.ti.com

APPLICATION HINTS

POWER DISSIPATION AND DEVICE OPERATION

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power

dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces

between the die and ambient air. As stated in Note 3 of the Operating Ratings table, the allowable power

dissipation for the device in a given package can be calculated using the equation:

The actual power dissipation across the device can be represented by the following equation:

PD= (VIN – VOUT) x IOUT

This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage

drop across the device, and the continuous current capability of the device. These two equations should be used

to determine the optimum operating conditions for the device in the application.

EXTERNAL CAPACITORS

Like any low-dropout regulator, the LP5990 requires external capacitors for regulator stability. The LP5990 is

specifically designed for portable applications requiring minimum board space and smallest components. These

capacitors must be correctly selected for good performance.

INPUT CAPACITOR

An input capacitor is required for stability. The input capacitor should be at least equal to or greater than the

output capacitor. It is recommended that a 1.0 µF capacitor be connected between the LP5990 input pin and

ground.

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground

impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to

connect the battery or other power source to the LP5990, then it is recommended to increase the input capacitor

to at least 2.2µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected

to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at

the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain

0.3 μF over the entire operating temperature range.

OUTPUT CAPACITOR

The LP5990 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor

(dielectric types X5R or X7R) 1.0 μF, and with ESR between 5 mΩto 500 mΩ, is suitable in the LP5990

application circuit.

Other ceramic capacitors such as Y5V and Z5U are less suitable owing to their inferior temperature

characteristics. (See section in Capacitor Characteristics).

For this device the output capacitor should be connected between the VOUT pin and a good ground connection

and should be mounted within 1 cm of the device.

It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as

attractive for reasons of size and cost (see the section Capacitor Characteristics).

The output capacitor must meet the requirement for the minimum value of capacitance (0.3μF) and have an ESR

value that is within the range 5 mΩto 500 mΩfor stability.

Product Folder Links: LP5990

0 1.0 2.0_3.0

4.0

5.0

CAP VALUE (% OF NOM. 1 µF)

DC Bias (V)

100%

80%

60%

40%

20%

0402, 6.3V, X5R

0603, 10V, X5R

LP5990

www.ti.com

SNVS438B –APRIL 2007–REVISED DECEMBER 2007

CAPACITOR CHARACTERISTICS

The LP5990 is designed to work with ceramic capacitors on the input and output to take advantage of the

benefits they offer. For capacitance values in the range of 1.0 μF to 4.7 μF, ceramic capacitors are the smallest,

least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise.

The ESR of a typical 1.0 μF ceramic capacitor is in the range of 20 mΩto 40 mΩ, which easily meets the ESR

requirement for stability for the LP5990

For both input and output capacitors careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly depending on the conditions of operation and

capacitor type.

In particular the output capacitor selection should take account of all the capacitor parameters to ensure that the

specification is met within the application.Capacitance value can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.

The capacitor parameters are also dependant on particular case size with smaller sizes giving poorer

performance figures in general. As an example Figure 16 shows a typical graph showing a comparison of

capacitor case sizes in a Capacitance versus DC Bias plot. As shown in the graph, as a result of the DC Bias

condition, the capacitance value may drop below the minimum capacitance value given in the recommended

capacitor table (0.3µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case

size capacitor at higher bias voltages. It is therefore recommend that the capacitor manufacturer's specifications

for the nominal value capacitor are consulted for all conditions as some capacitors may not be suited in the

application.

The temperature performance of ceramic capacitors varies by type and manufacturer. Most large value ceramic

capacitors (≥2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the

capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.

A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable

and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than

ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance

and voltage ratings in the 0.47 μF to 4.7 μF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about

2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.

Figure 16.

NO-LOAD STABILITY

The LP5990 will remain stable and in regulation with no external load.

Product Folder Links: LP5990

LP5990

SNVS438B –APRIL 2007–REVISED DECEMBER 2007

www.ti.com

ENABLE CONTROL

The LP5990 may be switched ON or OFF by a logic input at the ENABLE pin, VEN . A high voltage at this pin will

turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3

nA. If the application does not require the shutdown feature, the VEN pin should be tied to VIN to keep the

regulator output permanently on.

The signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off

voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.

DSBGA MOUNTING

The DSBGA package requires specific mounting techniques, which are detailed in TI Application Note AN-1112

(SNVA009).

For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the

DSBGA device.

DSBGA LIGHT SENSITIVITY

Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as

halogen lamps can affect electrical performance if they are situated in proximity to the device.

Light with wavelengths in the red and infra-red part of the spectrum have the most detrimental effect thus the

fluorescent lighting used inside most buildings has very little effect on performance.

Product Folder Links: LP5990

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP5990TM-1.2/NOPB ACTIVE DSBGA YFQ 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TM-1.8/NOPB ACTIVE DSBGA YFQ 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TM-2.8/NOPB ACTIVE DSBGA YFQ 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TM-3.0/NOPB ACTIVE DSBGA YFQ 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TM-3.6/NOPB ACTIVE DSBGA YFQ 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TMX-1.2/NOPB ACTIVE DSBGA YFQ 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TMX-1.8/NOPB ACTIVE DSBGA YFQ 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TMX-2.8/NOPB ACTIVE DSBGA YFQ 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TMX-3.3/NOPB ACTIVE DSBGA YFQ 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

LP5990TMX-3.6/NOPB ACTIVE DSBGA YFQ 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP5990TM-1.2/NOPB DSBGA YFQ 4 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TM-1.8/NOPB DSBGA YFQ 4 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TM-2.8/NOPB DSBGA YFQ 4 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TM-3.0/NOPB DSBGA YFQ 4 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TM-3.6/NOPB DSBGA YFQ 4 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TMX-1.2/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TMX-1.8/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TMX-2.8/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TMX-3.3/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

LP5990TMX-3.6/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP5990TM-1.2/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5990TM-1.8/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5990TM-2.8/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5990TM-3.0/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5990TM-3.6/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5990TMX-1.2/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

LP5990TMX-1.8/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

LP5990TMX-2.8/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

LP5990TMX-3.3/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

LP5990TMX-3.6/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 2

MECHANICAL DATA

YFQ0004xxx

www.ti.com

TMD04XXX (Rev A)

0.600±0.075

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

4215073/A 12/12

D: Max =

E: Max =

0.936 mm, Min =

0.902 mm, Min =

0.876 mm

0.842 mm

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