ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost FEATURES * * * * * * * 1 * * * Maximum Sample Rate: 200 MSPS 11-bit Resolution with No Missing Codes 90 dBc SFDR at Fin = 10 MHz 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW using TI proprietary SNRBoost technology Total Power 1.1 W at 200 MSPS 90 dB Cross-talk Double Data Rate (DDR) LVDS and Parallel CMOS Output Options * * * Programmable Gain up to 6dB for SNR/SFDR Trade-off DC Offset Correction Gain Tuning Capability in Fine Steps (0.001 dB) Allows Channel-to-channel Gain Matching Supports Input Clock Amplitude Down to 400 mV p-p Differential Internal and External Reference Support 64-QFN Package (9 mm x 9 mm) DESCRIPTION ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications. ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB). The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel's gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (-40C to 85C). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com DRGND DRVDD AGND AVDD These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LVDS INTERFACE DA0P/M Digital Processing Block Sample & Hold INA_P INA_M 14 bit ADC DA2P/M DA4P/M SNRBoost 11 bit DDR Serializer DA6P/M DA8P/M Channel A DA10P/M CLKP CLKM OUTPUT CLOCK BUFFER CLOCKGEN CLKOUTP/M DB0P/M INB_P Digital Processing Block Sample & Hold INB_M 14 bit ADC DB2P/M DB4P/M SNRBoost 11 bit DDR Serializer DB6P/M DB8P/M Channel B DB10P/M VCM REFERENCE CONTROL INTERFACE SDOUT RESET SCLK SEN SDATA CTRL1 CTRL2 CTRL3 ADS62C17 Figure 1. ADS62C17 Block Diagram PACKAGE/ORDERING INFORMATION 2 PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS62C17 QFN-64 RGC -40C to 85C AZ62C17 ADS62C17IRGCR ADS62C17IRGCT Tape and Reel Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 THERMAL CHARACTERISTICS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER RJA (2) RJT (1) (2) (3) (3) TEST CONDITIONS TYP Soldered thermal pad, no airflow 22 Soldered thermal pad, 200 LFM 15 Bottom of package (thermal pad) 0.57 UNIT C/W With a JEDEC standard high K board and 5x5 via array. See Exposed Pad in the Application Information. RJA is the thermal resistance from the junction to ambient. RJT is the thermal resistance from the junction to the thermal pads. ABSOLUTE MAXIMUM RATINGS (1) VALUE Supply voltage range AVDD -0.3 to 3.9 Supply voltage range DRVDD -0.3 to 2.2 Voltage between AGND and DRGND -0.3 to 0.3 Voltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 to 3.3 Voltage between DRVDD to AVDD (when DRVDD leads AVDD) -1.5 to 1.8 Voltage applied to external pin, VCM (in external refersnce mode) Voltage applied to analog input pins - INP_A, INM_A, INP_B, INM_B Voltage applied to input pins - CLKP, CLKM (2), RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3 UNIT V V -0.3 to 2.0 -0.3V to minimum (3.6, AVDD + 0.3V) V -0.3V to ADD + 0.3V TA Operating free-air temperature range -40 to 85 C TJ Operating junction temperature range 125 C Tstg Storage temperature range ESD, human body model (1) (2) -54 to 150 C 2 kV Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < |0.3V|. This prevents the ESD protection diodes at the clock input pins from turning on. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 3 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com RECOMMENDED OPERATING CONDITIONS (1) MIN TYP MAX UNIT SUPPLIES AVDD Analog supply voltage 3.15 3.3 3.8 V DRVDD Digital supply voltage 1.7 1.8 1.9 V ANALOG INPUTS Differential input voltage range 2 Input common-mode voltage VPP 1.5 0.1 Voltage applied on CM in external reference mode V 1.5 0.05 V Maximum analog input frequency with 2V pp input amplitude (1) 500 MHz Maximum analog input frequency with 1V pp input amplitude (1) 800 MHz CLOCK INPUT Input clock sample rate 1 200 MSPS Input Clock amplitude differential (VCLKP- VCLKM) Sine wave, ac-coupled 3.0 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 3.3 V Input clock duty cycle 0.2 40% 50% 60% DIGITAL OUTPUTS CL Maximum external load capacitance from each output pin to DRGND RL Differential external load resistance between the LVDS output (LVDS interface) TA Operating free-air temperature (1) 4 -40 5 pF 100 85 C See Theory of Operation in the application section. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 ELECTRICAL CHARACTERISTICS (1) Typical values are at 25C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, -1dBFS differential analog input, internal reference mode, LVDS and CMOS interfaces unless otherwise noted. Min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.8V PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 11 bits ANALOG INPUTS Differential input voltage range 2.0 VPP Differential input resistance (at dc) See Figure 44 >1 M Differential input capacitance See Figure 45 3.5 pF Analog input bandwidth 700 MHz Analog input common mode current (per channel) 3.6 A/MSPS VCM common mode voltage output 1.5 V VCM output current capability 4 mA 262 mA 120 mA 87 mA POWER SUPPLY IAVDD Analog supply current IDRVDD Output buffer supply current LVDS interface With 100 external termination IDRVDD Output buffer supply current CMOS interface No external load capacitance Analog power 865 1025 mW Digital power LVDS interface 216 306 mW 45 75 mW Global power down No missing codes Assured DC ACCURACY DNL Differential Non-Linearity Fin = 170 MHz -0.6 0.2 0.6 LSB INL Integral Non-Linearity Fin = 170 MHz -2.5 0.75 2.5 LSB -20 2 20 mV Offset Error Offset error temperature coefficient Offset error variation with supply 0.02 mV/C 0.5 mV/V There are two sources of gain error - internal reference inaccuracy and channel gain error Gain error due to internal reference inaccuracy alone -1 0.2 1 Gain error of channel alone (2) -1 +0.2 1 Channel gain error temperature coefficient Gain matching (1) (2) (3) (3) -2 Difference in gain errors between two channels across two devices -4 % FS %/C 0.002 Difference in gain errors between two channels within the same device % FS 2 % FS 4 In CMOS interface, the DRVDD current scales with the sampling frequency and the load capacitance on output pins. This is specified by design and characterization; it is not tested in production. For two channels within the same device, only the channel gain error matters, as the reference is common for both channels. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 5 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, -1dBFS differential analog input, internal reference mode, SNRBoost disabled, LVDS and CMOS interfaces unless otherwise noted. Min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.8V PARAMETER SNR Signal to noise ratio LVDS TEST CONDITIONS MIN TYP MAX Fin = 20 MHz 67 Fin = 70 MHz 66.8 Fin = 170 MHz 0 dB gain 64.5 6 dB gain UNIT dBFS 66.3 64.4 Table 1. SNR Enhancement With SNRBoost Enabled SNRBoost bath-tub centered at Fsx0.25, -1 dBFS input applied at Fin = 125MHz, Sampling frequency = 200MSPS SNR Within Specified bandwidth, dBFS Bandwidth, MHz (1) 6 With SNRBoost Enabled (1) In Default Mode (SNRBoost Disabled) MIN TYP 5 78.8 79.6 10 75.8 15 74 20 MAX MIN TYP 83 85.6 76.6 80 82.6 74.9 78.2 80.9 72.7 73.6 77 79.6 30 71 71.9 74.4 76.4 40 69.8 70.6 72.7 74.5 MAX Using recommended SNRBoost coefficients. See note on SNRBoost in application section. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 ELECTRICAL CHARACTERISTICS Typical values are at 25C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, -1dBFS differential analog input, internal reference mode, SNRBoost disabled, 0dB gain, LVDS and CMOS interfaces unless otherwise noted. Min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.8V PARAMETER TEST CONDITIONS MIN Fin= 20 MHz SINAD Signal to Noise and Distortion Ratio 66.6 0 dB gain 63.5 6 dB gain THD Total Harmonic Distortion 83 0 dB gain 73 6 dB gain 83 Fin = 70 MHz 81 0 dB gain 71.5 6 dB gain 90 0 dB gain 73 6 dB gain dBc 83 dBc 92 85 Fin = 70 MHz 83 0 dB gain 73 6 dB gain 78 dBc 81 Fin= 20 MHz Worst Spur Other than second, third harmonics 75.5 94 Fin= 20 MHz Fin = 170 MHz dBc 79 Fin = 70 MHz Fin = 170 MHz dBFS 81 Fin= 20 MHz HD3 Third Harmonic Distortion 78 Fin= 20 MHz Fin = 170 MHz HD2 Second Harmonic Distortion 65.7 85 Fin = 70 MHz Fin = 170 MHz UNIT 64.2 Fin= 20 MHz SFDR Spurious Free Dynamic Range MAX 66.9 Fin = 70 MHz Fin = 170 MHz TYP 94 Fin = 70 MHz 92 Fin = 170 MHz 80 IMD 2-Tone Inter-modulation Distortion F1 = 185 MHz, F2 = 190 MHz, Each tone at -7 dBFS Input Overload recovery Recovery to within 1% (of final value) for 6-dB overload with sine wave input at Fclk/4 Cross-talk PSRR AC Power Supply Rejection Ratio dBc 90 87 dBFS 1 clock cycles Up to 200 MHz cross-talk frequency 90 dB For 100 mV pp signal on AVDD supply 25 dB Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 7 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com DIGITAL CHARACTERISTICS -- ADS62C17 The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 3.3V, DRVDD = 1.8V PARAMETER TEST CONDITIONS DIGITAL INPUTS - CTRL1, CTRL2, CTRL3, RESET, SCLK, SDATA, SEN High-level input voltage MIN High-level input current Low-level input current MAX 1.3 All digital inputs support 1.8 V and 3.3 V CMOS logic levels. Low-level input voltage TYP UNIT (1) 0.4 SDATA, SCLK (2) VHIGH = 3.3 V 16 SEN (3) VHIGH = 3.3 V 10 SDATA, SCLK VLOW = 0 V 0 SEN VLOW = 0 V -20 Input capacitance V A A 4 pF DRVDD - DRVDD 0.1 V DIGITAL OUTPUTS - CMOS INTERFACE (DA0-DA10, DB0-DB10, CLKOUT, SDOUT) High-level output voltage Low-level output voltage Ioh = 1mA Iol = 1mA 0 Output capacitance (internal to device) 0.1 2 V pF DIGITAL OUTPUTS - LVDS INTERFACE (DA0P/M TO DA10P/M, DB0P/M TO DB10P/M, CLKOUTP/M) VODH, High-level output differential voltage With external 100 termination +275 +350 +425 mV VODL, Low-level output differential voltage With external 100 termination. -425 -350 -275 mV 1.0 1.15 1.40 VOCM, Output common-mode voltage Capacitance inside the device from each output to ground Output Capacitance (1) (2) (3) 2 V pF SCLK, SDATA, SEN function as digital input pins in serial configuration mode. SDATA, SCLK have internal 200 k pull-down resistor SEN has internal 100 k pull-up resistor to AVDD. DAnP / DBnP Logic 0 VODL = -350 mV* Logic 1 VODH = +350 mV* DAnM / DBnM VOCM GND GND * With external 100 W termination Figure 2. LVDS Output Voltage Levels 8 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 TIMING CHARACTERISTICS -- LVDS AND CMOS MODES (1) Typical values are at 25C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, sine wave input clock, CLOAD = 5pF (2), RLOAD = 100 (3), no internal termination, LOW SPEED mode disabled, unless otherwise noted. Min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.7V to 1.9V. PARAMETER ta TEST CONDITIONS Aperture delay Aperture delay matching tj MIN TYP MAX 0.7 1.2 1.7 between two channels of the same device Aperture jitter Wake-up time ADC Latency (4) UNIT ns 50 ps 145 fs rms Time to valid data after coming out of STANDBY mode 1 3 Time to valid data after coming out of global powerdown 20 50 Time to valid data after stopping and restarting the input clock 10 Default, after reset 22 s Clock cycles DDR LVDS MODE (5) Data setup time (6) tsu (7) th Data hold time tPDI Clock propagation delay tdelay Data valid (7) to zero-crossing of CLKOUTP 0.8 1.15 ns Zero-crossing of CLKOUTP to data becoming invalid (7) 0.8 1.15 ns Input clock falling edge cross-over to output clock rising edge cross-over 100 MSPS Sampling frequency 200 MSPS Ts = 1/Sampling frequency tPDI = 0.69xTs + tdelay 4.2 5.7 7.2 ns tdelay skew Difference in tdelay between two devices operating at same temperature & SVDD supply voltage. 500 LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP-CLKOUTM) 100 MSPS Sampling frequency 200 MSPS 52% tRISE, tFALL Data rise time, Data fall time Rise time measured from -100 mV to +100 mV Fall time measured from +100 mV to -100 mV 1MSPS Sampling frequency 200 MSPS 0.14 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from -100 mV to +100 mV Fall time measured from +100 mV to -100 mV 1 MSPS Sampling frequency 200 MSPS 0.14 ns tOE Output buffer enable to data delay Time to valid data after output buffer becomes active 100 ns ps PARALLEL CMOS MODE at Fs=200 MSPS (8) tSTART Input clock to data delay Input clock falling edge cross-over to start of data valid (7) tDV Data valid time Time interval of valid data (7) 1.7 tPDI Clock propagation delay Input clock falling edge cross-over to output clock rising edge cross-over 100 MSPS Sampling frequency 150 MSPS Ts = 1/Sampling frequency tPDI = 0.28xTs + tdelay tdelay 2.5 5.5 2.7 7.5 ns ns 8.5 ns Output clock duty cycle Duty cycle of output clock, CLKOUT 100 MSPS Sampling frequency 150 MSPS 43 tRISE, tFALL Data rise time, Data fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1 Sampling frequency 200 MSPS 1.2 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1 Sampling frequency 150 MSPS 0.8 ns tOE Output buffer enable (OE) to data delay Time to valid data after output buffer becomes active (1) (2) (3) (4) (5) (6) (7) (8) ns Timing parameters are ensured by design and characterization and not tested in production. CLOAD is the effective external single-ended load capacitance between each output pin and ground RLOAD is the differential load resistance between the LVDS output pair. At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. Measurements are done with a transmission line of 100 characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of -100.0mV. Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V. For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 9 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Table 2. LVDS Timings at Lower Sampling Frequencies Sampling Frequency, MSPS Setup Time, ns Hold Time, ns MIN TYP 185 0.9 1.25 MAX MIN TYP 0.85 1.25 150 1.15 1.6 1.1 1.5 125 1.6 2 1.45 1.85 <100 Enable LOW SPEED mode 2 MAX 2 tPDI, ns 1 Fs 100 Enable LOW SPEED mode MIN TYP MAX 12.6 Table 3. CMOS Timings at Lower Sampling Frequencies Timings Specified With Respect to Input Clock Sampling Frequency, MSPS tSTART, ns MIN TYP Data Valid Time, ns MAX MIN TYP 190 1.9 2 3 170 0.9 2.7 3.7 150 6 3.6 4.6 MAX Timings Specified With Respect to CLKOUT Sampling Frequency, MSPS Setup Time, ns MIN TYP 150 2.8 125 3.8 <100 Enable LOW SPEED mode 5 MAX Hold Time, ns MIN TYP 4.4 0.5 1.2 5.4 0.8 1.5 MAX 1.2 tPDI, ns 1 Fs 100 Enable LOW SPEED mode MIN TYP MAX 9 10 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 N+3 N+2 N+1 Sample N N+4 N+24 N+23 N+22 INPUT SIGNAL ta INPUT CLOCK CLKM CLKP CLKOUTM CLKOUTP 22 clock cycles * DDR LVDS OUTPUT DATA DXP, DXM E O E O E O E O E t PDI O E O E O E O E O E O E - Even bits D0, D2, D4... N-22 O - Odd bits D1, D3, D5... N-21 N-20 N-1 N-19 N N+2 N+1 CLKOUT t PDI 22 clock cycles * PARALLEL CMOS OUTPUT DATA D0:D10 N-22 N-21 N-20 N18 N-19 N-1 N N+1 N+2 Figure 3. Latency Diagram CLKP Input clock CLKM t PDI CLKOUTM Output clock CLKOUTP t su Output data pair DAnP/M DBnP/M th Dn* t su th Dn+1* *Dn - Bits D1,D3,D5... *Dn+1 - Bits D0,D2,D4... Figure 4. LVDS Interface Timing Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 11 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com CLKP CLKP Input Clock CLKM CLKM tPDI Output Clock CLKOUTCLKOUT tsu su Output Data DAn, DBn th Dn* CLKP CLKP Input Clock CLKM CLKM tSTART tDV Output Clock DAn, DBn Dn* *Dn - Bits D0, D1, D2....of channel A and B Figure 5. CMOS Interface Timing DEVICE CONFIGURATION ADS62C17 can be configured independently using either parallel interface control or serial interface programming. PARALLEL CONFIGURATION ONLY To put the device in parallel configuration mode, keep RESET tied to high (AVDD). Now, pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC. The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in Table 3 to Table 6. There is no need to apply reset and SDATA can be kept low. In this mode, SEN and SCLK function as parallel interface control pins. Frequently used functions can be controlled in this mode - Power down modes, internal/external reference, selection between LVDS/CMOS interface and output data format. Table 4 has a brief description of the modes controlled by the four parallel pins. Table 4. PARALLEL PIN DEFINITION PIN SCLK SEN CTRL1 CTRL2 CONTROLS MODES Analog control pins (controlled by analog voltage level, see Figure 5 Digital control pints (controlled by digital logic levels) Internal or External reference LVDS/CMOS interface and Output Data Format Control SNRBoost, Standby and MUX mode. CTRL3 12 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 SERIAL INTERFACE CONFIGURATION ONLY To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to be kept low. SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internal registers of the ADC. The registers can be reset either by applying a pulse on RESET pin or by setting the <RESET> bit high. The serial interface section describes the register programming and register reset in more detail. USING BOTH SERIAL INTERFACE and PARALLEL CONTROLLS For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3) can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device will automatically get configured as per the voltage settings on these pins (Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by setting bit <RST> = 1. After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. DETAILS OF PARALLEL CONFIGURATION ONLY The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is shown in Figure 6. Table 5. SCLK Control Pin SCLK DESCRIPTION 0 +200mV/-0mV Internal reference (3/8)AVDD 200mV External reference (5/8)2AVDD 200mV External reference AVDD +0mV/-200mV Internal reference Table 6. SEN Control Pin SEN DESCRIPTION 0 +200mV/-0mV Offset binary and DDR LVDS output (3/8)AVDD 200mV 2's complement format and DDR LVDS output (5/8)2AVDD 200mV 2's complement format and parallel CMOS output AVDD +0mV/-200mV Offset binary and parallel CMOS output Table 7. CTRL1, CTRL2 and CTRL3 Pins CTRL1 CTRL2 LOW LOW LOW Normal operation LOW LOW HIGH SNRBoost enabled for Channel B (1) LOW HIGH LOW SNRBoost enabled for Channel A (1) LOW HIGH HIGH SNRBoost enabled for Channel A and B (1) HIGH LOW LOW Global power down HIGH LOW HIGH Channel B standby (1) CTRL3 DESCRIPTION To enable & disable SNRBoost mode using the CTRL pins, reset the register bits <SNRBoost Enable CHA> = 0 & <SNRBoost Enable - CHB> = 0. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 13 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Table 7. CTRL1, CTRL2 and CTRL3 Pins (continued) CTRL1 CTRL2 CTRL3 HIGH HIGH LOW Channel A standby DESCRIPTION HIGH HIGH HIGH MUX mode of operation, Channel A and B data is multiplexed and output on DA10 to DA0 pins. AVDD (5/8)AVDD (5/8)AVDD AVDD GND (3/8)AVDD (3/8)AVDD To Parallel Pin GND Figure 6. Simple Scheme to Configure Parallel Pins SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty cycle. Register Initialization (when using serial interface only) After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two ways: 1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as shown in Figure 7 2. OR By applying software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to HIGH. This initializes internal registers to their default values and then self-resets the <RESET> bit to low. In this case the RESET pin is kept low. REGISTER DATA REGISTER ADDRESS SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 tSCLK D4 tDSU D3 D2 D1 D0 tDH SCLK SEN tSLOADH tSLOADS RESET Figure 7. Serial Interface Timing 14 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25C, min and max values across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.8V, unless otherwise noted. PARAMETER MIN >DC TYP MAX UNIT 20 MHz fSCLK SCLK frequency (= 1/ tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDS SDATA setup time 25 ns tDH SDATA hold time 25 ns Serial Register Readout The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. a. b. c. d. e. First, set register bit <SERIAL READOUT> = 1. This also disables any further writes into the registers. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. The device outputs the contents (D7-D0) of the selected register on the SDOUT pin. The external controller can latch the contents at the falling edge of SCLK. To enable register writes, reset register bit <SERIAL READOUT> =0. The serial register readout works with both CMOS and LVDS interfaces. When <SERIAL READOUT> is disabled, SDOUT pin is forced low by the device (and not put in high-impedance). If serial readout is not used, SDOUT pin has to be floated. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 15 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com A) Enable serial readout (<SERIAL READOUT> = 1) REGISTER DATA (D7:D0) = 0x01 REGISTER ADDRESS (A7:A0) = 0x00 SDATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SCLK SEN SDOUT Pin SDOUT is NOT in high-impedance state; it is forced low by the device (<SERIAL READOUT> = 0) B) Read contents of register 0x3F. This register has been initialized with 0x04 (device is put in global power down mode) REGISTER DATA (D7:D0 ) = XX (don't care) REGISTER ADDRESS (A7:A0) = 0x3F SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 SCLK SEN SDOUT Pin SDOUT functions as serial readout (<SERIAL READOUT> = 1) Figure 8. Serial Readout RESET TIMING (WHEN USING SERIAL INTERFACE ONLY) Typical values at 25C, min and max values across the full temperature range TMIN = -40C to TMAX = 85C, unless otherwise noted. PARAMETER CONDITIONS MIN t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse width Pulse width of active RESET signal TYP MAX 1 ns 10 ns 1 (1) t3 (1) 16 Register write delay Delay from RESET disable to SEN active 100 UNIT s ns The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1usec, the device could enter the parallel configuration mode briefly and then return back to serial interface mode. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 9. Reset Timing Diagram Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 17 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com SERIAL REGISTER MAP Table 8. Summary of Functions Supported by Serial Interface (1) REGISTER ADDRESS REGISTER FUNCTIONS A7 - A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 00 <RESET> Software Reset 0 0 0 0 0 0 <SERIAL READOUT> 0 0 <STAND BY> 0 0 0 0 <ENABLE LOW SPEED mode> <REF> Internal or external reference 0 0 0 20 0 0 3F 0 40 0 0 0 0 41 <LVDS CMOS> Output interface 0 0 0 0 <ENABLE INDEPENDENT CHANNEL CONTROL> 44 50 53 (1) 18 0 0 <CLKOUT EDGE CONTROL> 51 52 <POWER DOWN MODES> 0 0 0 0 0 0 0 <DATA FORMAT> 2s comp or offset binary <CUSTOM PATTERN LOW> 0 0 0 <CUSTOM PATTERN HIGH> 0 <OFFSET CORRECTION ENABLE - Common/Ch A> 0 0 0 0 55 <GAIN PROGRAMMABILITY - Common/Ch A> 0 to 6 dB in 0.5 dB steps <OFFSET CORRECTION TIME CONSTANT - Common/ Ch A > 56 <SNRBoost Coeff 1 - Common/ Ch A > <SNRBoost Coeff 2 - Common/ Ch A > <FINE GAIN ADJUST - Common/ Ch A > +0.001 dB to +0.134 dB, in 128 steps 57 0 59 0 0 0 0 0 62 0 0 0 0 0 63 0 0 66 0 <OFFSET CORRECTION ENABLE- Ch B> 0 0 <SNRBoost Enable - Common/ Ch A > <TEST PATTERNS - Common/ Ch A > <OFFSET PEDESTAL - Common/ Ch A > 0 0 0 0 0 0 68 <GAIN PROGRAMMABILITY - Ch B> 0 to 6 dB in 0.5 dB steps <OFFSET CORRECTION TIME CONSTANT - Ch B> 69 <SNRBoost Coeff 1 - Ch B> <SNRBoost Coeff 2 - Ch B> <FINE GAIN ADJUST - Ch B> +0.001 dB to +0.134 dB, in 128 steps 6A 0 6C 0 0 0 0 75 0 0 0 0 76 0 0 0 0 0 0 <SNRBoost Enable - Ch B> <TEST PATTERNS - Ch B> <OFFSET PEDESTAL - Ch B> Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 DESCRIPTION OF SERIAL REGISTERS A7 - A0 IN HEX 00 D7 D7 <RESET> Software Reset D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 <SERIAL READOUT> <RESET> 1 Software reset applied - resets all internal registers and self-clears to 0. D0 <SERIAL READOUT> 0 Serial readout disabled. SDOUT is forced high or low by the device (and not out in high impedance state). 1 Serial readout enabled, Pin SDOUT functions as serial data readout. This mode is available only with CMOS output interface. With LVDS interface, pin 56 becomes CLKOUTM. A7 - A0 IN HEX 20 D2 D7 0 D6 0 D5 0 D4 0 D3 0 D2 <ENABLE LOW SPEED MODE> D1 0 D0 0 <ENABLE LOW SPEED MODE> 0 LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS. 1 Enable LOW SPEED mode for sampling frequencies <= 100 MSPS. A7 - A0 IN HEX 3F D6-D5 D7 0 D6 D5 <REF> D4 0 D3 0 D2 0 D1 <STANDBY> D0 0 <REF> Internal or external reference selection 01 Internal reference enabled 11 External reference enabled D1 <STANDBY> 0 Normal operation 1 ADC is powered down for both channels. Internal references, output buffers are active. This results in quick wake-up time from standby. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 19 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com A7 - A0 IN HEX 40 D3-D0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 POWER DOWN MODES D0 <POWER DOWN MODES> 0000 Pins CTRL1, CTRL2 & CTRL3 determine power down modes. 1000 Normal operation 1001 Output buffer disabled for channel B 1010 Output buffer disabled for channel A 1011 Output buffer disabled for channel A and B 1100 Global power down 1101 Channel B standby 1110 Channel A standby 1111 Multiplexed mode, MUX- (only with CMOS interface) Channel A and B data is multiplexed and output on DA10 to DA0 pins. A7 - A0 IN HEX 41 D7 D7 <LVDS CMOS> D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 <LVDS CMOS> 0 Parallel CMOS interface 1 DDR LVDS interface 20 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 A7 - A0 IN HEX 44 D7 D6 D5 D4 <CLKOUT EDGE CONTROL> Output clock edge control D3 D2 D1 0 D0 0 LVDS Interface D7-D5 <CLKOUT POSN> Output clock rising edge position 000, 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by + (4/26)Ts 110 Rising edge aligned with data transition 111 Rising edge shifted by - (4/26)Ts D4-D2 <CLKOUT POSN> Output clock falling edge position 000, 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by + (4/26)Ts 110 Falling edge aligned with data transition 111 Falling edge shifted by - (4/26)Ts CMOS INterface D7-D5 <CLKOUT POSN> Output clock rising edge position 000, 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by + (4/26)Ts 110 Rising edge shifted by - (6/26)Ts 111 Rising edge shifted by - (4/26)Ts D4-D2 <CLKOUT POSN> Output clock falling edge position 000, 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by + (4/26)Ts 110 Falling edge shifted by - (6/26)Ts 111 Falling edge shifted by - (4/26)Ts A7 - A0 IN HEX 50 D6 D7 0 D6 <ENABLE INDEPENDENT CHANNEL CONTROL> D5 0 D4 0 D3 0 D2 D1 <DATA FORMAT> 2s complement or offset binary 0 D0 0 <ENABLE INDEPENDENT CHANNEL CONTROL> 0 Common control - both channels use common control settings for test patterns, offset correction, gain, gain correction and SNRBoost functions. These settings can be specified in a single set of registers. 1 Independent control - both channels can be programmed with independent control settings for test patterns, offset correction and SNRBoost functions. Separate registers are available for each channel. D2-D1 <DATA FORMAT> 10 2s complement 11 Offset binary Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 21 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com A7 - A0 IN HEX 51 52 D7-D3 D7 D6 0 0 D5 D4 <Custom Pattern Low> D3 D2 0 <Custom Pattern High> D1 0 D0 0 <CUSTOM LOW> 5 lower bits of custom pattern available at the output instead of ADC data D5-D0 <CUSTOM HIGH> 6 upper bits of custom pattern available at the output instead of ADC data A7 - A0 IN HEX 53 D6 D7 0 D6 <OFFSET CORRECTION ENABLE - Common/Ch A> Offset correction enable D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 <OFFSET CORRECTION ENABLE - Common/Ch A> Offset correction enable control for both channels (with common control) or for channel A only (with independent control). 0 Offset correction disabled 1 Offset correction enabled See Offset Correction 22 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 A7 - A0 IN HEX 55 D7-D4 D7 D6 D5 D4 <GAIN PROGRAMMABILITY - Common/Ch A> D3 D2 D1 D0 <OFFSET CORR TIME CONSTANT - Common/Ch A> Offset correction time constant <GAIN PROGRAMMABILITY - Common/Ch A> Gain control for both channels (with common control) or for channel A only (with independent control). 0000 0 dB gain, default after reset 0001 0.5 dB gain 0010 1.0 dB gain 0011 1.5 dB gain 0100 2.0 dB gain 0101 2.5 dB gain 0110 3.0 dB gain 0111 3.5 dB gain 1000 4.0 dB gain 1001 4.5 dB gain 1010 5.0 dB gain 1011 5.5 dB gain 1100 6.0 dB gain D3-D0 <OFFSET CORR TIME CONSTANT - Common/Ch A> Correction loop time constant in number of clock cycles. Applies to both channels (with common control) or for channel A only (with independent control). 0000 256 k 0001 512 k 0010 1 M 0011 2 M 0100 4 M 0101 8 M 0110 16 M 0111 32 M 1000 64 M 1001 128 M 1010 256 M 1011 512 M A7 - A0 IN HEX 56 D7 D6 D5 D4 <SNRBoost Coeff 1 - Common/CH A> D3 D2 D1 D0 <SNRBoost Coeff 2 - Common/CH A> See SNR enhancement using SNRBoost Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 23 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com A7 - A0 IN HEX 57 D7 0 D6 D5 D4 D3 D2 D1 D0 <FINE GAIN ADJUST - Common/Ch A> +0.001 dB to +0.134 dB, in 128 steps Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only additive, has 128 steps & a range of 0.134dB. The relation between the FINE GAIN ADJUST bits & the trimmed channel gain is: Channel Gain = 20 x log10[1 + (FINE GAIN ADJUST/8192)] Note that the total device gain = ADC gain + Channel gain. The ADC gain is determined by register bits <GAIN PROGRAMMABILITY> A7 - A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 59 0 0 0 0 0 0 0 <SNRBoost Enable - CH A> D0 <SNRBoost Enable - CH A> SNRBoost control for both channels (with common control) or for channel A only (with independent control). 0 SNRBoost disabled 1 SNRBoost enabled A7 - A0 IN HEX 62 D2-D0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 D1 <TEST PATTERNS> D0 <TEST PATTERNS> Test Patterns to verify data capture. Applies to both channels (with common control) for channel A only (with independent control) 000 Normal operation 001 Outputs all zeros 010 Outputs all ones 011 Outputs toggle pattern Output data <D10:D0> alternates between 01010101010 and 10101010101 every clock cycle. 100 Outputs digital ramp Output data increments by one LSB (12-bit) every 8th clock cycle from code 0 to code 2047. 101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern) 110 Unused 111 Unused 24 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 A7 - A0 IN HEX 63 D5-D0 D7 0 D6 0 D5 D4 D3 D2 <OFFSET PEDESTAL - Common/Ch A> D1 D0 <OFFSET PEDESTAL - Common/Ch A> When the offset correction is enabled, the final converged value after the offset is corrected will be the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. See "Offset Correction" in application section. Applies to both channels (with common control) or for channel A only (with independent control). 011111 PEDESTAL = 31 LSB 011110 PEDESTAL = 30 LSB 011101 PEDESTAL = 29 LSB .... 000000 PEDESTAL = 0 LSB .... 111111 PEDESTAL = -1 LSB 111110 PEDESTAL = -2 LSB .... 100000 PEDESTAL = -32LSB A7 - A0 IN HEX 66 D6 D7 0 D6 <OFFSET CORRECTION ENABLE - CH B> Offset correction enable D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 <OFFSET CORRECTION ENABLE - CH B> Offset correction enable control for channel B (only with independent control). 0 offset correction disabled 1 offset correction enabled Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 25 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com A7 - A0 IN HEX 68 D7-D4 D7 D6 D5 D4 <GAIN PROGRAMMABILITY - CH B> D3 D2 D1 D0 <OFFSET CORR TIME CONSTANT - CH B> Offset correction time constant <GAIN - CH B> Gain programmability in 0.5 dB steps Applies to channel B (only with independent control). 0000 0 dB gain, default after reset 0001 0.5 dB gain 0010 1.0 dB gain 0011 1.5 dB gain 0100 2.0 dB gain 0101 2.5 dB gain 0110 3.0 dB gain 0111 3.5 dB gain 1000 4.0 dB gain 1001 4.5 dB gain 1010 5.0 dB gain 1011 5.5 dB gain 1100 6.0 dB gain D3-D0 <OFFSET CORR TIME CONSTANT - CH B> Time constant of correction loop in number of clock cycles. Applies to channel B (only with independent control) 0000 256 k 0001 512 k 0010 1 M 0011 2 M 0100 4 M 0101 8 M 0110 16 M 0111 32 M 1000 64 M 1001 128 M 1010 256 M 1011 512 M A7 - A0 IN HEX 69 D7 D6 D5 <SNRBoost Coeff 1 - CH B> D4 D3 D2 D1 <SNRBoost Coeff 2 - CH B> D0 See SNR enhancement using SNRBoost 26 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 A7 - A0 IN HEX 6A D7 D6 D5 D4 D3 D2 D1 <GAIN CORRECTION - CH B> +0.001 dB to +0.134 dB, in 128 steps D0 Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only additive, has 128 steps & a range of 0.134dB. The relation between the FINE GAIN ADJUST bits & the trimmed channel gain is: Channel Gain = 20 x log10[1 + (FINE GAIN ADJUST/8192)] Note that the total device gain = ADC gain + Channel gain. The ADC gain is determined by register bits <GAIN PROGRAMMABILITY> A7 - A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 6C 0 0 0 0 0 0 0 <SNRBoost Enable - CH B> D0 <SNRBoost Enable - CH B> SNRBoost control for channel B (only with independent control). 0 SNRBoost disabled 1 SNRBoost enabled A7 - A0 IN HEX 75 D2-D0 D7 D6 D5 0 D4 0 D3 0 D2 D1 D0 <TEST PATTERNS - CH B> <TEST PATTERNS> Test Patterns to verify data capture Applies to both channels (with common control) for channel A only (with independent control) 000 Normal operation 001 Outputs all zeros 010 Outputs all ones 011 Outputs toggle pattern Output data <D10:D0> alternates between 01010101010 and 10101010101 every clock cycle. 100 Outputs digital ramp Output data increments by one LSB (12-bit) every 8th clock cycle from code 0 to code 2047. 101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern) 110 Unused 111 Unused Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 27 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com A7 - A0 IN HEX 76 D5-D0 D7 0 D6 0 D5 D4 D3 D2 D1 <OFFSET PEDESTAL - Common/Ch A> D0 <OFFSET PEDESTAL - Ch B> When the offset correction is enabled, the final converged value after the offset is corrected will be the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. See "Offset Correction" in application section. Applies to both channels (with common control) or for channel A only (with independent control). 011111 PEDESTAL = 31 LSB 011110 PEDESTAL = 30 LSB 011101 PEDESTAL = 29 LSB .... 000000 PEDESTAL = 0 LSB .... 111111 PEDESTAL = -1 LSB 111110 PEDESTAL = -2 LSB .... 100000 28 PEDESTAL = -32LSB Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 DB0M NC NC DRGND D R V DD C LKO UTP C LKOU TM DA 10P DA 10M DA8P DA8 M DA 6 P DA 6M 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 DRGND DB0P DRVDD SDOUT PIN CONFIGURATION (LVDS INTERFACE) - ADS62C17 1 48 DRVDD DB 2M 2 47 DA4P DB 2P 3 46 DA4M PAD (Connected to DRGND) 4 45 DA 2 P DB4P 5 44 DA 2M DB 6M 6 43 DA0P DB 6P 7 42 DA 0 M DB8M 8 41 NC DB8P 9 40 NC DB10M 10 39 DRGND DB10P 11 38 DRVDD RESET 12 37 CTRL 3 SCLK 13 36 CTRL 2 SDATA 14 35 CTRL 1 SEN 15 34 AVDD AVDD 16 25 26 27 28 29 30 31 AGND AGND IN P _ A IN M_ A AGND 32 AGND 24 C LKM AGND 23 C LKP IN M _ B 22 AGND 21 VCM 20 NC 19 IN P _ B AVDD 18 AGND AGND DB4M Figure 10. Pin Configuration Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 29 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com PIN ASSIGNMENTS (LVDS INTERFACE) - ADS62C17 PIN NUMBER NO. OF PINS PIN TYPE AVDD 16, 33, 34 3 I Analog power supply AGND 17,18,21,24, 27,28,31,32 8 I Analog ground CLKP, CLKM 25, 26 2 I Differential clock input INP_A, INM_A 29, 30 2 I Differential analog input, Channel A INP_B, INM_B 19, 20 2 I Differential analog input, Channel B 23 1 IO NAME VCM DESCRIPTION Internal reference mode - Common-mode voltage output. External reference mode - Reference input. The voltage forced on this pin sets the internal references. RESET 12 1 I Serial interface RESET input. When using the serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. Refer to Serial Interface section. In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK and SEN are used as parallel control pins in this mode) The pin has an internal 100 k pull-down resistor. SCLK 13 1 I This pin functions as serial interface clock input when RESET is low. It controls selection of internal or external reference when RESET is tied high. See Table 5 for detailed information. The pin has an internal 100 k pull-down resistor. SDATA 14 1 I Serial interface data input. The pin has an internal 100 k pull-down resistor. The pin has no function in parallel interface mode and can be tired to ground. SEN 15 1 I This pin functions as serial interface enable input when RESET is low. It controls selection of data format and interface type when RESET is tied high. See Table 6 for detailed information. The pin has an internal 100 k pull-up resistor to AVDD SDOUT 64 1 O This pin functions as serial interface register readout, when the <SERIAL READOUT> bit is enabled. CTRL1 35 1 I CTRL2 36 1 I CTRL3 37 1 I CLKOUTP 57 1 O Differential output clock, true CLKOUTM 56 1 O Differential output clock, complement DA0P, DA0M 2 O Differential output data pair, D0 and 0 multiplexed - Channel A DA2P, DA2M 2 O Differential output data D1 and D2 multiplexed, true - Channel A DA4P, DA4M 2 O Differential output data D3 and D4 multiplexed, true - Channel A DA6P, DA6M 2 O Differential output data D5 and D6 multiplexed, true - Channel A DA8P, DA8M 2 O Differential output data D7 and D8 multiplexed, true - Channel A DA10P, DA10M 2 O Differential output data D9 and D10 multiplexed, true - Channel A 2 O Differential output data pair, D0 and 0 multiplexed - Channel B DB2P, DB2M 2 O Differential output data D1 and D2 multiplexed, true - Channel B DB4P, DB4M 2 O Differential output data D3 and D4 multiplexed, true - Channel B DB6P, DB6M 2 O Differential output data D5 and D6 multiplexed, true - Channel B DB8P, DB8M 2 O Differential output data D7 and D8 multiplexed, true - Channel B DB10P, DB10M 2 O Differential output data D9 and D10 multiplexed, true - Channel B 4 I Output buffer supply When <SERIAL READOUT> = 0, this pin forces logic LOW & is not tri-stated. DB0P, DB0M DRVDD 30 Refer to Figure 10 1,38,48,58 Digital control input pins. Together, they control SNRBoost control and power down modes. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 PIN NAME DRGND NC NUMBER NO. OF PINS PIN TYPE 39,49,59,PAD 4 I DESCRIPTION Output buffer ground Refer to Figure 10 Do not connect DB0 NC NC NC DRGND DRVDD CLKOUT U NUSED DA10 DA9 DA8 DA7 DA6 DA5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 DRGND SDOUT PIN CONFIGURATION (CMOS INTERFACE) - ADS62C17 DRVDD 1 48 DRVDD DB1 2 47 DA4 DB2 3 46 DA3 PAD (Connected to DRGND) 4 45 DA2 DB 4 5 44 DA1 DB 5 6 43 DA0 DB 6 7 42 NC DB 7 8 41 NC DB 8 9 40 NC DB 9 10 39 DRGND DB10 11 38 DRVDD RESET 12 37 CTRL 3 SCLK 13 36 CTRL 2 SDATA 14 35 CTRL 1 SEN 15 34 AVDD AVDD 16 25 26 27 28 29 30 31 AGND AGND INP_A INM_A AGND 32 AGND 24 CLKM AGND 23 CLKP INM_B 22 AGND 21 VCM 20 NC 19 INP_B AVDD 18 AGND AGND DB3 Figure 11. Pin Configuration Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 31 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com PIN ASSIGNMENTS (CMOS INTERFACE) - ADS62C17 PIN NUMBER NO. OF PINS PIN TYPE AVDD 16, 33, 34 3 I Analog power supply AGND 17,18,21,24, 27,28,31, 32 8 I Analog ground CLKP, CLKM 25, 26 2 I Differential clock input INP_A, INM_A 29, 30 2 I Differential analog input, Channel A INP_B, INM_B 19, 20 2 I Differential analog input, Channel B 23 1 IO NAME VCM DESCRIPTION Internal reference mode - Common-mode voltage output. External reference mode - Reference input. The voltage forced on this pin sets the internal references. RESET 12 1 I Serial interface RESET input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. Refer to SERIAL INTERFACE section. In parallel interface mode, the user has to tie RESET pin permanently high. (SDATA and SEN are used as parallel control pins in this mode) The pin has an internal 100 k pull-down resistor. SCLK 13 1 I This pin functions as serial interface clock input when RESET is low. It controls selection of internal or external reference when RESET is tied high. See Table 5 for detailed information. The pin has an internal 100 k pull-down resistor. SDATA 14 1 I Serial interface data input. The pin has an internal 100 k pull-down resistor. The pin has no function in parallel interface mode and can be tired to ground. SEN 15 1 I This pin functions as serial interface enable input when RESET is low. It controls selection of data format and interface type when RESET is tied high. See Table 6 for detailed information. The pin has an internal 100 k pull-up resistor to AVDD SDOUT 64 1 O This pin functions as serial interface register readout, when the <SERIAL READOUT> bit is enabled. CTRL1 35 1 I CTRL2 36 1 I CTRL3 37 1 I CLKOUT 57 1 O CMOS output clock 11 O Channel A 11-bit ADC output data bits, CMOS levels 11 O Channel B 11-bit ADC output data bits, CMOS levels 1,38,48,58 4 I Output buffer supply 39,49,59,PAD 3 I Output buffer ground When <SERIAL READOUT> = 0, this pin forces logic LOW & is not tri-stated. DA0, DA10 DB0-DB10 DRVDD DRGND NC 32 Refer to Figure 11 Refer to Figure 11 Digital control input pins. Together, they control SNRBoost control & power down modes. Do not connect Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 TYPICAL CHARACTERISTICS All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL 0 Ain = -1 dBFS, SFDR = 83.8 dBc, SNR = 67 dBFS, SINAD = 66.9 dBFS, THD = 83.3 dBc Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 12. FFT for 60 MHz INPUT SIGNAL 0 Ain = -1 dBFS, SFDR = 83.6 dBc, SNR = 66.8 dBFS, SINAD = 66.8 dBFS, THD = 83 dBc Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 13. FFT for 170 MHz INPUT SIGNAL 0 Ain = -1 dBFS, SFDR = 74.2 dBc, SNR = 66.3 dBFS, SINAD = 65.7 dBFS, THD = 73.5 dBc Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 14. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 33 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) FFT for 270 MHZ INPUT SIGNAL 0 Ain = -1 dBFS, SFDR = 71.7 dBc, SNR = 65.7 dBFS, SINAD = 64.8 dBFS, THD = 70.8 dBc Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 15. FFT for 2-TONE INPUT SIGNAL (INTERMODULATION DISTORTION) 0 Ain = -7 dBFS each tone, Fin1 = 185 MHz, Fin2 = 190 MHz, AMD3 = 87.5 dBFS, SFDR = 90 dBFS Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 16. FFT for 2-TONE INPUT SIGNAL (INTERMODULATION DISTORTION) 0 Ain = -35 dBFS each tone, Fin1 = 185 MHz, Fin2 = 190 MHz, IMD3 = 107 dBFS, SFDR = 104 dBFS Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 17. 34 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) FFT with SNRBOOST ENABLED for 5MHz, 10MHZ, and 15 MHz BANDWIDTHS, Fin = 150 MHz, Fcenter = Fs/4 0 Ain = -36 dBFS, SNRBoost Coeff1 = 0x0, SNRBoost Coeff2 = 0x0, SFDR = 51.8 dBc, THD = 51 dBc, SNR over 5 M BW (47.5 M to 52.5 M) = 88.4 dBFS, SNR over 10 M BW (45 M to 55 M) = 84.5 dBFS, SNR over 15 M BW (42.5 M to 57.5 M) = 82.5 dBFS Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 18. FFT with SNRBOOST ENABLED for 20 MHz BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4 0 Ain = -36 dBFS, SNRBoost Coeff1 = 0xF, SNRBoost Coeff2 = 0x1, SFDR = 52 dBc, THD = 52.8 dBc, SNR over 20 M BW (40 M to 60 M) = 80.9 dBFS Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 19. FFT with SNRBOOST ENABLED for 30MHz, BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4 0 Ain = -36 dBFS, SNRBoost Coeff1 = 0xD, SNRBoost Coeff2 = 0x3, SFDR = 52.7 dBc, THD = 53.1 dBc, SNR over 30 M BW (35 M to 65 M) = 78.4 dBFS Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 20. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 35 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) FFT with SNRBOOST ENABLED for 40MHz, BANDWIDTH, Fin = 150 MHz, Fcenter = Fs/4 0 Ain = -36 dBFS, SNRBoost Coeff1 = 0xD, SNRBoost Coeff2 = 0x3, SFDR = 54.4 dBc, THD = 53.8 dBc, SNR over 40 M BW (30 M to 70 M) = 75.8 dBFS Amplitude - dB -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 f - Frequency - MHz 70 80 90 100 Figure 21. SNR with SNRBOOST ENABLE and DISABLED 90 88 SFDR ACROSS INPUT FREQUENCY 90 Ain = -36 dBFS, Fin = 150.2 MHz, SNRBoost Coeff2 = 0x1, Optimized for 20 MHz Bandwidth, SNR over 20 M BW (SNRBoost Disabled) = 73.7 dBFS, SNR over 20 M BW (SNRBoost Enabled) = 80.9 dBFS 86 SNRBoost Enabled 82 SFDR - dBc SNR - dBFS 86 84 82 SNRBoost Disabled 78 74 80 70 78 SNR SNR SNR SNR SNR (37.5 M to 42.5 M) (42.5 M to 47.5 M) (47.5 M to 52.5 M) (52.5 M to 57.5 M) (57.5 M to 62.5 M) 66 0 Figure 22. 36 100 200 300 400 Input Frequency - MHz 500 Figure 23. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) SNR ACROSS INPUT FREQUENCY SFDR ACROSS GAIN 68 92 Gain = 6 dB 88 67 Gain = 4 dB 66 SFDR - dBc SNR - dBFS 84 65 Gain = 5 dB 80 76 64 Gain = 3 dB 72 Gain = 2 dB Gain = 1 dB 63 68 0 100 200 300 400 Input Frequency - MHz 500 0 200 300 400 Input Frequency - MHz 500 Figure 24. Figure 25. SINAD SCROSS GAIN PERFORMANCE ACROSS INPUT AMPLITUDE SINGLE TONE 68 68 100 Gain = 0 dB 67 100 Gain = 0 dB SNR - dBFS 90 67.5 SFDR - dBc 66 65 67 70 66.5 60 64 Gain = 2 dB Gain = 3 dB Gain = 4 dB 63 80 SNR - dBFS SINAD - dBFS Gain = 1 dB 66 SFDR - dBc 50 65.5 Gain = 5 dB Gain = 6 dB 62 0 50 100 150 200 250 300 350 400 450 500 Input Frequency - MHz 40 -40 65 -35 Figure 26. -30 -25 -20 -15 -10 Input Amplitude - dBFs -5 0 Figure 27. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 37 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) INTER-MODULATION with 2-TONE INPUT ACROSS INPUT AMPLITUDE PERFORMANCE ACROSS INPUT COMMON-MODE VOLTAGE 68 86 110 Input Frequency = 60 106 98 94 84 67 83 66.5 SFDR - dBc 82 66 81 65.5 SNR - dBFS SNR - dBFS 102 SFDR - dBc IMD3, SFDR, dBFS 67.5 85 SFDR - dBFS IMD3 - dBFS 90 86 65 80 82 -7 -12 -18 -24 -30 -36 -42 Input Amplitude of each tone - dBFS 1.35 -48 1.4 1.45 1.5 1.55 1.6 1.65 Input Common Mode Voltage - V Figure 28. Figure 29. SFDR ACROSS TEMPERATURE vs AVDD SUPPLY SNR ACROSS TEMPERATURE vs AVDD SUPPLY 1.7 67.5 90 Input Frequency = 60 MHz Input Frequency = 60 MHz 89 87 AVDD = 3.3 V 67 AVDD = 3.6 V AVDD = 3.3 V 86 SNR - dBFS SFDR - dBc 88 AVDD = 3 V 66.5 AVDD = 3.6 V 85 84 66 AVDD = 3 V 83 65.5 82 -40 -25 25 55 TA - Free-Air Temperature - C 85 -40 Figure 30. 38 -25 25 55 TA - Free-Air Temperature - C 85 Figure 31. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 68 87 85 68 Input Frequency = 60 MHz Input Frequency = 60 MHz, AVDD = 3.3 V 67.5 86 SFDR - dBc 84 67.5 84 83 1.6 1.7 1.8 DRVDD - Supply Voltage - V 66.5 82 66 81 1.9 66.5 66 0.11 0.52 0.94 1.36 1.77 0.31 0.73 1.15 1.57 1.97 Input Clock Amplitude, VPP Differential Figure 32. Figure 33. PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE PERFORMANCE ACROSS EXTERNAL REFERENCE MODE 89 68 86 67.5 85 67 SNR - dBFS 83 SNR, dBFS SNR - dBFS SNR, dBFS 67 85 SFDR - dBc SFDR - dBc SFDR - dBc 2.15 68 67 87 SNR - dBFS 67.5 SFDR - dBc 84 67 SNR - dBFS SFDR - dBc SFDR - dBc SFDR - dBc 88 SNR, dBFS Input Frequency = 20 MHz SNR - dBFS 86 85 30 35 40 45 50 55 60 Input Clock Duty Cycle - % 65 70 66.5 83 66 82 66.5 66 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 Voltage Forced on VCM Pin - V Figure 34. 1.7 Figure 35. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 39 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) CMRR vs FREQUENCY POWER DISSIPATION ACROSS SAMPLING FREQUENCY -30 1.3 -35 1.2 1.1 Total Power - W CMRR - dB -40 -45 -50 -55 -60 1 0.9 LVDS 0.8 0.7 0.6 -65 CMOS (No load Capacitance) 0.5 -70 20 40 60 80 100 130 170 230 0.4 270 Common-Mode Frequency - MHz 50 75 100 125 150 Sampling frequency - MSPS Figure 36. Figure 37. 0 25 175 200 DRVDD CURRENT ACROSS SAMPLING FREQUENCY 140.4 Fin = 2.5 MHz DRVDD Current - mA 120.4 100.4 LVDS 80.4 60.4 40.4 CMOS No load Capacitance 20.4 CMOS 15 pF Load Capacitance 0.4 0 25 50 75 100 125 150 Sampling Frequency - MSPS 175 200 Figure 38. 40 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) SFDR CONTOUR 0 dB GAIN up to 500 MHz 200 Sampling Frequency - MSPS 180 160 140 120 100 80 20 50 100 70 150 75 200 80 250 300 350 85 Figure 39. 400 90 450 500 95 SFDR CONTOUR 6 dB GAIN up to 800 MHz 200 Sampling Frequency - MSPS 180 160 140 120 100 80 20 100 60 200 65 300 70 400 75 Figure 40. 500 700 600 80 85 800 90 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 41 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at 25 C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, SNRBoost disabled, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) SNR CONTOUR 0 dB GAIN up to 500 MHz 200 Sampling Frequency - MSPS 180 160 140 120 100 80 20 63 50 100 63.5 150 64 200 64.5 250 300 350 65.5 65 Figure 41. 400 66 450 66.5 500 67 SNR CONTOUR 6 dB GAIN up to 800 MHz 200 Sampling Frequency - MSPS 180 160 140 120 100 80 42 20 100 60 60.5 300 200 61 61.5 62 400 62.5 63 Figure 42. 500 63.5 Submit Documentation Feedback 700 600 64 64.5 800 65 65.5 Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 APPLICATION INFORMATION THEORY OF OPERATION ADS62C17 is a low power 11-bit pipeline A/D converters with maximum sampling rate up to 200 MSPS. At every falling edge of the input clock, the analog input signal of each channel is sampled simultaneously. The sampled signal in each channel is converted by a pipeline of low resolution stages. In each stage, the sampled and held signal is converted by a high speed, low resolution flash sub-ADC. The difference (residue) between the stage input and its quantized equivalent is gained and propagates to the next stage. At every clock, each succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are combined in a digital correction logic block and processed digitally to create the final 11 bit code, after a data latency of 22 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or binary 2s complement format. The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with 2V pp amplitude) and about 800MHz (with 1V pp amplitude). ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology results in very good AC performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available on VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5V and VCM - 0.5V, resulting in a 2Vpp differential input swing. Sampling switch Lpkg~ 2 nH INP Cbond ~1 pF 10 W R 200 W 100 W Ron C2 15 W 0.5 pF Ron 10 W C1 0.25 pF 10 W 100 W Ron 15 W INM Cbond ~1 pF R 200 W Csamp 2 pF 3 pF 3 pF Lpkg~ 2 nH Sampling capacitor RCR Filter C2 0.5 pF Csamp 2 pF Sampling capacitor Sampling switch Figure 43. Analog Input Circuit Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A 5 to 15 resistor in series with each input pin is recommended to damp out ringing caused by package parasitic. SFDR performance can be limited due to several reasons - the effect of sampling glitches (described below), non-linearity of the sampling circuit & non-linearity of the quantizer that follows the sampling circuit. Depending on the input frequency, sample rate & input amplitude, one of these plays a dominant part in limiting performance. At very high input frequencies (> about 300 MHz), SFDR is determined largely by the device's sampling circuit non-linearity. At low input amplitudes, the quantizer non-linearity usually limits performance. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 43 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Glitches are caused by the opening & closing of the sampling switches. The driving circuit should present a low source impedance to absorb these glitches. Otherwise, this could limit performance, mainly at low input frequencies (up to about 200 MHz). It is also necessary to present low impedance (< 50 ) for the common mode switching currents. This can be achieved by using two resistors from each input terminated to the common mode voltage (VCM). The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the sampling glitches inside the device itself. The cut-off frequency of the R-C filter involves a trade-off. A lower cut-off frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a higher cut-off frequency (smaller C), bandwidth support is maximized. But now, the sampling glitches need to be supplied by the external drive circuit. This has limitations due to the presence of the package bond-wire inductance. In ADS62C17, the R-C component values have been optimized while supporting high input bandwidth (up to 700 MHz). However, in applications with input frequencies up to 200-300MHz, the filtering of the glitches can be improved further using an external R-C-R filter (as shown in Figure 46 and Figure 47). In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure 44 and Figure 45 show the impedance (Zin = Rin || Cin) looking into the ADC input pins. 100 Resistance - kW 10 1 0.10 0.01 0 100 200 300 400 500 600 f - Frequency - MHz 700 800 900 1000 Figure 44. ADC Analog Input Resistance (Rin) Across Frequency 44 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 4.5 4 Capacitance - pF 3.5 3 2.5 2 1.5 1 0 100 200 300 400 500 600 700 800 900 1000 f - Frequency - MHz Figure 45. ADC Analog Input Capacitance (Cin) Across Frequency Driving Circuit Two example driving circuit configurations are shown in Figure 46 and Figure 47 - one optimized for low bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. In Figure 46, an external R-C-R filter using 22pF has been used. Together with the series inductor (39nH), this combination forms a filter and absorbs the sampling glitches. Due to the large capacitor (22pF) in the R-C-R and the 15 resistors in series with each input pin, the drive circuit has low bandwidth and supports low input frequencies (<100MHz). To support high input frequencies (up to about 300MHz, see Figure 47), the capacitance used in the R-C-R is reduced to 3.3pF and the series inductors are shorted out. Together with the lower series resistors (5), this drive circuit provides high bandwidth and supports high input frequencies. Transformers such as ADT1-1WT or ETC1-1-13 can be used up to 300MHz. Without the external R-C-R filter, the drive circuit has very high bandwidth & can support very high input frequencies (> 300MHz). For example, a transmission line transformer such as ADTL2-18 can be used (Figure 48). Note that both the drive circuits have been terminated by 50 ohms near the ADC side. The termination is accomplished by a 25 ohms resistor from each input to the 1.5V common-mode (VCM) from the device. This allows the analog inputs to be biased around the required common-mode voltage. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 45 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com 39 nH 0.1 mF 15 W 0.1 mF INP 50 W 0.1uF 50 W 25 W 22 pF 25 W 50 W 50 W 1:1 INM 1:1 15 W 0.1 mF 39 nH VCM Figure 46. Drive Circuit With Low Bandwidth (for low input frequencies) The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional termination resistor pair may be required between the two transformers as shown in the figures. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side have to be chosen to get an effective 50 (in the case of 50 source impedance). 0.1 mF 5W 0.1 mF INP 0.1 mF 50 W 25 W 3.3 pF 25 W 50 W INM 1:1 1:1 5W 0.1 mF VCM Figure 47. Drive Circuit With High Bandwidth (for high input frequencies) 0.1F INP 0.1F 25 25 T1 T2 INM 0.1F VCM Figure 48. Drive circuit with very high bandwidth (> 300 MHz) 46 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 All these examples show 1:1 transformers being used with a 50 ohms source. As explained in the "Drive Circuit Requirements", this helps to present a low source impedance to absorb the sampling glitches. With a 1:4 transformer, the source impedance will be 200 ohms. The higher impedance can lead to degradation in performance, compared to the case with 1:1 transformers. For applications where only a band of frequencies are used, the drive circuit can be tuned to present a low impedance for the sampling glitches. Figure 49 shows an example with 1:4 transformer, tuned for a band around 150MHz. 5 INP 25 100 0.1F Differential input signal 72 nH 15 pF 100 25 INM 5 1:4 VCM Figure 49. Drive circuit with 1:4 transformer Input common-mode To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1F low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 3.6 A / MSPS (about 720 A at 200 MSPS). REFERENCE ADS62C17 has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the converter can be controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the serial interface register bit <REF>. INTREF + _ VCM INTERNAL REFERENCE EXTREF _ + REFM REFP Figure 50. Reference Section Internal reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5V nominal) is output on VCM pin, which can be used to externally bias the analog input pins Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 47 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com External reference When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by the following: Full-scale differential input pp = (Voltage forced on VCM) x 1.33 In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally. SNR ENHANCEMENT USING SNRBOOST SNRBoost technology makes it possible to overcome SNR limitations due to quantization noise. With SNRBoost, enhanced SNR can be obtained for any bandwidth (less than Nyquist or Fs/2, see Table 1). The SNR improvement is achieved without affecting the default harmonic performance. SNRBoost is disabled after reset; it can be enabled using register bit <SNRBoost Enable> or using the control pins CTRL1, 2, 3. (While using the register bits to control SNRBoost, keep CTRL1, CTRL2, CTRL3 low. To use the CTRL pins as SNRBoost control, reset the <SNRBoost Enable> register bits). When it is enabled, the noise floor in the spectrum acquires a typical bath-tub shape as shown in Figure 51. The bath-tub is centered around a specific frequency (called center frequency). The center frequency is located mid-way between two corner frequencies, which are specified by the SNRBoost coefficients (Register bits <SNRBoost Coeff1> and SNRBoost Coeff2>). Table 9 shows the relation between each coefficient and its corner frequency. By choosing appropriate coefficients, the bath-tub can be positioned over the frequency range 0 to Fs/2 (Table 10 shows some examples). By positioning the bath-tub within the desired signal band, SNR improvement can be achieved (see Table 1). Note that as the bandwidth is increased, the amount of SNR improvement reduces. 0 Fs = 200MSPS Fin =150 MHz SNRBoost Coeff1 = 0x0F, SNRBoost Coeff2 = 0x01, Amplitude - dB -20 -40 Center Frequency = FS x 0.25 -60 -80 -100 -120 -140 0 0.05 0.10 0.15 0.20 0.25 0.30 f - Frequency - MHz 0.35 0.40 0.45 0.50 Figure 51. Specturm with SNRBoost Enabled Table 9. Setting the Corner Frequency 48 SNRBoost Coefficient Value Normalized Corner Frequency (f/fs) SNRBoost Coefficient value Normalized Corner Frequency (f/fs) 7 6 0.080 F 0.270 0.115 E 0.290 5 0.143 D 0.311 4 0.167 C 0.333 3 0.189 B 0.357 2 0.210 A 0.385 1 0.230 9 0.420 0 0.250 8 0.500 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 Table 10. Positioning the Corner Frequency SNRBoost Coefficient1, <SNRBoost Coeff1> Normalized Corner Frequency1 (f/fs) SNRBoost Coefficient1, <SNRBoost Coeff2> Center Frequency 0 0.250 0 Fs x 0.25 F 0.270 1 Fs x 0.25 6 0.115 2 Fs x 0.165 D 0.311 B Fs x 0.335 9 0.420 7 Fs x 0.25 Serial register write to enable SNRBoost Register address = 0x59 SDATA A7 A6 A1 Register data = 0x01 A0 D7 D6 D1 D0 10 clock cycles after the 16th SCLK falling edge, the device starts giving out valid SNRBoost data SCLK SEN clock cycle 1 clock cycle 9 clock cycle 10 CLKM CLKP N Analog Input Signal Output Data N+1 N-1 N-26 N-25 Valid SNRBoost data starts Figure 52. SNRBoost Active Delay SNRBoost does not introduce any group delay in the input signal path. The ADC latency increases by four clock cycle (to 26 clock cycles). When it is enabled using the serial interface, the mode becomes fully active 10 input clock cycles after the 16th SCLK falling edge. When it is disabled, normal data (without SNRBoost) resumes after 6 clock cycle. CLOCK INPUT ADS62C17 clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-k resistors as shown in Figure 53. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources (Figure 54 and Figure 55). Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 49 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Clock buffer Lpkg ~2 nH 20 W CLKP Cbond ~1 pF Ceq Ceq 5 kW R ~100 W VCM 2 pF 5 kW Lpkg ~ 2 nH 20 W CLKM Cbond ~1 pF R ~100 W Ceq~ 1 to 3 pF, equivalent input capacitance of clock buffer Figure 53. Internal Clock Buffer For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. 0.1 mF CLKP Differential sine-wave or PECL or LVDS clock input CLKM 0.1 mF Figure 54. Differential Clock Driving Circuit Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM tied to 1.5V common-mode voltage. As shown in Figure 55, CLKM can be tied to VCM pin. 50 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 0.1 mF CMOS clock input CLKP VCM CLKM 0.1 mF Figure 55. Single-Ended Clock Driving Circuit GAIN PROGRAMMABILITY ADS62C17 includes gain settings that can be used to get improved SFDR performance (compared to 0dB gain). The gain is programmable from 0dB to 6dB (in 0.5 dB steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 11. The SFDR improvement is achieved at the expense of SNR; for each 1dB gain step, the SNR degrades about 1dB. The SNR degradation is less at high input frequencies. As a result, the gain is very useful at high input frequencies as the SFDR improvement is significant with marginal degradation in SNR. So, the gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB. Table 11. Full-Scale Range Across Gains Gain, dB Full-Scale, Vpp 0 2V 1 1.78 2 1.59 3 1.42 4 1.26 5 1.12 6 1.00 OFFSET CORRECTION ADS62C17 has an internal offset correction algorithm that estimates and corrects dc offset up to +/-10mV. The correction can be enabled using the serial register bit <OFFSET CORRECTION ENABLE>. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using register bits <OFFSET CORR TIME CONSTANT> as described in Table 12. After the offset is estimated, the correction can be frozen by setting <OFFSET CORRECTION ENABLE> = 0. Once frozen, the last estimated value is used for offset correction every clock cycle. The correction does not affect the phase of the signal. Note that offset correction is disabled by default after reset. Figure 56 shows the time response of the offset correction algorithm, after it is enabled. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 51 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Table 12. Time Constant of Offset Correction Algorithm (1) <OFFSET CORR TIME CONSTANT> D3-D0 Time Constant (TCCLK), Number of Clock Cycles Time Constant, sec (=TCCLK x 1/Fs) (1) 0000 256 k 1.2 ms 0001 512 k 2.5 ms 0010 1M 5 ms 0011 2M 10 ms 0100 4M 20 ms 0101 8M 40 ms 0110 16 M 80 ms 0111 32 M 0.16 s 1000 64 M 0.32 s 1001 128 M 0.64 s 1010 256 M 1.28 s 1011 512 M 2.5 s 1100 RESERVED 1101 RESERVED 1110 RESERVED 1111 RESERVED Sampling frequency, Fs = 200 MSPS 1026 Offset correction enabled 1025 Output Codesm - LSB 1024 Output data with offset corrected Offset correction disabled 1023 1022 1021 1020 1019 1018 -2 Output data with 4 LSB offset 0 2 4 6 8 10 12 14 16 18 20 Time - ms Figure 56. Time Response of Offset Correction POWER DOWN ADS62C17 has three power down modes - power down global, individual channel standby and individual channel output buffer disable. These can be set using either the serial register bits or using the control pins CTRL1 to CTRL3. 52 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 Table 13. Power Down Controls POWER DOWN MODES CONFIGURE USING SERIAL INTERFACE PARALLEL CONTROL PINS low WAKE-UP TIME Normal operation <POWER DOWN MODES>=0000 low low - Output buffer disabled for channel B <POWER DOWN MODES>=1001 - Output buffer disabled for channel A <POWER DOWN MODES>=1010 The pins do not support output buffer disable Output buffer disabled for channel A and B <POWER DOWN MODES>=1011 Global power down <POWER DOWN MODES>=1100 high Channel B standby <POWER DOWN MODES>=1101 Channel A standby <POWER DOWN MODES>=1110 Multiplexed (MUX) mode - Output data of channel A and B is multiplexed & available on DA10 to DA0 pins. <POWER DOWN MODES>=1111 - Fast (100 ns) low low Slow (20 s) high low high Fast (1 s) high high low Fast (1 s) high high high - Power Down Global In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are powered down resulting in reduced total power dissipation of about 45mW. The output buffers are in high impedance state. The wake-up time from the global power down to data becoming valid in normal mode is typically 20 s. Channel Power Down (individual or both channels) Here, each channel's A/D converter can be powered down. The internal references are active, resulting in quick wake-up time of 1 s. The total power dissipation in standby is about 450 mW. Output Buffer Disable (individual or both channels) Each channel's output buffer can be disabled and put in high impedance state - wakeup time from this mode is fast, about 100 ns. Input Clock Stop In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The power dissipation is about 275 mW. POWER SUPPLY SEQUENCE During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. DIGITAL OUTPUT INTERFACE ADS62C17 provides 11-bit data and an output clock synchronized with the data. Two output interface options are available - Double Data Rate (DDR) LVDS and parallel CMOS. They can be selected using the serial interface register bit <LVDS_CMOS> or using DFS pin in parallel configuration mode. DDR LVDS Interface In this mode, the data bits and clock are output using LVDS (Low Voltage Differential Signal) levels. Two data bits are multiplexed and output on each LVDS differential pair. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 53 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com CLKOUTP Output Clock CLKOUTM DB0_P DB0_M Data bit D0 DB2_P DB2_M Data bits D1, D2 DB4_P DB4_M 11 bit ADC data Channel B DB6_P DB6_M Data bits D3, D4 Data bits D5, D6 DB8_P DB8_M Data bits D7, D8 DB10_P DB10_M ADS62C17 Data bits D9, D10 LVDS Buffers Figure 57. DDR LVDS Outputs Even data bits D0, D2, D4... are output at the falling edge of CLKOUTP and the odd data bits D1, D3, D5... are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to capture all the data bits (Figure 58). 54 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 CLKOUTM CLKOUTP DA0, DB0 DA2, DB2 DA4,DB4 0 D0 0 D0 D1 D2 D1 D2 D3 D4 D3 D4 D5 D6 D5 D6 D7 D8 D7 D8 D9 D10 D9 D10 DA6,DB6 DA8,DB8 DA10,DB10 SAMPLE N SAMPLE N+1 Figure 58. DDR LVDS Interface LVDS Buffer The equivalent circuit of each LVDS output buffer is shown in Figure 59. The buffer is designed to present an output impedance of 100 (Rout). The differential outputs can be terminated at the receive end by a 100 termination. The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its value cannot be changed. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 55 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Low - 0.35 V High 1.2 V High + 0.35 V Low ADS62C18 OUTP Rout OUTM Switch impedance is nominally 50 W (+/- 10%) When the "High" switches are closed , OUTP = 1.375 V, OUTM = 1.025 V When the "Low" switches are closed , OUTP = 1.025 V, OUTM = 1.375 V When the "High" (or "Low") switches are closed, Rout = 100 W Figure 59. LVDS Buffer Equivalent Circuit Parallel CMOS Interface In the CMOS mode, each data bit is output on separate pin as CMOS voltage level, every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver (for sampling frequencies up to 150 MSPS). Up to 150MSPS, the setup and hold timings of the output data with respect to CLKOUT are specified. It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them. For sampling frequencies above 150 MSPS, it is recommended to use an external clock to capture data. The delay from input clock to output data and the data valid times are specified for the higher sampling frequencies. These timings can be used to delay the input clock appropriately and use it to capture the data. 56 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 Pins DB0 DB1 DB2 DB8 11 bit ADC data Channel B DB9 DB10 SDOUT CLKOUT DA0 DA1 DA2 DA8 11 bit ADC data Channel A DA9 DA10 Figure 60. Parallel CMOS Outputs CMOS Interface Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching = CL x DRVDD x (N x FAVG), where CL = load capacitance, N x FAVG = average number of output bits switching. Figure 38 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input frequency. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 57 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Output Data Format Two output data formats are supported - 2s complement and offset binary. They can be selected using the serial interface register bit <DATA FORMAT> or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0x7FF in offset binary output format, and 0x3FF in 2s complement output format. For a negative input overdrive, the output code is 0x000 in offset binary output format and 0x400 in 2s complement output format. BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide (SLAU237A) for details on layout and grounding. Supply Decoupling As ADS62C17 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors would depend on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. Exposed Pad In addition to providing a path for heat dissipation, the pad is also electrically connected to digital ground internally. So, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON. PCB Attachment (SLUA271). MIGRATION FROM ADS62C15 TO ADS62C17 While migrating from the C15 to C17, note the following differences between the two devices. ADS62C15 ADS62C17 Pinout Pin 22 is AGND Pin 22 is NC Pin 64 is DRGND Pin 64 is SDOUT (Serial readout pin) Supply AVDD is 3.3V No change DRVDD is 1.8V to 3.3V (for CMOS interface) and is 3.3V (for LVDS interface) DRVDD is 1.8V (for both CMOS and LVDS interfaces) Serial Interface Protocol: 8 bit register address & 8 bit register data No change in protocol Serial register map is completely different 58 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 ADS62C17 www.ti.com ..................................................................................................................................................................................................... SLAS631 - APRIL 2009 DEFINITION OF SPECIFICATIONS Analog Bandwidth - The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay - The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels. The maximum variation is specified as aperture delay variation (channel-channel). Aperture Uncertainty (Jitter) - The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle - The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate - The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate - The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) - An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) - The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error - Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to reference inaccuracy and error due to the channel. Both these errors are specified independently as EGREF and EGCHAN. To a first order approximation, the total gain error will be ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = 0.5%, the full-scale input varies from (1-0.5/100) x FSideal to (1 + 0.5/100) x FSideal. Offset Error - The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift - The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX-TMIN. Signal-to-Noise Ratio - SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics. P SNR = 10Log10 S PN (3) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Signal-to-Noise and Distortion (SINAD) - SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD = 10Log10 PN + PD (4) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Effective Number of Bits (ENOB) - The ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 59 ADS62C17 SLAS631 - APRIL 2009 ..................................................................................................................................................................................................... www.ti.com ENOB = SINAD - 1.76 6.02 (5) Total Harmonic Distortion (THD) - THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD = 10Log10 S PN (6) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) - The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion - IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1-f2 or 2f2-f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. DC Power Supply Rejection Ratio (DC PSRR) - The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. AC Power Supply Rejection Ratio (AC PSRR) - AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If VSUP is the change in supply voltage and Vout is the resultant change of the ADC output code (referred to the input), then DVOUT (Expressed in dBc) PSRR = 20Log 10 DVSUP (7) Voltage Overload Recovery - The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from their expected values) is noted. Common Mode Rejection Ratio (CMRR) - CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If Vcm_in is the change in the common-mode voltage of the input pins and VOUT is the resultant change of the ADC output code (referred to the input), then DVOUT (Expressed in dBc) CMRR = 20Log10 DVCM (8) Cross-Talk (only for multi-channel ADC)- This is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. 60 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): ADS62C17 PACKAGE OPTION ADDENDUM www.ti.com 10-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS62C17IRGC25 PREVIEW VQFN RGC 64 ADS62C17IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS62C17IRGCT ACTIVE VQFN RGC 64 250 CU NIPDAU Level-3-260C-168 HR 25 TBD Green (RoHS & no Sb/Br) Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS62C17IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS62C17IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS62C17IRGCR VQFN RGC 64 2000 333.2 345.9 28.6 ADS62C17IRGCT VQFN RGC 64 250 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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