TIMING CHARACTERISTICS — LVDS AND CMOS MODES
(1)
ADS62C17
www.ti.com
..................................................................................................................................................................................................... SLAS631 – APRIL 2009
Typical values are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, sine wave input clock, C
LOAD
=5pF
(2)
, R
LOAD
= 100 Ω
(3)
, no internal termination, LOW SPEED mode disabled, unless otherwise noted.Min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = 3.3V, DRVDD = 1.7V to1.9V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
a
Aperture delay 0.7 1.2 1.7 ns
Aperture delay matching between two channels of the same device ± 50 ps
t
j
Aperture jitter 145 fs rms
Time to valid data after coming out of STANDBY mode 1 3
µsWake-up time Time to valid data after coming out of global powerdown 20 50
Time to valid data after stopping and restarting the input clock 10
Clock
cyclesADC Latency
(4)
Default, after reset 22
DDR LVDS MODE
(5)
t
su
Data setup time
(6)
Data valid
(7)
to zero-crossing of CLKOUTP 0.8 1.15 ns
t
h
Data hold time
(7)
Zero-crossing of CLKOUTP to data becoming invalid
(7)
0.8 1.15 ns
t
PDI
Clock propagation delay Input clock falling edge cross-over to output clock rising edge t
PDI
= 0.69 × Ts + t
delaycross-over
100 MSPS ≤Sampling frequency ≤200 MSPSt
delay
4.2 5.7 7.2 nsTs = 1/Sampling frequency
Difference in t
delay
between two devices operating at samet
delay
skew ± 500 pstemperature & SVDD supply voltage.
Duty cycle of differential clock, (CLKOUTP-CLKOUTM)LVDS bit clock duty cycle 52%100 MSPS ≤Sampling frequency ≤200 MSPS
Rise time measured from – 100 mV to +100 mVt
RISE
, t
FALL
Data rise time, Data fall time Fall time measured from +100 mV to – 100 mV 0.14 ns1MSPS ≤Sampling frequency ≤200 MSPS
Rise time measured from – 100 mV to +100 mVOutput clock rise time,t
CLKRISE
,
Fall time measured from +100 mV to – 100 mV 0.14 nst
CLKFALL
Output clock fall time
1 MSPS ≤Sampling frequency ≤200 MSPS
t
OE
Output buffer enable to data delay Time to valid data after output buffer becomes active 100 ns
PARALLEL CMOS MODE at Fs=200 MSPS
(8)
t
START
Input clock to data delay Input clock falling edge cross-over to start of data valid
(7)
2.5 ns
t
DV
Data valid time Time interval of valid data
(7)
1.7 2.7 ns
t
PDI
Clock propagation delay Input clock falling edge cross-over to output clock rising edge t
PDI
= 0.28 × Ts + t
delaycross-over
100 MSPS ≤Sampling frequency ≤150 MSPSt
delay
5.5 7.5 8.5 nsTs = 1/Sampling frequency
Duty cycle of output clock, CLKOUTOutput clock duty cycle 43100 MSPS ≤Sampling frequency ≤150 MSPS
Rise time measured from 20% to 80% of DRVDDt
RISE
, t
FALL
Data rise time, Data fall time Fall time measured from 80% to 20% of DRVDD 1.2 ns1≤Sampling frequency ≤200 MSPS
Rise time measured from 20% to 80% of DRVDDOutput clock rise time,t
CLKRISE
,
Fall time measured from 80% to 20% of DRVDD 0.8 nst
CLKFALL
Output clock fall time
1≤Sampling frequency ≤150 MSPS
Output buffer enable (OE) to datat
OE
Time to valid data after output buffer becomes active nsdelay
(1) Timing parameters are ensured by design and characterization and not tested in production.(2) C
LOAD
is the effective external single-ended load capacitance between each output pin and ground(3) R
LOAD
is the differential load resistance between the LVDS output pair.(4) At higher frequencies, t
PDI
is greater than one clock period and overall latency = ADC latency + 1.(5) Measurements are done with a transmission line of 100 Ωcharacteristic impedance between the device and the load.Setup and hold time specifications take into account the effect of jitter on the output data and clock.(6) Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of -100.0mV.(7) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V.(8) For Fs > 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT).
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