LTC3411AEDD#PBF - ANALOG DEVICES

LTC3411A

Rev. E

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TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

1.25A, 4MHz, Synchronous

Step-Down DC/DC Converter

The LT C

3411A is a constant frequency, synchronous

step-down DC/DC converter. Intended for medium power

applications, it operates from a 2.5V to 5.5V input voltage

range and has a user configurable operating frequency up

to 4MHz, allowing the use of tiny, low cost capacitors and

inductors 1mm or less in height. The output voltage is

adjustable from 0.8V to 5.5V. Internal synchronous power

switches provide high efficiency. The LTC3411A’s current

mode architecture and external compensation allow the

transient response to be optimized over a wide range of

loads and output capacitors.

The LTC3411A can be configured for automatic power

saving Burst Mode operation (IQ = 40µA) to reduce gate

charge losses when the load current drops below the level

required for continuous operation. For reduced noise and

RF interference, the SYNC/MODE pin can be configured

to skip pulses or provide forced continuous operation.

To further maximize battery life, the P-channel MOSFET

is turned on continuously in dropout (100% duty cycle).

In shutdown, the device draws <1µA.

Step-Down 2.5V/1.25A Regulator

n Uses Tiny Capacitors and Inductor

n High Frequency Operation: Up to 4MHz

n Low RDS(ON) Internal Switches: 0.15Ω

n High Efficiency: Up to 96%

n Selectable Low Ripple (25mVP-P) Burst Mode

Operation: IQ = 40µA

n Stable with Ceramic Capacitors

n Current Mode Operation for Excellent Line and Load

Transient Response

n Short-Circuit Protected

n Low Dropout Operation: 100% Duty Cycle

n Low Shutdown Current: IQ ≤ 1µA

n Output Voltages from 0.8V to 5V

n Synchronizable to External Clock

n Supports Prebiased Outputs

n Small 10-Lead 3mm × 3mm DFN or MSOP Package

n Notebook Computers

n Digital Cameras

n Cellular Phones

n Handheld Instruments

n Board Mounted Power Supplies

SYNC/MODESYNC

LTC3411A

PVIN

SVIN

PGOOD

ITH

SHDN/RT

PGNDSGND

VFB

2.2µH VOUT

2.5V

1.25A

VIN

2.5V TO 5.5V

887k

22pF

412k

680pF

3411a TA01a

22µF

12.1k

10µF

549k

Efficiency and Power Loss vs Output Current

OUTPUT CURRENT (mA)

0.1 1 10

EFFICIENCY (%)

POWER LOSS (W)

100 1

0.1

0.01

0.001

0.0001

1000100 10000

3411A TA01b

VIN = 2.7V

VIN = 3.6V

VIN = 4.2V

fO = 1MHz

Burst Mode OPERATION

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 5481178, 6580258, 6498466, 6611131..

LTC3411A

Rev. E

For more information www.analog.com

PIN CONFIGURATION

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

PVIN, SVIN Voltages .................................... –0.3V to 6V

VFB, ITH, SHDN/RT Voltages ......... –0.3V to (VIN + 0.3V)

SYNC/MODE Voltage ................... –0.3V to (VIN + 0.3V)

SW Voltage ................................. –0.3V to (VIN + 0.3V)

PGOOD Voltage ............................ –0.3V to (VIN + 0.3V)

(Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Operating Voltage Range l2.5 5.5 V

IFB Feedback Pin Input Current (Note 3) ±0.1 µA

VFB Feedback Voltage (Note 3) l0.784 0.8 0.816 V

ΔVLINEREG Reference Voltage Line Regulation VIN = 2.5V to 5.5V 0.04 0.2 %/V

ΔVLOADREG Output Voltage Load Regulation ITH = 0.55V to 0.9V l 0.02 0.2 %

gm(EA) Error Amplifier Transconductance ITH Pin Load = ±5µA (Note 3) 300 µS

TOP VIEW

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 11) IS PGND, MUST BE SOLDERED TO PCB

1ITH

VFB

PGOOD

SVIN

PVIN

SHDN/RT

SYNC/MODE

SGND

PGND

SHDN/RT

SYNC/MODE

SGND

PGND

ITH

VFB

PGOOD

SVIN

PVIN

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

JMAX

= 125°C, θ

= 120°C/W

The l denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at TA = 25°C, VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)

Operating Junction Temperature Range

(Notes 2, 5, 8) ........................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

Lead Temperature

(MS Package Soldering, 10 sec) ...........................300°C

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3411AEDD#PBF LTC3411AEDD#TRPBF LAJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LTC3411AIDD#PBF LTC3411AIDD#TRPBF LAJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LTC3411AEMS#PBF LTC3411AEMS#TRPBF LTAJK 10-Lead Plastic MSOP –40°C to 125°C

LTC3411AIMS#PBF LTC3411AIMS#TRPBF LTAJK 10-Lead Plastic MSOP –40°C to 125°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

LTC3411A

Rev. E

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at TA = 25°C, VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ISInput DC Supply Current (Note 4)

Active Mode

Sleep Mode

Shutdown

VSYNC/MODE = 3.6V, VFB = 0.75V

VSYNC/MODE = 3.6V, VFB = 0.84V

VSHDN/RT = 3.6V

330

0.1

450

µA

VSHDN/RT Shutdown Threshold High Active

Oscillator Resistor

VIN – 0.6

125k

VIN – 0.4

fOSC Oscillator Frequency RT = 125k

(Note 7)

2.25 2.5 2.8

MHz

fSYNC Synchronization Frequency (Note 7) 0.4 4 MHz

ILIM Peak Switch Current Limit VFB = 0.5V 1.6 2.1 2.6 A

RDS(ON) Top Switch On-Resistance MS Package

DD Package (Note 6)

0.15

0.21 Ω

Bottom Switch On-Resistance MS Package

DD Package (Note 6)

0.13

0.16 Ω

ISW(LKG) Switch Leakage Current VIN = 5.5V, VSHDN/RT = 5.5V, VSW = 0V

or 5.5V

0.01 1 µA

VUVLO Undervoltage Lockout Threshold VIN Ramping Down 1.8 2.1 2.4 V

PGOOD Power Good Threshold VFB Ramping Up from 0.68V to 0.8V

VFB Ramping Down from 0.92V to 0.8V

–5

–7

Power Bad Threshold VFB Ramping Down from 0.8V to 0.68V

VFB Ramping Up from 0.8V to 0.9V

–10

–12

RPGOOD Power Good Pull-Down On-Resistance 15 30 Ω

PGOOD Blanking VFB Step from 0V to 0.8V

VFB Step from 0.8V to 0V

105

µs

VSYNC-MODE Pulse Skip

Force Continuous

Burst

VIN = 2.5V to 5.5V

1.2

VIN – 0.6

0.6

VIN – 1.1

tSOFT-START 10% to 90% of Regulation 0.5 0.8 1.0 ms

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3411A is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3411AE is guaranteed to meet performance specifications

from 0°C to 85°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3411AI is guaranteed over the full –40°C to 125°C operating junction

temperature range. The maximum ambient temperature consistent with

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Note 3: The LTC3411A is tested in a feedback loop which servos VFB to

the midpoint for the error amplifier (VITH = 0.7V).

Note 4: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 5: TJ is calculated from the ambient TA and power dissipation PD

according to the following formulas:

LTC3411AEDD: TJ = T A + (PD • 43°C/W)

LTC3411AEMS: TJ = T A + (PD • 120°C/W)

Note 6: For the DD package, switch on-resistance is sampled at wafer level

measurements and assured by design, characterization and correlation

with statistical process controls.

Note 7: 4MHz operation is guaranteed by design but not production tested

and is subject to duty cycle limitations (see Applications Information).

Note 8: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

LTC3411A

Rev. E

For more information www.analog.com

Efficiency vs Output Current Efficiency vs Frequency Load Regulation

Line Regulation

Reference Voltage vs

Temperature

Frequency Variation vs

Temperature

OUTPUT CURRENT (mA)

0.1 1 10

EFFICIENCY (%)

100

1000100 10000

3411A G04

VOUT = 1.8V

Burst Mode

OPERATION

FORCED CONTINUOUS

PULSE

SKIP

FREQUENCY (MHz)

3411A G05

0 3 5

1 2 4

EFFICIENCY (%)

VOUT = 1.8V

ILOAD = 400mA

4.7µH

1µH

2.2µH

INPUT VOLTAGE(V)

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

3411A G07

2.5 4.0 5.0 5.5

3.0 3.5 4.5

VOUT ERROR (%)

VOUT = 1.8V

ILOAD = 400mA

TEMPERATURE(°C)

–2

–4

–6

3411A G09

–50 25 75 100 125

–25 0 50

FREQUENCY VARIATION (%)

OUTPUT CURRENT(mA)

1.00

0.75

0.50

0.25

0.00

–0.25

–0.50

3411A G06

0 600 1000 1200 1400

200 400 800

VOUT ERROR (%)

VOUT = 1.8V

FORCED CONTINUOUS

Burst Mode OPERATION

PULSE SKIP

TEMPERATURE(°C)

815

810

805

800

795

790

785

3411A G08

–50 25 75 100 125

–25 0 50

REFERENCE VOLTAGE (mV)

VIN = 3.6V

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Input Voltage Efficiency vs Output Current Efficiency vs Output Current

TA = 25°C, VIN = 3.6V, fO = 1MHz, unless

otherwise noted.

INPUT VOLTAGE(V)

2.5

100

30 4.0 5.0

3411A G01

3.0 3.5 4.5 5.5

EFFICIENCY (%)

IOUT = 100mA

IOUT = 1.25A

VOUT = 1.8V

IOUT = 1mA

IOUT = 0.1mA

IOUT = 10mA

OUTPUT CURRENT (mA)

0.1 1 10

EFFICIENCY (%)

100

1000100 10000

3411A G02

VIN = 2.7V

VIN = 3.6V

VIN = 4.2V

VOUT = 1.8V

OUTPUT CURRENT (mA)

0.1 1 10

EFFICIENCY (%)

100

1000100 10000

3411A G03

VIN = 2.7V

VIN = 3.6V

VIN = 4.2V

VOUT = 1.5V

LTC3411A

Rev. E

For more information www.analog.com

Frequency Variation vs VIN RDS(ON) vs Input Voltage RDS(ON) vs Temperature

VIN (V)

–2

–4

–6

–8

3411A G10

2.5 4.0 5.0

5.5

3.0 3.5 4.5

FREQUENCY VARIATION (%)

INPUT VOLTAGE (V)

0.25

0.20

0.15

0.10

0.05

0.0

3411A G11

2.5 4.0 5.0 5.5

3.0 3.5 4.5

DS(ON)

(Ω)

MAIN SWITCH

SYNCHRONOUS SWITCH

TEMPERATURE (°C)

0.30

0.25

0.20

0.15

0.10

0.05

0.0

3411A G12

–50 25 75 100 125

–25 0 50

DS(ON)

(Ω)

MAIN SWITCH

SYNCHRONOUS SWITCH

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VIN = 3.6V, fO = 1MHz, unless

otherwise noted.

Dynamic Supply Current vs Input

Voltage

Dynamic Supply Current vs

Temperature

VIN (V)

0.001

3.0 3.5 4.0 4.5 5.0 5.52.5

DYNAMIC SUPPLY CURRENT (mA)

0.1

100

3411A G13

0.01

10 FORCED CONTINUOUS

PULSE SKIP

Burst Mode

OPERATION

VOUT = 1.8V

ILOAD = 0A

TEMPERATURE (°C)

0.001

–25 0 25 50 75 100 125–50

DYNAMIC SUPPLY CURRENT (mA)

0.1

100

3411A G14

0.01

10 FORCED CONTINUOUS

PULSE SKIP

Burst Mode

OPERATION

VOUT = 1.8V

ILOAD = 0A

INPUT VOLTAGE(V)

2500

2000

1500

1000

500

3411A G15

0 3 5 6

1 2 4

SWITCH LEAKAGE (pA)

SYNCHRONOUS SWITCH

MAIN SWITCH

TEMPERATURE (°C)

600

500

400

300

200

100

3411A G16

–50 25 75 100 125

–25 0 50

SWITCH LEAKAGE (nA)

MAIN SWITCH

SYNCHRONOUS SWITCH

VIN = 3.6V

VOUT = 1.8V

ILOAD = 50mA

2V/DIV

VOUT

50mV/DIV

AC COUPLED

200mA/DIV

3411A G17

4µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 5mA

2V/DIV

VOUT

50mV/DIV

AC COUPLED

200mA/DIV

3411A G18

4µs/DIV

Switch Leakage vs Input Voltage

Switch Leakage vs Temperature Burst Mode Operation Pulse Skipping Mode

LTC3411A

Rev. E

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VIN = 3.6V fO = 1MHz, unless

otherwise noted.

VIN = 3.6V

VOUT = 1.8V

ILOAD = 80mA

2V/DIV

VOUT

50mV/DIV

AC COUPLED

200mA/DIV

3411A G19

2µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 0A

SHDN/RT

2V/DIV

VOUT

1V/DIV

1A/DIV

3411A G20

200µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 1.25A

SHDN/RT

2V/DIV

VOUT

1V/DIV

1A/DIV

3411A G21

200µs/DIV

Forced Continuous Mode Start-Up from Shutdown Start-Up from Shutdown

VIN = 3.6V

PREBIASED VOUT = 3V, VOUT = 1.8V

ILOAD = 0A

VOUT

1V/DIV

500mA/DIV

3411A G22

200µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 0A to 1.25A

Burst Mode OPERATION

VOUT

100mV/DIV

AC COUPLED

1A/DIV

ILOAD

1A/DIV

3411A G23

40µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 50mA to 1.25A

Burst Mode OPERATION

VOUT

100mV/DIV

AC COUPLED

1A/DIV

ILOAD

1A/DIV

3411A G24

40µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 250mA to 1.25A

Burst Mode OPERATION

VOUT

100mV/DIV

AC COUPLED

1A/DIV

ILOAD

1A/DIV

3411A G25

40µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 0A

VOUT

1V/DIV

2A/DIV

3411A G26

40µs/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 0A

VOUT

1V/DIV

500mA/DIV

3411A G27

40µs/DIV

Start-Up from Shutdown with

a Prebiased Output (Forced

Continuous Mode) Load Step Load Step

Load Step VOUT Short to Ground VOUT Short to VIN (Forced

Continuous Mode)

LTC3411A

Rev. E

For more information www.analog.com

SHDN/RT (Pin 1): Combination Shutdown and Timing

Resistor Pin. The oscillator frequency is programmed by

connecting a resistor from this pin to ground. Forcing

this pin to SV

causes the device to be shut down. In

shutdown all functions are disabled.

SYNC/MODE (Pin 2): Combination Mode Selection and

Oscillator Synchronization Pin. This pin controls the oper-

ation of the device. When tied to SV

or SGND, Burst

Mode operation or pulse skipping mode is selected,

respectively. If this pin is held at half of SVIN, the forced

continuous mode is selected. The oscillation frequency

can be synchronized to an external oscillator applied to

this pin. When synchronized to an external clock pulse

skip mode is selected.

SGND (Pin 3): The Signal Ground Pin. All small-signal com-

ponents and compensation components should be con-

nected to this ground (see Board Layout Considerations).

SW (Pin 4): The Switch Node Connection to the Inductor.

This pin swings from PVIN to PGND.

PIN FUNCTIONS

PGND (Pin 5): Main Power Ground Pin. Connect to the

(–) terminal of COUT, and (–) terminal of CIN.

PVIN (Pin 6): Main Supply Pin. Must be closely decoupled

to PGND.

SVIN (Pin 7): The Signal Power Pin. All active circuitry

is powered from this pin. Must be closely decoupled to

SGND. SVIN must be greater than or equal to PVIN.

PGOOD (Pin 8): The Power Good Pin. This common drain

logic output is pulled to SGND when the output voltage is

not within ±7% of regulation.

VFB (Pin 9): Receives the feedback voltage from the exter-

nal resistive divider across the output. Nominal voltage

for this pin is 0.8V.

(Pin 10): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. Nominal voltage range for this pin is 0.4V to 1.4V.

PGND (Exposed Pad Pin 11, DFN Package): Power

Ground. Must be soldered to electrical ground on PCB.

NOMINAL (V) ABSOLUTE MAX (V)

PIN NAME DESCRIPTION MIN TYP MAX MIN MAX

1 SHDN/RTShutdown/Timing Resistor –0.3 0.8 SVIN –0.3 SVIN + 0.3

2 SYNC/MODE Mode Select/Synchronization Pin 0 SVIN –0.3 SVIN + 0.3

3 SGND Signal Ground 0

4 SW Switch Node 0 PVIN –0.3 PVIN + 0.3

5 PGND Main Power Ground 0

6PVIN Main Power Supply –0.3 5.5 –0.3 SVIN + 0.3

7 SVIN Signal Power Supply 2.5 5.5 –0.3 6

8 PGOOD Power Good Pin 0 SVIN –0.3 6

9 VFB Output Feedback Pin 0 0.8 1.0 –0.3 SVIN + 0.3

10 ITH Error Amplifier Compensation and Run Pin 0 1.5 –0.3 SVIN + 0.3

LTC3411A

Rev. E

For more information www.analog.com

BLOCK DIAGRAM

–

9–

–

0.74V

0.8V

ERROR

AMPLIFIER

VBBURST

COMPARATOR

BCLAMP

NMOS

COMPARATOR

PMOS CURRENT

COMPARATOR

REVERSE

COMPARATOR

0.86V

PGOOD

ITH

VFB

SHDN/RT2

SYNC/MODE

3411A BD

PVIN

SGND

SVIN

SLOPE

COMPENSATION

VOLTAGE

REFERENCE

OSCILLATOR

LOGIC

ITH

LIMIT

–

PGND

LTC3411A

Rev. E

For more information www.analog.com

OPERATION

The LTC3411A uses a constant frequency, current mode

architecture. The operating frequency is determined by

the value of the RT resistor or can be synchronized to an

external oscillator. To suit a variety of applications, the

selectable MODE pin allows the user to trade-off noise

for efficiency.

The output voltage is set by an external divider returned to

the VFB pin. An error amplifier compares the divided out-

put voltage with the reference voltage of 0.8V and adjusts

the peak inductor current accordingly. Overvoltage and

undervoltage comparators will pull the PGOOD output

low if the output voltage is not within ±7% of its regulated

value. A tripping delay of 40µs and untripping delay of

105µs ensures PGOOD will not glitch due to transient

spikes on VOUT.

Main Control Loop

During normal operation, the top power switch (P-channel

MOSFET) is turned on at the beginning of a clock cycle.

Current flows through this switch into the inductor and the

load, increasing until the peak inductor current reaches

the limit set by the voltage on the ITH pin. Then the top

switch is turned off, the bottom switch is turned on, and

the energy stored in the inductor forces the current to flow

through the bottom switch and the inductor, out into the

load until the next clock cycle.

The peak inductor current is controlled by the voltage

on the ITH pin, which is the output of the error amplifier.

The output is developed by the error amplifier comparing

the feedback voltage, VFB, to the 0.8V reference voltage.

When the load current increases, the output voltage and

VFB decrease slightly. This decrease in VFB causes the

error amplifier to increase the ITH voltage until the average

inductor current matches the new load current.

The main control loop is shut down by pulling the

SHDN/RT pin to SVIN, resetting the internal soft-start.

Re-enabling the main control loop by releasing the SHDN/

RT pin activates the internal soft-start, which slowly

ramps the output voltage over approximately 0.8ms until

it reachesregulation.

Low Current Operation

Three modes are available to control the operation of the

LTC3411A at low currents. All three modes automatically

switch from continuous operation to the selected mode

when the load current is low.

To optimize efficiency, the Burst Mode operation can be

selected. When the load is relatively light, the LTC3411A auto-

matically switches into Burst Mode

operation in which the

PMOS switch operates intermittently based on load demand.

By running cycles periodically, the switching losses which are

dominated by the gate charge losses of the power MOSFETs

are minimized. The main control loop is interrupted when

the output voltage reaches the desired regulated value. The

burst comparator trips when ITH is below approximately 0.5V,

shutting off the switch and reducing the power. The output

capacitor and the inductor supply the power to the load until

ITH rises above approximately 0.5V, turning on the switch and

the main control loop which starts another cycle.

For lower output voltage ripple at low currents, pulse skip-

ping mode can be used. In this mode, the LTC3411A con-

tinues to switch at a constant frequency down to very low

currents, where it will eventually begin skipping pulses.

Finally, in forced continuous mode, the inductor current

is constantly cycled which creates a fixed output voltage

ripple at all output current levels. This feature is desirable

in telecommunications since the noise is at a constant fre-

quency and is thus, easy to filter out. Another advantage of

this mode is that the regulator is capable of both sourcing

current into a load and sinking current from the output.

Dropout Operation

When the input supply voltage decreases toward the out-

put voltage, the duty cycle increases to 100% which is the

dropout condition. In dropout, the PMOS switch is turned

on continuously with the output voltage being equal to the

input voltage minus the voltage drop across the internal

P-channel MOSFET and the inductor.

Low Supply Operation

The LTC3411A incorporates an undervoltage lockout cir-

cuit which shuts down the part when the input voltage

drops below about 2.1V to prevent unstable operation.

LTC3411A

Rev. E

For more information www.analog.com

APPLICATIONS INFORMATION

A general LTC3411A application circuit is shown in

Figure4. External component selection is driven by the

load requirement, and begins with the selection of the

inductor L1. Once L1 is chosen, CIN and COUT can be

selected.

Operating Frequency

Selection of the operating frequency is a trade-off between

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequencies improves efficiency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output ripple voltage.

The operating frequency, fO, of the LTC3411A is deter-

mined by an external resistor that is connected between

the RT pin and ground. The value of the resistor sets the

ramp current that is used to charge and discharge an

internal timing capacitor within the oscillator and can be

calculated by using the following equation:

RT = 5 • 107 (fO)–1.6508 (kΩ),

where fO is in kHz, or can be selected using Figure1.

The maximum usable operating frequency is limited by

the minimum on-time and the duty cycle. This can be

calculated as:

fO(MAX) ≈ 6.67 •VOUT

VIN(MAX)

(MHz)

The minimum frequency is internally set at around 200kHz.

Inductor Selection

The operating frequency, fO, has a direct effect on the

inductor value, which in turn influences the inductor rip-

ple current ΔIL:

ΔIL=VOUT

fO• L • 1−VOUT

VIN

⎛

⎝

⎜⎞

⎠

⎟

The inductor ripple current decreases with larger induc-

tance or frequency, and increases with higher V

or V

OUT

Accepting larger values of ΔIL allows the use of lower

inductances, but results in higher output ripple voltage,

greater core loss and lower output capability.

A reasonable starting point for setting ripple current

is ΔI

= 0.4 • I

OUT(MAX)

, where I

OUT(MAX)

is 1.25A. The

largest ripple current ΔIL occurs at the maximum input

voltage. To guarantee that the ripple current stays below a

specified maximum, the inductor value should be chosen

according to the following equation:

L=VOUT

fO•ΔIL

• 1−VOUT

VIN(MAX)

⎛

⎝

⎜⎞

⎠

⎟

The inductor value will also have an effect on Burst Mode

operation. The transition from low current operation

begins when the peak inductor current falls below a level

set by the burst clamp. Lower inductor values result in

higher ripple current which causes this to occur at lower

load currents. This causes a dip in efficiency in the upper

range of low current operation. In Burst Mode operation,

Figure1. Frequency vs RT

lower inductance values will cause the burst frequency

to increase.

Inductor Core Selection

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

Toroid or shielded pot cores in ferrite or permalloy mate-

rials are small and don’t radiate much energy, but gen-

erally cost more than powdered iron core inductors with

similar electrical characteristics. The choice of which style

RT (kΩ)

FREQUENCY (kHz)

500

1500

2000

2500

5000

4500

3411A F01

1000

400 800 1200 1600

3000

3500

4000

TA = 25°C

LTC3411A

Rev. E

For more information www.analog.com

APPLICATIONS INFORMATION

inductor to use often depends more on the price vs size

requirements and any radiated field/EMI requirements

than on what the LTC3411A requires to operate. Table1

1 shows some typical surface mount inductors that work

well in LTC3411A applications.

Table1. Representative Surface Mount Inductors

MANU-

FACTURER

PART NUMBER

VALUE

MAX DC

CURRENT

DCR

HEIGHT

Toko A914BYW-1R2M=P3:

D52LC

1.2µH 2.15A 44mΩ 2mm

A960AW-1R2M=P3:

D518LC

1.2µH 1.8A 46mΩ 1.8mm

DB3015C-1068AS-1R0N 1.0µH 2.1A 43mΩ 1.5mm

DB3018C-1069AS-1R0N 1.0µH 2.1A 45mΩ 1.8mm

DB3020C-1070AS-1R0N 1.0µH 2.1A 47mΩ 2mm

A914BYW-2R2M-D52LC 2.2µH 2.05A 49mΩ 2mm

A915AY-2ROM-D53LC 2.0µH 3.3A 22mΩ 3mm

Coilcraft LPO1704-122ML 1.2µH 2.1A 80mΩ 1mm

D01608C-222 2.2µH 2.3A 70mΩ 3mm

LP01704-222M 2.2µH 2.4A 120mΩ1mm

Sumida CR32-1R0 1.0µH 2.1A 72mΩ 3mm

CR5D11-1R0 1.0µH 2.2A 40mΩ 1.2mm

CDRH3D14-1R2 1.2µH 2.2A 36mΩ 1.5mm

CDRH4D18C/LD-1R1 1.1µH 2.1A 24mΩ 2mm

CDRH4D28C/LD-1R0 1.0µH 3.0A 17.5mΩ 3mm

CDRH4D28C-1R1 1.1µH 3.8A 22mΩ 3mm

CDRH4D28-1R2 1.2µH 2.56A 23.6mΩ 3mm

CDRH6D12-1R0 1.0µH 2.80A 37.5mΩ 1.5mm

CDRH4D282R2 2.2µH 2.04A 23mΩ 3mm

CDC5D232R2 2.2µH 2.16A 30mΩ2.5mm

Taiyo Yuden NPO3SB1ROM 1.0µH 2.6A 27mΩ 1.8mm

N06DB2R2M 2.2µH 3.2A 29mΩ 3.2mm

N05DB2R2M 2.2µH 2.9A 32mΩ 2.8mm

Murata LQN6C2R2M04 2.2µH 3.2A 24mΩ 5mm

FDK MIPW3226DORGM 0.9µH 1.4A 80mΩ 1mm

Catch Diode Selection

Although unnecessary in most applications, a small

improvement in efficiency can be obtained in a few

applications by including the optional diode D1 shown in

Figure4, which conducts when the synchronous switch

is off. When using Burst Mode operation or pulse skip

mode, the synchronous switch is turned off at a low

current and the remaining current will be carried by the

optional diode. It is important to adequately specify the

diode peak current and average power dissipation so

as not to exceed the diode ratings. The main problem

with Schottky diodes is that their parasitic capacitance

reduces the efficiency, usually negating the possible

benefits for LTC3411A circuits. Another problem that a

Schottky diode can introduce is higher leakage current at

high temperatures, which could reduce the low current

efficiency.

Remember to keep lead lengths short and observe

proper grounding (see Board Layout Considerations)

to avoid ringing and increased dissipation when using a

catchdiode.

Input Capacitor (CIN) Selection

In continuous mode, the input current of the converter is a

square wave with a duty cycle of approximately V

OUT

To prevent large voltage transients, a low equivalent series

resistance (ESR) input capacitor sized for the maximum

RMS current must be used. The maximum RMS capacitor

current is given by:

IRMS ≈ IMAX

VOUT(VIN − VOUT )

VIN

where the maximum average output current IMAX equals

the peak current minus half the peak-to-peak ripple cur-

rent, IMAX = ILIM – ΔIL/2.

This formula has a maximum at VIN = 2VOUT, where

IRMS ≅ IOUT/2. This simple worst case is commonly used

to design because even significant deviations do not offer

much relief. Note that capacitor manufacturer’s ripple cur-

rent ratings are often based on only 2000 hours lifetime.

This makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet the size or height requirements of the design. An

additional 0.1µF to 1µF ceramic capacitor is also recom-

mended on VIN for high frequency decoupling, when not

using an all ceramic capacitor solution.

LTC3411A

Rev. E

For more information www.analog.com

Output Capacitor (COUT) Selection

The selection of COUT is driven by the required ESR to

minimize voltage ripple and load step transients. Typically,

once the ESR requirement is satisfied, the capacitance is

adequate for filtering. The output ripple (ΔVOUT) is deter-

mined by:

ΔVOUT ≈ ΔILESR +1

8fOCOUT

⎛

⎝

⎜⎞

⎠

⎟

where f

= operating frequency, C

OUT

= output capaci-

tance and ΔI

= ripple current in the inductor. The out-

put ripple is highest at maximum input voltage since ΔIL

increases with input voltage. With ΔIL = 0.4 • IOUT(MAX) the

output ripple will be less than 100mV at maximum VIN, a

minimum COUT value of 10µF and fO = 1MHz with:

ESRCOUT < 150mΩ

Once the ESR requirements for COUT have been met, the

RMS current rating generally far exceeds the IRIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or RMS

current handling requirement of the application. Aluminum

electrolytic, special polymer, ceramic and dry tantalum

capacitors are all available in surface mount packages.

The OS-CON semiconductor dielectric capacitor available

from Sanyo has the lowest ESR(size) product of any alu-

minum electrolytic at a somewhat higher price. Special

polymer capacitors, such as Sanyo POSCAP, offer very

low ESR, but have a lower capacitance density than other

types. Tantalum capacitors have the highest capacitance

density, but it has a larger ESR and it is critical that the

capacitors are surge tested for use in switching power

supplies. An excellent choice is the AVX TPS series of sur-

face mount tantalums, available in case heights ranging

from 2mm to 4mm. Aluminum electrolytic capacitors have

a significantly larger ESR, and is often used in extremely

cost-sensitive applications provided that consideration is

given to ripple current ratings and long term reliability.

Ceramic capacitors have the lowest ESR and cost but also

have the lowest capacitance density, a high voltage and

temperature coefficient and exhibit audible piezoelectric

effects. In addition, the high Q of ceramic capacitors along

with trace inductance can lead to significant ringing. Other

capacitor types include the Panasonic specialty polymer

(SP) capacitors.

In most cases, 0.1µF to 1µF of ceramic capacitors should

also be placed close to the LTC3411A in parallel with the

main capacitors for high frequency decoupling.

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high rip-

ple current, high voltage rating and low ESR make them

ideal for switching regulator applications. Because the

LTC3411A’s control loop does not depend on the output

capacitor’s ESR for stable operation, ceramic capacitors

can be used freely to achieve very low output ripple and

small circuit size.

However, care must be taken when ceramic capacitors

are used at the input and the output. When a ceramic

capacitor is used at the input and the power is supplied

by a wall adapter through long wires, a load step at the

output can induce ringing at the input, VIN. At best, this

ringing can couple to the output and be mistaken as loop

instability. At worst, a sudden inrush of current through

the long wires can potentially cause a voltage spike at VIN,

large enough to damage the part.

When choosing the input and output ceramic capacitors,

choose the X5R or X7R dielectric formulations. These

dielectrics have the best temperature and voltage char-

acteristics of all the ceramics for a given value and size.

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulfill a charge stor-

age requirement. During a load step, the output capac-

itor must instantaneously supply the current to support

the load until the feedback loop raises the switch current

enough to support the load. The time required for the

feedback loop to respond is dependent on the compensa-

tion components and the output capacitor size. Typically,

3 to 4 cycles are required to respond to a load step, but

only in the first cycle does the output drop linearly. The

output droop, VDROOP, is usually about 2 to 3 times the

linear drop of the first cycle. Thus, a good place to start is

with the output capacitor value of approximately:

APPLICATIONS INFORMATION

LTC3411A

Rev. E

For more information www.analog.com

COUT ≈ 2.5 ∆IOUT

fO•VDROOP

More capacitance may be required depending on the duty

cycle and load step requirements.

In most applications, the input capacitor is merely required

to supply high frequency bypassing, since the impedance

to the supply is very low. A 10µF ceramic capacitor is

usually enough for these conditions.

Setting the Output Voltage

The LTC3411A develops a 0.8V reference voltage between

the feedback pin, VFB, and the signal ground as shown in

Figure4. The output voltage is set by a resistive divider

according to the following formula:

VOUT ≈0.8V 1+

⎛

⎝

⎜⎞

⎠

⎟

Keeping the current small (<5µA) in these resistors max-

imizes efficiency, but making them too small may allow

stray capacitance to cause noise problems and reduce the

phase margin of the error amp loop.

To improve the frequency response, a feed-forward capac-

itor CF may also be used. Great care should be taken to

route the VFB line away from noise sources, such as the

inductor or the SW line.

Shutdown and Soft-Start

The SHDN/RT pin is a dual purpose pin that sets the oscil-

lator frequency and provides a means to shut down the

LTC3411A. This pin can be interfaced with control logic in

several ways, as shown in Figure2 and Figure3. In both

configurations, Run = “0” shuts down the LTC3411A and

Run = “1” activates the LTC3411A.

Care must be taken when using Figure3 to shut down

the part in force continuous mode. The pull up resistor

should be as small as the application would allow and

the pull down transistor should be as small as possible

to minimize its parasitic drain capacitance. If possible,

always shut down the part while in pulse skipping mode or

Burst Mode operation. Figure4 shows an example of how

to switch from force continuous mode to pulse skipping

mode when RUN goes low. The parasitic drain capacitance

of a large transistor coupled with a large pull up resistor

results in large RC constants. As RUN goes low, the tran-

sistor drain charges up slowly, gradually decreasing the

oscillator frequency of the part. This leads to large induc-

tor current ripples translating into large output voltage

ripples. In some cases, the output voltage could rise up

to dangerous levels.

When activating the LTC3411A, an internal soft-start

slowly ramps the output voltage up until regulation.

Soft-start prevents surge currents from VIN by gradually

ramping the output voltage up during start-up. The output

will ramp from zero to full scale over a time period of

approximately 0.7ms. This prevents the LTC3411A from

having to quickly charge the output capacitor and thus

supplying an excessive amount of instantaneous current.

APPLICATIONS INFORMATION

Figure2. SHDN/RT Pin Activated with a Logic Input Figure4. Automatic Mode Change Circuit

3411A F02

RUN

SHDN/R

Figure3. SHDN/RT Pin Activated with a Switch

3411A F03

RUN

SHDN/RT

100k

SVIN

3411A F04

SHDN/RT

SVIN

100k

SYNC/MODE

ONOFF

LTC3411A

Rev. E

For more information www.analog.com

The LTC3411A can start into a back-biased output in

forced continuous operation. When the output is pre-

biased at either a higher or lower value than the regu-

lated output voltage, the LTC3411A will sink or source

current as needed to bring the output back into regulation.

However, during soft-start the regulator will always start

in pulse skipping mode ignoring the mode selected with

the SYNC/MODE pin. This prevents the output from dis-

charging to below the regulation point when soft-starting.

Mode Selection and Frequency Synchronization

The SYNC/MODE pin is a multipurpose pin which pro-

vides mode selection and frequency synchronization.

Connecting this pin to V

enables Burst Mode opera-

tion, which provides the best low current efficiency at the

cost of a higher output voltage ripple. When this pin is

connected to ground, pulse skipping operation is selected

which provides the lowest output voltage and current rip-

ple at the cost of low current efficiency. Applying a voltage

that is half the value of the input voltage results in forced

continuous mode, which creates a fixed output ripple and

is capable of sinking up to 0.4A. Since the switching noise

is constant in this mode, it is also the easiest to filter out.

The LTC3411A can also be synchronized to an external

clock signal by the SYNC/MODE pin. The internal oscilla-

tor frequency should be set to ±20% of the external clock

frequency to ensure adequate slope compensation, since

slope compensation is derived from the internal oscillator.

During synchronization, the mode is set to pulse skipping

and the top switch turn on is synchronized to the falling

edge of the external clock.

Checking Transient Response

The OPTI-LOOP

compensation allows the transient

response to be optimized for a wide range of loads and

output capacitors. The availability of the ITH pin not

only allows optimization of the control loop behavior

but also provides a DC coupled and AC filtered closed

loop response test point. The DC step, rise time and set-

tling time at this test point truly reflects the closed loop

response. Assuming a predominantly second order sys-

tem, phase margin and/or damping factor can be esti-

mated using the percentage of overshoot seen at this pin.

The bandwidth can also be estimated by examining the

rise time at the pin.

The ITH external components shown in the circuit on the

front page of this data sheet will provide an adequate

starting point for most applications. The series R-C fil-

ter sets the dominant pole-zero loop compensation. The

values can be modified slightly (from 0.5 to 2 times their

suggested values) to optimize transient response once the

final PC layout is done and the particular output capacitor

type and value have been determined. The output capac-

itors need to be selected because the various types and

values determine the loop feedback factor gain and phase.

An output current pulse of 20% to 100% of full load cur-

rent having a rise time of 1µs to 10µs will produce output

voltage and ITH pin waveforms that will give a sense of the

overall loop stability without breaking the feedback loop.

Switching regulators take several cycles to respond to a

step in load current. When a load step occurs, V

OUT

imme-

diately shifts by an amount equal to ΔILOAD • ESR, where

ESR is the effective series resistance of COUT. ΔILOAD also

begins to charge or discharge COUT generating a feedback

APPLICATIONS INFORMATION

PVIN

LTC3411A

PGOOD PGOOD

SVIN

SYNC/MODE

VFB

ITH

SHDN/RT

OPTIONAL

VIN

SGND PGND

3411A F05

CITH

VOUT

CIN

PGND

SGND

PGND

SGND SGND SGND SGNDGND

PGND PGND

COUT

SGND

Figure5. LTC3411A General Schematic

LTC3411A

Rev. E

For more information www.analog.com

error signal used by the regulator to return VOUT to its

steady-state value. During this recovery time, VOUT can

be monitored for overshoot or ringing that would indicate

a stability problem.

The initial output voltage step may not be within the band-

width of the feedback loop, so the standard second order

overshoot/DC ratio cannot be used to determine phase mar-

gin. The gain of the loop increases with R and the bandwidth

of the loop increases with decreasing C. If R is increased by

the same factor that C is decreased, the zero frequency will

be kept the same, thereby keeping the phase the same in the

most critical frequency range of the feedback loop. In addi-

tion, a feedforward capacitor CF can be added to improve the

high frequency response, as shown in Figure5. Capacitor CF

provides phase lead by creating a high frequency zero with

R2 which improves the phase margin.

The output voltage settling behavior is related to the sta-

bility of the closed-loop system and will demonstrate the

actual overall supply performance. For a detailed expla-

nation of optimizing the compensation components,

including a review of control loop theory, refer to ADI

Application Note 76.

Although a buck regulator is capable of providing the full

output current in dropout, it should be noted that as the

input voltage VIN drops toward VOUT, the load step capa-

bility does decrease due to the decreasing voltage across

the inductor. Applications that require large load step capa-

bility near dropout should use a different topology such as

SEPIC, Zeta or single inductor, positive buck/boost.

In some applications, a more severe transient can be

caused by switching in loads with large (>1µF) input

capacitors. The discharged input capacitors are effec-

tively put in parallel with COUT, causing a rapid drop in

VOUT. No regulator can deliver enough current to prevent

this problem, if the switch connecting the load has low

resistance and is driven quickly. The solution is to limit

the turn-on speed of the load switch driver. A Hot Swap™

controller is designed specifically for this purpose and

usually incorporates current limiting, short-circuit pro-

tection, and soft-starting.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3411A circuits: 1) VIN current, 2) switching

losses, 3) I2R losses, 4) other losses.

1) The VIN current is the DC supply current given in

the electrical characteristics which excludes MOSFET

driver and control currents. VIN current results in a small

(<0.1%) loss that increases with VIN, even at no load.

2) The switching current is the sum of the MOSFET

driver and control currents. The MOSFET driver current

results from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

from VIN to ground. The resulting dQ/dt is a current out

of VIN that is typically much larger than the DC bias cur-

rent. In continuous mode, IGATECHG = fO(QT + QB), where

QT and QB are the gate charges of the internal top and

bottom MOSFET switches. The gate charge losses are

proportional to V

and thus their effects will be more

pronounced at higher supply voltages.

APPLICATIONS INFORMATION

Figure6. Power Loss vs Load Current

LOAD CURRENT (mA)

VOUT = 1.2V

VOUT = 1.5V

VOUT = 1.8V

0.0001

POWER LOSS (W)

0.001

0.1 1 10 100 1000 10000

3411A F06

0.01

0.1

VIN = 3.6V

fO = 1MHz

VOUT = 1.2V - 1.8V

LTC3411A

Rev. E

For more information www.analog.com

APPLICATIONS INFORMATION

3) I2R Losses are calculated from the DC resistances of

the internal switches, RSW, and external inductor, RL. In

continuous mode, the average output current flowing

through inductor L is “chopped” between the internal top

and bottom switches. Thus, the series resistance looking

into the SW pin is a function of both top and bottom

MOSFET RDS(ON) and the duty cycle (DC) as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteristics

curves. Thus, to obtain I2R losses:

I2R losses = IOUT2(RSW + RL)

4) Other “hidden” losses such as copper trace and internal

battery resistances can account for additional efficiency

degradations in portable systems. It is very important

to include these “system” level losses in the design of a

system. The internal battery and fuse resistance losses

can be minimized by making sure that CIN has adequate

charge storage and very low ESR at the switching fre-

quency. Other losses including diode conduction losses

during dead-time and inductor core losses which gener-

ally account for less than 2% total additional loss.

Thermal Considerations

In a majority of applications, the LTC3411A does not

dissipate much heat due to its high efficiency. However,

in applications where the LTC3411A is running at high

ambient temperature with low supply voltage and high

duty cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will be turned off and the SW node

will become high impedance.

To avoid the LTC3411A from exceeding the maximum junc-

tion temperature, the user will need to do some thermal

analysis. The goal of the thermal analysis is to determine

whether the power dissipated exceeds the maximum junction

temperature of the part. The temperature rise is given by:

TRISE = PD • θJA

where P

is the power dissipated by the regulator and θ

is the thermal resistance from the junction of the die to

the ambient temperature.

The junction temperature, TJ, is given by:

TJ = TRISE + TAMBIENT

As an example, consider the case when the LTC3411A

is in dropout at an input voltage of 3.3V with a load cur-

rent of 1A. From the Typical Performance Characteristics

graph of Switch Resistance, the RDS(ON) resistance of the

P-channel switch is 0.15Ω. Therefore, power dissipated

by the part is:

PD = I2 • RDS(ON) = 150mW

The MS10 package junction-to-ambient thermal resis-

tance, θJA, will be in the range of 100°C/W to 120°C/W.

Therefore, the junction temperature of the regulator oper-

ating in a 70°C ambient temperature is approximately:

TJ = 0.15 • 120 + 70 = 88°C

Remembering that the above junction temperature is

obtained from an R

DS(ON)

at 25°C, we might recalculate

the junction temperature based on a higher RDS(ON) since it

increases with temperature. However, we can safely assume

that the actual junction temperature will not exceed the

absolute maximum junction temperature of 125°C.

Design Example

As a design example, consider using the LTC3411A in a

portable application with a Li-Ion battery. The battery pro-

vides a VIN = 2.5V to 4.2V. The load requires a maximum

of 1.25A in active mode and 10mA in standby mode. The

output voltage is VOUT = 2.5V. Since the load still needs

power in standby, Burst Mode operation is selected for

good low load efficiency.

First, calculate the timing resistor for 1MHz operation:

RT = 5 • 107 (103)–1.6508 = 557.9k

Use a standard value of 549k. Next, calculate the inductor

value for about 40% ripple current at maximum VIN:

L=2.5V

1MHz • 500mA • 1−2.5V

4.2V









=2µH

Choosing the closest standard inductor value from a ven

dor of 2.2µH, results in a maximum ripple current of:

ΔIL=

2.5V

1MHz • 2.2µ• 1−

2.5V

4.2V

⎛

⎝

⎜⎞

⎠

⎟=460mA

LTC3411A

Rev. E

For more information www.analog.com

APPLICATIONS INFORMATION

For cost reasons, a ceramic capacitor will be used. COUT

selection is then based on load step droop instead of ESR

requirements. For a 5% output droop:

COUT ≈ 2.5 1.25A

1MHz •(5% •2.5V) = 25µF

The closest standard value is 22µF. Since the output

impedance of a Li-Ion battery is very low, CIN is typically

10µF. In noisy environments, decoupling SVIN from PVIN

with an R6/C8 filter of 1Ω/0.1µF may help, but is typically

not needed.

The output voltage can now be programmed by choosing the

values of R1 and R2. To maintain high efficiency, the current

in these resistors should be kept small. Choosing 2µA with

the 0.8V feedback voltage makes R1~400k. A close standard

1% resistor value is 412k. Then R2 is 887k.

The compensation should be optimized for these com-

ponents by examining the load step response but a

good place to start for the LTC3411A is with a 12.1kΩ

and 680pF filter. The output capacitor may need to be

increased depending on the actual undershoot during a

load step.

The PGOOD pin is a common drain output and requires a

pull-up resistor. A 100k resistor is used for adequate speed.

The circuit on page 1 of this data sheet shows the com-

plete schematic for this design example.

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3411A. These items are also illustrated graphically

in the layout diagram of Figure7. Check the following in

your layout:

1. Does the capacitor C

connect to the power V

(Pin 6) and power GND (Pin 5) as close as possible?

This capacitor provides the AC current to the internal

power MOSFETs and their drivers.

2. Are the COUT and L1 closely connected? The (–) plate of

COUT returns current to PGND and the (–) plate of CIN.

3. The resistor divider, R1 and R2, must be connected

between the (+) plate of C

OUT

and a ground line terminated

near SGND (Pin 3). The feedback signal VFB should be

routed away from noisy components and traces, such as

the SW line (Pin 4), and its trace should be minimized.

4. Keep sensitive components away from the SW pin. The

input capacitor CIN, the compensation capacitor CC and

CITH and all the resistors R1, R2, RT, and RC should be

routed away from the SW trace and the inductor L1. The

SW pin pad should be kept as small as possible.

5. A ground plane is preferred, but if not available, keep

the signal and power grounds segregated with small sig-

nal components returning to the SGND pin at one point

which is then connected to the PGND pin.

6. Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise of

power components. These copper areas should be con-

nected to one of the input supplies: PVIN, PGND, SVIN

orSGND.

Figure7. LTC3411A Layout Diagram (See Board Layout Checklist)

PVIN

LTC3411A

PGND

SVIN

SGND

PGOODPGOOD

VFB SYNC/MODE

ITH SHDN/RT

VIN

BMPS

VIN

VOUT

CITH

R1R2

3411A F07

BOLD LINES INDICATE HIGH CURRENT PATHS

CIN

COUT

LTC3411A

Rev. E

For more information www.analog.com

SVIN

LTC3411A

PGOOD PGOOD

PVIN

SYNC/MODE VFB

ITH SHDN/RT

SGND

2.2µH

VIN

2.5V TO

5.5V

VOUT

1.2V/1.5V/1.8V

AT 1.25A

100k

549k

R1A

357k

12.1k

RS1

RS2

3411A TA02a

680pF

C4 22pF

R2 442k

22µF

SGND SGND

R1B

511k

R1C

887k

PGND

10µF

PGND

PGNDSGND

NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE

C1, C2: TAIYO YUDEN JMK325BJ226MM

L1: TOKO A914BYW-2R2M (D52LC SERIES)

GND

1.8V 1.5V 1.2V

General Purpose Buck Regulator Using Ceramic Capacitors

Efficiency vs Output Current

TYPICAL APPLICATIONS

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

00.1 1 10 100 1000 10000

3411A TA02b

Burst Mode

OPERATION

VIN = 3.6V

VOUT = 1.2V

fO = 1MHz

FORCED CONTINUOUS

PULSE SKIP

VIN = 3.6V

VOUT = 1.2V

ILOAD = 100mA TO 1.25A

Burst Mode OPERATION

VOUT

100mV/DIV

AC COUPLED

1A/DIV

3411A TA02c

40µs/DIV

ILOAD

1A/DIV

VIN = 3.6V

VOUT = 1.8V

ILOAD = 100mA TO 1.25A

PULSE SKIPPING MODE

VOUT

100mV/DIV

AC COUPLED

1A/DIV

3411A TA02d

40µs/DIV

ILOAD

1A/DIV

LTC3411A

Rev. E

For more information www.analog.com

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.125

TYP

2.38 ±0.10

(2 SIDES)

106

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV C 0310

0.25 ±0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.15 ±0.05

0.50

BSC

0.70 ±0.05

3.55 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

PACKAGE DESCRIPTION

LTC3411A

Rev. E

For more information www.analog.com

MSOP (MS) 0213 REV F

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ±0.152

(.193 ±.006)

0.497 ±0.076

(.0196 ±.003)

REF

8910 76

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ±0.038

(.0120 ±.0015)

TYP

0.50

(.0197)

BSC

0.1016 ±0.0508

(.004 ±.002)

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661 Rev F)

PACKAGE DESCRIPTION

LTC3411A

Rev. E

For more information www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

B 4/10 Remove θJC from Pin Configuration Section

Update Minimum for VSYNC/MODE in Electrical Characteristics Update Note 2

Update Pin 11 Description in Pin Functions

C 10/13 Changed parameters and limits on VSYNC-MODE test 3

D 6/14 Modified ABS Max PGOOD Voltage

Specified MS Package for Lead Temperature ABS Max

E 9/19 Changed Top Switch RDS(ON) from 0.18Ω to 0.21Ω Max in the Electrical Characteristics Table 3

(Revision history begins at Rev B)

LTC3411A

Rev. E

For more information www.analog.com

 ANALOG DEVICES, INC. 2008-2019

09/19

www.analog.com

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TYPICAL APPLICATION

1mm Height, 2MHz, Li-Ion to 1.8V Converter

OUTPUT CURRENT (mA)

0.1 1 10

EFFICIENCY (%)

100

1000100 10000

3411A TA04b

VIN = 2.7V

VIN = 3.6V

VIN = 4.2V

VOUT = 1.8V

fO = 2MHz VIN = 3.6V

VOUT = 1.8V

ILOAD = 50mA TO 1.25A

VOUT

100mV/DIV

AC COUPLED

1A/DIV

3411A TA04c

40µs/DIV

ILOAD

1A/DIV

VIN = 3.6V

VOUT = 1.8V

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3411A TA04d

40µs/DIV

VOUT

100mV/DIV

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1A/DIV

ILOAD

1A/DIV

Efficiency vs Output Current

PVIN

LTC3411A

PGOOD PGOOD

SVIN

SYNC/MODE

VFB

ITH

SHDN/RT

0.9µH

VOUT

1.8V

AT 1.25A

VIN

2.5V

TO 4.2V

SGND PGND

100k

C4 22pF

178k

13.3k

698k

887k

3411A TA04a

470pF

10µF

×2

10µF

C1, C2: TAIYO YUDEN JMK107BJ106MA

L1: FDK MIPW3226DORGM