ADS800E/1K - Texas Instruments

12-Bit, 40MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●LOW POWER: 390mW

●INTERNAL REFERENCE

●WIDEBAND TRACK-AND-HOLD: 65MHz

●SINGLE +5V SUPPLY

DESCRIPTION

The ADS800 is a low-power, monolithic 12-bit, 40MHz Ana-

log-to-Digital (A/D) converter utilizing a small geometry CMOS

process. This complete converter includes a 12-bit quantizer,

wideband track-and-hold, reference, and three-state outputs.

It operates from a single +5V power supply and can be

configured to accept either differential or single-ended input

signals.

The ADS800 employs digital error correction to provide

excellent Nyquist differential linearity performance for de-

manding imaging applications. Its low distortion, high SNR,

and high oversampling capability give it the extra margin

needed for telecommunications, test instrumentation, and

video applications.

This high-performance A/D converter is specified over tem-

perature for AC and DC performance at a 40MHz sampling

rate. The ADS800 is available in an SO-28 package.

Pipeline

A/D

Converter

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H 12-Bit

Digital

Data

CLK

+1.25V

+3.25V

MSBI OE

REFT

REFB

APPLICATIONS

●IF AND BASEBAND DIGITIZATION

●DIGITAL COMMUNICATIONS

●ULTRASOUND IMAGING

●GAMMA CAMERAS

●TEST INSTRUMENTATION

●CCD IMAGING

Copiers

Scanners

Cameras

●VIDEO DIGITIZING

ADS800

SBAS035B – FEBRUARY 1995 – REVISED FEBRUARY 2005

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS800U

All trademarks are the property of their respective owners.

ADS800

2SBAS035B

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ADS800U

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

ABSOLUTE MAXIMUM RATINGS(1)

+VS....................................................................................................... +6V

Analog Input.............................................................. 0V to (+VS + 300mV)

Logic Input ................................................................ 0V to (+VS + 300mV)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +125°C

External Top Reference Voltage (REFT) .................................. +3.4V Max

External Bottom Reference Voltage (REFB).............................. +1.1V Min

NOTE: (1) Stresses above these ratings may permanently damage the device.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper han-

dling and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

Resolution 12 Bits

Specified Temperature Range TAMBIENT 0 +70 °C

Operating Temperature Range TAMBIENT –40 +85 °C

ANALOG INPUT

Differential Full-Scale Input Range Both Inputs, +1.25 +3.25 V

180° Out-of-Phase

Common-Mode Voltage +2.25 V

Analog Input Bandwidth (–3dB)

Small-Signal –20dBFS(1) Input +25°C 400 MHz

Full-Power 0dBFS Input +25°C65MHz

Input Impedance 1.25 || 4 MΩ || pF

DIGITAL INPUT

Logic Family TTL/HCT Compatible CMOS

Convert Command Start Conversion Falling Edge

ACCURACY(2) fS = 2.5MHz

Gain Error +25°C±0.4 ±1.5 %

Full ±0.6 ±2.5 %

Gain Drift ±95 ppm/°C

Power-Supply Rejection of Gain ∆ +VS = ±5% +25°C 0.01 0.15 %FSR/%

Input Offset Error Full ±2.6 ±3.5 %

Power-Supply Rejection of Offset ∆ +VS = ±5% +25°C 0.02 0.15 %FSR/%

CONVERSION CHARACTERISTICS

Sample Rate 10k 40M Sample/s

Data Latency 6.5 Convert Cycle

DYNAMIC CHARACTERISTICS

Differential Linearity Error

f = 500kHz tH = 13ns(3) +25°C±0.6 ±1.0 LSB

Full ±0.8 LSB

f = 12MHz +25°C±0.4 ±1.0 LSB

Full ±0.5 LSB

No Missing Codes tH = 13ns(3) +25°C Tested LSB

Integral Linearity Error at f = 500kHz Full ±1.9 LSB

Spurious-Free Dynamic Range (SFDR)

f = 500kHz (–1dBFS input) +25°C 65 72 dBFS

Full 60 66 dBFS

f = 12MHz (–1dBFS input) +25°C5861 dBFS

Full 55 61 dBFS

SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

ADS800U SO-28 DW –40°C to +85°C ADS800U ADS800U Rails, 28

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at

www.ti.com.

PACKAGE/ORDERING INFORMATION(1)

NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure

DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope

signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.

ADS800 3

SBAS035B www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

ADS800U

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

DYNAMIC CHARACTERISTICS (Cont.)

2-Tone Intermodulation Distortion (IMD)(4)

f = 4.4MHz and 4.5MHz (–7dBFS each tone) +25°C –63 dBc

Full –62 dBc

Signal-to-Noise Ratio (SNR)

f = 500kHz (–1dBFS input) +25°C6164 dB

Full 57 63 dB

f = 12MHz (–1dBFS input) +25°C6162 dB

Full 56 62 dB

Signal-to-(Noise + Distortion) (SINAD)

f = 500kHz (–1dBFS input) +25°C5963 dB

Full 54 64 dB

f = 12MHz (–1dBFS input) +25°C5658 dB

Full 51 57 dB

Differential Gain Error NTSC or PAL +25°C 0.5 %

Differential Phase Error NTSC or PAL +25°C 0.1 degrees

Aperture Delay Time +25°C2ns

Aperture Jitter +25°C 7 ps rms

Over-Voltage Recovery Time(5) 1.5x Full-Scale Input +25°C2ns

OUTPUTS

Logic Family TTL/HCT Compatible CMOS

Logic Coding Logic Selectable SOB or BTC

Logic Levels Logic “LO”, Full 0 0.4 V

CL = 15pF max

Logic “HI”, Full +2.5 +VSV

CL = 15pF max

3-State Enable Time 20 40 ns

3-State Disable Time Full 2 10 ns

POWER-SUPPLY REQUIREMENTS

Supply Voltage: +VSOperating Full +4.75 +5.0 +5.25 V

Supply Current: +ISOperating +25°C7893mA

Operating Full 78 97 mA

Power Consumption Operating +25°C 390 465 mW

Operating Full 390 485 mW

Thermal Resistance,

SO-28 75 °C/W

NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure

DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope

signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.

ADS800

4SBAS035B

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PIN CONFIGURATION

Top View SO PIN DESIGNATOR DESCRIPTION

1 GND Ground

2 B1 Bit 1, Most Significant Bit

3 B2 Bit 2

4 B3 Bit 3

5 B4 Bit 4

6 B5 Bit 5

7 B6 Bit 6

8 B7 Bit 7

9 B8 Bit 8

10 B9 Bit 9

11 B10 Bit 10

12 B11 Bit 11

13 B12 Bit 12, Least Significant Bit

14 GND Ground

15 +VS+5V Power Supply

16 CLK Convert Clock Input, 50% Duty Cycle

17 +VS+5V Power Supply

18 OE HI: High Impedance State. LO or Floating: Nor-

mal Operation. Internal pull-down resistors.

19 MSBI Most Significant Bit Inversion, HI: MSB inverted

for complementary output. LO or Floating: Straight

output. Internal pull-down resistors.

20 +VS+5V Power Supply

21 REFB Bottom Reference Bypass. For external bypass-

ing of internal +1.25V reference.

22 CM Common-Mode Voltage. It is derived by (REFT +

REFB)/2.

23 REFT Top Reference Bypass. For external bypassing

of internal +3.25V reference.

24 +VS+5V Power Supply

25 GND Ground

26 IN Input

27 IN Complementary Input

28 GND Ground

PIN DESCRIPTIONS

GND

B10

B11

B12

GND

REFT

REFB

MSBI

CLK

ADS800

TIMING DIAGRAM

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tCONV Convert Clock Period 25 100µsns

tLClock Pulse LOW 12 12.5 ns

tHClock Pulse HIGH 12(2) 12.5 ns

tDAperture Delay 2 ns

t1Data Hold Time, CL = 0pF 3.9 ns

t2New Data Delay Time, CL = 15pF max 12.5 ns

NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.

(2) tH must be 13ns minimum if no missing codes is desired only for the conditions of tCONV ≤ 28ns

and fIN < 2MHz.

Track Hold

“N”Hold

“N + 1”Hold

“N + 2”Hold

“N + 3”

Hold

“

N + 4

”Hold

“

N + 5

”

Hold

“

N + 6

”

Track

Data Valid

N – 7 Data Valid

N – 6

Internal

Track-and-Hold

Convert

Clock

Output

Data

DATA LATENCY

(6.5 Clock Cycles)

CONV

Track Track Track Track

N – 3N – 5N – 4N – 2N – 1 N

Track Track

Data Valid

N – 8

(1)

Data Invalid

ADS800 5

SBAS035B www.ti.com

TYPICAL CHARACTERISTICS

At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

SPECTRAL PERFORMANCE

Frequency (MHz)

Amplitude (dB)

0 5 10 15 20

–20

–40

–60

–80

–100

–120

fIN = 500kHz

SPECTRAL PERFORMANCE

Frequency (MHz)

Amplitude (dB)

0 5 10 15 20

–20

–40

–60

–80

–100

–120

= 1MHz

–20

–40

–60

–80

–100

–120

SPECTRAL PERFORMANCE

Frequency (MHz)

Amplitude (dB)

0 5 10 15 20

= 5MHz

SPECTRAL PERFORMANCE

Frequency (MHz)

Amplitude (dB)

0 5 10 15 20

–20

–40

–60

–80

–100

–120

= 12MHz

–20

–40

–60

–80

–100

–120

SPECTRAL PERFORMANCE

Frequency (MHz)

Amplitude (dB)

012345

fIN = 1MHz

fS = 10MHz

–20

–40

–60

–80

–100

–120

2-TONE INTERMODULATION

Amplitude (dB)

0 5 10 15 20

Frequency (MHz)

f1 = 12.5MHz

f2 = 12.0MHz

ADS800

6SBAS035B

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TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

2.0

1.0

–1.0

–2.0

DIFFERENTIAL LINEARITY ERROR

Code

DLE (LSB)

0 1024 2048 3072 4096

fIN = 500kHz

DIFFERENTIAL LINEARITY ERROR

Code

0 1024 2048 3072 4096

= 12MHz

2.0

1.0

–1.0

–2.0

DLE (LSB)

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

Frequency (MHz)

SFDR, SNR (dB)

500.1 1 10 100

SFDR

SNR

100

Input Amplitude (dBm)

SFDR (dBFS)

SWEPT POWER SFDR

–50 –40 –30 –20 –10 0 10

fIN = 12MHz

Input Amplitude (dBm)

SWEPT POWER SNR

–50 –40 –30 –20 –10 0 10

SNR (dB)

= 12MHz

4.0

2.0

–2.0

–4.0

INTEGRAL LINEARITY ERROR

ILE (LSB)

0 1024 2048 3072 4096

Code

fIN = 500kHz

ADS800 7

SBAS035B www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

DYNAMIC PERFORMANCE

vs SINGLE-ENDED FULL-SCALE INPUT RANGE

45231Single-Ended Full-Scale Range (Vp-p)

Dynamic Range (dB)

= 12MHz

SFDR

SNR

NOTE: REFT

EXT

varied,

REFB is fixed at the internal value of +1.25V.

DYNAMIC PERFORMANCE

vs DIFFERENTIAL FULL-SCALE INPUT RANGE

2 3 4

Differential Full-Scale Input Range (Vp-p)

Dynamic Range (dB)

SNR (f

= 12MHz)

SFDR (f

= 500kHz)

SNR (f

= 500kHz)

SFDR (f

= 12MHz)

NOTE: REFT

EXT

varied,

REFB is fixed at the internal value of +1.25V.

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

vs TEMPERATURE

Temperature (°C)

SFDR (dBFS)

50–25 0 25 50 75

= 500kHz

= 12MHz

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

Temperature (°C)

SNR (dB)

40–25 0 25 50 75

= 500kHz

= 12MHz

SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

Temperature (°C)

SINAD (dB)

50–25 0 25 50 75

= 500kHz

= 12MHz

SUPPLY CURRENT vs TEMPERATURE

Temperature (°C)

(mA)

70–25 0 25 50 75

ADS800

8SBAS035B

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TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

POWER DISSIPATION vs TEMPERATURE

Temperature (°C)

Power (mW)

425

400

375

350–25 0 25 50 75

GAIN ERROR vs TEMPERATURE

Temperature (°C)

Gain (%FSR)

0.75

0.25

–0.25

–0.75

–1.25–25 0 25 50 75

OFFSET ERROR vs TEMPERATURE

Ambient Temperature (°C)

Offset (%FSR)

–2.25

–2.5

–2.75–25 0 25 50 75

TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH

Frequency (Hz)

Track-Mode Input Response (dB)

10k

–1

–2

–3

–4

–5100k 1M 10M 100M 1G

OUTPUT NOISE HISTOGRAM (NO SIGNAL)

Counts

800k

600k

400k

200k

0.0

Code

N – 1N – 2 N N + 1 N + 2

ADS800 9

SBAS035B www.ti.com

THEORY OF OPERATION

The ADS800 is a high-speed, sampling A/D converter with

pipelining. It uses a fully differential architecture and digital

error correction to ensure 12-bit resolution. The differential

track-and-hold circuit is shown in Figure 1. The switches are

controlled by an internal clock which has a non-overlapping

2-phase signal, φ1 and φ2. At the sampling time, the input

signal is sampled on the bottom plates of the input capaci-

tors. In the next clock phase, φ2, the bottom plates of the

input capacitors are connected together and the feedback

capacitors are switched to the op amp output. At this time,

the charge redistributes between CI and CH, completing one

track-and-hold cycle. The differential output is a held DC

representation of the analog input at the sample time. The

track-and-hold circuit can also convert a single-ended input

signal into a fully differential signal for the quantizer.

The pipelined quantizer architecture has 11 stages with each

stage containing a 2-bit quantizer and a 2-bit Digital-to-

Analog Converter (DAC), as shown in Figure 2. Each 2-bit

quantizer stage converts on the edge of the sub-clock, which

is twice the frequency of the externally applied clock. The

output of each quantizer is fed into its own delay line to time-

FIGURE 2. Pipeline A/D Converter Architecture.

FIGURE 1. Input Track-and-Hold Configuration with Timing

Signals.

φ1

φ1φ2φ1

φ1φ1

φ1

φ2

φ1φ2φ1

φ2

OUT

Op Amp

Bias V

Op Amp

Bias V

Input Clock (50%)

Internal Non-Overlapping Clock

B1 (MSB)

B10

B11

B12 (LSB)

2-Bit

Flash

Input

T/H Digital Delay

2-Bit

DAC

2-Bit

DAC

2-Bit

DAC

2-Bit

Flash

Digital Delay

2-Bit

Flash Digital Delay

2-Bit

Flash

Digital Delay

Digital Error Correction

STAGE 1

STAGE 2

STAGE 10

STAGE 11

+–

ADS800

10 SBAS035B

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DIGITAL OUTPUT DATA

The 12-bit output data is provided at CMOS logic levels. The

standard output coding is Straight Offset Binary (SOB) where

a full-scale input signal corresponds to all “1’s” at the output,

as shown in Table 1. This condition is met with pin 19 “LO”

or Floating due to an internal pull-down resistor. By applying

a logic “HI” voltage to this pin, a Binary Two’s Complement

(BTC) output will be provided where the most significant bit

is inverted. The digital outputs of the ADS800 can be set to

a high-impedance state by driving

(pin 18) with a logic

“HI”. Normal operation is achieved with pin 18 “LO” or

Floating due to internal pull-down resistors. This function is

provided for testability purposes and is not meant to drive

digital buses directly or be dynamically changed during the

conversion process.

align it with the data created from the following quantizer

stages. This aligned data is fed into a digital error correction

circuit which can adjust the output data based on the infor-

mation found on the redundant bits. This technique gives the

ADS800 excellent differential linearity and ensures no miss-

ing codes at the 12-bit level.

Since there are two pipeline stages per external clock cycle,

there is a 6.5 clock cycle data latency from the start convert

signal to the valid output data. The output data is available in

Straight Offset Binary (SOB) or Binary Two’s Complement

(BTC) format.

THE ANALOG INPUT AND INTERNAL REFERENCE

The analog input of the ADS800 can be configured in various

ways and driven with different circuits, depending on the

nature of the signal and the level of performance desired.

The ADS800 has an internal reference that sets the full-scale

input range of the A/D converter. The differential input range

has each input centered around the common-mode of +2.25V,

with each of the two inputs having a full-scale range of

+1.25V to +3.25V. Since each input is 2Vp-p and 180° out-

of-phase with the other, a 4V differential input signal to the

quantizer results. As shown in Figure 3, the positive full-scale

reference (REFT) and the negative full-scale (REFB) are

brought out for external bypassing. In addition, the common-

mode voltage (CM) may be used as a reference to provide

the appropriate offset for the driving circuitry. However, care

must be taken not to appreciably load this reference node.

For more information regarding external references, single-

ended input, and ADS800 drive circuits, refer to the applica-

tions section.

•For most applications, the clock duty should be set to

50%. However, for applications requiring no missing codes,

a slight skew in the duty cycle will improve DNL perfor-

mance for conversion rates > 35MHz and input frequen-

cies < 2MHz (see Timing Diagram) in the SO package.

For the best performance in the SSOP package, the clock

should be skewed under all input frequencies with conver-

sion rates > 35MHz. A possible method for skewing the

50% duty cycle source is shown in Figure 4.

+1.25V

+3.25V

2kΩ

0.1µF

+2.25V

REFT

REFB

ADS800

Internal

Comparators

FIGURE 3. Internal Reference Structure.

CLOCK REQUIREMENTS

The CLK pin accepts a CMOS level clock input. Both the

rising and falling edges of the externally applied clock control

the various interstage conversions in the pipeline. Therefore,

the clock signal’s jitter, rise-and-fall times, and duty cycle can

affect conversion performance.

•Low clock jitter is critical to SNR performance in fre-

quency-domain signal environments.

•Clock rise-and-fall times should be as short as possible

(< 2ns for best performance).

0.1µF

2kΩ

0.1µF

CLK

OUT

CLK

IC2IC1

IC1, IC2 = ACT04

= 217Ω, typical

FIGURE 4. Clock Skew Circuit.

+FS (IN = +3.25V, IN = +1.25V) 111111111111 011111111111

+FS – 1LSB 111111111111 011111111111

+FS – 2LSB 111111111110 011111111110

+3/4 Full-Scale 111000000000 011000000000

+1/2 Full-Scale 110000000000 010000000000

+1/4 Full-Scale 101000000000 001000000000

+1LSB 100000000001 000000000001

Bipolar Zero (IN = IN = +2.25V) 100000000000 000000000000

–1LSB 011111111111 111111111111

–1/4 Full-Scale 011000000000 111000000000

–1/2 Full-Scale 010000000000 110000000000

–3/4 Full-Scale 001000000000 101000000000

–FS + 1LSB 000000000001 100000000001

–FS (IN = +1.25V, IN = +3.25V) 000000000000 100000000000

NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.

TABLE I. Coding Table for the ADS800.

OUTPUT CODE

SOB BTC

PIN 19 PIN 19

DIFFERENTIAL INPUT(1) FLOATING or LO HI

ADS800 11

SBAS035B www.ti.com

APPLICATIONS

DRIVING THE ADS800

The ADS800 has a differential input with a common-mode of

+2.25V. For AC-coupled applications, the simplest way to

create this differential input is to drive the primary winding of

a transformer with a single-ended input. A differential output

is created on the secondary if the center tap is tied to the

common-mode voltage of +2.25V, as per Figure 5. This

transformer-coupled input arrangement provides good high-

frequency AC performance. It is important to select a trans-

former that gives low distortion and does not exhibit core

saturation at full-scale voltage levels. Since the transformer

does not appreciably load the ladder, there is no need to

buffer the Common-Mode (CM) output in this instance. In

general, it is advisable to keep the current draw from the CM

output pin below 0.5µA to avoid nonlinearity in the internal

reference ladder. A FET input operational amplifier such as

the OPA130 can provide a buffered reference for driving

external circuitry. The analog IN and

inputs should be

bypassed with 22pF capacitors to minimize track-and-hold

glitches and to improve high input frequency performance.

Figure 6 illustrates another possible low-cost interface circuit

which utilizes resistors and capacitors in place of a trans-

former. Depending on the signal bandwidth, the component

values should be carefully selected in order to maintain the

FIGURE 6. AC-Coupled Differential Input Circuit.

product performance. The input capacitors, CIN, and the input

resistors, RIN, create a high-pass filter with the lower corner

frequency at fC = 1/(2pRINCIN). The corner frequency can be

reduced by either increasing the value of RIN or CIN. If the

circuit operates with a 50Ω or 75Ω impedance level, the

resistors are fixed and only the value of the capacitor can be

increased. Usually, AC-coupling capacitors are electrolytic or

tantalum capacitors with values of 1µF or higher. It should be

noted that these large capacitors become inductive with

increased input frequency, which could lead to signal ampli-

tude errors or oscillation. To maintain a low AC-coupling

impedance throughout the signal band, a small value (e.g.

1µF) ceramic capacitor could be added in parallel with the

polarized capacitor.

Capacitors CSH1 and CSH2 are used to minimize current

glitches resulting from the switching in the input track-and-

hold stage and to improve signal-to-noise performance. These

capacitors can also be used to establish a low-pass filter and

effectively reduce the noise bandwidth. In order to create a

real pole, resistors RSER1 and RSER2 were added in series

with each input. The cutoff frequency of the filter is deter-

mined by fC = 1/(2pRSER • (CSH + CADC)) where RSER is the

resistor in series with the input, CSH is the external capacitor

from the input to ground, and CADC is the internal input

capacitance of the A/D converter (typically 4pF).

Resistors R1 and R2 are used to derive the necessary

common-mode voltage from the buffered top and bottom

references. The total load of the resistor string should be

selected so that the current does not exceed 1mA. Although

the circuit in Figure 6 uses two resistors of equal value so

that the common-mode voltage is centered between the top

and bottom reference (+2.25V), it is not necessary to do so.

In all cases the center point, VCM, should be bypassed to

ground in order to provide a low-impedance AC ground.

If the signal needs to be DC coupled to the input of the

ADS800, an operational amplifier input circuit is required. In the

differential input mode, any single-ended signal must be modi-

fied to create a differential signal. This can be accomplished by

FIGURE 5. AC-Coupled Single-Ended to Differential Drive

Circuit Using a Transformer.

Mini-Circuits

TT1-6-KK81

or equivalent

ADS800

AC Input

Signal 22pF

22pF

0.1µF

ADS8xx

RSER1(1)

49.9Ω

1kΩ

(6kΩ)

0.1µF

CSH1

22pF

CSH2

22pF

0.1µF

CIN

0.1µF

VCM

CIN

0.1µF

RIN1

25Ω

RIN2

25Ω

RSER2(1)

49.9Ω

+3.25V

Top Reference

+1.25V

Bottom Reference

NOTE: (1) Indicates optional component.

ADS800

12 SBAS035B

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using two operational amplifiers, one in the noninverting mode

for the input and the other amplifier in the inverting mode for the

complementary input. The low distortion circuit in Figure 7 will

provide the necessary input shifting required for signals cen-

tered around ground. It also employs a diode for output level

shifting to ensure a low distortion +3.25V output swing. Other

amplifiers can be used in place of the OPA842s if the lowest

distortion is not necessary. If output level shifting circuits are

not used, care must be taken to select operational amplifiers

that give the necessary performance when swinging to +3.25V

with a ±5V supply operational amplifier.

The ADS800 can also be configured with a single-ended

input full-scale range of +0.25V to +4.25V by tying the

complementary input to the common-mode reference volt-

age, as shown in Figure 8. This configuration will result in

increased even-order harmonics, especially at higher input

frequencies. However, this tradeoff may be quite acceptable

for time-domain applications. The driving amplifier must give

adequate performance with a +0.25V to +4.25V output swing

in this case.

EXTERNAL REFERENCES AND ADJUSTMENT

OF FULL-SCALE RANGE

The internal reference buffers are limited to approximately

1mA of output current. As a result, these internal +1.25V and

+3.25V references may be overridden by external references

that have at least 18mA (at room temperature) of output drive

capability. In this instance, the common-mode voltage will be

FIGURE 8. Single-Ended Input Connection.

ADS800

0.1µF

Single-Ended

Input Signal

Full Scale = +0.25V to +4.25V with internal references.

22pF

FIGURE 7. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit.

604Ω

301Ω

604Ω

49.9Ω

301Ω

604Ω

2.49kΩ

2.49kΩ+2.25V

OPA842

OPA130

301Ω

0.1µF

OPA842

+5V

–5V

+5V(2)

+5V

–5V

+5V

–5V

BAS16(1)

301Ω

24.9ΩInput Level

Shift Buffer

Optional

High Impedance

Input Amplifier

DC-Coupled

Input Signal

26 IN

22 CM

27 IN

ADS800

NOTES: (1) A Philips BAS16 diode or equivalent

may be used. (2) Supply bypassing not shown.

22pF

604Ω

0.1µF

ADS800 13

SBAS035B www.ti.com

set halfway between the two references. This feature can be

used to adjust the gain error, improve gain drift, or to change

the full-scale input range of the ADS800. Changing the full-

scale range to a lower value has the benefit of easing the

swing requirements of external input drive amplifiers. The

external references can vary as long as the value of the

external top reference (REFTEXT) is less than or equal to

+3.4V, the value of the external bottom reference (REFBEXT)

is greater than or equal to +1.1V, and the difference between

the external references are greater than or equal to 1.5V.

For the differential configuration, the full-scale input

range will be set to the external reference values that are

selected. For the single-ended mode, the input range is

2 • (REFTEXT – REFBEXT), with the common-mode being

centered at (REFTEXT + REFBEXT)/2. Refer to the typical

characteristics for “Expected Performance vs Full-Scale In-

put Range”.

The circuit in Figure 10 works completely on a single +5V

supply. As a reference element, it uses the micro-power

reference REF1004-2.5, which is set to a quiescent current

of 0.1mA. Amplifier A2 is configured as a follower to buffer the

+1.25V generated from the resistor divider. To provide the

necessary current drive, a pull-down resistor, RP, is added.

Amplifier A1 is configured as an adjustable gain stage, with

a range of approximately 1 to 1.32. The pull-up resistor

again relieves the op amp from providing the full current

drive. The value of the pull-up/down resistors is not critical

and can be varied to optimize power consumption. The

need for pull-up, pull-down resistors depends only on the

drive capability of the selected drive amplifiers and thus can

be omitted.

FIGURE 9. ADS800 Interface Schematic with AC-Coupling and External Buffers.

GND

LSB

MSB

GND

CLK

MSBI

REFB

REFT

GND

ADS800

0.1µF

0.1µF0.1µF

0.1µF

0.1µF0.1µF

50Ω

Ext

Clk

AC Input

Signal

Dir

G+

19 Dir

G+

–541

Mini-Circuits

TT1-6-KK81

or equivalent

22pF

(1)

NOTE: (1) All capacitors should be located as close to the pins as the manufacturing

process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.

+5V

ADS800

14 SBAS035B

www.ti.com

PC BOARD LAYOUT AND BYPASSING

A well-designed, clean PC board layout will assure proper

operation and clean spectral response. Proper grounding

and bypassing, short lead lengths, and the use of ground

planes are particularly important for high-frequency circuits.

Multilayer PC boards are recommended for best perfor-

mance but if carefully designed, a two-sided PC board with

large, heavy ground planes can give excellent results. It is

recommended that the analog and digital ground pins of the

ADS800 be connected directly to the analog ground plane.

In our experience, this gives the most consistent results. The

A/D converter power-supply commons should be tied to-

gether at the analog ground plane. Power supplies should

be bypassed with 0.1µF ceramic capacitors as close to the

pin as possible.

DYNAMIC PERFORMANCE TESTING

The ADS800 is a high performance converter and careful

attention to test techniques is necessary to achieve accurate

results. Highly accurate phase-locked signal sources allow

high resolution FFT measurements to be made without using

data windowing functions. A low jitter signal generator such as

the HP8644A for the test signal, phase-locked with a low jitter

HP8022A pulse generator for the A/D converter clock, gives

excellent results. Low-pass filtering (or bandpass filtering) of

test signals is absolutely necessary to test the low distortion of

the ADS800. Using a signal amplitude slightly lower than full-

scale will allow a small amount of “headroom” so that noise or

DC offset voltage will not over-range the A/D converter and

cause clipping on signal peaks.

DYNAMIC PERFORMANCE DEFINITIONS

1. Signal-to-Noise-and-Distortion Ratio (SINAD):

10 15

log SinewaveSignalPower

Noise HarmonicPower first harmonics+

(

)

2. Signal-to-Noise Ratio (SNR):

10log SinewaveSignalPower

NoisePower

3. Intermodulation Distortion (IMD):

10 5

log PrHighestIMD oductPower to th order

SinewaveSignalPower −

(

)

IMD is referenced to the larger of the test signals, f1 or f2. Five

“bins” either side of peak are used for calculation of funda-

mental and harmonic power. The “0” frequency bin (DC) is

not included in these calculations as it is of little importance

in dynamic signal processing applications.

FIGURE 10. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.

2kΩ

+2.5V to +3.25V

+5V

220Ω

10kΩ

6.2kΩ

0.1µF+2.5V

10kΩ

1/2

OPA2234

1/2

OPA2234

Bottom

Reference

Top

Reference

REF1004

+1.25V

10kΩ

(1)

10kΩ

(1)

NOTE: (1) Use parts alternatively for adjustment capability.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

ADS800E OBSOLETE SSOP DB 28 TBD Call TI Call TI

ADS800E/1K OBSOLETE SSOP DB 28 TBD Call TI Call TI

ADS800U ACTIVE SOIC DW 28 20 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS800U/1K ACTIVE SOIC DW 28 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS800U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS800UG4 ACTIVE SOIC DW 28 20 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 31-Mar-2008

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS800U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Mar-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS800U/1K SOIC DW 28 1000 346.0 346.0 49.0

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Mar-2008

Pack Materials-Page 2

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