Make sure the next Card you purchase has... DD-42900 ARINC 429 MICROPROCESSOR INTERFACE DEVICE (R) FEATURES * Four ARINC 429 Receive Channels * Two ARINC 429 Transmit Channels * 128 x 32 Shared RAM Interface * Label and Destination Decoding and Sorting * Four 32 x 32 Receive FIFOs * Two 32 x 32 Transmit FIFO's * Interfaces Easily to 8- or 16-Bit Microprocessors * Built-in Fault Detection Circuitry * Free "C" Library Software DESCRIPTION DDC's DD-42900 provides a complete and flexible interface between a microprocessor and an ARINC 429 data bus. The DD-42900 interfaces to a processor through a 128 x 32 bit static ram as well as four 32 x 32 receive FIFO's and two 32 x 32 transmit FIFO's. The DD42900 can be easily interfaced to 8- or 16-bit processors via a buffered shared RAM configuration. * Available as a Chipset: - DD-00429VP ASIC P - DD-00429FP ASIC P The DD-42900 supports four ARINC 429 Receive channels (Rx0, Rx1, Rx2 and Rx3) each receiving data independently. The receive data rates (high or low speed) for channel Rx0 and Rx1 can be programmed independently from Rx2 and Rx3. The DD-42900 can decode and sort data based on the ARINC 429 Label and SDI bits via the Data Match Processor, and store it in RAM and/or FIFO's via the Data Store Processor. The DD-42900 supports two ARINC 429 Transmit channels (Tx0 and Tx1) and can transmit data independently. The transmit data rate can also be programmed independently. There are two 32 x 32 bit FIFO's for each of the transmitters that send out data. The DD-42900 has the capability of programming three general purpose interrupts as well as generating an interrupt based on an error condition. The general purpose interrupts can be programmed to trigger other external hardware. They can either be LEVEL or PULSE driven. The features built into the DD-42900 enable the user to off-load the host processor and use that processing time to implement operations other than polling the ARINC 429 Bus. The decoding and sorting of data allows the user to gather data much quicker than past designs. If the user requires a microprocessor in the avionics box, this device will facilitate a clean and quick design. FOR MORE INFORMATION CONTACT: Technical Support: 1-800-DDC-5757 ext. 7771 Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com All trademarks are the property of their respective owners. (c) 1998, 1999 Data Device Corporation Data Device Corporation www.ddc-web.com 2 DD-42900 H-12/06-0 2 2 WRAPAROUND WRAPAROUND WRAPAROUND WRAPAROUND ARINC 429 T x LOGIC ARINC 429 Tx LOGIC ARINC 429 Rx LOGIC ARINC 429 Rx LOGIC ARINC 429 Rx LOGIC ARINC 429 Rx LOGIC DD-03282 DEVICE (x2) ARINC 429 TRANSMIT 1 ARINC 429 TRANSMIT 0 ARINC 429 RECEIVE 3 ARINC 429 RECEIVE 2 ARINC 429 RECEIVE 1 ARINC 429 RECEIVE 0 DMP DATA ADDR DD-42900 IRQ 3 ADDR DATA DATA ADDR ADDR 12 ADDR 16 DATA DD-00429FP ASIC DATA CONTROL CPU INTERFACE DATA DATA STORE PROCESSOR MICROPROCESSOR OR CPU INTERRUPT CONTROLLER DATA DATA MATCH PROCESSOR CTRL DATA ADDR CTRL DATA ADDR FIGURE 1. DD-42900 BLOCK DIAGRAM Tx FIFO 32 WORDS Tx FIFO 32 WORDS Rx DATA 128 X 32 STATIC RAM Rx RAM 128 X 16 STATIC RAM DMT RAM Rx3 FIFO 32 WORDS Rx2 FIFO 32 WORDS Rx1 FIFO 32 WORDS Rx0 FIFO 32 WORDS TABLE 1. DD-42900 ABSOLUTE MAXIMUM RATINGS (TC = +25C UNLESS OTHERWISE SPECIFIED) PARAMETER MIN MAX UNITS DC Supply Voltage -0.3 6.0 Vdc Signal Input Voltage (logic inputs) -0.3 Vdd + 0.3 Vdc ARINC 429 Input Voltage -29 +29 Vdc Storage Temperature -85 125 C Operating Temperature -40 85 C Lead Temperature (soldering) 300 (for 10 sec) C Body Temperature (soldering) 210 (for 30 sec) C +29 Vdc Signal Input Voltage(ARINC 429 Inp) -29 TABLE 2. DD-42900 ELECTRICAL SPECIFICATIONS (4.5V VDD, 5.5V= -40C, TC = +85C UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage Vdd 4.5 5.5 Vdc DC Supply Current Idd 42.2 mA Schmitt "0" Threshold Vt- 0.2*Vdd Vdc RESET RC, 16 MHZ CLOCK Schmitt "1" Threshold Vt+ 0.8*Vdd Vdc RESET RC, 16 MHZ CLOCK Schmitt Hysteresis Vh 1 Vdc RESET RC, 16 MHZ CLOCK Input Logic Voltage Low Vil Input Logic Voltage High Vih 2.0 Input Logic Current Low Iil -25.3 Input Logic Current Low Iil Input Logic Current High Iih Output Voltage Logic Low Vol Output Voltage Logic High Voh 2.4 Output Leakage Current, Hi-Z Ioz -10 LOGIC INPUTS/OUTPUTS 0.8 Device operation @ 16 MHz, Typical Idd = 38.4 mA @ 5.0V. (@85C) Vdc All other Inputs. (See Note 1). Vdc All other Inputs. (See Note 1). -137 A Input pins with internal pull-up logic: INT/MOT, 8/16, ZERO WAIT MODE and MASTER RESET @ Vdd = 5.5V -1.0 1.0 A All other Inputs. (See Note 1). -1.0 1.0 A All other Inputs. (See Note 1). 0.4 Vdc Iol=3.84 mA minimum @Vdd= 4.5V. (See note 2) Vdc Ioh=3.84 mA minimum @Vdd= 4.5V. (See note 2) A For TXDB0-TXDB15, D0-D15, READY, DTACK, ERROR, IRQ3, IRQ2 and IRQ1 @ Vdd = 5.5V 10 NOTES: 1. TTL compatible input logic voltage levels at CMOS input logic current levels. 2. CMOS output logic voltage at current levels. Data Device Corporation www.ddc-web.com 3 DD-42900 H-12/06-0 TABLE 3. DD-42900 SPECIFICATIONS (TC = +25C UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL MIN MAX UNITS NOTES Logic 1 Input Voltage Vih 6.5 13.0 Vdc nominal +10 V, differential Vab Logic 0 Input Voltage Vil -6.5 -13.0 Vdc nominal -10 V, differential Vab Null Input Voltage Vnul -2.5 +2.5 Vdc nominal 0 V, differential Vab Common Mode Voltage Vcm 5 Vdc LOGIC INPUTS/OUTPUTS ARINC 429 LINE INPUTS Differential Input Impedance Ri 12 k Ohms Input Impedance to Vdd Rh 12 k Ohms Input Impedance to Ground Rg 12 k Ohms Input Capacitance Ci 20 pF Input Capacitance to Vcc Ch 20 pF Input Capacitance to Ground Cg 20 pF ARINC 429 RECEIVERS received ARINC 429 data and the criteria stored in a DMT entry is found, the received data, the storage address and modes, and interrupt parameters are passed to the Data Store Processor (DSP). The storage address in the Receive RAM is the address of the first matching DMT entry minus 200 hex. The DD-42900 supports four ARINC 429 inputs, designated Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The architecture of each of the four receiver circuits is identical and each receives data independently. ARINC 429 data is directly received into the DD-42900 with no additional circuitry required. Input protection, in accordance with the ARINC 429 specification, is provided along with voltage level translation from +5 V bipolar, nonreturn-to-zero data to conventional, +5 V logic levels. There are three requirements that must be met in order to match incoming ARINC 429 data to each DMT entry: 1) System Address Label: Bits 0-7 of the DMT are compared to the System Address Label (SAL) of the incoming ARINC 429 data word. If the DMT SAL entry is zero then the SAL of the incoming data word is ignored (or considered a match). Receive Data Rates: Data rates can be programmed for channels 0 and 1 independently of channels 2 and 3 via bits 2 and 3 of Arinc Control Register 2. The receiver circuitry will successfully decode an incoming ARINC 429 data stream as long as the data rate is within 5% of the nominal rate as determined by the Hi Speed/Low Speed Bit and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock inputs may be tied to the 1 MHz clock output or may be connected to another clock source. The ARINC CLK input should nominally be 10 times (for High-Speed Mode) or 80 times (for Low-Speed Mode) the desired ARINC Data Rate. ARINC CLK 0 is used to synchronize channels Rx0 and Rx1 while ARINC CLK 1 is used to synchronize channels Rx2 and Rx3. 2) Source/Destination Bits: Bits 8 and 9 of each DMT entry are compared to the Source/Destination (S/D) bits of the incoming ARINC 429 data word. If these bits match, or if Bit 10 of the DMT entry is set to a 1, then the S/D bit comparison is considered a match. It is also possible, through the DMP Control Register 1, to enable "All Call Mode" as defined in the ARINC 429 specification. When enabled for a particular receive channel, the S/D bits will be considered a match when the incoming ARINC 429 data contains a 00 in its S/D bit pair. Filtering and Sorting Rx Data: The receiver circuitry converts the serial data stream to a 32-bit-wide parallel data word. The 32bit word is processed internally by a Data Match Processor (DMP). It compares the incoming data to a table of data initialized by the processor. This determines what incoming data is to be saved, where it is going to be saved, and if any interrupts are to be generated. The table of data is stored in a 128 word x 16 bit Data Match Table (DMT) RAM. When a match between the Data Device Corporation www.ddc-web.com 3) Receive Channel Number: Bits 12 and 13 of each DMT entry are compared to the number of the channel which received the ARINC 429 data. A Data Match has occurred when all of the previous conditions are satisfied; the data will then be stored in a RAM location whose address equals the matching DMT entry minus 200 hex. 4 DD-42900 H-12/06-0 INTERRUPT OPERATIONAL MODES Bit 11 of each DMT entry, when set, will cause the incoming ARINC 429 data to be stored in the corresponding receive channel FIFO (as well as the Rx RAM) when the data match conditions are met. The DD-42900 provides four interrupt outputs. Three of these interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose programmable interrupts. The fourth interrupt is an Error interrupt output which is specifically used to provide indications of various error conditions and is nonmaskable. Bits 14 and 15 of each DMT entry provide the ability to cause one of three general purpose interrupts upon a data match condition. If set to "00" then no interrupt will occur upon a data match condition (more information on interrupts is described later). ERROR INTERRUPT OPERATION When an error condition occurs, the ERROR output pin goes low to indicate the presence of an error. The error pin will go high again when the Error Status Register is clear. Each of these bits is cleared by either reading the Error Status Register or removing the error condition. ARINC 429 TRANSMITTER(S) The DD-42900 supports two ARINC 429 transmitters. Each of these channels transmits data independently and are designated Tx0 and Tx1. The transmit output of the DD-42900 is a TTL encoded digital data stream which can be connected directly to the ARINC 429 line driver. GENERAL PURPOSE INTERRUPTS The three general purpose interrupt outputs can be used for multilevel interrupts or to trigger other external hardware for various conditions. Each condition can be mapped to any one of the three general purpose interrupts or disabled (by mapping to IRQ0 which does not exist). Each interrupt output can be programmed to be either a LEVEL interrupt or PULSE interrupt via IRQ Control Register 2. When programmed for pulse interrupt mode, the associated interrupt pin will go low for 1 S and return high again. When programmed for LEVEL interrupt mode, the interrupt will remain until the associated IRQ Status Register is read, thus clearing the associated bits in each interrupt register. Transmit Data Rates: Data rates can be programmed for channels 0 and 1 independently. The transmit data rate is determined by the High-Speed/Low-Speed Bit for each of the Tx channels in ARINC Control Register 1 and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two, 1 MHz ARINC clock inputs may be tied to the 1 MHz clock output or may be connected to another clock source to achieve transmit data rates other than 100 kHz or 12.5 kHz. The transmit clock input should be 10 times (for High-Speed Mode) or 80 times (for Low-Speed Mode) the desired ARINC transmit data rate. Each of the individual interrupt registers can be masked by setting their corresponding bit in IRQ Control Register 1. It should be noted that the masking function only prevents the associated IRQ pin from becoming active. When the mask bit is cleared, an interrupt can occur in LEVEL IRQ mode if one or more interrupt conditions occurred during the time when the mask was set. If the user needs to ensure the interrupt will not occur upon clearing the mask bit, the CPU should be programmed to read the associated interrupt status register immediately prior to clearing the IRQ mask bit. Transmit FIFOs: Each transmitter channel is provided with an output FIFO which is 32 words deep by 32 bits wide. When writing data to the Tx FIFO, the associated Disable Tx(n) bit in ARINC Control Register 2 can be set to a logic zero until the FIFO is loaded with the desired data. Upon setting the Disable Tx(n) low the transmit channel will send the 32-bit message words with appropriate interword gaps on the ARINC 429 output. A status bit indicating that the FIFO is empty is supplied for each transmitter in the ARINC Status Register. ZERO WAIT MODE OPERATION When Zero Wait Mode is enabled by not grounding the ZERO WAIT pin, the host microprocessor may read data from the DD42900 shared memory resources (DMT and Rx RAM) without using the READY or DTACK signals to insert wait states into the microprocessor cycle. This is accomplished by an additional "dummy read" of the desired address. This dummy read causes the DD-42900 to fetch the data from the source and place it in a latch. The data can then be read from the latch (word-by-word or byte-by-byte) by reading the same addresses. Thus for a 32-bit read in 8-bit mode, the microprocessor would perform a total of five read operations. The first read would be the dummy read; subsequent reads would transfer the data. Wraparound testing can be performed from Tx0 to Rx0 and Rx1, and from Tx1 to Rx2 and Rx3. Wraparound testing is enabled by setting the appropriate bits in ARINC Control Register 1. The parity of the transmitted word can be altered to even parity (instead of the usual odd parity) by setting the associated Txn Parity bit in the ARINC Control Register 1. This is useful to verify proper operation of the parity check circuitry for each of the receive circuits during wraparound test mode. PROCESSOR INTERFACE The processor interface allows for the use of either an 8- or 16bit data bus. Intel or Motorola control signal formats can also be used. Data Device Corporation www.ddc-web.com 5 DD-42900 H-12/06-0 0.004 1.102 (27.99 0.1 ) 39 EQ. SP. @ 0.0256 = 0.998 (0.65 = 25.36) (TOL. NONCUM) 1 PIN NO. 1 INDEX PIN NUMBERS FOR REF. ONLY 121 160 SEE DETAIL "A" 120 1 +0.008 0.146 -0.000 (3.71) 0.133 (3.38) (REF) 39 EQ. SP. @ 0.004 1.102 0.0256 = 0.998 (27.99 0.1 ) (0.65 = 25.36) (TOL. NONCUM) 1 +0.000 0.013 -0.003 (0.33) 0.077(1.96) (TYP) 0.01 0.0256 (.65) (TYP) 1.256 (31.9) (TYP) 0.003 0.012 (0.3 0.08 ) (TYP) 40 81 41 DETAIL "A" NTS 80 0.016 (0.41) (MIN) (TYP) 0.007 0.002 (0.18) (TYP) Notes: 1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN 0.010 (0.25). 2. DIMENSIONS IN INCHES (MILLIMETERS). 0.031(.79) (TYP) FIGURE 2. DD-00429FP ASIC MECHANICAL OUTLINE (PLASTIC) TABLE 4. DD-42900 PINOUTS (DIP AND FLAT PACK) PIN NO. FUNCTION PIN NO. FUNCTION PIN NO. FUNCTION PIN NO. FUNCTION 1 GND 17 A8 33 D0 49 IRQ3 2 GND 18 A9 34 D1 50 IRQ2 3 INTEL/MOTO 19 A10 35 D2 51 IRQ1 4 8/16 BIT 20 CS0 36 D3 52 1 MHZ OUT 5 TX0 A 21 CS1 37 D4 53 ARINC CLK 1 6 TX0 B 22 CS2 38 D5 54 ARINC CLK 0 7 TX1 A 23 GND 39 D6 55 +5V 8 TX1 B 24 GND 40 D7 56 +5V 9 A0 25 ZERO WAIT MODE 41 D8 57 RX3 B 10 A1 26 READY 42 D9 58 RX3 A 11 A2 27 RD (DS) 43 D10 59 RX2 B 12 A3 28 WR (RD/WR) 44 D11 60 RX2 A 13 A4 29 DTACK 45 D12 61 RX1 B 14 A5 30 ERROR 46 D13 62 RX1 A 15 A6 31 MASTER RESET 47 D14 63 RX0 B 16 A7 32 16 MHZ CLOCK 48 D15 64 RX0 A Data Device Corporation www.ddc-web.com 6 DD-42900 H-12/06-0 1.800 0.550 .010 PIN NUMBERS FOR REF ONLY .010 7 EQ. SP. @ 0.100=0.700 (TOL NON CUM) 1 64 COMPONENT ENVELOPE 0.100 57 0.200(MAX) 0.040 .010 2.000 (TYP) 56 .010 SEE DETAIL "A" 2.400 .010 0.020 (TYP) Component Side DETAIL "A" NTS .003 23 EQ. SP. @ 0.100 = 2.300 (TOL NON CUM) 1 0.070 (TYP) 32 0.34 (MIN) 0.080 (TYP) 0.100 (TYP) 24 25 0.020 R MAX (TYP) 0.015 (TYP) 0.010 .002 (TYP) 0.100 (REF) 33 FIGURE 3A. DD-42900DP DIP MECHANICAL ASSEMBLY 1.800 .010 PIN NUMBERS FOR REF ONLY 7 EQ. SP. @ 0.100=0.700 (TOL NON CUM) 0.550 1 2.400 .010 0.200 (MAX) 0.185 64 57 .010 SEE DETAIL "A" DETAIL "A" NTS .003 0.020 (TYP) 23 EQ. SP. @ 0.100 = 2.300 (TOL NON CUM) 0.080 (TYP) 0.040 (TYP) 0.015 (TYP) 0.020 R MAX (TYP) 0.010 .002 (TYP) 0.075 (TYP) 0.100 (TYP) 32 0.040 2.170 (TYP) 1 24 25 .010 56 Component Side .010 COMPONENT ENVELOPE 0.065 (TYP) 0.185 (REF) 33 NOTES: 1 LEAD CLUSTER TO BE CENTRALIZED ABOUT PWB CENTERLINE WITHIN .010 FIGURE 3B. DD-42900FP FLAT PACK MECHANICAL ASSEMBLY Data Device Corporation www.ddc-web.com 7 DD-42900 H-12/06-0 TABLE 5. DD-00429FP ASIC PINOUTS PIN NO. DESCRIPTION PIN NO. DESCRIPTION PIN NO. DESCRIPTION PIN NO. DESCRIPTION 1 +5V 41 +5V 81 +5V 121 +5V 2 TX DB11 42 XTAL1 (N/C) 82 OSC CLK OUT (N/C) 122 RESET 1 3 TX DB12 43 GND 83 BIST T1A (N/C) 123 CW STRB1 4 TX DB13 44 TSB2 (N/C) 84 BIST T1B (N/C) 124 EN TX1 OUT 5 TX DB14 45 TSB3 (N/C) 85 BIST DMT (N/C) 125 TX1 B IN 6 TX DB15 46 TSA0 (N/C) 86 BIST RAM7 (N/C) 126 TX1 A IN 7 EN RX1 47 TSA1 (N/C) 87 BIST RAM24 (N/C) 127 TX1 EMPTY 8 EN RX0 48 TSA2 (N/C) 88 D0 128 LD TX1 HI 9 SELECT 49 TSA3 (N/C) 89 D1 129 LD TX1 LO 10 RX RDY1 50 TMA0 (N/C) 90 D2 130 +5V 11 RX RDY0 51 TMA1 (N/C) 91 D3 131 GND 12 GND 52 TMA2 (N/C) 92 D4 132 +5V 13 GND 53 TMA3 (N/C) 93 D5 133 16 MHZ CLOCK 14 GND 54 TMA4 (N/C) 94 D6 134 EN RX3 15 INTEL/MOTO 55 TMA5 (N/C) 95 D7 135 EN RX2 16 8/16 BIT 56 TMA6 (N/C) 96 GND 136 RX RDY 3 17 +5V 57 TMA7 (N/C) 97 +5V 137 RX RDY 2 18 TX0 A 58 TSB0 (N/C) 98 GND 138 +5V 19 TX0 B 59 TSB1 (N/C) 99 +5V 139 GND 20 TX1 A 60 +5V 100 D8 140 RESET 0 21 TX1 B 61 GND 101 D9 141 CW STRB0 22 GND 62 TMB0 (N/C) 102 D10 142 EN TX0 OUT 23 A0 63 TMB1 (N/C) 103 D11 143 TX0B IN 24 A1 64 TMB2 (N/C) 104 D12 144 TX0A IN 25 A2 65 TMB3 (N/C) 105 D13 145 TX0 EMPTY 26 A3 66 TMB4 (N/C) 106 D14 146 LOAD TX0 HI 27 A4 67 TMB5 (N/C) 107 D15 147 LD TX0 LO 28 A5 68 TMB6 (N/C) 108 GND 148 GND 29 A6 69 TMB7 (N/C) 109 GND 149 TX DB0 30 A7 70 ZERO WAIT MODE 110 IRQ3 150 TX DB1 31 A8 71 READY 111 IRQ2 151 TX DB2 32 A9 72 RD or DS 112 IRQ1 152 TX DB3 33 A10 73 WR or RD/WR 113 RESET RC 153 TX DB4 34 CS0 74 DTACK 114 ARINC CLK OUT 154 TX DB5 35 CS1 75 ERROR 115 ARINC CLK 1 155 TX DB6 36 CS2 76 MASTER RESET 116 ARINC CLK 0 156 TX DB7 37 BIST R3 (N/C) 77 +5V 117 BIST R0 (N/C) 157 TX DB8 38 GND 78 BIST TOA (N/C) 118 BIST R1 (N/C) 158 TX DB9 39 +5V 79 BIST TOB (N/C) 119 BIST R2 (N/C) 159 TX DB10 40 GND 80 GND 120 GND 160 GND Data Device Corporation www.ddc-web.com 8 DD-42900 H-12/06-0 ORDERING INFORMATION Chip Set: Full Assembly: *DD-00429XP - X00 Temperature Range: 2 = -40C to +85C DD-4290XXP - 200 Burn-in: 0 = No Burn-in ASIC Package Type: P = Plastic Temperature Range: 2 = -40C to +85C Lead Type: F = 160-Pin Quad Flat Pack V = 144-Pin TQFP ASIC Package Type: P = Plastic Lead Type: D = Dip F = Flat Pack *Note: The DD-03182 and DD-03282 are required to complete the ARINC 429 Interface. The DD-00429 is the Microprocessor Interface/RAM/FIFO and Interrupt Controller. Coating: 0 = Conformally Coated With Urethane 1 = Not Conformally Coated Application Note AN/A-6 DD-42900 Frequently Asked Questions is available on request. These products contain tin-lead solder. Note: These Transceiver/Line Driver part numbers are provided for historical reference only. These components are now provided by Device Engineering Inc. For a complete cross-reference chart, please visit DEI at www.deiaz.com,(480) 303-0822. STANDARD DDC PROCESSING FOR PLASTIC MONOLITHIC PRODUCTS MIL-STD-883 TEST INSPECTION / WORKMANSHIP ELECTRICAL TEST Data Device Corporation www.ddc-web.com METHOD(S) 2017, and 2032 DDC ATP 9 CONDITION(S) -- -- DD-42900 H-12/06-0 NOTES: Data Device Corporation www.ddc-web.com 10 DD-42900 H-12/06-0 NOTES: Data Device Corporation www.ddc-web.com 11 DD-42900 H-12/06-0 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our web site at www.ddc-web.com for the latest information. 105 Wilbur Place, Bohemia, New York 11716-2426 For Technical Support - 1-800-DDC-5757 ext. 7771 Headquarters - Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com U (R) H-12/06-0 12 PRINTED IN THE U.S.A.