FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
FEATURES
•Four ARINC 429 Receive
Channels
•Two ARINC 429 Transmit Channels
•128 x 32 Shared RAM Interface
•Label and Destination Decoding
and Sorting
•Four 32 x 32 Receive FIFOs
•Two 32 x 32 Transmit FIFO's
•Interfaces Easily to 8- or 16-Bit
Microprocessors
•Built-in Fault Detection Circuitry
•Free “C” Library Software
•Available as a Chipset:
- DD-00429VP ASIC µP
- DD-00429FP ASIC µP
DESCRIPTION
DDC's DD-42900 provides a complete and flexible interface between
a microprocessor and an ARINC 429 data bus. The DD-42900 inter-
faces to a processor through a 128 x 32 bit static ram as well as four
32 x 32 receive FIFO's and two 32 x 32 transmit FIFO's. The DD-
42900 can be easily interfaced to 8- or 16-bit processors via a
buffered shared RAM configuration.
The DD-42900 supports four ARINC 429 Receive channels (Rx0, Rx1,
Rx2 and Rx3) each receiving data independently. The receive data rates
(high or low speed) for channel Rx0 and Rx1 can be programmed inde-
pendently from Rx2 and Rx3. The DD-42900 can decode and sort data
based on the ARINC 429 Label and SDI bits via the Data Match Processor,
and store it in RAM and/or FIFO's via the Data Store Processor.
The DD-42900 supports two ARINC 429 Transmit channels (Tx0 and
Tx1) and can transmit data independently. The transmit data rate can
also be programmed independently. There are two 32 x 32 bit FIFO's
for each of the transmitters that send out data.
The DD-42900 has the capability of programming three general purpose
interrupts as well as generating an interrupt based on an error condition.
The general purpose interrupts can be programmed to trigger other
external hardware. They can either be LEVEL or PULSE driven.
The features built into the DD-42900 enable the user to off-load the
host processor and use that processing time to implement operations
other than polling the ARINC 429 Bus. The decoding and sorting of
data allows the user to gather data much quicker than past designs.
If the user requires a microprocessor in the avionics box, this device
will facilitate a clean and quick design.
© 1998, 1999 Data Device Corporation
DD-42900
ARINC 429 MICROPROCESSOR
INTERFACE DEVICE
All trademarks are the property of their respective owners.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
®
Make sure the next
Card you purchase
has...
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DD-42900
H-12/06-0
FIGURE 1. DD-42900 BLOCK DIAGRAM
ARINC 429
Rx LOGIC
ARINC 429
Rx LOGIC
ARINC 429
Rx LOGIC
ARINC 429
Rx LOGIC
ARINC 429
Tx LOGIC
ARINC 429
T x LOGIC
Tx FIFO
32 WORDS
Tx FIFO
32 WORDS
Rx0 FIFO
32 WORDS
Rx1 FIFO
32 WORDS
Rx2 FIFO
32 WORDS
Rx3 FIFO
32 WORDS
ARINC 429
RECEIVE 0
ARINC 429
RECEIVE 1
ARINC 429
RECEIVE 2
ARINC 429
RECEIVE 3
ARINC 429
TRANSMIT 0
ARINC 429
TRANSMIT 1
2
2
WRAPAROUND
Rx DATA DATA
MATCH
PROCESSOR
DATA
ADDR
CTRL DATA ADDR
128 X 16
STATIC RAM
DMT RAM
CTRL DATA ADDR
128 X 32
STATIC RAM
Rx RAM
DATA
STORE
PROCESSOR
DATA ADDR
DMP
DATA
ADDR
ADDR
DATA
DATA
INTERRUPT
CONTROLLER
316 12
IRQ DATA ADDR CONTROL
MICROPROCESSOR
OR CPU
CPU INTERFACE
DATA
DD-00429FP ASIC
DD-03282 DEVICE (x2)
DD-42900
WRAPAROUND
WRAPAROUND
WRAPAROUND
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DD-42900
H-12/06-0
LOGIC INPUTS/OUTPUTS
NOTESUNITSMAXMINSYMBOL
TABLE 1. DD-42900 ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER MIN MAX UNITS
DC Supply Voltage -0.3 6.0 Vdc
Signal Input Voltage (logic inputs) -0.3 Vdd + 0.3 Vdc
ARINC 429 Input Voltage -29 +29 Vdc
Storage Temperature -85 125 °C
Operating Temperature -40 85 °C
Lead Temperature (soldering) 300 (for 10 sec) °C
Body Temperature (soldering) 210 (for 30 sec) °C
Signal Input Voltage(ARINC 429 Inp) -29 +29 Vdc
Iil
Schmitt “0” Threshold Vt- Vdc0.2*Vdd
All other Inputs. (See Note 1).µA1.0-1.0Input Logic Current Low
Vdd
Input Logic Current Low
Idd
Input pins with internal pull-up logic: INT/MOT,
8/16, ZERO WAIT MODE and MASTER
RESET @ Vdd = 5.5V
µA-137-25.3
Schmitt “1” Threshold
Vdc
Vt+
Iil
Vdc
0.8*Vdd
DC Supply Current Device operation @ 16 MHz,
Typical Idd = 38.4 mA @ 5.0V. (@85°C)
mA42.2
5.54.5DC Supply Voltage
RESET RC, 16 MHZ CLOCK
RESET RC, 16 MHZ CLOCK
Vil All other Inputs. (See Note 1).Vdc0.8Input Logic Voltage Low
Schmitt Hysteresis RESET RC, 16 MHZ CLOCK
Vdc
1
Vh
Input Logic Voltage High All other Inputs. (See Note 1).Vdc2.0Vih
Iih All other Inputs. (See Note 1).µA1.0-1.0Input Logic Current High
Vol Iol=3.84 mA minimum @Vdd= 4.5V.
(See note 2)
Vdc0.4Output Voltage Logic Low
Voh Ioh=3.84 mA minimum @Vdd= 4.5V.
(See note 2)
Vdc2.4Output Voltage Logic High
Ioz For TXDB0-TXDB15, D0-D15, READY, DTACK,
ERROR, IRQ3, IRQ2 and IRQ1 @ Vdd = 5.5V
µA10-10Output Leakage Current, Hi-Z
NOTES:
1. TTL compatible input logic voltage levels at CMOS input logic current levels.
2. CMOS output logic voltage at current levels.
PARAMETER
TABLE 2. DD-42900 ELECTRICAL SPECIFICATIONS
(4.5V VDD, 5.5V= -40°C, TC = +85°C UNLESS OTHERWISE SPECIFIED)
4
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DD-42900
H-12/06-0
LOGIC INPUTS/OUTPUTS
NOTESUNITSMAXMINSYMBOLPARAMETER
TABLE 3. DD-42900 SPECIFICATIONS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
ARINC 429 LINE INPUTS
Logic 0 Input Voltage -6.5 -13.0 Vdc nominal -10 V, differential VabVil
Null Input Voltage -2.5 +2.5 Vdc nominal 0 V, differential VabVnul
Common Mode Voltage 5 VdcVcm
Input Impedance to Vdd 12 k OhmsRh
Differential Input Impedance 12 k OhmsRi
Input Impedance to Ground 12 k OhmsRg
Input Capacitance 20 pFCi
Input Capacitance to Vcc 20 pFCh
Input Capacitance to Ground 20 pFCg
Logic 1 Input Voltage 6.5 13.0 Vdc nominal +10 V, differential VabVih
ARINC 429 RECEIVERS
The DD-42900 supports four ARINC 429 inputs, designated
Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The
architecture of each of the four receiver circuits is identical and
each receives data independently. ARINC 429 data is directly
received into the DD-42900 with no additional circuitry required.
Input protection, in accordance with the ARINC 429 specifica-
tion, is provided along with voltage level translation from +5 V
bipolar, nonreturn-to-zero data to conventional, +5 V logic levels.
Receive Data Rates: Data rates can be programmed for chan-
nels 0 and 1 independently of channels 2 and 3 via bits 2 and 3
of Arinc Control Register 2. The receiver circuitry will success-
fully decode an incoming ARINC 429 data stream as long as the
data rate is within ±5% of the nominal rate as determined by the
Hi Speed/Low Speed Bit and the associated ARINC Clock input
(ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock
inputs may be tied to the 1 MHz clock output or may be con-
nected to another clock source. The ARINC CLK input should
nominally be 10 times (for High-Speed Mode) or 80 times (for
Low-Speed Mode) the desired ARINC Data Rate. ARINC CLK 0
is used to synchronize channels Rx0 and Rx1 while ARINC CLK
1 is used to synchronize channels Rx2 and Rx3.
Filtering and Sorting Rx Data: The receiver circuitry converts
the serial data stream to a 32-bit-wide parallel data word. The 32-
bit word is processed internally by a Data Match Processor
(DMP). It compares the incoming data to a table of data initial-
ized by the processor. This determines what incoming data is to
be saved, where it is going to be saved, and if any interrupts are
to be generated. The table of data is stored in a 128 word x 16
bit Data Match Table (DMT) RAM. When a match between the
received ARINC 429 data and the criteria stored in a DMT entry
is found, the received data, the storage address and modes, and
interrupt parameters are passed to the Data Store Processor
(DSP). The storage address in the Receive RAM is the address
of the first matching DMT entry minus 200 hex.
There are three requirements that must be met in order to match
incoming ARINC 429 data to each DMT entry:
1) System Address Label: Bits 0-7 of the DMT are com-
pared to the System Address Label (SAL) of the incoming
ARINC 429 data word. If the DMT SAL entry is zero then
the SAL of the incoming data word is ignored (or consid-
ered a match).
2) Source/Destination Bits: Bits 8 and 9 of each DMT entry
are compared to the Source/Destination (S/D) bits of the
incoming ARINC 429 data word. If these bits match, or if Bit
10 of the DMT entry is set to a 1, then the S/D bit compar-
ison is considered a match. It is also possible, through the
DMP Control Register 1, to enable “All Call Mode” as
defined in the ARINC 429 specification. When enabled for
a particular receive channel, the S/D bits will be considered
a match when the incoming ARINC 429 data contains a 00
in its S/D bit pair.
3) Receive Channel Number: Bits 12 and 13 of each DMT
entry are compared to the number of the channel which
received the ARINC 429 data.
A Data Match has occurred when all of the previous conditions
are satisfied; the data will then be stored in a RAM location
whose address equals the matching DMT entry minus 200 hex.
5
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DD-42900
H-12/06-0
Bit 11 of each DMT entry, when set, will cause the incoming
ARINC 429 data to be stored in the corresponding receive chan-
nel FIFO (as well as the Rx RAM) when the data match condi-
tions are met.
Bits 14 and 15 of each DMT entry provide the ability to cause
one of three general purpose interrupts upon a data match con-
dition. If set to “00” then no interrupt will occur upon a data match
condition (more information on interrupts is described later).
ARINC 429 TRANSMITTER(S)
The DD-42900 supports two ARINC 429 transmitters. Each of
these channels transmits data independently and are designat-
ed Tx0 and Tx1. The transmit output of the DD-42900 is a TTL
encoded digital data stream which can be connected directly to
the ARINC 429 line driver.
Transmit Data Rates: Data rates can be programmed for chan-
nels 0 and 1 independently. The transmit data rate is determined
by the High-Speed/Low-Speed Bit for each of the Tx channels in
ARINC Control Register 1 and the associated ARINC Clock input
(ARINC CLK 0 or ARINC CLK 1). The two, 1 MHz ARINC clock
inputs may be tied to the 1 MHz clock output or may be con-
nected to another clock source to achieve transmit data rates
other than 100 kHz or 12.5 kHz. The transmit clock input should
be 10 times (for High-Speed Mode) or 80 times (for Low-Speed
Mode) the desired ARINC transmit data rate.
Transmit FIFOs: Each transmitter channel is provided with an
output FIFO which is 32 words deep by 32 bits wide. When writ-
ing data to the Tx FIFO, the associated Disable Tx(n) bit in
ARINC Control Register 2 can be set to a logic zero until the
FIFO is loaded with the desired data. Upon setting the Disable
Tx(n) low the transmit channel will send the 32-bit message
words with appropriate interword gaps on the ARINC 429 output.
A status bit indicating that the FIFO is empty is supplied for each
transmitter in the ARINC Status Register.
Wraparound testing can be performed from Tx0 to Rx0 and Rx1,
and from Tx1 to Rx2 and Rx3. Wraparound testing is enabled by
setting the appropriate bits in ARINC Control Register 1. The
parity of the transmitted word can be altered to even parity
(instead of the usual odd parity) by setting the associated Txn
Parity bit in the ARINC Control Register 1. This is useful to veri-
fy proper operation of the parity check circuitry for each of the
receive circuits during wraparound test mode.
PROCESSOR INTERFACE
The processor interface allows for the use of either an 8- or 16-
bit data bus. Intel or Motorola control signal formats can also be
used.
INTERRUPT OPERATIONAL MODES
The DD-42900 provides four interrupt outputs. Three of these
interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose
programmable interrupts. The fourth interrupt is an Error interrupt
output which is specifically used to provide indications of various
error conditions and is nonmaskable.
ERROR INTERRUPT OPERATION
When an error condition occurs, the ERROR output pin goes low
to indicate the presence of an error. The error pin will go high
again when the Error Status Register is clear. Each of these bits
is cleared by either reading the Error Status Register or remov-
ing the error condition.
GENERAL PURPOSE INTERRUPTS
The three general purpose interrupt outputs can be used for mul-
tilevel interrupts or to trigger other external hardware for various
conditions. Each condition can be mapped to any one of the
three general purpose interrupts or disabled (by mapping to
IRQ0 which does not exist). Each interrupt output can be pro-
grammed to be either a LEVEL interrupt or PULSE interrupt via
IRQ Control Register 2. When programmed for pulse interrupt
mode, the associated interrupt pin will go low for 1 µS and return
high again. When programmed for LEVEL interrupt mode, the
interrupt will remain until the associated IRQ Status Register is
read, thus clearing the associated bits in each interrupt register.
Each of the individual interrupt registers can be masked by set-
ting their corresponding bit in IRQ Control Register 1. It should
be noted that the masking function only prevents the associated
IRQ pin from becoming active. When the mask bit is cleared, an
interrupt can occur in LEVEL IRQ mode if one or more interrupt
conditions occurred during the time when the mask was set. If
the user needs to ensure the interrupt will not occur upon clear-
ing the mask bit, the CPU should be programmed to read the
associated interrupt status register immediately prior to clearing
the IRQ mask bit.
ZERO WAIT MODE OPERATION
When Zero Wait Mode is enabled by not grounding the ZERO
WAIT pin, the host microprocessor may read data from the DD-
42900 shared memory resources (DMT and Rx RAM) without
using the READY or DTACK signals to insert wait states into the
microprocessor cycle. This is accomplished by an additional
“dummy read” of the desired address. This dummy read causes
the DD-42900 to fetch the data from the source and place it in a
latch. The data can then be read from the latch (word-by-word or
byte-by-byte) by reading the same addresses. Thus for a 32-bit
read in 8-bit mode, the microprocessor would perform a total of
five read operations. The first read would be the dummy read;
subsequent reads would transfer the data.
CS0
6
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DD-42900
H-12/06-0
39 EQ. SP. @
0.0256 = 0.998
(0.65 = 25.36)
(TOL. NONCUM)
1
39 EQ. SP. @
0.0256 = 0.998
(0.65 = 25.36)
(TOL. NONCUM)
1
PIN NO. 1
INDEX
1
160
120
121
81
80
41
40
PIN NUMBERS
FOR REF. ONLY
0.0256
(.65)
(TYP)
0.133 (3.38)
(REF)
0.077(1.96)
(TYP)
1.256 ±0.01
(31.9) (TYP)
SEE DETAIL "A"
DETAIL "A"
NTS
0.016 (0.41)
(MIN) (TYP)
0.031(.79)
(TYP)
0.007 ±0.002
(0.18) (TYP)
0.146 +0.008
(3.71) -0.000
0.013 +0.000
(0.33) -0.003
0.012 ±0.003
(0.3 ±0.08 )
(TYP)
1.102 ±0.004
(27.99 ±0.1 )
1.102 ±0.004
(27.99 ±0.1 )
Notes:
1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN ±0.010 (±0.25).
2. DIMENSIONS IN INCHES (MILLIMETERS).
FIGURE 2. DD-00429FP ASIC MECHANICAL OUTLINE (PLASTIC)
TABLE 4. DD-42900 PINOUTS (DIP AND FLAT PACK)
PIN NO.
1
FUNCTION
GND
PIN NO.
17
FUNCTION
A8
PIN NO.
33
FUNCTION
D0
PIN NO.
49
FUNCTION
IRQ3
2GND 18 A9 34 D1 50 IRQ2
3INTEL/MOTO 19 A10 35 D2 51 IRQ1
48/16 BIT 20 36 D3 52 1 MHZ OUT
5TX0 A 21 CS1 37 D4 53 ARINC CLK 1
6TX0 B 22 CS2 38 D5 54 ARINC CLK 0
7TX1 A 23 GND 39 D6 55 +5V
8TX1 B 24 GND 40 D7 56 +5V
9A0 25 ZERO WAIT MODE 41 D8 57 RX3 B
10 A1 26 READY 42 D9 58 RX3 A
11 A2 27 RD (DS)43 D10 59 RX2 B
12 A3 28 WR (RD/WR)44 D11 60 RX2 A
13 A4 29 DTACK 45 D12 61 RX1 B
14 A5 30 ERROR 46 D13 62 RX1 A
15 A6 31 MASTER RESET 47 D14 63 RX0 B
16 A7 32 16 MHZ CLOCK 48 D15 64 RX0 A
7
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DD-42900
H-12/06-0
FIGURE 3B. DD-42900FP FLAT PACK MECHANICAL ASSEMBLY
±.010
2.400
0.550
24 25 32 33
0.185
±.010
ENVELOPE
COMPONENT
(MAX)
0.040
(TYP)
2.170
±.010
0.200
SEE DETAIL "A"
0.065
(TYP)
DETAIL "A"
(REF)
NTS
(TYP)
0.075
0.185
(TYP)
0.040
0.015
(TYP)
(TYP)
0.080
(TYP)
±.002
(TYP)
0.010
0.020 R MAX
FOR REF ONLY
PIN NUMBERS
23 EQ. SP. @
(TOL NON CUM)
0.100 = 2.300
164 57
0.100
(TYP)
0.020
56
±.010
(TOL NON CUM)
7 EQ. SP. @
±
.010
0.100=0.700
1.800
(TYP)
1
LEAD CLUSTER TO BE CENTRALIZED
1ABOUT PWB CENTERLINE WITHIN
±
.010
NOTES:
±.003
24
25
32
33
0.100=0.700
7 EQ. SP. @
(TOL NON CUM)
1.800
2.400
.010
64
1
0.550
±.010
(TYP)
0.100
57 56
0.020
0.100 = 2.300
(TOL NON CUM)
23 EQ. SP. @
±.010
FOR REF ONLY
PIN NUMBERS
(TYP)
±.003
1
SEE DETAIL "A"
DETAIL "A"
NTS
(TYP)
0.015
0.070 (TYP)
0.080
(TYP)
(TYP) 0.010
0.020 R MAX
(TYP)
0.34
(MIN)
±.002
0.100
(REF)
2.000
(TYP)
0.100
±.010
0.040
ENVELOPE
COMPONENT
±.010
0.200(MAX)
FIGURE 3A. DD-42900DP DIP MECHANICAL ASSEMBLY
Component
Side
Component
Side
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DD-42900
H-12/06-0
GND
TX DB10
TX DB9
160
159
158
GND
BIST R2 (N/C)
BIST R1 (N/C)
120
119
118
GND
BIST TOB (N/C)
BIST TOA (N/C)
80
79
78
GND
+5V
GND
40
39
38
TX DB8157BIST R0 (N/C)117+5V77BIST R3 (N/C)37
TX DB7156ARINC CLK 0116MASTER RESET76CS236
TX DB6155ARINC CLK 1115ERROR75CS135
TX DB5154ARINC CLK OUT114DTACK74CS034
TX DB4153RESET RC113WR or RD/WR73A1033
TX DB3152IRQ1112RD or DS72A932
TX DB2151IRQ2111READY71A831
TX DB1150IRQ3110ZERO WAIT MODE70A730
TX DB0149GND109TMB7 (N/C)69A629
GND148GND108TMB6 (N/C)68A528
LD TX0 LO147D15107TMB5 (N/C)67A427
LOAD TX0 HI146D14106TMB4 (N/C)66A326
TX0 EMPTY145D13105TMB3 (N/C)65A225
TX0A IN144D12104TMB2 (N/C)64A124
TX0B IN143D11103TMB1 (N/C)63A023
EN TX0 OUT142D10102TMB0 (N/C)62GND22
CW STRB0141D9101GND61TX1 B21
RESET 0140D8 100+5V60TX1 A20
GND139+5V 99TSB1 (N/C)59TX0 B19
+5V138GND 98TSB0 (N/C)58TX0 A18
RX RDY 2
137+5V 97TMA7 (N/C)57+5V17
RX RDY 3136GND96TMA6 (N/C)568/16 BIT16
EN RX2135D7 95TMA5 (N/C)55INTEL/MOTO15
EN RX3134D6 94TMA4 (N/C)54GND14
16 MHZ CLOCK133D5 93TMA3 (N/C)53GND13
+5V132D4 92TMA2 (N/C)52GND12
GND131D3 91TMA1 (N/C)51RX RDY011
+5V130D290TMA0 (N/C)50RX RDY110
LD TX1 LO129D189TSA3 (N/C)49SELECT9
LD TX1 HI128D088TSA2 (N/C)48EN RX08
TX1 EMPTY127BIST RAM24 (N/C)87TSA1 (N/C)47EN RX17
TX1 A IN126BIST RAM7 (N/C) 86TSA0 (N/C)46TX DB156
TX1 B IN125BIST DMT (N/C)85TSB3 (N/C)45TX DB145
EN TX1 OUT124BIST T1B (N/C)84TSB2 (N/C)44TX DB134
CW STRB1123BIST T1A (N/C)83GND43TX DB123
RESET 1122OSC CLK OUT (N/C)82XTAL1 (N/C)42TX DB112
+5V121+5V81+5V41+5V1
DESCRIPTIONPIN NO.DESCRIPTIONPIN NO.DESCRIPTIONPIN NO.DESCRIPTIONPIN NO.
TABLE 5. DD-00429FP ASIC PINOUTS
9
Data Device Corporation
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DD-42900
H-12/06-0
Chip Set:
*DD-00429XP - X00
Temperature Range:
2 = -40°C to +85°C
ASIC Package Type:
P = Plastic
Lead Type:
F = 160-Pin Quad Flat Pack
V = 144-Pin TQFP
*Note: The DD-03182†and DD-03282†are required to com-
plete the ARINC 429 Interface. The DD-00429 is the
Microprocessor Interface/RAM/FIFO and Interrupt
Controller.
Application Note AN/A-6 DD-42900 Frequently Asked
Questions is available on request.
†Note: These Transceiver/Line Driver part numbers are provid-
ed for historical reference only. These components are
now provided by Device Engineering Inc. For a complete
cross-reference chart, please visit DEI at
www.deiaz.com,(480) 303-0822.
STANDARD DDC PROCESSING
FOR PLASTIC MONOLITHIC PRODUCTS
MIL-STD-883
TEST METHOD(S) CONDITION(S)
INSPECTION / WORKMANSHIP 2017, and 2032 —
ELECTRICAL TEST DDC ATP —
ORDERING INFORMATION
Full Assembly:
DD-4290XXP - 200
Burn-in:
0 = No Burn-in
Temperature Range:
2 = -40°C to +85°C
ASIC Package Type:
P = Plastic
Lead Type:
D = Dip
F = Flat Pack
Coating:
0 = Conformally Coated
With Urethane
1 = Not Conformally Coated
These products contain tin-lead solder.
10
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DD-42900
H-12/06-0
NOTES:
11
Data Device Corporation
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DD-42900
H-12/06-0
NOTES:
12
H-12/06-0 PRINTED IN THE U.S.A.
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York 11716-2426
For Technical Support - 1-800-DDC-5757 ext. 7771
Headquarters - Tel: (631) 567-5600, Fax: (631) 567-7358
Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
®
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