TLV717xx Series
GND
EN
IN OUT
VIN VOUT
On
Off
CIN COUT
1 F
Ceramic
m
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV717P
SBVS176B –OCTOBER 2011–REVISED APRIL 2016
TLV717P 150-mA, Low-Dropout Regulator With Foldback Current Limit for Portable
Devices
1
1 Features
1• Very Low Dropout: 215 mV at 150 mA
• Accuracy: 0.5% (typical)
• Low IQ: 35 µA
• Available in Fixed-Output Voltages:
1.2 V to 5 V
• High PSRR:
– 70 dB at 1 kHz
– 50 dB at 1 MHz
• Stable With Effective Output Capacitance:
0.1 µF
• Foldback Current Limit
• Package: 1-mm × 1-mm DQN
(1) See the Package Option Addendum at the end of this
document for a complete list of available voltage options.
(2) See Input and Output Capacitor Requirements for more
details.
2 Applications
• PCs and Notebooks
• Smart Phones
• Portable Electronics and Battery-Powered Devices
• Electronic Point of Sale
3 Description
The TLV717P series of low-dropout (LDO) linear
regulators are low quiescent current LDOs with
excellent line and load transient performance and are
designed for power-sensitive applications. These
devices provide a typical accuracy of 0.5%.
The TLV717P series offer current foldback that
throttles down the output current with a decrease in
load resistance. The typical value at which current
foldback initiates is 350 mA; the typical value of the
output short current limit value is 40 mA.
Furthermore, these devices are stable with an
effective output capacitance of only 0.1 µF. This
feature enables the use of cost-effective capacitors
that have higher bias voltages and temperature
derating. The devices regulate to specified accuracy
with no output load.
The TLV717P series is available in a 1-mm × 1-mm
DQN package that makes them ideal for hand-held
applications. The TLV717P provides an active
pulldown circuit to quickly discharge output loads.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV717P X2SON (4) 1.00 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
7 Detailed Description.............................................. 9
7.1 Overview................................................................... 9
7.2 Functional Block Diagram......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8 Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application.................................................. 11
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
10.3 Power Dissipation ................................................. 13
11 Device and Documentation Support................. 14
11.1 Device Support...................................................... 14
11.2 Documentation Support ........................................ 14
11.3 Community Resource............................................ 14
11.4 Trademarks........................................................... 14
11.5 Electrostatic Discharge Caution............................ 14
11.6 Glossary................................................................ 14
12 Mechanical, Packaging, and Orderable
Information........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2012) to Revision B Page
• Deleted all instances of TLV717xx; Replaced with generic part number, TLV717P.............................................................. 1
• Updated Applications. ............................................................................................................................................................ 1
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed TJ= –25°C to TJ= 25°C in the conditions statement in Absolute Maximum Ratings............................................. 4
• Changed TAto TJthroughout Electrical Characteristics......................................................................................................... 5
• Changed TAto TJin the conditions statement in Typical Characterisitcs ............................................................................. 6
• Changed TAto TJin the conditions statement in Typical Characterisitcs ............................................................................. 7
• Changed TAto TJin the conditions statement in Typical Characterisitcs ............................................................................. 8
• Changed junction temperature range from –40°C to 125°C to –40°C to 85°C in Overview.................................................. 9
• Deleted TLV717xx functional block diagram.......................................................................................................................... 9
Changes from Original (October 2011) to Revision A Page
• Changed document status from Product Preview to Production Data................................................................................... 1
GND OUT
EN IN
3 4
2 1
OUT GND
IN EN
1 2
4 3
3
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5 Pin Configuration and Functions
DQN Package
4-Pin X2SON
Top View DQN Package
4-Pin X2SON
Bottom View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
EN 3 I Enable pin. Driving EN over 1.2 V turns on the regulator. Driving EN below 0.4 V puts the regulator
into shutdown mode.
GND 2 — Ground pin
IN 4 I Input pin. A small capacitor is recommended from this pin to ground to assure stability. See the
Input and Output Capacitor Requirements section in the Application and Implementation for more
details.
OUT 1 O Regulated output voltage pin. A small 1-μF ceramic capacitor is recommended from this pin to
ground to assure stability. See the Input and Output Capacitor Requirements section in the
Application and Implementation for more details.
Thermal
pad — — Connect to GND for improved thermal performance.
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
At TJ= 25°C, unless otherwise noted. All voltages are with respect to GND.(1)
MIN MAX UNIT
Voltage
Input range, VIN –0.3 6
VEnable range, VEN –0.3 VIN + 0.3
Output range, VOUT –0.3 6
Current Maximum output, IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation, PDISS See Thermal Information
Temperature Junction, TJ–55 150 °C
Storage junction, Tstg –55 150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±500
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN MAX UNIT
VIN Input voltage 1.7 5.5 V
VOUT Output voltage 1.2 5 V
IOUT Output current 0 150 mA
VEN Enable pin voltage 0 VIN V
TJJunction temperature –40 85 °C
6.4 Thermal Information
THERMAL METRIC
TLV717P
UNITDQN (X2SON)
4 PINS
RθJA Junction-to-ambient thermal resistance 393.3 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 140.3 °C/W
RθJB Junction-to-board thermal resistance 330 °C/W
ψJT Junction-to-top characterization parameter 6.5 °C/W
ψJB Junction-to-board characterization parameter 329 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 147.5 °C/W
5
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6.5 Electrical Characteristics
At operating temperature range (TJ= –40°C to 85°C), TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT = 10 mA, VEN
= VIN, and COUT = 1 µF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 1.7 5.5 V
VOUT Output voltage range 1.2 5 V
IOUT Output current 150 mA
DC output accuracy TJ= +25°C 0.5%
VOUT ≥1.2 V, –40°C ≤TJ≤+85°C –1.5% 1.5%
VOUT ≤1.2 V 25 mV
ΔVO/VIN Line regulation VOUT(NOM) + 0.5 V ≤VIN ≤5.5 V 1 5 mV
ΔVO/IOUT Load regulation 0 mA ≤IOUT ≤150 mA 10 20 mV
VDO Dropout voltage VIN = 0.98 × VOUT(NOM),
IOUT = 150 mA
1.2 V ≤VOUT < 1.5 V 330 500 mV1.5 V ≤VOUT < 1.8 V 330 450
1.8 V ≤VOUT ≤5 V 215 350
IGND Ground pin current IOUT = 0 mA 35 55 µA
ISHDN Shutdown current VEN ≤0.4 V, 2 V ≤VIN ≤4.5 V 0.1 0.5 µA
PSRR Power-supply
rejection ratio VIN = 3.3 V, VOUT = 2.8 V,
IOUT = 30 mA
f = 10 Hz 70
dB
f = 100 Hz 70
f = 1 kHz 65
f = 10 kHz 60
f = 100 kHz 43
VNOISE Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V,
IOUT = 10 mA 55 µVRMS
tSTR Start-up time COUT = 1 μF, IOUT = 150 mA 100 µs
ISC Short current limit VIN = min (VOUT(NOM) + 1 V, 5.5 V), VOUT = 0 V 40 mA
VHI Enable high (enabled) 0.9 VIN V
VLO Enable low (disabled) 0 0.4 V
IEN EN pin current EN = 5.5 V 0.01 µA
RPULLDOWN Pulldown resistor 120 Ω
UVLO Undervoltage lockout VIN rising 1.6 V
Output Current (mA)
50 150
0.3
0.25
0.2
0.15
0.1
0.05
0
Dropout Voltage (V)
60 70 80 90
G005
+85 C°
+25 C°
- °40 C
100 130 140120110
Temperature( C)°
-40 85
2.838
2.828
2.818
2.808
2.798
2.788
2.778
2.768
2.758
OutputVoltage(V)
-27.5 -15 -2.5 10
G006
10mA
150mA
22.5 60 72.547.535
Fixed Output Voltage Versions (V)
1.5 5
0.3
0.25
0.2
0.15
0.1
Dropout Voltage (V)
2 2.5 3 3.5
G004
+85 C°
+25 C°
- °40 C
4 4.5
I (mA)
OUT
0 200
2.9
2.88
2.86
2.84
2.82
2.8
2.78
2.76
2.74
2.72
2.7
V (V)
OUT
20 40 60 80 100
G001
120 140 160 180
+85 C°
+25 C°
- °40 C
6
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6.6 Typical Characteristics
At operating temperature range (TJ= –40°C to 85°C), TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT
= 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
Figure 1. Load Regulation Figure 2. Line Regulation
Figure 3. Line Regulation Figure 4. Dropout Voltage vs Fixed Output Voltage Versions
Figure 5. Dropout Voltage vs Output Current Figure 6. Output Voltage vs Temperature
Frequency(Hz)
10 10M
80
70
60
50
40
30
20
10
0
Power-SupplyRejectionRatio(dB)
100 1k 10k
G011
100k 1M
I =30mA
OUT
I =150mA
OUT
V V =0.5V-
IN OUT
Frequency(Hz)
10 10M
80
70
60
50
40
30
20
10
0
Power-SupplyRejectionRatio(dB)
100 1k 10k
G012
100k 1M
I =30mA
OUT
I =150mA
OUT
V V =1V-
IN OUT
Temperature ( C)°
-40 85
45
40
35
30
25
20
15
10
5
0
Ground Pin Current ( A)m
-27.5 -15 -2.5 10
G009
22.5 60 72.547.535
I = 0 mA
OUT
OutputCurrent(mA)
0 350
3
2.5
2
1.5
1
0.5
0
OutputVoltage(V)
50 100 150 200
G010
250 300
+85 C°
+25 C°
- °40 C
Input Voltage (V)
3 5.5
45
40
35
30
25
20
15
10
5
0
Ground Pin Current ( A)m
3.5 4 4.5 5
G007
+85 C°
+25 C°
- °40 C
I = 0 mA
OUT
OutputCurrent(mA)
0 150
3000
2500
2000
1500
1000
500
0
GroundPinCurrent( A)m
25 50
G008
+85 C°
+25 C°
- °40 C
75 100 125
7
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Typical Characteristics (continued)
At operating temperature range (TJ= –40°C to 85°C), TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT
= 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
Figure 7. Ground Pin Current vs Input Voltage Figure 8. Ground Pin Current vs Output Current
Figure 9. Ground Pin Current vs Temperature Figure 10. Output Voltage vs Output Current
Figure 11. TLV71728PSRR vs Frequency Figure 12. TLV71728PSRR vs Frequency
InputVoltage(V)
3.6 4.3
90
80
70
60
50
40
30
20
10
0
Power-SupplyRejectionRatio(dB)
3.7 3.8 3.9
G013
4 4.1
1kHz
10kHz
100kHz
4.2
Frequency(Hz)
10 10M
10
1
0.1
0.01
0
NoiseSpectralDensity( V/ )m ÖHz
100 1k 10k
G014
100k 1M
1.2
2.8
5
8
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Typical Characteristics (continued)
At operating temperature range (TJ= –40°C to 85°C), TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT
= 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
Figure 13. PSRR vs Input Voltage Figure 14. Output Spectral Noise Density vs Frequency
Foldback Current
Limit
UVLO
Bandgap
IN
EN
OUT
LOGIC
120 W
GND
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7 Detailed Description
7.1 Overview
The TLV717P belongs to a new family of next-generation value low-dropout (LDO) regulators. These devices
consume low quiescent current and deliver excellent line and load transient performance. These characteristics,
combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for
RF portable applications.
This family of regulators offers current foldback. Device operating junction temperature is –40°C to 85°C.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV717P has an internal foldback current limit that helps to protect the regulator during fault conditions. The
current supplied by the device is gradually throttled down as the output voltage decreases. When the output is
shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in
current limit, and is VOUT = ILIMIT × RLOAD. The advantage of foldback current limit is that the ILIMIT value is less
than the fixed current limit. Therefore, the power that the PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] is
much less.
The TLV717P PMOS pass element has a built-in body diode that conducts current when the voltage at OUT
exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,
external limiting to 5% of the rated output current is recommended.
10
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Feature Description (continued)
7.3.2 Shutdown
The enable pin (EN) is active high. The device is enabled when the voltage at the EN pin goes above 0.9 V. This
relatively lower voltage value required to turn the LDO on can be exploited to power the LDO with a GPIO of
recent processors whose GPIO logic 1 voltage level is lower than traditional microcontrollers. The device is
turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be
connected to the IN pin.
7.3.3 Undervoltage Lockout (UVLO)
The TLV717P uses an undervoltage lockout circuit (UVLO = 1.6 V) to keep the output shut off until the internal
circuitry operates properly.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and not decreased below the
enable falling threshold.
• The output current is less than the current limit.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout may result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
When the device is disabled, the active pulldown resistor discharges the output.
Table 1 lists the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE PARAMETER
VIN VEN IOUT
Normal mode VIN > VOUT(nom) + VDO
and VIN > UVLORISE VEN > VEN(HI) IOUT < ILIM
Dropout mode UVLORISE < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < ILIM
Disabled mode
(any true condition disables
the device) VIN < UVLOFALL VEN < VEN(LO) —
TLV717xx Series
GND
EN
IN OUT
VIN VOUT
On
Off
CIN COUT
1 F
Ceramic
m
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV717P is a low-dropout regulator (LDO) with low quiescent current that delivers excellent line and load
transient performance. This LDO regulator offers a foldback current limit. The operating junction temperature of
this device series is –40°C to 85°C.
8.2 Typical Application
Figure 15. Typical Application Circuit
8.2.1 Design Requirements
Table 2 lists the parameters for this application.
Table 2. Design Parameters
PARAMETER DESIGN REQUIREMENT
Input voltage 3.8 V
Output voltage 2.8 V ±1%
Output current 30 to 150 mA
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
TI recommends X5R- and X7R-type ceramic capacitors because they have minimal variation in value and
equivalent series resistance (ESR) over temperature. The TLV717P is designed to be stable with an effective
capacitance of 0.1 µF or larger at the output, though TI recommends a 1-µF ceramic capacitor for typical
applications. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective
capacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective capacitance
refers to the capacitance that the LDO detects under operating bias voltage and temperature conditions; that is,
the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing
the use of cheaper dielectrics, this capability of being stable with 0.1-µF effective capacitance also enables the
use of smaller footprint capacitors that have higher derating in size- and space-constrained applications. Using a
0.1-µF rated capacitor at the LDO output does not ensure stability because the effective capacitance under the
specified operating conditions would be less than 0.1 µF. Maximum ESR should be less than 200 mΩ.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to 1-
µF, low ESR capacitor across the IN and GND pins of the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast, rise-time load transients are anticipated, or if the device is not located close to the power
source. If source impedance is more than 2 Ω, a 0.1-µF input capacitor may be necessary to ensure stability.
OutputCurrent(mA)
0 150
3000
2500
2000
1500
1000
500
0
GroundPinCurrent( A)m
25 50
G008
+85 C°
+25 C°
- °40 C
75 100 125
Frequency(Hz)
10 10M
10
1
0.1
0.01
0
NoiseSpectralDensity( V/ )m ÖHz
100 1k 10k
G014
100k 1M
1.2
2.8
5
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8.2.2.2 Dropout Voltage
The TLV717P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout.
8.2.2.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
8.2.3 Application Curves
Figure 16. Ground Pin Current vs Output Current Figure 17. Output Spectral Noise Density vs Frequency
COUT
VOUT VIN
GND PLANE
CIN
Represents via used for
application specific connections
1
23
4
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9 Power Supply Recommendations
Connect a low-output impedance power supply directly to the IN pin of the TLV717P. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during start-up or
load transient events. If inductive impedances are unavoidable, use an input capacitor.
10 Layout
10.1 Layout Guidelines
Input and output capacitors should be placed as close to the device pins as possible. To improve AC
performance (such as PSRR, output noise, and transient response), TI recommends designing the board with
separate ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In
addition, the output capacitor ground connection should be connected directly to the device GND pin. High ESR
capacitors may degrade PSRR performance.
10.2 Layout Example
Figure 18. Recommended Layout Example
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC-low and high-K boards are given in
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition, plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in Equation 1.
PD= (VIN – VOUT)×IOUT (1)
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(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV717P.
SLVU553 details the design kits and evaluation modules for TLV71733PEVM-072.
The EVM can be requested at the Texas Instruments website through the TLV717P product folder, or purchased
directly from the TI eStore.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature(1)
PRODUCT VOUT
TLV717xx(x)Pyyyz
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; otherwise, three digits are used (for example, 28 =
2.8 V; 475 = 4.75 V).
Pindicates an active output discharge feature. All members of TLV717P family will actively
discharge the output when the device is disabled.
YYY is the package designator.
Zis the package quantity. R is for 3000 pieces, T is for 250 pieces.
11.2 Documentation Support
11.2.1 Related Documentation
TLV71733PEVM-072 Evaluation Module user guide,SLVU553
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15
TLV717P
www.ti.com
SBVS176B –OCTOBER 2011–REVISED APRIL 2016
Product Folder Links: TLV717P
Submit Documentation FeedbackCopyright © 2011–2016, Texas Instruments Incorporated
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Jul-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV71712PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UX
TLV71712PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UX
TLV71712PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UX
TLV71713PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VC
TLV71713PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VC
TLV71715PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UY
TLV71715PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UY
TLV717185PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VN
TLV717185PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VN
TLV71718PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UZ
TLV71718PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UZ
TLV71721PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AR
TLV71721PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AR
TLV71725PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VA
TLV71725PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VA
TLV71727PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AS
TLV71727PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AS
PACKAGE OPTION ADDENDUM
www.ti.com 15-Jul-2016
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV717285PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM VE
TLV717285PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VE
TLV71728PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VD
TLV71728PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VD
TLV71728PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VD
TLV71729PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VI
TLV71729PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VI
TLV71730PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VF
TLV71730PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VF
TLV71733PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VG
TLV71733PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VG
TLV71736PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VH
TLV71736PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Jul-2016
Addendum-Page 3
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV71712PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71712PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71712PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 2.0 8.0 Q3
TLV71712PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71712PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71713PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71713PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71713PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71713PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71715PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71715PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71715PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71715PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV717185PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV717185PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71718PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71718PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71721PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2018
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV71721PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71721PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71721PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71725PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71725PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71725PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71725PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71727PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71727PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV717285PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV717285PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV717285PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV717285PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71728PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71728PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71728PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 2.0 8.0 Q3
TLV71728PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71728PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71729PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71729PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71730PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71730PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71730PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71730PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71733PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71733PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71733PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TLV71736PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71736PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71736PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV71736PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2018
Pack Materials-Page 2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV71712PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71712PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71712PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0
TLV71712PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV71712PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71713PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71713PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71713PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV71713PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71715PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71715PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71715PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71715PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV717185PDQNR X2SON DQN 4 3000 210.0 185.0 35.0
TLV717185PDQNT X2SON DQN 4 250 210.0 185.0 35.0
TLV71718PDQNR X2SON DQN 4 3000 210.0 185.0 35.0
TLV71718PDQNT X2SON DQN 4 250 210.0 185.0 35.0
TLV71721PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71721PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71721PDQNT X2SON DQN 4 250 184.0 184.0 19.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2018
Pack Materials-Page 3
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV71721PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV71725PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71725PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71725PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV71725PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71727PDQNR X2SON DQN 4 3000 210.0 185.0 35.0
TLV71727PDQNT X2SON DQN 4 250 210.0 185.0 35.0
TLV717285PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV717285PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV717285PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV717285PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71728PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71728PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71728PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0
TLV71728PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71728PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV71729PDQNR X2SON DQN 4 3000 210.0 185.0 35.0
TLV71729PDQNT X2SON DQN 4 250 210.0 185.0 35.0
TLV71730PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71730PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71730PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71730PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV71733PDQNR X2SON DQN 4 3000 210.0 185.0 35.0
TLV71733PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71733PDQNT X2SON DQN 4 250 210.0 185.0 35.0
TLV71736PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV71736PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV71736PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV71736PDQNT X2SON DQN 4 250 183.0 183.0 20.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2018
Pack Materials-Page 4
PACKAGE OUTLINE
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
BA
SEATING PLANE
C
0.08
PIN 1
INDEX AREA
0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL)
NOTE 4
EXPOSED
THERMAL PAD
1
23
4
1
1.05
0.95
1.05
0.95
0.4 MAX
2X 0.65
0.48+0.12
-0.1
3X 0.30
0.15
0.3
0.2
4X 0.28
0.15
0.05
0.00
(0.11)
NOTE 5
NOTE 6
NOTE 6
5
(0.07) TYP
(0.05) TYP
EXAMPLE BOARD LAYOUT
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
LAND PATTERN EXAMPLE
SCALE: 40X
SYMM
SYMM
1
2
3
4
4X (0.21)
4X (0.36)
(0.65)
(0.86)
( 0.48)
SEE DETAIL
4X (0.18)
(0.22) TYP
EXPOSED METAL
CLEARANCE
4X
(0.03)
EXPOSED METAL
5
EXAMPLE STENCIL DESIGN
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
SYMM
SYMM
1
2
3
4
SOLDER MASK
EDGE
4X (0.21)
4X (0.4)
(0.65)
(0.9)
( 0.45)
4X (0.03)
4X (0.235)
4X (0.22)
5
IMPORTANT NOTICE
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used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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