Am29F100T-70SCB - Advanced Micro Devices

FINAL

Publication# 18926 Rev: CAmendment/+2

Issue Date: March 1998

Am29F100

1 Megabit (128 K x 8-bit/64 K x 16-bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

—5.0 V ± 10% for read, erase, and program

operations

— Simplifies system-level power requirements

■High performan c e

— 70 ns maximum access time

■Low power consumptio n

— 20 mA typical active read current for byte mode

— 28 mA typical active read current for word mode

— 30 mA typical program/erase current

— 25 µA typical standby current

■Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

one 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

one 32 Kword sectors (word mode)

— Any combination of sectors can be erased

— Supports full chip erase

■Top or bottom boot block configurations

available

■Sector protection

— Hardware-based feature that disables/re-

enables program and erase operations in any

combination of sectors

— Sector protection/unprotection can be

implemented using standard PROM

programming equipment

— Temporary Sector Unprotect feature allows in-

system code changes in protected sectors

■Embe dded Algorith ms

— Embedded Erase algorithm automatically

pre-programs and erases the chip or any

combination of designated sector

— Embedded Program algorithm automatically

programs and verifies data at specified address

■Minimum 100,000 program/erase cycles

guaranteed

■Package options

— 44-pin SO

— 48-pin TSOP

■Compatible with JEDEC standar ds

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protecti on

■Data# Polling and Toggl e Bits

— Provides a software method of detecting

program or erase cycle completion

■Ready/Busy pin (RY/BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■Erase Suspend/Erase Resume

— Suspends an erase operation t o read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■Hardware RESET# pin

— Hardware method of resetting the device to

reading array data

2 Am29F100

GENERAL DESCRIPTION

The Am29F100 is a 1 Mbit, 5. 0 V olt-only Flash memory

organized as 131,072 bytes or 65,536 words. The

Am29F100 is offered in 44-pin SO and 48-pin TSOP

packages. Word-wide data appears on DQ0-DQ15;

byte-wide data on DQ0-DQ7. The device is designed to

be programmed in-system with the standard system

5.0 Volt VCC supply. A 12.0 volt VPP is not required for

program or erase operations. The device can also be

programmed or erased in standard EPROM program-

mers.

The standard device offers access times of 70, 90,

120, and 150 ns, allowing high-speed microproces-

sors to operate without wait states. To eliminate bus

contention the device has separate chip enable

(CE#), write enable (WE#) and output enable (OE#)

controls.

The device requires only a single 5 .0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input t o an internal state machi ne that controls

the erase and programming circuitry. Write cycles also

internally latc h addresses and data need ed for the pro-

gramming and erase operations. Reading data out of

the device is similar to reading from other Flash or

EPROM devices.

Device programming occurs by executing the program

command sequence. This invokes the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This invokes the Embedded Erase

algorithm—an internal algorit hm that aut omatically pre-

programs the array (if it is not already programmed) be-

fore executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

The Erase Suspend fea ture enables the system to put

erase on hold for any period of time to read data from,

or program data to, a sector that is not being erased.

The sector erase ar chitecture all ows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is erased

when shipped from the factory.

The hardware data protection measures include a

low VCC detector automatically inhibits write operations

during power transitions. The hardware sector pro-

tection feature disables bot h program and erase oper-

ations in any combination of the sectors of memory,

and is implemented using standard EPROM program-

mers. The tem porary sector unprotec t feature allows

in-system changes to protected sectors.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied t o the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standb y mode.

Power consumption is gr eatly reduced in t his mode.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability, and cost

effectiveness. The device electrically erases all bits

within a sector simultaneously via Fowler-Nordheim

tunneling. The bytes are programmed one byte at a

time using the EPROM programming mechanism of

hot electron injecti on.

Am29F100 3

PRODUCT SELECTOR GUIDE

Note: See the AC Characteristics section for full specifications.

BLOCK DIAGRAM

Family Part Numb er Am29F100

Speed Option (VCC = 5.0 V ± 10%) -70 -90 -120 -150

Max Access Time (ns) 70 90 120 150

CE# Access (ns) 70 90 120 150

OE# Access (ns) 30 35 50 55

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

CE#

OE#

STB

DQ0

–

DQ15

RESET#

Data

Latch

Y-Gating

Cell Matrix

18926C-1

Address Latch

A0–A15

RY/BY#

Buffer RY/BY#

BYTE#

A-1

4 Am29F100

CONNECTION DIAGRAMS

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

18926C-2

Standard TSOP

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

18926C-3

Reverse TSOP

Am29F100 5

CONNECTION DIAGRAMS

PIN CONFIGURATION

A0–A15 = 16 Addresses

DQ0–DQ14= 15 Data Inputs/Outputs

DQ15/A-1 = DQ15 (Data Input/Out put, word mode),

A-1 (LSB Address Input, byte mode)

CE# = Chip Enable

OE# = Output Enable

WE# = Write Enable

BYTE# = Selects 8-bit or 16-bit mode

RESET# = Hardware Reset Pin, Active Low

RY/BY# = Ready/Busy Output

VCC = +5.0 Volt Single Power Supply

(See Product Sele ctor Guide for speed

options and voltage supply tolerances)

VSS = Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

18926C-4

RY/BY#

CE#

VSS

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET#

WE#

A10

A11

A12

A13

A14

A15

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

16 or 8

DQ0–DQ15

(A-1)

A0–A15

CE#

OE#

WE#

18926C-5

RESET#

RY/BY#

BYTE#

6 Am29F100

ORDERING INFORMATION

Standard Pro d ucts

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed

by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am29F100

1 Megabit (128 K x 8-Bit/64 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program, and Erase

Am29F100 -70 E C

OPTIONAL PROCESSING

Blank = Standard Pro ces sin g

B = Burn-In

(Contact an AMD representative for more infor-

mation.)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I=Industrial (–40°C to +85°C)

E = E xte nd ed (–5 5°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package

(TSOP) Rever se Pino ut (TS R0 48)

S = 44-Pin Small Outline Package

(SO 044)

SPEED OP TIO N

See Product Selector Guide and

Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

Valid Combinations

AM29F100T-70,

AM29F100B-70

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

AM29F100T-90,

AM29F100B-90

AM29F100T-120,

AM29F100B-120

AM29F100T-150,

AM29F100B-150

Am29F100 7

DEVICE BUS OPERATIONS

This section des cribes t he requirements and use of the

device bus operations, which are initiated through the

internal command register . The command register itself

does not occupy any addressable memory location.

The register is compos ed of latches that store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. The appropriate device bus operations table

lists the inputs and control levels required, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F100 Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0

0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A15:A0 in word mode (BYTE# = VIH), A15:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-

tection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the by te or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pi ns DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stat ed, and the DQ15 p in is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

main at VIH. The BYTE# pin determines whether the de-

vice outputs array data in words or bytes.

The internal state machine is set for reading array

data upon device power-up, or after a hardware re-

set. This ensures that no spurious alteration of the

memory content occurs during the power transition.

No command is necessary in this mode to obtain

array data. Standard microprocessor read cycles that

assert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. ICC1 in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE # to V IH.

For program operations , the BYTE# pin determ ines

whether the device accepts program data in bytes

or words. Refer to “Word/Byte Configuration” for

more information.

Operation CE# OE# WE# RESET# Addresses

(Note 1) DQ0–

DQ7

DQ8–DQ15

BYTE#

= VIH

BYTE#

= VIL

Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z,

DQ15 = A-1

Write L H L H AIN DIN DIN

Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z

Output Dis able L H H H X High-Z H igh -Z Hig h-Z

Hardware Reset X X X L X High-Z High-Z High-Z

Tem por ary Sec tor

Unprotect XXXV

ID AIN DIN DIN High-Z

8 Am29F100

An erase operation can erase one sector , multiple sec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “sector address” consists of the addres s bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the en-

tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operat ion, the sy stem may

check the status of the operation by reading the status

bits on DQ7–DQ0. St andard read cycle timings and I CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the d evice,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when CE#

and RESET# pins are both held at VCC ± 0.5 V. (Note

that this is a more restricted voltage range than VIH.)

The device enters the TTL standby mode when CE#

and RESET# pins are both held at VIH. The device re-

quires standard access time (tCE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics tables, ICC3 represents the

standby current specification.

RESET#: HARDWARE RESET PIN

The RESET# pin provides a hardware method of reset-

ting the device to readi ng array data. When the system

drives the RESET# pin low for at least a period of tRP,

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The oper ation that was in-

terrupted sh ould be reini tiated once th e device is ready

to accept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VIL, the device enters

the TTL standby mode; if RESET# is held at VSS ±

0.5 V, the device enters the CMOS standby mode.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or eras e oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine wh ether

the reset operation is complete. If RESET # is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the RE-

SET# pin returns to VIH.

Refer to the AC Charac teristics t ables for RESET# pa-

rameters and timing diagram.

Output Disable Mode

When the OE# input is at V IH, output from the de vice is

disabled. The output pins are placed in the high imped-

ance state.

Am29F100 9

Table 2. Sector Addresses Tables (Am29F100T)

Table 3. Sector Addresses Tables (Am29F100B)

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Autoselect Codes (High Voltage Method) table. In ad-

dition, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining addre ss bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions table. This method does not require VID. See

“Command Definitions” for details on using the autose-

lect mode.

Table 4. Am29F100 Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

A15 A14 A13 A12 (x8) Address Ra ng e (x16) Address Rang e

SA0 0 X X X 00000h-0FFFFh 00000h-07FFFh

SA1 1 0 X X 10000h-17FFFh 08000h-0BFFFh

SA2 1 1 0 0 18000h-19FFFh 0C000h-0CFFFh

SA3 1 1 0 1 1A000h-1BFFFh 0D000h-0DFFFh

SA4 1 1 1 X 1C000h-1FFFFh 0E000h-0FFFFh

A15 A14 A13 A12 (x8) Address Ra ng e (x16) Address Rang e

SA0 0 0 0 X 00000h-03FFFh 00000h-01FFFh

SA1 0 0 1 0 04000h-05FFFh 02000h-02FFFh

SA2 0 0 1 1 06000h-07FFFh 03000h-03FFFh

SA3 0 1 X X 08000h-0FFFFh 04000h-07FFFh

SA4 1 X X X 10000h-1FFFFh 08000h-0FFFFh

Description Mode CE# OE# WE#

A15

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8

DQ15

DQ7

DQ0

Manufa ctu rer ID: AMD L L H X X VID XLXLL X 01h

Device ID:

Am29F100

(Top Boot Block)

Word L L H XXV

ID XLXLH22h D9h

Byte L L H X D9h

Device ID:

Am29F 100

(Bottom Boot Block)

Word L L H XXV

ID XLXLH22h DFh

Byte L L H X DFh

Sector Pro tec tion Verificatio n L L H SA X VID XLXHL X01h

(protected)

X00h

(unprotected)

10 Am29F100

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The

hardware sector unprotection feature re-enables

both program and erase operations in previously pro-

tected sectors.

Sector protection/unprotection must be implemented

using programming equipment. The procedure re-

quires a high voltage (VID) on address pin A9 and the

control pins. Details on this method are provided in a

supplement, publication number 20373. Contact an

AMD representative to obtain a copy of th e appropriate

document.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is protec ted

or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Secto r Unprotec t mode is a ctivated by set ting the

RESET# pin to VID. During this mode, formerly pro-

tected sectors can be programmed or erased by se-

lecting the sector addresses. Once VID is removed

from the RESET# pin, all the previously protected

sectors are pro tected again . Figure 1 sh ows the al go-

rithm, and the Temporary Sector Unprotect (Figure

17) di agra m shows t he ti ming wav e forms , fo r thi s fea-

ture.

Figure 1. Temporary Sector Unprotect Operation

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect

Completed (Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

18926C-6

Am29F100 11

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures prevent accidental erasure or pro-

gramming, which might otherwise be caused by spuri-

ous system level signals during VCC power-up and

power-down transitions, or from system noise.

Low V CC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuit s are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical In hibit

Write cycles are inhibited by holding any one of OE#

= VIL, CE# = VIH or WE# = VIH. To initiate a write cy-

cle, CE# and WE# mus t be a logical zero while OE#

is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power

up, the device does not accept commands on the

rising edge of WE#. The internal state machine is

automatically reset to reading array data on

power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the dev ice accept s an Erase S uspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a p rogramming operation in the Erase

Suspend mode, t he system may onc e again read array

data with the same exception. See “Erase Suspend/

Erase Resume Commands” for more information on

this mode.

The system

must

issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device re sets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. Th is reset s the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

12 Am29F100

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes ,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements . This method is an alternat ive to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires VID on address bit A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code.

A read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is un-

protec ted. Refer to th e Secto r Addre ss tab les for va lid

sector add resses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by byte or word,

on depending on the state of the BYTE# pin. Prog ram-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program se t-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is

not

required to provide further controls or tim-

ings. The device automatically provides internally gen-

erated program pulses and verify the programmed cell

margin. The Command Definitions take shows the ad-

dress and data requirements for the byte program com-

mand sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the device has reset to read-

ing array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempti ng to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Note: See the appropriate Command Definitions table for

program comma nd seque nce.

Figure 2. Program Operation

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

18926C-7

Am29F100 13

Chip Erase Command Sequence

Chip erase is a six-bus-c ycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Tw o additional

unlock write cycles are then fol lowed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not

require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically pr eprograms and v erifi es the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings durin g these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure dat a int egrity.

The system can determine the status of the erase

operation by using DQ7, DQ6, or RY/BY#. See

“Write Operation Status” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and addresses are no longer latc hed.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to t he Chip/Sector

Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, f ollowed by a set-up command. Two ad-

ditional unlock wri te cycles are then followed b y the ad-

dress of the sector to be erased, and the sector erase

command. The Command Definitions table shows the

address and data requirements for the sector erase

command sequence.

The device does

not

require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be writte n. L oading t he sector e rase buf fer

may be done in any sequence , and the number o f sec-

tors may be from on e sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor in terrupts be disabled dur ing this time to

ensure all commands are accepted. The interr upts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

The system can monitor DQ3 to dete rmine if the s ector

erase timer has timed out. (See the “DQ3: Sector

Erase Timer” section.) The time-out begins from the ris-

ing edge of the final WE# pulse in the command se-

quence.

Once the sector erase operation has begun, only the

Erase Suspend command is v alid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the op-

eration. The Sector Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrit y.

When the Embedded Erase algorithm is complete, the

device returns to reading ar ray data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, or RY/

BY#. Refer to “Write Operation Status” for information

on these status bits.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for par ameters, and to

the Sector Erase Operations T iming diagram for timing

waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operat ion. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

When the Erase Suspe nd command is written d uring a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

14 Am29F100

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The devic e “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7 to det ermine if a sector is act ively erasing

or is erase-suspended. See “Write Operation Status”

for information on these status bits.

After an erase-suspended program operation is com-

plete, the syst em can once again rea d array data within

non-suspended sectors. The system can determine the

status of the program operation us ing the DQ7 or DQ6

status bits, just as in the standard program operation.

See “Write Operation Status” for more information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Auto select Command Seq uence ”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operati on. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Notes:

1. See the appropriate Command Definitions table f or erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

18926C-8

Am29F100 15
Table 5. Am29F100 Command Definitions
Legend:
X = Don’t care
RA = Address of the me mory location to be read. 
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. 
Addresses latch on the falling edge of the WE# or CE# pulse, 
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the 
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or 
erased. Address bits A15–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles 
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and 
command cycles.
5. No unlock or command cycles required when reading array 
data.
6. The Reset command i s required to return to reading array 
data when device is in the autoselect mode, or if DQ5 goes 
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequen ce is a 
read operation.
8. The data is 00h for an unprotected sector and 01h for a 
protected sector. See “Autoselect Command Sequence” for 
more information.
9. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend 
mode. The Erase Sus pend command is valid only during a 
sector erase operation.
10. The Erase Resume command is valid only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–4)
First Second Third  Fourth Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 R A RD
Reset (Note 6) 1 XXXX F0
Manufacturer ID Word 45555 AA 2AAA 55 5555 90 XX00 01
Byte AAAA 5555 AAAA
Device ID, 
Top Boot Block  Word 45555 AA 2AAA 55 5555 90 XX01 22D9
Byte AAAA 5555 AAAA XX02 D9
Device ID,
Bottom Boot Block Word 45555 AA 2AAA 55 5555 90 XX01 22DF
Byte AAAA 5555 AAAA XX02 DF
Sector Protect Verify 
(Note 8)
Word 45555 AA 2AAA 55 5555 90
(SA)
X02 XX00
XX01
Byte AAAA 5555 AAAA (SA)
X04 00
01
Program Word 45555 AA 2AAA 55 5555 A0 PA PD
Byte AAAA 5555 AAAA
Chip Erase Word 65555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Byte AAAA 5555 AAAA AAAA 5555 AAAA
Sector Erase Word 65555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
Byte AAAA 5555 AAAA AAAA 5555
Erase Suspend (Note 9) 1 XXXX B0
Erase Resume (Note 10) 1 XXXX 30
Cycles
Autoselect (Note 7)

16 Am29F100

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ3, DQ5, DQ6, DQ7, and

RY/BY#. Table 6 and the following subsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# Polling is valid after the ris-

ing edge of the final WE# pulse in the program or

erase command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. I f a program address f alls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 2 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” o n DQ7. When the Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum out put

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid st atus in-

formation on DQ7.

After an erase command sequenc e is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is activ e for approximately 100 µs, the n the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the

following

read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. The Data# Poll-

ing Timings (During Embedded Algorithms) figure in

the “AC Characteristics” section illustrate s this.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

18926C-9

Figure 4. Data# Polling Algorithm

Am29F100 17

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is v alid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/ BY# is an open-drain output, sev-

eral RY/BY# pins can be tied t ogether in parallel with a

pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia-

grams for read, reset, program, and erase shows the

relationship of RY/BY# to other signals.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (pri or to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approxi mately 100 µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The Write O peration Status table s hows the outputs for

Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

Reading Toggle Bit DQ6

Refer to Figure 5 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whe th er a to ggle bit is togg ling . Typically, a

system would note and store the value of the toggle

bit afte r th e fi r st r e ad . A fte r th e s ec on d re a d, th e sy s-

tem would compare the new value of the toggle bit

with the fi rst. If the toggle bit i s not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indic ates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may rea d DQ3 to dete rmine whet her or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selec ted for eras ure, the entir e time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can g uarantee t hat th e time bet ween ad-

ditional sector erase commands will always be less

18 Am29F100

than 50 µs. See also the “Sector Erase Command Se-

quence” section.

After the sector erase command sequence is written,

the system should read the stat us on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and t hen read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all fur ther commands ( other than Er ase Su spend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system sof tware should check t he status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

18926C-10

Figure 5. Toggle Bit Algorithm

(Notes

1, 2)

Am29F100 19

Table 6. Write Operation Status

Notes:

1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Operation DQ7

(Note 1) DQ6 DQ5

(Note 2) DQ3 RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A 0

Embedded Erase Algorithm 0 Toggle 0 1 0

Erase

Suspend

Mode

Reading with in Era se

Suspend ed Sec tor 1 No toggle 0 N/A 1

Reading within Non-Erase Suspended

Sector Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A 0

20 Am29F100

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +13.5 V

All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pin is –0.5 V . During

voltage transitions, inputs may overshoot V SS to –2.0 V

for periods of up to 20 ns. See Figure 6. Maximum DC

voltage on input and I/O pins is VCC + 0.5 V. During volt-

age transi ti ons , inp ut and I/O pi ns may overs hoot to VCC

+ 2.0 V for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9 pin is –0.5V. During

voltage transitions, A9 pins may overshoot VSS to –2.0 V

for periods of up to 20 ns. See Figure 6. Maximum DC in-

put voltage on A9 is +12.5 V which may overshoot to 13.5

V for periods up to 20 ns.

3. No more than one output shorted at a time. Duration of

the short circuit should not be greater than one second.

Stresse s above thos e listed unde r “Absolute Ma ximum Rat-

ings” may caus e per ma nent d amage to the device. This is a

stress ratin g on ly; fun ctio nal ope ration of t he d evice at the se

or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

Figure 6. Maximum Negative Overshoot

Waveform

Figure 7. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Case Temperature (TA) . . . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Case Temperature (TA) . . . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Case Temperature (TA) . . . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . .+4.50 V to +5.50 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

18926C-11

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

18926C-12

Am29F100 21

DC CHARACTERISTICS

TTL/NMOS Compatible

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.

2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Description Min Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Lea ka ge Cur ren t VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Current (Note 1) VCC = VCC Max, CE# = VIL,

OE# = VIH

Byte 40 mA

Word 50 mA

ICC2 VCC Active Current (Notes 2, 3) VCC = VCC Max, CE# = VIL, OE# = VIH 60 mA

ICC3 VCC Standby Cur ren t VCC = VCC Max, CE# = VIH, OE# = VIH 1.0 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VID Voltage for Autoselect and

Tem por ary Se ctor Unpro tec t VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH Output Hig h Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VLKO Low VCC Lock-out Voltage 3.2 4.2 V

22 Am29F100

DC CHARACTERISTICS (continued)

CMOS Compatible

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.

2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Description Min Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Current (Note 1) VCC = VCC Max,

CE# = VIL, OE# = VIH

Byte 40 mA

Word 50

ICC2 VCC Active Current (Notes 2, 3) VCC = VCC Max, CE# = VIL, OE# = VIH 60 mA

ICC3 VCC Standby Current VCC = VCC Max, OE# = VIH,

CE# and RESET# = VCC ± 0.5 V 100 µA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.5 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC –0.4 V

VLKO Low VCC Lock-out Voltage 3.2 4.2 V

Am29F100 23

TEST CONDITIONS

Table 7. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

18926C-13

Figure 8. Test Setup

Note: Diodes are IN3064 or equivalent

Test Condition -70 All others Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8 V

Output timing measurement

reference levels 1.5 2.0 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

24 Am29F100

AC CHARACTERISTICS

Read-only Operations Characteristics

Notes:

1. Not 100% tested.

2. Output Driver Disable Time.

3. See Figure 8 and Table 7 for test specifications.

Parameter

Symbol

Parameter Description Test Setup -70 -90 -120 -150 UnitJEDEC Std.

tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 70 90 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 30 35 50 55 ns

tEHQZ tDF Chip Enable to Output High Z (Notes 1, 2) Max 20 20 30 35 ns

tGHQZ tDF Output Enable to Output High Z

(Notes 1, 2) Max 20 20 30 35 ns

tOEH Output Enable Hold Time (Note 1) Read Min 0 ns

Toggle and Data

Polling Min 10 ns

tAXQX tOH Output Hold Time From Addresses CE# or

OE#, Whichever Occurs First Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

18926C-14

Figure 9. Read Operations Timings

Am29F100 25

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (Se e Note ) Min 50 ns

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

18926C-15

Figure 10. RESET# Timings

26 Am29F100

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

-70 -90 -120 -150JEDEC Std. Description Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 20 20 30 35 ns

tFHQV BYTE# Switching High to Output Active Min 70 90 120 150 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Ou tpu t

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

18926C-16

Figure 11. BYTE# Timings for Read Operations

Note:

Refer to the Erase/Program Operations table for tAS and tAH spe cific ati ons.

18926C-17

Figure 12. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

Am29F100 27

AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Symbol

Parameter Description -70 -90 -120 -150 UnitJEDEC Standard

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 45 45 50 50 ns

tDVWH tDS Data Setup Time Min 30 45 50 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tGHWL tGHWL Read Recover Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 35 45 50 50 ns

tWHWL tWPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 14 µs

tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.5 sec

tVCS VCC Set Up Time (Note 1) Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 30 35 50 55 ns

28 Am29F100

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tGHWL

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

Notes:

1. PA = program address, PD = program data, DOUT is the true data at the program address.

2. Illust ration shows device in word mode.

Figure 13. Program Operation Ti m ings

18926C-13

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 14. Chip/Sector Erase Operation Timings

18926C-13

Am29F100 29

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

18926C-18

Figure 15. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

tOE

DQ6

RY/BY#

tBUSY

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

tACC

tRC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

18926C-19

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

30 Am29F100

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std. Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

RESET#

tVIDR

12 V

0 or 5 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5 V

18926C-20

Figure 17. Temporary Sector Unprotect Timi ng Diagram

Am29F100 31

AC CHARACTERISTICS

Erase and Program Operations

Alternate CE# Controlled Writes

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Symbol

Parameter Description -70 -90 -120 -150 UnitJEDEC Standard

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 50 50 ns

tDVEH tDS Data Setup Time Min 30 45 50 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recover Time Before Write Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 35 45 50 50 ns

tEHEL tCPH CE# Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 14 µs

tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.5 sec

32 Am29F100

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

18926C-21

Figure 18. Alternate CE# Controlled Write Operation Timings

Am29F100 33

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 5.0 V VCC, 100,0 00 cyc les. Additio na lly,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 4.5 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level ov erhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.

LATCHUP CHARACTERISTIC

Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25

C, f = 1.0 MHz.

DATA RETENTION

Parameter

Limits

CommentsTyp (Note 1) Max (Note 2) Unit

Chip/Sector Erase Time 1.5 15 sec Excludes 00h programming prior to

erasure (Note 4)

Byte Programming Time 14 1000 µsExcludes system-level overhead

(Note 5)

Word Programming Time 28 2000 µs

Chip Programming Time (Note 3) 1.8 12.5 sec

Parameter Description Min Max

Input Voltage with respect to VSS on I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Conditions Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 8 10 pF

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C10 Years

125°C20 Years

34 Am29F100

PH YS ICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

44 23

122

13.10

13.50 15.70

16.30

1.27 NOM.

28.00

28.40

2.17

2.45

0.35

0.50 0.10

0.35

2.80

MAX. SEATING

PLANE

16-038-SO44-2

SO 044

DF83

8-8-96 lv

0.10

0.21

0.60

1.00

0°

8°

END VIEW

SIDE VIEW

TOP VIEW

Am29F100 35

PH YS ICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2

TS 048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

18.30

18.50

19.80

20.20

11.90

12.10

SEATING PLANE

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48

TSR048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

36 Am29F100

REVISION SUMMARY FOR AM29F100

Revision B+1

Product Selector Guide

Replaced the -75 column (70 ns, ±5%) with the -70 col-

umn (70 ns, ±10%).

Ordering Information, Standard Products

The -70 designation is now listed in the part number ex-

ample.

Valid Combinations:

Replaced the -75 combinations

with -70. The 70 ns speed grade is now available in the

same combinations as the other speed grades.

Operating Ranges

VCC Supply Voltages:

Changed the -75 designation

to -70 .

AC Characteristics

Read Only Operations:

Changed the -75 column head

to -70. All parameters remain the same.

Figure 7, Test Conditions:

Changed CL in Note 1 from -

75 to -70.

Write/Erase/Program Operations:

Changed the -75

column head to -70. Changed byte programming and

chip/sector erase times (tWHWH1 and tWHWH2, respec-

tively).

Switching Waveforms

Temporary Sector Unprotect Timing Diagram, Figure

18:

Corrected the top waveform. RESET# begins at 0

V, then rises to 12 V in tVIDR.

AC Characteristics

Alternate CE# Controlled Writes:

Changed the -75 col-

umn head to -70. Changed byte programming and

chip/sector erase times (tWHWH1 and tWHWH2, respec-

tively).

Erase and Programming Performance

Combined sector and chip erase times, added word

programming times and erase/program cycle times.

Updated specifications.

Revision C

Global

Made formatting and layout consistent with other data

sheets. Used updated common tables and diagrams.

Revision C+1

Table 5, Command Definitions

Address bits A0–A14 are required for unlock cycles.

Therefore, addresses for second and fifth write cycles

are 2AAAh in word mode and 5555h in by te mode. Ad-

dresses for first, third, fourth, and sixth cycles are

5555h in word mode and AAAAh in byte mode. Read

cycles are not affected. Deleted Note 5 to reflect the

correction.

Revision C+2

AC Characteristics

Erase/Program Operations; Erase and Program Oper-

ations Alternate CE# Controlled Wr ites:

Corrected the

notes reference for t WHWH1 and tWHWH2. These param-

eters are 100% tested. Corrected the note reference

for tVCS. This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for tVIDR. This parameter is not

100% tested.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.