ASITM Advanced AS-Interface IC Data Sheet 1 Features 2 AS-i Complete Specification V2.11 compliant Description ASITM is a monolithic CMOS integrated circuit certified for AS-i (Actuator Sensor-interface) networks. AS-i networks are intended for industrial automation. Integrated EEPROM Additional addressing channel using an optoelectronic interface Extended address mode operation as programmable option (up to 62 slaves) High impedance AS-i line input, additional pins for further impedance optimizations DC voltage output, approximately 24 volts, not stabilized 5 volt DC voltage output, stabilized, CMOS logic can be supplied directly (e.g. C) LED status indicator output (compliant to the standard indication recommendation) Integrated watchdog The main advantage of AS-i solutions is that actuators and sensors are connected using a twowire unshielded cable that is easy to install. This cable transports both power and information/data. AS-i network communication is based on the masterslave principle. The network can be extended (to cable lengths greater than 100m) by using the ASITM in the repeater mode configuration. AS-i is a standard for the automation industry based on IEC 62026-2 and EN 50295. The device is available in a 28-pin SSOP package. 3 Block Diagram 1 F 5V 24V 8 MHz 10 F U IN CAP A2SITM U OUT U5R ELECTRONIC INDUCTOR U5RD POWER SUPPLY OSC1/2 OSCILLATOR POWERFAIL DETECTION ASI+ ASI- 4 4 ASIP DIGITAL LOGIC DIx DSR PST ASIN TRANSMIT THERMAL PROTECTION GND2 4 GND1 0V GND Figure 1: Block Diagram Revision 2.2 June 2001 Pages (total): 28 DOx RECEIVE 1 IRD AMP IRD LED FID Px ASITM Advanced AS-Interface IC Data Sheet 4 Pin Description Table 1: Pin Description PIN # PIN NAME TYPE DESCRIPTION 1 ASIP INOUT To be connected to the AS-i-line ASI+ via reverse polarity protection diode 2 ASIN INOUT To be connected to the AS-i-line ASI- 3 0V 4 IRD IN Addressing channel input 5 FID IN Input peripheral fault indication 6 OSC2 INOUT Crystal oscillator (8 MHz x-tal) 7 OSC1 IN 8 DO3 OUT Output of data D3 9 DO2 OUT Output of data D2 10 DO1 OUT Output of data D1 11 DO0 OUT Output of data D0 12 GND 13 P3 I/O Input/output of parameter P3 14 P2 I/O Input/output of parameter P2 / receive strobe in "Master Mode" 15 P1 I/O Input/output of parameter P1 / power fail in "Master Mode" 16 P0 I/O Input/output of parameter P0 / data clock in "Master Mode" 17 DI0 IN Input of data D0 18 DI1 IN Input of data D1 19 DI2 IN Input of data D2 20 DI3 IN Input of data D3 21 PST OUT 22 DSR I/O 23 U5RD 24 LED OUT 25 CAP IN/OUT 26 U5R OUT Internal 5V supply that might be used to supply external circuits as well 27 UOUT OUT Supply of external circuitry (e.g. sensor, actuator, etc.), approx. VUIN minus 7 volt 28 UIN Revision 2.2 June 2001 Pages (total): 28 SUPPLY Common 0V for all ports except ASIP/ASIN (to be connected to ASI- line) Crystal oscillator / external clock input SUPPLY Digital IO ground, must be connected to pin 0V Parameter strobe output Data strobe output/reset input SUPPLY Digital 5V supply input, should be connected to U5R Output LED "AS-i-Diagnosis" / addressing channel output For connection of external RC components SUPPLY Input of the power supply block (usually to be connected to the AS-i-line ASI+ via reverse polarity protection diode) 2 ASITM Advanced AS-Interface IC Data Sheet Pin Configuration 6.2 ASIP 1 28 UIN ASIN 0V 2 3 27 26 UOUT U5R IRD FID 4 5 25 24 CAP LED OSC2 OSC1 6 7 23 22 U5RD DSR DO3 DO2 8 9 21 20 DO1 DO0 GND 10 11 19 18 PST DI3 DI2 12 13 17 16 14 15 P3 P2 A2SITM 5 The receiver detects signals on the AS-i line and delivers the appropriate pulses to the digital logic. The DC value of the input signal is removed and the AC signal is band-pass filtered. The digital output 2 signals are extracted from the sin -shaped input pulses by a set of comparators. The maximum voltage of the first negative pulse determines the threshold level for all following pulses. The maximum value is digitally filtered to guarantee stable conditions (burst spikes have no effect). This approach combines a fast adaptation to changing signal amplitudes with a high detection safety. The receiver delivers positive (P-PULSE) and negative (N-PULSE) pulses to the IC's logic. The logic resets the comparators after receiving the REC-RESET signal. When the receiver is turned on, the transmitter is turned off to reduce power consumption. DI1 DI0 P0 P1 6.3 Figure 2: Pin Configuration, 28-Pin SSOP 6 6.1 Transmitter The transmitter draws a modulated current between ASIP and ASIN pins to generate the communication signals. The shape of the current corresponds to the 2 integral of a sin -function. The transmitter uses a current DAC and a high current driver. In order to activate high current drive capability, a small current will be turned on automatically prior to each transmission (slave mode only). The current will be ramped up slowly to avoid false voltage pulses on the AS-I line. The amount of circuitry between ASI+ and ASI- pins is minimized to allow high impedance values. When the transmitter is turned on, the receiver is turned off to reduce power consumption. Functional Block Description Power Supply An on-chip electronic inductor provides a de-coupled voltage at pin UOUT and the power supply regulates the internal 5V operating voltage. The de-coupling circuit (electronic coil) is connected between UIN and UOUT pins and guarantees a high impedance seen at UIN. An external capacitor and resistor are required to allow a low-pass filter with a very high time constant. This high time-constant value is necessary to maximize the input impedance. The de-coupling circuit limits the current that can be drawn from UOUT. The power supply will shut down the de-coupling circuit in case of an overload condition to prevent a total malfunction of the complete AS-i line. The regulated 5 volt supply voltage is connected to pin U5R. Two external capacitors are necessary to cope with fast internal and external load changes (spikes). Current drawn from pin U5R (up to 4 mA) has to be subtracted from the total load current. The power supply circuit dissipates the major amount of power. 6.4 Digital Logic The digital logic block performs analysis of the received signal, controls reaction of the IC, transmits slave response, switches I/O-ports, and controls the internal EEPROM. Its principal function is described in detail in section 7. 6.5 Protection Circuitry The device has several protection cells that prevent disruption and malfunction of the complete AS-i line. The total power dissipation shall not exceed the specified values of Figure 6. The ground reference voltage for both UOUT and U5R is defined by the 0V pin. This pin must be connected to ASI- (ref. Figure 1). Revision 2.2 June 2001 Pages (total): 28 Receiver The thermal detection shuts down the power supply in case of over-heating condition (temperature > 140C typically for more than 2 seconds) and when UOUT is shorted to GND for more than 2 seconds. 3 ASITM Advanced AS-Interface IC Data Sheet mode (master/repeater mode only), input signals have to be CMOS levels between 0V and VU5R. The device can only be reactivated by a power-on reset. An over-heating condition can occur by overloading any output pin. Therefore, the circuit monitors the operating conditions of the power supply (effectively monitors UOUT) and measures the temperature of the silicon. The power-fail detector consists of a comparator that generates a logic signal in case the power supply drops below 22VDC (Power-Fail) for a time of more than tLoff (0.8 0.1 ms). The power fail signal will be presented at pin P1 in master mode only. Infrared Diode Input The photo current input can be used as an alternative communication pin in slave mode. The IRD circuitry will be turned off when the communication has been switched to AS-i line. In Slave mode the logic sets IRD input to photo-detector mode and disables CMOS mode. In this photo-detector mode, signals of an external photo diode are amplified. In CMOS U5R OSCILLATOR DATA-IN P-PULSE N-PULSE RESET PARAM IRD In GND2 GND1 0V GND CMOS AC INPUT Current STAGE INPUT OUTPUT STAGE INPUT STAGE IRD LED FID Figure 3: Functional Block Diagram Revision 2.2 June 2001 Pages (total): 28 4 INPUT STAGE DI(3:0) I/O STAGE DSR OUTPUT STAGE PST INPUT STAGE OUT IN OVER-HEAT FAULT SEND-SBY LED THERMAL PROTECTION SEND-D OUT TRANSMIT PARAM STRB Logic ASIN DO(3:0) DATA-STRB DIGITAL LOGIC REC-RESET AC ASIP PARAM RECEIVE OUTPUT STAGE IN POWER-FAIL OSC1/2 CLK POWERFAIL DETECTION POWER SUPPLY RESET ELECTRONIC INDUCTOR U5RD DATA-OUT UOUT POWER-ON CAP A2SITM Power-fail detection monitors the value of the ASIP voltage. It will activate a logic signal if power fails for more than 1ms. The device is then buffered by the external capacitor at UOUT and the internal circuitry will be reset when U5R supply voltage fails. UOUT U IN Power-Fail Detection SHUT-DOWN 6.6 6.7 P(3:0) OUTPUT STAGE ASITM Advanced AS-Interface IC Data Sheet 7 Description of Digital Logic The digital logic is structured in four (4) parts (see Figure 4): 1. the UART, which analyses the incoming signal from the AS-i line and ensures correct timing of output signals; 2. the STATE MACHINE, reaction of the IC; which controls 3. the PORTS, which contain registers and digital I/O's; 4. and finally the EPROM, which contains the non2 volatile data of the A SITM circuit. Digital Logic P-PULSE P-Pulse N-PULSE REC -REG -0 DO-REG -0 DATA-OUT-0 REC -REG -1 DO-REG -1 DATA-OUT-1 REC -REG -2 DO-REG -2 REC -REG -3 DO-REG -3 DATA-OUT-2 DATA-OUT-3 REC -REG -5 SEND-SBY REC-RESET UART REC -REG -6 REC -REG -7 REC -REG -8 REC -REG -9 REC -REG -10 REC-STRB SEND -REG-0 DI-REG -0 DATA-STRB DI-REG -1 RESET DI-REG -2 DATA-IN-0 DI-REG -3 DATA-IN-1 PO-REG -0 DATA-IN-2 PO-REG -1 PO-REG -2 DATA-IN-3 PO-REG -3 PARAM-OUT-0 SEND -REG-1 SEND -REG-2 PI-0 SEND -REG-3 PI-1 SEND -STRB PI-2 PI-3 PORTS SEND-D STATE MACHINE REC -REG -4 PARAM-OUT-1 PARAM-OUT-2 PARAM-OUT-3 PARAM-STRB PARAM-IN-0 PARAM-IN-1 E2PROM PARAM-IN-2 PARAM-IN-3 ADD-CLK IRD-IN ADD-OUT FAULT-IN ADD-IN LED-OUT POWER-FAIL OVER-HEAT POWER-ON RESET U OUT SHOUTDOWN Figure 4: Digital Logic Revision 2.2 June 2001 Pages (total): 28 5 the ASITM Advanced AS-Interface IC Data Sheet 7.1 The IRD signal is connected with Send-Muxer to SEND-D via ADD-IN. The IRD signal is latched every 500 ns as long as there is activity on the input pin. If there is a high level on the IRD input longer then 7.0 s, Activity-Checker will recognize this as no activity and Receive-Muxer is returning to idle state. The information on pin IRD is transported to pin SEND-D with a delay of 2.0 s up to 2.5 s. The sender is always in non-standby mode. The SENDSBY signal is constant low and there is no generation of ADD-CLK. UART Operational Modes 7.1.1 Master/Repeater Mode 7.1.1.1 IRD Input (CMOS Input) The IC sends signal retrieved from pin IRD to AS-i line as an AS-i telegram. The input signal is Manchester-coded and active low. A falling edge of the IRD signal, which is conducted to ADD-IN, starts the receiving process and triggers the ActivityChecker. Receive-Muxer selects pin IRD as input for the receive data. P-PULSE N-PULSE PULSE ENCODER UART REC -REG -0 RECEIVE MUXER ADD-IN REC -REG -1 REC -REG -2 REC -REG -3 ACTIVITY CHECKER REC -REG -4 MAN CODE CHECKER RECEIVE REGISTER S END -REG -2 S END -REG -3 REC -REG -6 REC -REG -7 REC -REG -8 S END -REG -0 S END -REG -1 REC -REG -5 REC -REG -9 R EC-R EG -10 SEND REGISTER SEND-D SEND MUXER STROBE UNIT SEND-STRB REC-STRB CONTROL UNIT Figure 5: UART Block Diagram Revision 2.2 June 2001 Pages (total): 28 ADD-OUT 6 ADD-CLK SEND-SBY REC-RESET ASITM Advanced AS-Interface IC Data Sheet 7.1.1.2 7.1.1.3 AS-i Input Functional assignments of some IC ports depend on the operational mode of the IC. Thus, these ports perform multiple functions that are related to a particular mode of the IC. A signal on the AS-i-line generates signals at the receiver output that are pulse coded with a minimal pulse width of 750 ns up to 875 ns. A pulse on the AS-i line starts the receiver and triggers the ActivityChecker through N-PULSE or P-PULSE. The Receive-Muxer selects AS-i-line pins as input for the receive data. The N-PULSE and P-PULSE signals are latched every 500 ns as long as there is activity on the input pins. If there is a pulse distance on the AS-i-line inputs longer then 7.0 s, the receiver will recognize this as no activity and the Receive-Muxer is going to the idle state. In Master Mode, following signals and ports are connected: The Pulse-Encoder is used to convert the active high pulse-coded signal to a active low Manchester-IIcoded (MAN) signal. It will also check the pulse stream for timing and pulse errors (e.g. alternation error). In Master/Repeater mode the Pulse-Encoder additionally resynchronizes an error-free MAN telegram into a proper 3 s time base. This is to eliminate the pulse jitter of the transformed AS-i telegram. The synchronized MAN signal is sent to ADD-OUT through the Send-Muxer. ADD-OUT is connected to LED-OUT on a higher hierarchy level. All in all, information on the AS-i-line pins is transported to pin LED-OUT with a delay of 2.5 s up to 3.0 s. In Master/Repeater mode the sender is never in standby mode, hence SEND-SBY signal is always low. PIN Slave Function Master Repeater P0 Parameter output port bit 0 REC-CLK REC-CLK P1 Parameter output port bit 1 POWERFAIL - P2 Parameter output port bit 2 REC-STRB - LED LED output/addressing channel output MAN-OUT MAN-OUT IRD Fault indicator input/addressing channel input MAN-IN MAN-IN 7.1.2 Slave Mode After IC-reset, Receive-Muxer is watching the two input channels (AS-i-line and IRD pin) depending on a multiplex select signal MPX. MPX has a frequency of about 1.0 kHz. If MPX is low, the Receive-Muxer selects the AS-i-line and vice versa if it is high, it selects the IRD pin as data input. The channel, from which a valid master call is received first, will be locked until the next IC-reset occurs. A generation of ADD-CLK is provided to simplify external processing of Manchester-coded data. The rising edge of the ADD-CLK signal is in the middle of the second half of the Manchester data assuring that correct binary data can be clocked into a shift register. The ADD-CLK starts with a rising edge 2.0 s after the falling edge of the start bit at ADD-OUT with a period of 6.0 s and a ratio of 1:1. The last rising edge of the ADD-CLK signal occurs 2.0 s after the falling edge of the end bit at ADD-OUT. 7.1.2.1 IRD Input Mode (Photo Diode Input) The photo diode current on the IRD input is Manchester-coded and low active (ref. 8.2.2 Addressing Channel Input IRD). A low level of the IRD signal starts the receiver and triggers the Activity-Checker. The Control-Unit is enabling the Receive-Register and the received information is clocked every 6 s into the Receive-Register. If there is a high level on the IRD input longer then 7.0 s, the Control-Unit will recognize this as no activity and the Receive-Register will be disabled. If the received information is a correct master call with Start-Bit, eleven Data-Bits, Parity-Bit, End-Bit, and following pause of either greater than 6.0 s (Synchronous Mode) or 18.0 s (Asynchronous Mode), the UART generates the internal active high REC-STRB signal with a pulse width of 500 ns. If the received signal in the Master Mode is a valid slave answer with start bit, four (4) data bits, parity, and end bit and if a pause is following with a length greater than 6.0 s, the UART generates the active high REC-STRB signal with a pulse width of 500 ns. The REC-STRB signal is connected to the P2 Parameter Output in this mode. It appears 10.0 to 10.5 s after the rising edge of the end bit on AS-iline. Revision 2.2 June 2001 Pages (total): 28 Ports 7 ASITM Advanced AS-Interface IC Data Sheet If the received telegram contained an error, the Control-Unit will not generate the REC-STRB signal but go to its asynchronous state waiting for a pause at the IRD input. After a pause was detected, the UART is ready to receive the next telegram from the IRD input. The Pulse-Encoder is used to convert the active high pulse coded signal to an active low Manchester-IIcoded (MAN) signal. It will also check the pulse stream for timing and pulse errors (e.g. alternation error). The Control-Unit enables the Receive-Register so that the received information can be clocked in every 6 s. If there is a pulse distance on the AS-iline input longer than 7.0 s, the Control-Unit recognizes this as no activity and disables the Receive-Register. If a REC-STRB signal is generated, it occurs 9.5 s up to 10.0 s (Synchronous Mode) or 21.0 s up to 21.5 s (Asynchronous Mode), respectively, after the rising edge of the End-Bit on the IRD pin signal. If the slave was in asynchronous state, it now transforms to synchronous state. The Rec-Muxer is locked to the IRD input until the next IC-reset. After the generation of a REC-STRB signal the Control-Unit is waiting for about 6.0 s for the SEND-STRB to be generated by the Main-State-Machine. If the received information is a correct master call with Start-Bit, eleven (11) Data-Bits, Parity-Bit, EndBit, and following pause of either greater than 6.0 s (Synchronous Mode) or 18.0 s (Asynchronous Mode), the UART generates the internal active high REC-STRB signal. If the received telegram contained an error, the Control-Unit will not generate the RECSTRB signal but go to its asynchronous state waiting for a pause at the AS-i line input. After a pause was detected the UART is ready to receive the next telegram from the AS-i line input. If the Control-Unit receives the active high SENDSTRB signal, it starts the transmission of the SendRegister data. Therefore, the Send-Register data will be converted to an active low Manchester II-coded (MAN) signal which is sent to the LED-OUT pin via ADD-OUT. The first falling edge of the MAN signal occurs 11.75 s (Synchronous Mode) or 12.25 s (Asynchronous Mode) after the rising edge of the REC-STRB signal. Hence, the delay from the rising edge of the End-Bit of the master call (IRD input) to the first falling edge of the slave response (LED output) is 21.25 to 21.75 s (Synchronous Mode) or 33.25 to 33.75 s (Asynchronous Mode). After the pause was detected, the UART is ready to receive the next telegram from the IRD input. If a REC-STRB signal is generated, it occurs 10.0 to 10.5 s (Synchronous Mode) or 21.5 to 22 s (Asynchronous Mode), respectively, after the rising edge (receiver comparator switching point) of the End-Bit on the AS-i line input. If the slave was in asynchronous state, it now transforms to synchronous state. The Rec-Muxer is locked to the AS-i line input until the next IC-reset. After the generation of a REC-STRB signal the Control-Unit is waiting for about 6.0 s for the SEND-STRB to be generated by the Main-State-Machine. In case the Control-Unit will not receive a SENDSTRB signal within the given time frame (for instance, if this slave was not addressed), it will check for activity on the IRD input. Otherwise, it will just wait for the end of the response time (60 s). In both cases the Control-Unit stays synchronous. Once a slave pause was detected, the UART is ready to receive the next telegram from the IRD input. 7.1.2.2 If the Control-Unit receives the active high SENDSTRB signal (pulse width 500 ns), it starts the transmission of the Send-Register data. Therefore, the Send-Register data will be converted to an active low Manchester II-coded (MAN) signal which is sent to the AS-i line transmitter via SEND-D. The first falling edge of the MAN signal occurs 11.75 s (Synchronous Mode) or 12.25 s (Asynchronous Mode) after the rising edge of the REC-STRB signal. AS-i Input Mode A signal on the AS-i-line generates two pulse-coded signals (N-PULSE, P-PULSE) at the receiver output with a minimum pulse width of 750 to 875 ns. A pulse on the AS-i line starts the receiver and triggers the Activity-Checker through N-PULSE or P-PULSE. Revision 2.2 June 2001 Pages (total): 28 Hence, the delay from the rising edge of the End-Bit of the master call (AS-i input) to the first falling edge of the slave response (AS-i output) is 21.75 to 22.25 s (Synchronous Mode) or 33.75 to 34.25 s (Asynchronous Mode). 8 ASITM Advanced AS-Interface IC Data Sheet An active FID (logic high) signal shall cause a flashing status LED (frequency approx. 2Hz) and Bit 1 of the Status-Register (S1) shall be set as well. If FID The SEND-SBY will always be set low 0.5 s after the rising edge of REC-STRB. This is to turn on the transmitter and let it settle at its operation point. The small offset current, which is required to operate the transmitter, will be ramped up slowly to avoid any false voltage pulses on the AS-i line. is not active (logic low), S1 is cleared. In that case the status LED operation depends on the DataExchange-Disable flag. If all data is sent, the Control-Unit sets the sender in standby mode (SEND-SBY is high) and checks for a slave pause on the AS-i line input. After the pause was detected, the UART is ready to receive the next telegram from the AS-i line input. If the Data-Exchange-Disable flag is set (no data exchange allowed) a steady-on LED shall indicate that the communication is off. Note: An active FID has priority and will cause a flashing LED even if the Data-Exchange-Disable flag is set. In case the Control-Unit will not receive a SENDSTRB signal within the given time frame (for instance, if this slave was not addressed), it will check for activity on the AS-i line. If any activity is detected in a time frame of about 60 s (another slave is transmitting data), the Control-Unit will wait for the next pause (slave pause). Otherwise, it will just wait for the end of the response time (60 s). In both cases the Control-Unit stays synchronous. Once a slave pause was detected, the UART is ready to receive the next telegram from the AS-i line input. 7.1.2.3 If the UART has selected the IRD input channel, the LED output should not toggle. In this mode the LED pin does not operate as indicator LED output. Hence, periphery failures or status information will not be signaled. If OVER-HEAT is TRUE the IC will be put into shutdown and stay there until the next power-on reset occurs. If INVERT-DATA-IN is TRUE, all input data is inverted. This feature will simplify the circuitry for NPN-inputs. Ports In the Slave Mode it is not necessary to decode the IO-Configuration; all Data-Out and Data-In signals are directly connected to the respective port. 7.1.2.4 If the Multiplex-Flag-nvmem is TRUE, the output ports will switch to high impedance state for a certain period of time following the rising edge of the DataStrobe. The so-called Main-State-Machine performs the 2 central control of the A SITM IC concerning the mode control, the access to the EEPROM; the processing of master requests; and the control of the IC ports. There is a register interface (receive and send register) between Main-State-Machine and UART (controls the serial data communication channels). This register interface is used to exchange communication data between UART and Main-StateMachine. In contrast to the master mode, the parameter port pin performs a parameter input and output function according to the AS-i Complete Specification. Also compliant to the AS-I Complete Specification, The IC contains an independent watchdog which can be activated by setting Watchdog-active-Flag-nvmem to TRUE. To avoid the situation in which a single slave IC is accidentally locked in a not allowed state and thereby could jeopardize the entire system, all prohibited states of the state machine will lead to a RESET. This means that the IC will execute its reset procedure by performing the instruction "Reset Slave (RES)". If Watchdog-Flag is TRUE (no data exchange for more than 40 ms) and Watchdog-active-Flag-nvmem is TRUE, a reset (INIT) will be performed. Revision 2.2 June 2001 Pages (total): 28 State Machine 9 ASITM Advanced AS-Interface IC Data Sheet 7.2 7.3 Summary of Master Calls Program Mode Provided that the non-volatile configuration flag, Program-Mode-Disable, has not been set, the device can be transferred in program mode by utilizing the "Enter Program Mode" call. In the following diagram all Master Calls that will be 2 decoded by the A SITM are listed. The "Enter Program Mode" call is intended for factory programming of the IC only. 2 Please refer to the A SITM Application Note [4] for details of the programming process. In order to achieve EEPROM firmware protection and to comply to the complete AS-i specification, the call "Enter Program Mode" has to be deactivated before shipment of the slave. AS-i Complete Specification compliance note: In order to ensure full compliance with the AS-i Complete Specification, the Program-Mode-Disable flag must be set in the final manufacturing and configuration process before an AS-i slave device is being delivered to field application users. Table 2: ASI Master Calls and Related Slave Responses Instruction Master Request A2 A1 A0 MNE ST CB A4 A3 Data Exchange DEXG 0 0 A4 A3 A2 A1 A0 0 Write Parameter WPAR 0 0 A4 A3 A2 A1 A0 1 Address Assignment ADRA 0 0 0 0 0 0 0 A4 A3 Write Extented ID Code-1 WID1 0 1 0 0 0 0 0 0 Delete Address DELA 0 1 A4 A3 A2 A1 A0 0 Reset Slave RES 0 1 A4 A3 A2 A1 A0 1 Read IO Configuration RDIO 0 1 A4 A3 A2 A1 A0 1 Read ID Code RDID 0 1 A4 A3 A2 A1 A0 1 Read ID Code-1 RID1 0 1 A4 A3 A2 A1 A0 1 Read ID Code-2 RID2 0 1 A4 A3 A2 A1 A0 1 Read Status RDST 0 1 A4 A3 A2 A1 A0 1 Broadcast (Reset) BR01 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 Enter Program Mode PRGM I4 I3 I2 D3 D2 ~Sel P3 P2 ~Sel I0 PB EB SB D1 D0 PB 1 0 P1 P0 PB 1 0 A2 A1 A0 PB 1 0 0 1 1 0 PB 1 ID3 ID2 ID1 ID0 PB 1 0 0 0 0 0 PB 1 0 Sel 0 0 0 PB 1 0 0 0 0 0 PB 1 1 0 0 PB 1 0 0 1 1 0 PB 1 0 0 0 PB 1 0 IO3 IO2 IO1 IO0 PB 1 0 0 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1 0 1 0 PB 1 0 ID3 ID2 ID1 ID0 PB 1 0 1 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1 1 1 0 PB 1 0 S3 S2 S1 S0 PB 1 0 1 0 1 PB 1 --- no slave response --- 1 1 0 1 PB 1 --- no slave response --- 1 ~Sel 0 Sel 0 Sel 0 Sel 0 Sel 1 ~Sel I3 D3 E3 P3 I3 Slave Response I2 I1 I0 PB D2 D1 D0 PB E2 E1 E0 P2 P1 P0 PB I2 I1 I0 I1 EB 1 1 Note: In extended address mode the "Select Bit" defines whether the A-Slave or B-Slave is being addressed. Dependent on the type of master call the I3 bit carries the select bit information (Sel) or the inverted select bit information (~Sel). Revision 2.2 June 2001 Pages (total): 28 10 ASITM Advanced AS-Interface IC Data Sheet 8 Electrical Specification 8.1 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may effect device performance, functionality, and reliability. Table 3: Absolute Maximum Ratings SYMBOL PARAMETER MIN. MAX. UNITS V0V ,VGND Voltage reference VASIP 0 0 V Positive AS-i supply voltage -0.3 40 V VASIN Negative AS-i supply voltage -0.3 20 V 1 VASIP-ASIN Voltage difference from ASIP to ASIN (VASIP - VASIN) -0.3 40 V 2 VASIPP AS-i supply pulse voltage, voltage difference between pins ASIP and ASIN (from ASIP to ASIN) 50 V 3 VUIN Aux. power supply input voltage 40 V VUINPV Aux. power supply input voltage pulse 50 V 3 Vinputs1 Voltage at pins DI3 - DI0, DO3 - DO0, P3 - P0, DSR, PST, LED, FID, UOUT -0.3 VUIN + 0.3 V Vinputs1 40V Vinputs2 Voltage at pins OSC1, OSC2, IRD, CAP, U5R, U5RD -0.3 7 V Iin Input current into any pin except supply pins -25 25 mA H Humidity non-condensing VHBM1 Electrostatic discharge - human body model (HBM1) 4000 V 5 VHBM2 Electrostatic discharge - human body model (HBM2) 2000 V 6 VEDM Electrostatic discharge - equipment discharge model (EDM) 400 V 7 STG Storage temperature -55 Ptot Total power dissipation 1 2 3 4 5 6 7 8 -0.3 NOTE 4 125 C 0.85 W 8 ASIN-pin shall be shorted to 0V-pin on PCB. Reverse polarity protection has to be performed externally. Pulse with 50s, repetition rate 0.5 Hz. Defined in DIN 40040 cond. F. HBM1: C = 100pF charged to VHBM1 with resistor R = 1.5k in series, valid for ASIP-ASIN only. HBM2: C = 100pF charged to VHBM2 with resistor R = 1.5k in series, valid for all pins except ASIP-ASIN. EDM: C = 200pF charged to VEDM with no resistor in series, valid for ASIP-ASIN only. At maximum operating temperature, the allowed total power dissipation depends on the additional thermal resistance from case to ambient and on the operation ambient temperature (see Figure 6). CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to high-energy electrostatic discharge. Revision 2.2 June 2001 Pages (total): 28 11 ASITM Advanced AS-Interface IC Data Sheet Ptot = f (Ta); 1L / 2L = 1 layer / 2 layer PCB 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 Ptot (2L) Ptot (1L) -25 0 25 50 75 Ta 100 Figure 6: Maximum Power Dissipation, PTOT = f(Ambient Temperature) Table 4: Operating Conditions SYMBOL PARAMETER MIN. MAX. UNITS NOTE VUIN Positive supply voltage 16 33.1 V 1 VASIN Negative AS-i supply voltage 0 0 V 2 V0V, VGND Negative supply voltage 0 0 V IASI Supply current at VASI = 30V 9 mA ICL1 Max. output sink current at pins DO3 - DO0, DSR 10 mA ICL2 Max. output sink current at pins P0 - P3, PST 10 mA amb Ambient temperature range, operating range 85 C -25 3 1 DC voltage 2 ASIN shall be shorted with 0V to ensure proper functionality of transmitter circuit. 3 fc = 8.000 MHz, no load at any pin without reaction of the circuit, ASIP is short-cut to UIN and ASIN to 0V respectively. 8.2 DC and AC Characteristics All parameters are valid for the recommended range of VASIP - VASIN, VUIN - V0V, and amb. The devices are tested within the recommended range of VASIP - VASIN, VIN - V0V, amb = +25C (+ 85C and - 25C on sample base only) unless otherwise stated. Unused input pins shall be connected to a suitable potential within the application circuit because there are no internal pull-up/down resistors. It is recommended to connect these pins either to 0V or via resistor to UOUT or U5R respectively. With an external LOW signal at the data strobe pin DSR (pull-down open drain driver) for more than 44s, the IC will execute its reset procedure. During power on procedure all data and parameter ports will stay on highimpedance state. If the IC has been put in its initialization procedure by an external reset via DSR, the LED pin should not be toggled externally to avoid that the IC control logic transfers to test mode. Revision 2.2 June 2001 Pages (total): 28 12 ASITM Advanced AS-Interface IC Data Sheet 8.2.1 Digital Input and Output Pins Table 5: Input/Output Voltage and Current SYMBOL PARAMETER MIN. MAX. UNITS NOTE Pins DI0 - DI3, P0 - P3, DSR, FID, PST VIL Voltage range for input "low" level, not P0 - P3 0 2.5 V VIL Voltage range for input "low" level, only P0 - P3 0 2.4 V VIH Voltage range for input "high" level 3.5 VUOUT V VHYST Hysteresis for switching level 0.25 IIL Current range for input "low" level -20 -5 A IIH Current range for input "high" level -10 10 A VO = 5V IIHV Current range for high voltage input 2 mA VO = 30V V 1 Pins DO0 - DO3, P0 - P3, DSR, PST VOL1 Voltage range for output "low" level 0 1 V IOL1 = 10mA VOL2 Voltage range for output "low" level 0 0.4 V IOL2 = 2mA IOH Output leakage current -10 10 A VOH = 4.5V CDL Capacitance at pin DSR 10 pF 2 0 1 V IOL1 = 10mA -10 30 A VOH = 40V Pin LED VOL Voltage range for output "low" level IOH Output leakage current 3 4 1 Switching level approximately 3V, i.e. 3V VHYST. 2 For higher capacitive load an external pull-up resistor connected to UOUT is necessary to reach VICH 3.5V at DSR in less than 35 s after beginning of DSR = Low pulse, otherwise a reset will be executed. 3 The output driver sends a "low" (LED on). 4 The output driver sends a "high" (equivalent to tri-state, LED off). Revision 2.2 June 2001 Pages (total): 28 13 ASITM Advanced AS-Interface IC Data Sheet Table 6: Timing Parameter Port SYMBOL PARAMETER MIN. MAX. UNITS NOTE tsetup Valid output data; P0 - P3 to PST-H/L 0.1 0.5 s See Figure 7 tPST PST pulse width 5 6 s tPI-latch PST-H/L to parameter input latch 11 13.5 s tCYCLE Next cycle 150 s 1 The parameter input data must be stable within the period that is defined by minimum and maximum tPI-latch. tCYCLE tsetup tPST PST keep stable PO0-PO3 Parameter port output data min max tPI-latch parameter input value (PIx) = parameter output value (POx) wired AND with external signal source value Figure 7: Timing Diagram Parameter Port P0 - P3 Revision 2.2 June 2001 Pages (total): 28 14 1 ASITM Advanced AS-Interface IC Data Sheet Table 7: Timing Data Port Outputs SYMBOL PARAMETER MIN. MAX. UNITS NOTE tsetup Valid output data; DO0 - DO3 to DSR-H/L 0.1 0.5 s Figure 8 thold Valid output data; DO0 - DO3 to DSR-L/H 0.1 0.5 s tDSTR DSR pulse width 5 6 s tDI-latch DSR-H/L to data input latch 11 13.5 s tCYCLE Next cycle 150 s 1 The data input must be stable within the period that is defined by minimum and maximum of tDI-latch. tCYCLE tsetup tDSR DSR data remains, if multiplex flag is not set DO0-DO3 hi-z, if multiplex flag is set Data port output data keep stable thold DI0-DI3 Data port input data min tDI-latch Figure 8: Timing Diagram Data Port DO0 - DO3 Revision 2.2 June 2001 Pages (total): 28 15 max 1 ASITM Advanced AS-Interface IC Data Sheet Table 8: Timing Reset Signal SYMBOL PARAMETER tALM1 MIN. MAX. UNITS Ext. DSR (no reset) 35 s tALM2 Ext. DSR to DO0 - DO3 Hi-Z 44 s tRESET1 Reset time after DSR = external L ->H transition 2 ms DSR NOTE tRESET1 >0 hi-z DO0-DO3 Data port output data PO0-PO3 Parameter port output data hi-z tALM1 tALM2 Figure 9: Timing Diagram External Reset via DSR 8.2.2 Addressing Channel Input IRD The addressing channel input IRD is a dedicated photo-diode input. The photo-diode can be connected to the pins IRD and 0V directly. The IRD input is a AC current input. A valid signal at the current input has to have a certain amplitude (range) and should not exceed a certain offset value (see Figure 10 and Table 9). A logic "low" at the IRD input will be detected, if the present signal value drops below IIRDO, and a "high" will be detected, if its present value is greater than IIRDO + IIRDA. IRD input current MAX IIRDA MIN IIRDA MAX IIRDO time Figure 10: Photo Current Waveforms Revision 2.2 June 2001 Pages (total): 28 16 ASITM Advanced AS-Interface IC Data Sheet Table 9: AC Current Amplitude of IR Diode Input in Slave Mode SYMBOL PARAMETER IIRDO Input current offset IIRDA Input current amplitude MIN. MAX. UNITS NOTE 10 APP 10 100 APP MIN. MAX. Table 10: Digital Input IRD in Master/Repeater Mode SYMBOL PARAMETER UNITS NOTE VIL Voltage range for input "low" level 0 2.5 V VIH Voltage range for input "high" level 3.5 VU5R V Tr /Tf Rise/fall time 100 ns 1 1 In order to avoid jittery on the AS-i line, the rise/fall time of the IRD input signal should be as low as possible. 8.2.3 Fault Indication Input, FID The fault indication input FID is a digital input dedicated for a periphery fault messaging signal (for properties see Table 5). The S1 status bit is equivalent to the FID input signal. A FID transition will occur at S1 with a certain delay, because a synchronizer circuit is put in between. Revision 2.2 June 2001 Pages (total): 28 17 ASITM Advanced AS-Interface IC Data Sheet 8.2.4 Voltage Outputs Table 11: Properties of Voltage Output Pins UOUT and U5R SYMBOL PARAMETER MIN. MAX. UNITS NOTE VUOUT UOUT output supply voltage VUINVDROPmax VUINVDROPmin V IUOUT = 30mA VUOUTp UOUT output voltage pulse deviation 1.5 V 1 tUOUTp UOUT output voltage pulse deviation width 2 ms 1 VDROP Voltage drop from pin UIN to pin UOUT 6.5 7.7 V VUIN > 22V VU5R 5V supply voltage 4.5 5.5 V IUOUT UOUT output supply current 0 30 mA I5V U5R output supply current 0 4 mA Io Total voltage output current IUOUT + I5V 30 mA IUOUTS Short circuit output current 50 CLUOUT Load capacitance at UOUT 10 CL5V Load capacitance at U5R 1 1 COUT = 10 F, output current switches from 0 to 30 mA and vice versa. 2 11.0V < VOUT < 27.6V. Revision 2.2 June 2001 Pages (total): 28 18 mA 470 F F IU5R = 0 2 IUOUT < 26 mA ASITM Advanced AS-Interface IC Data Sheet 8.2.5 AS-i Bus Load The following parameters are determined with short-cut between the pins ASIP and UIN and the pins ASIN and 0V, respectively. Table 12: AS-i Bus Interface Properties (Pins ASIP/ASIN and UIN) SYMBOL PARAMETER MIN. MAX. UNITS NOTE VUIN Input AS-i voltage at UIN VUOUTmin+ VDROPmax VUOUTmax + VDROPmin V 1 ILIN Input current limit at UIN 56 mA VSIG Input signal voltage difference between ASIP and ASIN 3 8 VPP ISIG Modulated output peak current from ASIP to ASIN 55 68 mAP CZener Parasitic capacitance of the external overvoltage protection diode (zener diode) 20 pF 2 RIN1 Equivalent resistor of the device 16 k 2, 3 LIN1 Equivalent inductor of the device 18 mH 2, 3 CIN1 Equivalent capacitor of the device pF 2, 3 RIN2 Equivalent resistor of the device 16 k 2, 3 LIN2 Equivalent inductor of the device 12 18 mH 2, 3 CIN2 Equivalent capacitor of the device 15 + (L-12mH)*2.5pF/mH pF 2, 3 30 1 DC Parameter 2 The equivalent circuit of a slave (which is calculated from the impedance of the device and the paralleled external over-voltage protection diode (zener diode)) has to satisfy the Complete AS-i-Specification v.2.1 concerning the requirements for the extended address range. 3 Subtracting the maximum parasitic capacitance of the external over voltage protection diode (20pF) either the triple RIN1, LIN1 and CIN1 or the triple RIN2, LIN2 and CIN2 has to be committed by the device to fulfil the Complete AS-i-Specification v2.1. 8.2.6 Input Impedance Control Table 13: CAP Pin SYMBOL PARAMETER RCAP External filter resistor CCAP External filter capacitor MIN. MAX. UNITS NOTE 0 2.2 k 1 4.7 100 nF 1, 2 1 Recommended values for optimal impedance are: RCAP = 1.2 k and CCAP = 10 nF. 2 The de-coupling capacitor and serial resistor define internal low-pass filter time constant; lower values decrease the impedance but improve the turn-on time. Higher values do not improve the impedance but do increase the turn-on time. The turn-on time also depends on the load capacitor at UOUT. After connecting the slave to the power the capacitor is charged with the maximum current IUOUT. The impedance will increase when the voltage allows the analog circuitry to fully operate. Revision 2.2 June 2001 Pages (total): 28 19 ASITM Advanced AS-Interface IC Data Sheet 8.2.7 Oscillator Table 14: Oscillator Pins (OSC1 and OSC2) SYMBOL PARAMETER MIN. MAX. COSC UNITS NOTE External parasitic capacitor at oscillator pins OSC1, OSC2 0 5 pF VIL Input "low" voltage 0 1.5 V VIH Input "high" voltage 3.5 VU5R V 1 1 For external clock applied to OSC1 only. 8.2.8 Development Information Data Table 15: Information Data Conditions: Asynchronous mode, reset to default comparator level at line pause". SYMBOL PARAMETER MIN. MAX. UNITS NOTE VLSIGon Receiver comparator threshold level (see Figure 11) 45 50 % Related to st amplitude of 1 pulse treset1 Reset time after Master Call Reset AS-i-Slave" or DSR = external L ->H transition 2 ms 1 treset2 Reset time after power on 30 ms 2 treset3 Reset time after power on with high capacitive load 1000 ms 3 VASIP-PF VASIP voltage to detect power fail (master mode only) 21.5 23.5 V tLoff Power supply break down time (master mode only) 0.7 0.9 ms 4 VPOR1F VU5R voltage to trigger internal reset procedure, falling voltage 3.0 4.0 V 1 VPOR1R VU5R voltage to trigger INIT procedure, rising voltage 2.5 3.5 V 1 tLow Power-on reset pulse width 4 6 s TShut Chip temperature for thermal shut down (overheating) 125 160 C 1 Guaranteed by design only. 2 `Power_on' starts latest at VUIN = 18V, external capacitor at pin UOUT = 10F. 3 CUOUT = 470F, treset3 is guaranteed by design only. 4 CUOUT > 10F, no power fail generated at VASIP < VASIP-PF for t < tLoff (in master mode only). Revision 2.2 June 2001 Pages (total): 28 20 ASITM Advanced AS-Interface IC Data Sheet "DC level" VLSIGon = (0.45 - 0.50) * VSIG / 2 VLSIGon The IC determines the amplitude of the first negative pulse of the ASI telegram. This amplitude is asserted to be VSIG / 2. VSIG / 2 First negative pulse of the ASI telegram Figure 11: Receiver Comparator Set Up MASTER MODE only VASIP All Modes VUIN VASIP-PF < ca. 15V tLoff VU5R VPOR1F VPOR1R 0V VASIN tLow POR (active low) No reset, but if the break down time exceeds tLoff, a power-fail signal will be generated Power-on Reset will be active, if the VU5R drops below VPOR1F Reset will be initalized Figure 12: Power-Fail Generation (in Master Mode) and Reset Behavior (All Modes) Revision 2.2 June 2001 Pages (total): 28 21 ASITM Advanced AS-Interface IC Data Sheet 9 Application Circuits 2 The following figures show typical application cases of the A SITM IC. Figure 14 shows an application circuit in 2 2 which the A SITM is replacing an ASI3+ circuit. Finally, Figure 15 shows how the A SITM circuit can be used to perform the analog/digital interface between the AS-i-line and the master electronics. Furthermore this figure shows that the IC can be used in repeater applications as well. 9.1 EMC Precautions Precaution must be taken to avoid radio frequency interference. It is recommended to keep input lines as short as possible and to connect unused inputs to UOUT through a pull-up resistor. Furthermore, the supply pins should be de-coupled with ceramic capacitors (10 to 100 nF) in addition to the normal de-coupling capacitors. Also, it is recommended to connect a pull-up resistor from DSR (pin 22) to UOUT or U5R in order to avoid unintentional reset under difficult EMC conditions. 9.2 Typical Slave Application A2SITM 28 7 UIN OSC1 8 MHz 6 OSC2 17 18 19 20 DI_0 DI_1 DI_2 DI_3 DO0 DO1 DO2 DO3 11 10 9 8 DO_0 DO_1 DO_2 DO_3 P0 P1 P2 P3 16 15 14 13 22 P0 P1 P2 P3 21 PST DSR 1 ASIP ASI+ DI0 DI1 DI2 DI3 PST 39V/1W FID 2 ASI- U5RD ASIN U5R C CAP 3 5 Fault Input 23 22 k 26 +5V U OUT 27 25 CAP R CAP DS&Reset 0V LED 24 IRD 4 +24V RED GND GREEN 10 F 10n 10n 1 F 12 0V Figure 13: Typical Application, Slave Mode Note: Figure 13 and 14 show all digital (data and parameter) ports without the application specific connections. For correct function, it is important to consider that all output drivers are open drain stages and hence each port must be connected with an appropriate pull-up resistor. Revision 2.2 June 2001 Pages (total): 28 22 ASITM Advanced AS-Interface IC Data Sheet 9.3 Typical ASI3+ Compatible Application 7 OSC1 A2SITM 8 MHz 6 28 1 ASI+ DI0 DI1 DI2 DI3 DO0 DO1 DO2 DO3 OSC2 UIN P0 P1 P2 P3 ASIP DSR 39V/1W PST 2 ASI- 25 FID ASIN U5RD CAP U5R 17 18 19 20 11 10 9 8 DIO-0 DIO-1 DIO-2 DIO-3 16 15 14 13 P0 P1 P2 P3 22 DS&Reset 21 PS 5 23 26 +5V U OUT 27 RCAP LED C CAP 3 0V IRD +24V 24 4 1 F GND 10n 12 10 F 10n 0V Figure 14: Typical ASI3+ Compatible Application Note: Depending on I/O-configuration, DO- and DI-ports are connected and Multiplex-Flag is set. Revision 2.2 June 2001 Pages (total): 28 23 ASITM Advanced AS-Interface IC Data Sheet 9.4 Typical Master/Repeater Application ISOLATION UOUT 27 A2SITM 28 7 UIN 8 MHz 6 1 ASI+ DI0 DI1 DI2 DI3 P0 P1 P2 P3 OSC2 DSR ASIP REC-CLK (optional) GND +UB Vo REC-STRB (optional) GND +UB Vo 16 15 14 13 22 RECEIVE DATA GND /POWER-FAIL FID 5 LED 24 39V 2 ASI- 25 RCAP +UB Vo DO0 DO1 DO2 DO3 OSC1 +5V U5RD ASIN U5R IRD CAP CCAP PST 3 23 +UB Vo 26 GND 4 21 SEND 0V 10 F 0V GND 12 10n 1 F 10n Figure 15: Master/Repeater Application For further information see also ASITM Application Note. The information furnished here by AMIS is believed to be correct and accurate. However, AMIS shall not be liable to licensee or any third party for any damages, including but no limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental, or consequential damages of any kind in connection with or arising out of the furnishing, performance, or use of the technical data. No obligation or liability to licensee or any third party shall arise or flow out of AMIS' rendering technical or other services. Revision 2.2 June 2001 Pages (total): 28 24 ASITM Advanced AS-Interface IC Data Sheet 10 Package Outline Figure 17: SSOP Package Figure 18: Package Dimensions Table 16: Package Dimensions (mm) Symbol Nominal Maximum Minimum Revision 2.2 June 2001 Pages (total): 28 A 1.86 1.99 1.73 A1 0.13 0.21 0.05 A2 1.73 1.78 1.68 B 0.30 0.38 0.25 C 0.15 0.20 0.13 D 10.20 10.33 10.07 25 E 5.30 5.38 5.20 E 0.65 BSC H 7.80 7.90 7.65 L 0.75 0.95 0.55 4 8 0 ASITM Advanced AS-Interface IC Data Sheet 11 Package Marking TOP VIEW BOTTOM VIEW A2SI AMI + AAAA R-XXXX YZZ PIN 1 PIN 1 Figure 19: Package Marking Top Marking: ASI AMIS or AMI RXXXX Y ZZ Product name Manufacturer Revision code Date code (year and week) Assembly location Traceability Bottom Marking: AAAA Country of assembly The yellow dot indicating pre-programmed Master function is printed at the pin 1 marking . Revision 2.2 June 2001 Pages (total): 28 26 ASITM Advanced AS-Interface IC Data Sheet 12 Ordering Information 12.1 Device Ordering Codes Ordering Code Description Operating Temperature Range Package Type Device Marking Shipping Form A2SI-ST Standard version of ASI -25C to 85C 28-pin SSOP (5.3 x 10.2) ASI Tubes (47 parts/tube) A2SI-SR Standard version of ASI -25C to 85C 28-pin SSOP (5.3 x 10.2) ASI Tape-and-Reel (1500 parts/reel) A2SI-MT Pre-programmed master function -25C to 85C 28-pin SSOP (5.3 x 10.2) ASI + yellow dot Tubes (47 parts/tube) A2SI-MR Pre-programmed master function -25C to 85C 28-pin SSOP (5.3 x 10.2) ASI + yellow dot Tape-and-Reel (1500 parts/reel) 12.2 Demo Kit Ordering Code Ordering Code Kit for Device A2SI-KIT ASI Description Kit includes: * Evaluation board with ASITM * 3 ASI samples * 1 ASI-M sample * Literature (Brochure, Data Sheet, Application Note) Evaluation board dimensions (L x W x H): 34 x 31 x 8 mm Revision 2.2 June 2001 Pages (total): 28 27 ASITM Advanced AS-Interface IC Data Sheet 13 Application Support 13.1 AMIS Partners for Application Support Bihl+Wiedemann Flosswoerthstrasse 41 D-68199 Mannheim, Germany Tel.: +49 621 3 3996 0 Fax: +49 621 3 3922 39 Email: mail@bihl-wiedemann.de http://www.bihl-wiedemann.de fieldbus specialists 217 Colchester Road, Kilsyth 3137 Victoria, Australia Tel.: +61 3 9761 4653 Fax: +61 3 9761 5525 Email: fs_sales@fieldbus.com.au http://www.fieldbus.com.au 13.2 General Information on AS-Interface AS-International Association Contact - Rolf Becker Zum Taubengarten 52 D-63571 Gelnhausen PO Box 1103 Zip (63551) Tel: +49 6051 47 32 12 Fax: +49 6051 4732 82 Email: as-interface@t-online.de http://www.as-interface.net Further Information is available on http:// www.amis.com/a2si/ Sales Offices on http://www.amis.com/sales/ Products sold by AMIS are covered exclusively by the warranty, patent indemnification and other provisions appearing in AMIS standard "Terms of Sale" (as the same may be amended by AMIS, at its sole discretion, from time to time). AMIS makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the Materials pertaining to AMIS products, or regarding the freedom of any products described in the Materials from patent and/or other infringement. AMIS reserves the right to discontinue production and change specifications and prices of its products at any time and without notice. AMIS products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional mutually agreed upon processing by AMIS for such applications. AMIS reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ASITM is a trademark of AMI Semiconductor, Inc. (c) Copyright 2000 AMI Semiconductor, Inc. 2300 Buckskin Road Pocatello, Idaho 83201, U.S.A. All rights reserved. Revision 2.2 June 2001 Pages (total): 28 28