A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 1
1 Features
AS-i Complete Specification V2.11 compliant
Integrated EEPROM
Additional addressing channel using an opto-
electronic interface
Extended address mode operation as
programmable option (up to 62 slaves)
High impedance AS-i line input, additional pins
for further impedance optimizations
DC voltage output, approximately 24 volts, not
stabilized
5 volt DC voltage output, stabilized, CMOS logic
can be supplied directly (e.g. µC)
LED status indicator output (compliant to the
standard indication recommendation)
Integrated watchdog
2 Description
A²SI™ is a monolithic CMOS integrated circuit
certified for AS-i (Actuator Sensor-interface)
networks. AS-i networks are intended for industrial
automation.
The main advantage of AS-i solutions is that
actuators and sensors are connected using a two-
wire unshielded cable that is easy to install. This
cable transports both power and information/data.
AS-i network communication is based on the master-
slave principle. The network can be extended (to
cable lengths greater than 100m) by using the A²SI™
in the repeater mode configuration.
AS-i is a standard for the automation industry based
on IEC 62026-2 and EN 50295.
The device is available in a 28-pin SSOP package.
3 Block Diagram
RECEIVE
TRANSMIT
ELECTRONIC
INDUCTOR
POWER
SUPPLY OSCILLATOR
4
4
4
DIGITAL
LOGIC
THERMAL
PROTECTION
A2SI™
GND2 GND1
ASI+
ASI–
8 MHz
DOx
DIx
DSR
PST
Px
FIDLEDIRDGND0V
UIN UOUT U5R U5RD OSC1/2
CAP
ASIP
ASIN
10 µF
1
µ
F
5V
24V
POWERFAIL
DETECTION
IRD
AMP
Figure 1: Block Diagram
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 2
4 Pin Description
Table 1: Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 ASIP INOUT To be connected to the AS-i-line ASI+ via reverse polarity protection diode
2 ASIN INOUT To be connected to the AS-i-line ASI-
3 0V SUPPLY Common 0V for all ports except ASIP/ASIN (to be connected to ASI- line)
4 IRD IN Addressing channel input
5 FID IN Input peripheral fault indication
6 OSC2 INOUT Crystal oscillator (8 MHz x-tal)
7 OSC1 IN Crystal oscillator / external clock input
8 DO3 OUT Output of data D3
9 DO2 OUT Output of data D2
10 DO1 OUT Output of data D1
11 DO0 OUT Output of data D0
12 GND SUPPLY Digital IO ground, must be connected to pin 0V
13 P3 I/O Input/output of parameter P3
14 P2 I/O Input/output of parameter P2 / receive strobe in ”Master Mode”
15 P1 I/O Input/output of parameter P1 / power fail in ”Master Mode”
16 P0 I/O Input/output of parameter P0 / data clock in ”Master Mode”
17 DI0 IN Input of data D0
18 DI1 IN Input of data D1
19 DI2 IN Input of data D2
20 DI3 IN Input of data D3
21 PST OUT Parameter strobe output
22 DSR I/O Data strobe output/reset input
23 U5RD SUPPLY Digital 5V supply input, should be connected to U5R
24 LED OUT Output LED "AS-i-Diagnosis" / addressing channel output
25 CAP IN/OUT For connection of external RC components
26 U5R OUT Internal 5V supply that might be used to supply external circuits as well
27 UOUT OUT Supply of external circuitry (e.g. sensor, actuator, etc.), approx. VUIN minus 7
volt
28 UIN SUPPLY Input of the power supply block (usually to be connected to the AS-i-line ASI+
via reverse polarity protection diode)
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 3
5 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ASIP
ASIN
0V
IRD
FID
OSC2
OSC1
DO1
DO3
DO2
GND
P3
P2 P1
UIN
UOUT
U5R
CAP
LED
U5RD
DSR
PST
DI3
DO0
DI2
DI1
DI0
A2SI™
P0
Figure 2: Pin Configuration, 28-Pin SSOP
6 Functional Block Description
6.1 Power Supply
An on-chip electronic inductor provides a de-coupled
voltage at pin UOUT and the power supply regulates
the internal 5V operating voltage. The de-coupling
circuit (electronic coil) is connected between UIN and
UOUT pins and guarantees a high impedance seen at
UIN. An external capacitor and resistor are required to
allow a low-pass filter with a very high time constant.
This high time-constant value is necessary to
maximize the input impedance. The de-coupling
circuit limits the current that can be drawn from UOUT.
The power supply will shut down the de-coupling
circuit in case of an overload condition to prevent a
total malfunction of the complete AS-i line. The
regulated 5 volt supply voltage is connected to pin
U5R. Two external capacitors are necessary to cope
with fast internal and external load changes (spikes).
Current drawn from pin U5R (up to 4 mA) has to be
subtracted from the total load current. The power
supply circuit dissipates the major amount of power.
The total power dissipation shall not exceed the
specified values of Figure 6. The ground reference
voltage for both UOUT and U5R is defined by the 0V
pin. This pin must be connected to ASI- (ref. Figure
1).
6.2 Receiver
The receiver detects signals on the AS-i line and
delivers the appropriate pulses to the digital logic.
The DC value of the input signal is removed and the
AC signal is band-pass filtered. The digital output
signals are extracted from the sin2-shaped input
pulses by a set of comparators. The maximum
voltage of the first negative pulse determines the
threshold level for all following pulses. The maximum
value is digitally filtered to guarantee stable
conditions (burst spikes have no effect). This
approach combines a fast adaptation to changing
signal amplitudes with a high detection safety. The
receiver delivers positive (P-PULSE) and negative
(N-PULSE) pulses to the IC's logic. The logic resets
the comparators after receiving the REC-RESET
signal. When the receiver is turned on, the transmitter
is turned off to reduce power consumption.
6.3 Transmitter
The transmitter draws a modulated current between
ASIP and ASIN pins to generate the communication
signals. The shape of the current corresponds to the
integral of a sin2-function. The transmitter uses a
current DAC and a high current driver. In order to
activate high current drive capability, a small current
will be turned on automatically prior to each
transmission (slave mode only). The current will be
ramped up slowly to avoid false voltage pulses on the
AS-I line. The amount of circuitry between ASI+ and
ASI- pins is minimized to allow high impedance
values. When the transmitter is turned on, the
receiver is turned off to reduce power consumption.
6.4 Digital Logic
The digital logic block performs analysis of the
received signal, controls reaction of the IC, transmits
slave response, switches I/O-ports, and controls the
internal EEPROM. Its principal function is described
in detail in section 7.
6.5 Protection Circuitry
The device has several protection cells that prevent
disruption and malfunction of the complete AS-i line.
The thermal detection shuts down the power supply
in case of over-heating condition (temperature >
140°C typically for more than 2 seconds) and when
UOUT is shorted to GND for more than 2 seconds.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 4
The device can only be reactivated by a power-on
reset. An over-heating condition can occur by
overloading any output pin. Therefore, the circuit
monitors the operating conditions of the power supply
(effectively monitors UOUT) and measures the
temperature of the silicon.
6.6 Infrared Diode Input
The photo current input can be used as an alternative
communication pin in slave mode. The IRD circuitry
will be turned off when the communication has been
switched to AS-i line. In Slave mode the logic sets
IRD input to photo-detector mode and disables
CMOS mode. In this photo-detector mode, signals of
an external photo diode are amplified. In CMOS
mode (master/repeater mode only), input signals
have to be CMOS levels between 0V and VU5R.
6.7 Power-Fail Detection
The power-fail detector consists of a comparator that
generates a logic signal in case the power supply
drops below 22VDC (Power-Fail) for a time of more
than tLoff (0.8 ± 0.1 ms). The power fail signal will be
presented at pin P1 in master mode only.
Power-fail detection monitors the value of the ASIP
voltage. It will activate a logic signal if power fails for
more than 1ms. The device is then buffered by the
external capacitor at UOUT and the internal circuitry
will be reset when U5R supply voltage fails.
RECEIVE
TRANSMIT
POWERFAIL
DETECTION
POWER
SUPPLY OSCILLATOR
DIGITAL
LOGIC
THERMAL
PROTECTION
A2SI™
GND2 GND1
DO(3:0)
DI(3:0)
DSR
PST
P(3:0)
FIDLEDIRDGND
0V
UIN UOUT U5R U5RD OSC1/2
CAP
ASIP
ASIN
OVER-HEAT
P-PULSE
N-PULSE
REC-RESET
SEND-D
SEND-SBY
POWER-FAIL
POWER-ON
RESET
UOUT
SHUT-DOWN
CLK
OUTPUT
STAGE
INPUT
STAGE
I/O
STAGE
OUTPUT
STAGE
INPUT
STAGE
OUTPUT
STAGE
OUTPUT
STAGE
INPUT
STAGE
CMOS
INPUT
STAGE
AC
Current
INPUT
DATA-OUT
DATA-IN
DATA-STRB
RESET
PARAM
STRB
PARAM
IN
PARAM
OUT
LED
OUT
FAULT
IN
IRD In
Logic
AC
ELECTRONIC
INDUCTOR
Figure 3: Functional Block Diagram
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 5
7 Description of Digital Logic
The digital logic is structured in four (4) parts (see
Figure 4):
1. the UART, which analyses the incoming signal
from the AS-i line and ensures correct timing of
output signals;
2. the STATE MACHINE, which controls the
reaction of the IC;
3. the PORTS, which contain registers and digital
I/O’s;
4. and finally the E²PROM, which contains the non-
volatile data of the A2SI™ circuit.
DATA-OUT-0
DATA-OUT-1
DATA-OUT-2
DATA-OUT-3
DATA-STRB
RESET
DATA-IN-0
DATA-IN-1
DATA-IN-2
DATA-IN-3
PARAM-OUT-0
PARAM-OUT-1
PARAM-OUT-2
PARAM-OUT-3
PARAM-STRB
PARAM-IN-0
PARAM-IN-1
PARAM-IN-2
PARAM-IN-3
IRD-IN
FAULT-IN
LED-OUT
OVER-HEAT
UOUT SHOUTDOWN
PORTS
DO-REG -0
DO-REG -1
DO-REG -2
DO-REG -3
DI-REG -0
DI-REG -1
DI-REG -2
DI-REG -3
PO-REG -0
PO-REG -1
PO-REG -2
PO-REG -3
PI-0
PI-1
PI-2
PI-3
E2PROM
STATE MACHINE
REC -REG -0
REC -REG -1
REC -REG -2
REC -REG -3
REC -REG -4
REC -REG -5
REC -REG -6
REC -REG -7
REC -REG -8
REC -REG -9
REC -REG -10
REC-STRB
SEND -REG-0
SEND -REG-1
SEND -REG-2
SEND -REG-3
SEND -STRB
UART
ADD-CLK
ADD-OUT
ADD-IN
P-PULSE
N-PULSE
SEND-D
SEND-SBY
REC-RESET
Digital Logic
POWER-FAIL
POWER-ON RESET
P-Pulse
Figure 4: Digital Logic
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 6
7.1 UART Operational Modes
7.1.1 Master/Repeater Mode
7.1.1.1 IRD Input (CMOS Input)
The IC sends signal retrieved from pin IRD to AS-i
line as an AS-i telegram. The input signal is
Manchester-coded and active low. A falling edge of
the IRD signal, which is conducted to ADD-IN, starts
the receiving process and triggers the Activity-
Checker. Receive-Muxer selects pin IRD as input for
the receive data.
The IRD signal is connected with Send-Muxer to
SEND-D via ADD-IN. The IRD signal is latched every
500 ns as long as there is activity on the input pin. If
there is a high level on the IRD input longer then
7.0 µs, Activity-Checker will recognize this as no
activity and Receive-Muxer is returning to idle state.
The information on pin IRD is transported to pin
SEND-D with a delay of 2.0 µs up to 2.5 µs. The
sender is always in non-standby mode. The SEND-
SBY signal is constant low and there is no generation
of ADD-CLK.
REC -REG -0
REC -REG -1
REC -REG -2
REC -REG -3
REC -REG -4
REC -REG -5
REC -REG -6
REC -REG -7
REC -REG -8
REC -REG -9
REC-REG -10
UART
SEND -REG -0
SEND -REG -1
SEND -REG -2
SEND -REG -3
RECEIVE
REGISTER
SEND
MUXER
SEND-D
ADD-OUT
RECEIVE
MUXER
MAN CODE
CHECKER
CONTROL
UNIT
PULSE
ENCODER
ACTIVITY
CHECKER
SEND
REGISTER
STROBE
UNIT
P-PULSE
N-PULSE
ADD-IN
SEND-STRB
REC-STRB
ADD-CLK
SEND-SBY
REC-RESET
Figure 5: UART Block Diagram
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 7
7.1.1.2 AS-i Input
A signal on the AS-i-line generates signals at the
receiver output that are pulse coded with a minimal
pulse width of 750 ns up to 875 ns. A pulse on the
AS-i line starts the receiver and triggers the Activity-
Checker through N-PULSE or P-PULSE. The
Receive-Muxer selects AS-i-line pins as input for the
receive data. The N-PULSE and P-PULSE signals
are latched every 500 ns as long as there is activity
on the input pins. If there is a pulse distance on the
AS-i-line inputs longer then 7.0 µs, the receiver will
recognize this as no activity and the Receive-Muxer
is going to the idle state.
The Pulse-Encoder is used to convert the active high
pulse-coded signal to a active low Manchester-II-
coded (MAN) signal. It will also check the pulse
stream for timing and pulse errors (e.g. alternation
error). In Master/Repeater mode the Pulse-Encoder
additionally resynchronizes an error-free MAN
telegram into a proper 3 µs time base. This is to
eliminate the pulse jitter of the transformed AS-i
telegram. The synchronized MAN signal is sent to
ADD-OUT through the Send-Muxer. ADD-OUT is
connected to LED-OUT on a higher hierarchy level.
All in all, information on the AS-i-line pins is
transported to pin LED-OUT with a delay of 2.5 µs up
to 3.0 µs. In Master/Repeater mode the sender is
never in standby mode, hence SEND-SBY signal is
always low.
A generation of ADD-CLK is provided to simplify
external processing of Manchester-coded data. The
rising edge of the ADD-CLK signal is in the middle of
the second half of the Manchester data assuring that
correct binary data can be clocked into a shift
register. The ADD-CLK starts with a rising edge 2.0
µs after the falling edge of the start bit at ADD-OUT
with a period of 6.0 µs and a ratio of 1:1. The last
rising edge of the ADD-CLK signal occurs 2.0 µs
after the falling edge of the end bit at ADD-OUT.
If the received signal in the Master Mode is a valid
slave answer with start bit, four (4) data bits, parity,
and end bit and if a pause is following with a length
greater than 6.0 µs, the UART generates the active
high REC-STRB signal with a pulse width of 500 ns.
The REC-STRB signal is connected to the P2
Parameter Output in this mode. It appears 10.0 to
10.5 µs after the rising edge of the end bit on AS-i-
line.
7.1.1.3 Ports
Functional assignments of some IC ports depend on
the operational mode of the IC. Thus, these ports
perform multiple functions that are related to a
particular mode of the IC.
In Master Mode, following signals and ports are
connected:
PIN Slave Function Master Repeater
P0 Parameter output
port bit 0
REC-CLK REC-CLK
P1 Parameter output
port bit 1
POWER-
FAIL
-
P2 Parameter output
port bit 2
REC-STRB -
LED LED
output/addressing
channel output
MAN-OUT MAN-OUT
IRD Fault indicator
input/addressing
channel input
MAN-IN MAN-IN
7.1.2 Slave Mode
After IC-reset, Receive-Muxer is watching the two
input channels (AS-i-line and IRD pin) depending on
a multiplex select signal MPX. MPX has a frequency
of about 1.0 kHz. If MPX is low, the Receive-Muxer
selects the AS-i-line and vice versa if it is high, it
selects the IRD pin as data input. The channel, from
which a valid master call is received first, will be
locked until the next IC-reset occurs.
7.1.2.1 IRD Input Mode (Photo Diode Input)
The photo diode current on the IRD input is
Manchester-coded and low active (ref. 8.2.2
Addressing Channel Input IRD). A low level of the
IRD signal starts the receiver and triggers the
Activity-Checker. The Control-Unit is enabling the
Receive-Register and the received information is
clocked every 6 µs into the Receive-Register. If there
is a high level on the IRD input longer then 7.0 µs,
the Control-Unit will recognize this as no activity and
the Receive-Register will be disabled. If the received
information is a correct master call with Start-Bit,
eleven Data-Bits, Parity-Bit, End-Bit, and following
pause of either greater than 6.0 µs (Synchronous
Mode) or 18.0 µs (Asynchronous Mode), the UART
generates the internal active high REC-STRB signal
with a pulse width of 500 ns.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 8
If the received telegram contained an error, the
Control-Unit will not generate the REC-STRB signal
but go to its asynchronous state waiting for a pause
at the IRD input. After a pause was detected, the
UART is ready to receive the next telegram from the
IRD input.
If a REC-STRB signal is generated, it occurs 9.5 µs
up to 10.0 µs (Synchronous Mode) or 21.0 µs up to
21.5 µs (Asynchronous Mode), respectively, after the
rising edge of the End-Bit on the IRD pin signal. If the
slave was in asynchronous state, it now transforms to
synchronous state. The Rec-Muxer is locked to the
IRD input until the next IC-reset. After the generation
of a REC-STRB signal the Control-Unit is waiting for
about 6.0 µs for the SEND-STRB to be generated by
the Main-State-Machine.
If the Control-Unit receives the active high SEND-
STRB signal, it starts the transmission of the Send-
Register data. Therefore, the Send-Register data will
be converted to an active low Manchester II-coded
(MAN) signal which is sent to the LED-OUT pin via
ADD-OUT. The first falling edge of the MAN signal
occurs 11.75 µs (Synchronous Mode) or 12.25 µs
(Asynchronous Mode) after the rising edge of the
REC-STRB signal. Hence, the delay from the rising
edge of the End-Bit of the master call (IRD input) to
the first falling edge of the slave response (LED
output) is 21.25 to 21.75 µs (Synchronous Mode) or
33.25 to 33.75 µs (Asynchronous Mode). After the
pause was detected, the UART is ready to receive
the next telegram from the IRD input.
In case the Control-Unit will not receive a SEND-
STRB signal within the given time frame (for
instance, if this slave was not addressed), it will
check for activity on the IRD input. Otherwise, it will
just wait for the end of the response time (60 µs). In
both cases the Control-Unit stays synchronous. Once
a slave pause was detected, the UART is ready to
receive the next telegram from the IRD input.
7.1.2.2 AS-i Input Mode
A signal on the AS-i-line generates two pulse-coded
signals (N-PULSE, P-PULSE) at the receiver output
with a minimum pulse width of 750 to 875 ns. A pulse
on the AS-i line starts the receiver and triggers the
Activity-Checker through N-PULSE or P-PULSE.
The Pulse-Encoder is used to convert the active high
pulse coded signal to an active low Manchester-II-
coded (MAN) signal. It will also check the pulse
stream for timing and pulse errors (e.g. alternation
error). The Control-Unit enables the Receive-Register
so that the received information can be clocked in
every 6 µs. If there is a pulse distance on the AS-i-
line input longer than 7.0 µs, the Control-Unit
recognizes this as no activity and disables the
Receive-Register.
If the received information is a correct master call
with Start-Bit, eleven (11) Data-Bits, Parity-Bit, End-
Bit, and following pause of either greater than 6.0 µs
(Synchronous Mode) or 18.0 µs (Asynchronous
Mode), the UART generates the internal active high
REC-STRB signal. If the received telegram contained
an error, the Control-Unit will not generate the REC-
STRB signal but go to its asynchronous state waiting
for a pause at the AS-i line input. After a pause was
detected the UART is ready to receive the next
telegram from the AS-i line input.
If a REC-STRB signal is generated, it occurs 10.0 to
10.5 µs (Synchronous Mode) or 21.5 to 22 µs
(Asynchronous Mode), respectively, after the rising
edge (receiver comparator switching point) of the
End-Bit on the AS-i line input. If the slave was in
asynchronous state, it now transforms to
synchronous state. The Rec-Muxer is locked to the
AS-i line input until the next IC-reset. After the
generation of a REC-STRB signal the Control-Unit is
waiting for about 6.0 µs for the SEND-STRB to be
generated by the Main-State-Machine.
If the Control-Unit receives the active high SEND-
STRB signal (pulse width 500 ns), it starts the
transmission of the Send-Register data. Therefore,
the Send-Register data will be converted to an active
low Manchester II-coded (MAN) signal which is sent
to the AS-i line transmitter via SEND-D. The first
falling edge of the MAN signal occurs 11.75 µs
(Synchronous Mode) or 12.25 µs (Asynchronous
Mode) after the rising edge of the REC-STRB signal.
Hence, the delay from the rising edge of the End-Bit
of the master call (AS-i input) to the first falling edge
of the slave response (AS-i output) is 21.75 to
22.25 µs (Synchronous Mode) or 33.75 to 34.25 µs
(Asynchronous Mode).
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 9
The SEND-SBY will always be set low 0.5 µs after
the rising edge of REC-STRB. This is to turn on the
transmitter and let it settle at its operation point. The
small offset current, which is required to operate the
transmitter, will be ramped up slowly to avoid any
false voltage pulses on the AS-i line.
If all data is sent, the Control-Unit sets the sender in
standby mode (SEND-SBY is high) and checks for a
slave pause on the AS-i line input. After the pause
was detected, the UART is ready to receive the next
telegram from the AS-i line input.
In case the Control-Unit will not receive a SEND-
STRB signal within the given time frame (for
instance, if this slave was not addressed), it will
check for activity on the AS-i line. If any activity is
detected in a time frame of about 60 µs (another
slave is transmitting data), the Control-Unit will wait
for the next pause (slave pause). Otherwise, it will
just wait for the end of the response time (60 µs). In
both cases the Control-Unit stays synchronous. Once
a slave pause was detected, the UART is ready to
receive the next telegram from the AS-i line input.
7.1.2.3 Ports
In the Slave Mode it is not necessary to decode the
IO-Configuration; all Data-Out and Data-In signals
are directly connected to the respective port.
If the Multiplex-Flag-nvmem is TRUE, the output
ports will switch to high impedance state for a certain
period of time following the rising edge of the Data-
Strobe.
In contrast to the master mode, the parameter port
pin performs a parameter input and output function
according to the AS-i Complete Specification.
Also compliant to the AS-I Complete Specification,
The IC contains an independent watchdog which can
be activated by setting Watchdog-active-Flag-nvmem
to TRUE.
If Watchdog-Flag is TRUE (no data exchange for
more than 40 ms) and Watchdog-active-Flag-nvmem
is TRUE, a reset (INIT) will be performed.
An active FID (logic high) signal shall cause a
flashing status LED (frequency approx. 2Hz) and Bit
1 of the Status-Register (S1) shall be set as well. If
FID
is not active (logic low), S1 is cleared. In that case
the status LED operation depends on the Data-
Exchange-Disable flag.
If the Data-Exchange-Disable flag is set (no data
exchange allowed) a steady-on LED shall indicate
that the communication is off. Note: An active FID
has priority and will cause a flashing LED even if the
Data-Exchange-Disable flag is set.
If the UART has selected the IRD input channel, the
LED output should not toggle. In this mode the LED
pin does not operate as indicator LED output. Hence,
periphery failures or status information will not be
signaled.
If OVER-HEAT is TRUE the IC will be put into shut-
down and stay there until the next power-on reset
occurs.
If INVERT-DATA-IN is TRUE, all input data is
inverted. This feature will simplify the circuitry for
NPN-inputs.
7.1.2.4 State Machine
The so-called Main-State-Machine performs the
central control of the A2SI™ IC concerning the mode
control, the access to the EEPROM; the processing
of master requests; and the control of the IC ports.
There is a register interface (receive and send
register) between Main-State-Machine and UART
(controls the serial data communication channels).
This register interface is used to exchange
communication data between UART and Main-State-
Machine.
To avoid the situation in which a single slave IC is
accidentally locked in a not allowed state and thereby
could jeopardize the entire system, all prohibited
states of the state machine will lead to a RESET.
This means that the IC will execute its reset
procedure by performing the instruction ”Reset Slave
(RES)”.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 10
7.2 Summary of Master Calls
In the following diagram all Master Calls that will be
decoded by the A2SI™ are listed. The "Enter
Program Mode" call is intended for factory
programming of the IC only.
In order to achieve EEPROM firmware protection and
to comply to the complete AS-i specification, the call
"Enter Program Mode" has to be deactivated before
shipment of the slave.
7.3 Program Mode
Provided that the non-volatile configuration flag,
Program-Mode-Disable, has not been set, the device
can be transferred in program mode by utilizing the
“Enter Program Mode” call.
Please refer to the A
2SI™ Application Note [4] for
details of the programming process.
AS-i Complete Specification compliance note:
In order to ensure full compliance with the AS-i Complete Specification, the Program-Mode-Disable flag must be set
in the final manufacturing and configuration process before an AS-i slave device is being delivered to field
application users.
Table 2: A²SI Master Calls and Related Slave Responses
Master Re
q
uest Slave Res
p
onse
Instruction MNE ST CB A4 A3 A2 A1 A0 I4 I3 I2 I1 I0 PB EB SB I3 I2 I1 I0 PB EB
Data Exchange DEXG 0 0 A4 A3 A2 A1 A0 0 D3
~Sel D2 D1 D0 PB 1 0 D3
E3
D2
E2
D1
E1
D0
E0 PB 1
Write Parameter WPAR 0 0 A4 A3 A2 A1 A0 1 P3
~Sel P2 P1 P0 PB 1 0 P3
I3
P2
I2
P1
I1
P0
I0 PB 1
Address Assignment ADRA 0 0 0 0 0 0 0 A4 A3 A2 A1 A0 PB 1 0 0 1 1 0 PB 1
Write Extented ID
Code-1 WID1 01000000ID3ID2ID1ID0PB1 00000PB1
Delete Address DELA 0 1 A4 A3 A2 A1 A0 0 0 Sel 0 0 0 PB 1 0 0 0 0 0 PB 1
Reset Slave RES 0 1 A4A3A2A1A0 1 1
~Sel 100PB1 00110PB1
Read IO
Confi
g
uration RDIO 0 1 A4A3A2A1A0 1 0
Sel 0 0 0 PB 1 0 IO3 IO2 IO1 IO0 PB 1
Read ID Code RDID 0 1 A4A3A2A1A0 1 0
Sel 0 0 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Read ID Code-1 RID1 0 1 A4 A3 A2 A1 A0 1 0
Sel 0 1 0 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Read ID Code-2 RID2 0 1 A4 A3 A2 A1 A0 1 0
Sel 0 1 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Read Status RDST 0 1 A4A3A2A1A0 1 1
~Sel 1 1 0 PB 1 0 S3 S2 S1 S0 PB 1
Broadcast (Reset) BR01 011111110101PB1 --- no slave response ---
Enter Program Mode PRGM010000011101PB1 --- no slave response ---
Note: In extended address mode the "Select Bit" defines whether the A-Slave or B-Slave is being addressed. Dependent on
the type of master call the I3 bit carries the select bit information (Sel) or the inverted select bit information (~Sel).
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 11
8 Electrical Specification
8.1 Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a
stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification
is not implied. Exposure to maximum rating conditions for extended conditions may effect device performance, functionality, and reliability.
Table 3: Absolute Maximum Ratings
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
V0V ,VGND Voltage reference 0 0 V
VASIP Positive AS-i supply voltage -0.3 40 V
VASIN Negative AS-i supply voltage -0.3 20 V 1
VASIP-ASIN Voltage difference from ASIP to ASIN (VASIP - VASIN) -0.3 40 V
2
VASIPP AS-i supply pulse voltage, voltage difference between pins
ASIP and ASIN (from ASIP to ASIN)
50 V 3
VUIN Aux. power supply input voltage -0.3 40 V
VUINPV Aux. power supply input voltage pulse 50 V 3
Vinputs1 Voltage at pins DI3 - DI0, DO3 - DO0, P3 - P0, DSR, PST,
LED, FID, UOUT
-0.3 VUIN +
0.3
V Vinputs1
≤ 40V
Vinputs2 Voltage at pins OSC1, OSC2, IRD, CAP, U5R, U5RD -0.3 7 V
Iin Input current into any pin except supply pins -25 25 mA
H Humidity non-condensing
4
VHBM1 Electrostatic discharge – human body model (HBM1) 4000 V 5
VHBM2 Electrostatic discharge – human body model (HBM2) 2000 V 6
VEDM Electrostatic discharge – equipment discharge model
(EDM)
400 V 7
θSTG Storage temperature -55 125 °C
Ptot Total power dissipation 0.85 W 8
1 ASIN-pin shall be shorted to 0V-pin on PCB.
2 Reverse polarity protection has to be performed externally.
3 Pulse with ≤ 50µs, repetition rate ≤ 0.5 Hz.
4 Defined in DIN 40040 cond. F.
5 HBM1: C = 100pF charged to VHBM1 with resistor R = 1.5kΩ in series, valid for ASIP-ASIN only.
6 HBM2: C = 100pF charged to VHBM2 with resistor R = 1.5kΩ in series, valid for all pins except ASIP-ASIN.
7 EDM: C = 200pF charged to VEDM with no resistor in series, valid for ASIP-ASIN only.
8 At maximum operating temperature, the allowed total power dissipation depends on the additional thermal resistance from case to ambient
and on the operation ambient temperature (see Figure 6).
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to high-energy
electrostatic discharge.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 12
Ptot = f (Ta); 1L / 2L = 1 layer / 2 layer PCB
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-25 0 25 50 75 100
Ta
Ptot (2L)
Ptot (1L)
Figure 6: Maximum Power Dissipation, PTOT = f(Ambient Temperature)
Table 4: Operating Conditions
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VUIN Positive supply voltage 16 33.1 V 1
VASIN Negative AS-i supply voltage 0 0 V 2
V0V, VGND Negative supply voltage 0 0 V
IASI Supply current at VASI = 30V 9 mA 3
ICL1 Max. output sink current at pins DO3 - DO0, DSR 10 mA
ICL2 Max. output sink current at pins P0 - P3, PST 10 mA
θamb Ambient temperature range, operating range -25 85 °C
1 DC voltage
2 ASIN shall be shorted with 0V to ensure proper functionality of transmitter circuit.
3 fc = 8.000 MHz, no load at any pin without reaction of the circuit, ASIP is short-cut to UIN and ASIN to 0V respectively.
8.2 DC and AC Characteristics
All parameters are valid for the recommended range of VASIP - VASIN, VUIN - V0V, and θamb. The devices are tested
within the recommended range of VASIP - VASIN, VIN - V0V, θamb = +25°C (+ 85°C and - 25°C on sample base only)
unless otherwise stated. Unused input pins shall be connected to a suitable potential within the application circuit
because there are no internal pull-up/down resistors. It is recommended to connect these pins either to 0V or via
resistor to UOUT or U5R respectively.
With an external LOW signal at the data strobe pin DSR (pull-down open drain driver) for more than 44µs, the IC
will execute its reset procedure. During power on procedure all data and parameter ports will stay on high-
impedance state.
If the IC has been put in its initialization procedure by an external reset via DSR, the LED pin should not be toggled
externally to avoid that the IC control logic transfers to test mode.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 13
8.2.1 Digital Input and Output Pins
Table 5: Input/Output Voltage and Current
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
Pins DI0 - DI3, P0 - P3, DSR, FID, PST
VIL Voltage range for input ”low” level, not P0 – P3 0 2.5 V
VIL Voltage range for input ”low” level, only P0 – P3 0 2.4 V
VIH Voltage range for input ”high” level 3.5 VUOUT V
VHYST Hysteresis for switching level 0.25 V 1
IIL Current range for input ”low” level -20 -5 µA
IIH Current range for input ”high” level -10 10 µA VO = 5V
IIHV Current range for high voltage input 2 mA VO = 30V
Pins DO0 - DO3, P0 - P3, DSR, PST
VOL1 Voltage range for output ”low” level 0 1 V IOL1 = 10mA
VOL2 Voltage range for output ”low” level 0 0.4 V IOL2 = 2mA
IOH Output leakage current -10 10 µA VOH = 4.5V
CDL Capacitance at pin DSR 10 pF 2
Pin LED
VOL Voltage range for output ”low” level 0 1 V IOL1 = 10mA 3
IOH Output leakage current -10 30 µA VOH = 40V 4
1 Switching level approximately 3V, i.e. 3V ± VHYST.
2 For higher capacitive load an external pull-up resistor connected to UOUT is necessary to reach VICH ≥ 3.5V at DSR in less than 35 µs after
beginning of DSR = Low pulse, otherwise a reset will be executed.
3 The output driver sends a “low” (LED on).
4 The output driver sends a “high” (equivalent to tri-state, LED off).
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Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 14
Table 6: Timing Parameter Port
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
tsetup Valid output data; P0 - P3 to PST-H/L 0.1 0.5 µs See Figure 7
tPST PST pulse width 5 6 µs
tPI-latch PST-H/L to parameter input latch 11 13.5 µs 1
tCYCLE Next cycle 150 µs
1 The parameter input data must be stable within the period that is defined by minimum and maximum tPI-latch.
PST
tsetup tPST
tCYCLE
tPI-latch
Parameter port output data
parameter input value (PIx) = parameter output value (POx) wired AND
with external signal source value
keep stable
min max
PO0-PO3
Figure 7: Timing Diagram Parameter Port P0 - P3
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Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 15
Table 7: Timing Data Port Outputs
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
tsetup Valid output data; DO0 - DO3 to DSR-H/L 0.1 0.5 µs Figure 8
thold Valid output data; DO0 - DO3 to DSR-L/H 0.1 0.5 µs
tDSTR DSR pulse width 5 6 µs
tDI-latch DSR-H/L to data input latch 11 13.5 µs 1
tCYCLE Next cycle 150 µs
1 The data input must be stable within the period that is defined by minimum and maximum of tDI-latch.
DSR
tsetup tDSR
tCYCLE
tDI-latch
Data port output data
keep stable
min max
DO0-DO3
DI0-DI3 Data port input data
thold
data remains, if multiplex
flag is not set
hi-z, if multiplex flag is set
Figure 8: Timing Diagram Data Port DO0 - DO3
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Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 16
Table 8: Timing Reset Signal
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
tALM1 Ext. DSR (no reset) 35 µs
tALM2 Ext. DSR to DO0 - DO3 Hi-Z 44 µs
tRESET1 Reset time after DSR = external L ->H transition 2 ms
DSR
DO0-DO3
tALM1
tALM2
>0
tRESET1
hi-z
PO0-PO3
hi-z
Data port output data
Parameter port output data
Figure 9: Timing Diagram External Reset via DSR
8.2.2 Addressing Channel Input IRD
The addressing channel input IRD is a dedicated photo-diode input. The photo-diode can be connected to the pins
IRD and 0V directly. The IRD input is a AC current input. A valid signal at the current input has to have a certain
amplitude (range) and should not exceed a certain offset value (see Figure 10 and Table 9). A logic "low" at the
IRD input will be detected, if the present signal value drops below IIRDO, and a "high” will be detected, if its present
value is greater than IIRDO + IIRDA.
MIN
IIRDA
MAX
IIRDA
MAX
IIRDO
time
IRD
input
current
Figure 10: Photo Current Waveforms
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Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 17
Table 9: AC Current Amplitude of IR Diode Input in Slave Mode
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
IIRDO Input current offset 10 µAPP
IIRDA Input current amplitude 10 100 µAPP
Table 10: Digital Input IRD in Master/Repeater Mode
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VIL Voltage range for input ”low” level 0 2.5 V
VIH Voltage range for input ”high” level 3.5 VU5R V
Tr /Tf Rise/fall time 100 ns
1
1 In order to avoid jittery on the AS-i line, the rise/fall time of the IRD input signal should be as low as possible.
8.2.3 Fault Indication Input, FID
The fault indication input FID is a digital input dedicated for a periphery fault messaging signal (for properties see
Table 5). The S1 status bit is equivalent to the FID input signal. A FID transition will occur at S1 with a certain
delay, because a synchronizer circuit is put in between.
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Data Sheet Advanced AS-Interface IC
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Pages (total): 28 18
8.2.4 Voltage Outputs
Table 11: Properties of Voltage Output Pins UOUT and U5R
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VUOUT U
OUT output supply voltage VUIN-
VDROPmax
VUIN-
VDROPmin
V IUOUT = 30mA
VUOUTp U
OUT output voltage pulse deviation 1.5 V 1
tUOUTp U
OUT output voltage pulse deviation width 2 ms 1
VDROP Voltage drop from pin UIN to pin UOUT 6.5 7.7 V VUIN > 22V
VU5R 5V supply voltage 4.5 5.5 V
IUOUT U
OUT output supply current 0 30 mA IU5R = 0 2
I5V U5R output supply current 0 4 mA IUOUT < 26 mA
Io Total voltage output current IUOUT + I5V 30 mA
IUOUTS Short circuit output current 50 mA
CLUOUT Load capacitance at UOUT 10 470 µF
CL5V Load capacitance at U5R 1 µF
1 COUT = 10 µF, output current switches from 0 to 30 mA and vice versa.
2 11.0V < VOUT < 27.6V.
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Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 19
8.2.5 AS-i Bus Load
The following parameters are determined with short-cut between the pins ASIP and UIN and the pins ASIN and 0V,
respectively.
Table 12: AS-i Bus Interface Properties (Pins ASIP/ASIN and UIN)
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VUIN Input AS-i voltage at UIN V
UOUTmin+
VDROPmax
VUOUTmax +
VDROPmin
V 1
ILIN Input current limit at UIN 56 mA
VSIG Input signal voltage difference between ASIP
and ASIN
3 8 VPP
ISIG Modulated output peak current from ASIP to
ASIN
55 68 mAP
CZener Parasitic capacitance of the external over-
voltage protection diode (zener diode)
20 pF
2
RIN1 Equivalent resistor of the device 16 kΩ 2, 3
LIN1 Equivalent inductor of the device 18 mH 2, 3
CIN1 Equivalent capacitor of the device 30 pF 2, 3
RIN2 Equivalent resistor of the device 16 kΩ 2, 3
LIN2 Equivalent inductor of the device 12 18 mH 2, 3
CIN2 Equivalent capacitor of the device 15 +
(L-12mH)*2.5pF/mH pF 2, 3
1 DC Parameter
2 The equivalent circuit of a slave (which is calculated from the impedance of the device and the paralleled external over-voltage protection
diode (zener diode)) has to satisfy the Complete AS-i-Specification v.2.1 concerning the requirements for the extended address range.
3 Subtracting the maximum parasitic capacitance of the external over voltage protection diode (20pF) either the triple RIN1, LIN1 and CIN1 or
the triple RIN2, LIN2 and CIN2 has to be committed by the device to fulfil the Complete AS-i-Specification v2.1.
8.2.6 Input Impedance Control
Table 13: CAP Pin
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
RCAP External filter resistor 0 2.2 kΩ 1
CCAP External filter capacitor 4.7 100 nF 1, 2
1 Recommended values for optimal impedance are: RCAP = 1.2 kΩ and CCAP = 10 nF.
2 The de-coupling capacitor and serial resistor define internal low-pass filter time constant; lower values decrease the impedance but improve
the turn-on time. Higher values do not improve the impedance but do increase the turn-on time. The turn-on time also depends on the load
capacitor at UOUT. After connecting the slave to the power the capacitor is charged with the maximum current IUOUT. The impedance will
increase when the voltage allows the analog circuitry to fully operate.
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Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 20
8.2.7 Oscillator
Table 14: Oscillator Pins (OSC1 and OSC2)
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
COSC External parasitic capacitor at oscillator pins OSC1,
OSC2
0 5 pF
VIL Input ”low” voltage 0 1.5 V 1
VIH Input ”high” voltage 3.5 VU5R V
1 For external clock applied to OSC1 only.
8.2.8 Development Information Data
Table 15: Information Data
Conditions: Asynchronous mode, reset to default comparator level at „line pause“.
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VLSIGon Receiver comparator threshold level (see Figure
11)
45 50 % Related to
amplitude of 1st
pulse
treset1 Reset time after Master Call „Reset AS-i-Slave“ or
DSR = external L ->H transition
2 ms 1
treset2 Reset time after power on 30 ms 2
treset3 Reset time after power on with high capacitive load 1000 ms 3
VASIP-PF V
ASIP voltage to detect power fail (master mode
only)
21.5 23.5 V
tLoff Power supply break down time (master mode only) 0.7 0.9 ms 4
VPOR1F V
U5R voltage to trigger internal reset procedure,
falling voltage
3.0 4.0 V 1
VPOR1R V
U5R voltage to trigger INIT procedure, rising voltage 2.5 3.5 V 1
tLow Power-on reset pulse width 4 6 µs
TShut Chip temperature for thermal shut down
(overheating)
125 160 °C
1 Guaranteed by design only.
2 ‘Power_on’ starts latest at VUIN = 18V, external capacitor at pin UOUT = 10µF.
3 CUOUT = 470µF, treset3 is guaranteed by design only.
4 CUOUT > 10µF, no power fail generated at VASIP < VASIP-PF for t < tLoff (in master mode only).
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 21
First negative
pulse of the
ASI telegram
VLSIGon
VLSIGon =
(
0.45 - 0.50
)
* VSIG / 2
The IC determines the
amplitude of the first
negative pulse of the
ASI telegram. This
amplitude is asserted
to be VSIG / 2.
"DC level"
VSIG / 2
Figure 11: Receiver Comparator Set Up
VASIP
VPOR1R
VPOR1F
VUIN
VU5R
POR (active low)
No reset, but if the break down
time exceeds tLoff, a power-fail
signal will be generated
Reset will
be initalized
< ca. 15V
0V
≤ tLoff
VA
S
IP-PF
tLow
Power-on Reset will
be active, if the VU5R
drops below VPOR1F
MASTER MODE only All Modes
VA
S
IN
Figure 12: Power-Fail Generation (in Master Mode) and Reset Behavior (All Modes)
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 22
9 Application Circuits
The following figures show typical application cases of the A2SI™ IC. Figure 14 shows an application circuit in
which the A2SI™ is replacing an ASI3+ circuit. Finally, Figure 15 shows how the A2SI™ circuit can be used to
perform the analog/digital interface between the AS-i-line and the master electronics. Furthermore this figure shows
that the IC can be used in repeater applications as well.
9.1 EMC Precautions
Precaution must be taken to avoid radio frequency interference. It is recommended to keep input lines as short as
possible and to connect unused inputs to UOUT through a pull-up resistor. Furthermore, the supply pins should be
de-coupled with ceramic capacitors (10 to 100 nF) in addition to the normal de-coupling capacitors. Also, it is
recommended to connect a pull-up resistor from DSR (pin 22) to UOUT or U5R in order to avoid unintentional reset
under difficult EMC conditions.
9.2 Typical Slave Application
ASI+
ASI–
8 MHz
CCAP
DSR
PST
FID
LED
IRD
GND
0V
UIN
UOUT
U5R
U5RD
OSC1
CAP
ASIP
ASIN
10 µF
1 µF
A2SI™
OSC2
0V
+24V
+5V
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
DI_0
DI_1
DI_2
DI_3
DO_0
DO_1
DO_2
DO_3
P0
P1
P2
P3
DS&Reset
PST
Fault Input39V/1W
RCAP RED GREEN
10n 10n
17
18
19
20
11
10
9
8
16
15
14
13
22
21
5
23
26
27
24
4
12
3
25
2
1
6
7
28
22 kΩ
Figure 13: Typical Application, Slave Mode
Note: Figure 13 and 14 show all digital (data and parameter) ports without the application specific connections. For
correct function, it is important to consider that all output drivers are open drain stages and hence each port must
be connected with an appropriate pull-up resistor.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 23
9.3 Typical ASI3+ Compatible Application
ASI+
ASI–
CCAP
DSR
PST
FID
LED
IRD
GND
0V
UIN
UOUT
U5R
U5RD
CAP
ASIP
ASIN
10 µF
1 µF
A2SI™
8 MHz
OSC1
OSC2
0V
+24V
+5V
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
DIO-0
DIO-1
DIO-2
DIO-3
P0
P1
P2
P3
DS&Reset
PS
39V/1W
RCAP
10n
10n
22
21
5
24
4
26
17
18
19
20
11
10
9
8
16
15
14
13
23
27
12
7
6
28
1
2
25
3
Figure 14: Typical ASI3+ Compatible Application
Note: Depending on I/O-configuration, DO- and DI-ports are connected and Multiplex-Flag is set.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 24
9.4 Typical Master/Repeater Application
ASI+
ASI–
8 MHz
CCAP
DSR
PST
FID
LED
IRD
GND
0V
UIN
UOUT
U5R
U5RD
OSC1
CAP
ASIP
ASIN
1 µF
10 µF
A2SI™
OSC2
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
39V
+UB
Vo
GND
+UB
Vo
GND
+UB
Vo
GND
+UB
Vo
GND
+5V
REC-CLK
(optional)
REC-STRB
(optional)
RECEIVE
DATA
SEND
0V
ISOLATION
/POWER-FAIL
RCAP
10n
10n
27
16
15
14
13
22
5
24
23
26
4
21
12
3
25
2
1
6
7
28
Figure 15: Master/Repeater Application
For further information see also A²SI™ Application Note.
The information furnished here by AMIS is believed to be correct and accurate. However, AMIS shall not be liable to licensee or any third party
for any damages, including but no limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect,
special, incidental, or consequential damages of any kind in connection with or arising out of the furnishing, performance, or use of the technical
data. No obligation or liability to licensee or any third party shall arise or flow out of AMIS’ rendering technical or other services.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 25
10 Package Outline
Figure 17: SSOP Package
Figure 18: Package Dimensions
Table 16: Package Dimensions (mm)
Symbol A A1 A2 B C D E E H L α
Nominal 1.86 0.13 1.73 0.30 0.15 10.20 5.30 7.80 0.75 4°
Maximum 1.99 0.21 1.78 0.38 0.20 10.33 5.38 7.90 0.95 8°
Minimum 1.73 0.05 1.68 0.25 0.13 10.07 5.20
0.65
BSC 7.65 0.55 0°
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 26
11 Package Marking
PIN 1
TOP VIEW BOTTOM VIEW
PIN 1
AAAA
A2SI AMI
R-XXXX YZZ
+
Figure 19: Package Marking
Top Marking: A²SI Product name
AMIS or AMI Manufacturer
R- Revision code
XXXX Date code (year and week)
Y Assembly location
ZZ Traceability
Bottom Marking: AAAA Country of assembly
The yellow dot indicating pre-programmed Master function is printed at the pin 1 marking ⊕.
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 27
12 Ordering Information
12.1 Device Ordering Codes
Ordering Code Description Operating Temperature
Range
Package Type Device
Marking
Shipping Form
A2SI-ST Standard version of
A²SI
-25°C to 85°C 28-pin SSOP
(5.3 x 10.2)
A²SI Tubes
(47 parts/tube)
A2SI-SR Standard version of
A²SI
-25°C to 85°C 28-pin SSOP
(5.3 x 10.2)
A²SI Tape-and-Reel
(1500 parts/reel)
A2SI-MT Pre-programmed
master function
-25°C to 85°C 28-pin SSOP
(5.3 x 10.2)
A²SI
+ yellow dot
Tubes
(47 parts/tube)
A2SI-MR Pre-programmed
master function
-25°C to 85°C 28-pin SSOP
(5.3 x 10.2)
A²SI
+ yellow dot
Tape-and-Reel
(1500 parts/reel)
12.2 Demo Kit Ordering Code
Ordering Code Kit for Device Description
A2SI-KIT A²SI Kit includes:
• Evaluation board with A²SI™
• 3 A²SI samples
• 1 A²SI-M sample
• Literature (Brochure, Data Sheet, Application Note)
Evaluation board dimensions (L x W x H): 34 x 31 x 8 mm
A²SI™
Data Sheet Advanced AS-Interface IC
Revision 2.2
June 2001
Pages (total): 28 28
13 Application Support
13.1 AMIS Partners for Application Support
Bihl+Wiedemann
Flosswoerthstrasse 41
D-68199 Mannheim, Germany
Tel.: +49 621 3 3996 0
Fax: +49 621 3 3922 39
Email: mail@bihl-wiedemann.de
http://www.bihl-wiedemann.de
fieldbus specialists
217 Colchester Road, Kilsyth
3137 Victoria, Australia
Tel.: +61 3 9761 4653
Fax: +61 3 9761 5525
Email: fs_sales@fieldbus.com.au
http://www.fieldbus.com.au
13.2 General Information on AS-Interface
AS-International Association
Contact - Rolf Becker
Zum Taubengarten 52
D-63571 Gelnhausen
PO Box 1103 Zip (63551)
Tel: +49 6051 47 32 12
Fax: +49 6051 4732 82
Email: as-interface@t-online.de
http://www.as-interface.net
Further Information is available on http:// www.amis.com/a2si/
Sales Offices on http://www.amis.com/sales/
Products sold by AMIS are covered exclusively by the warranty, patent indemnification and other provisions appearing in AMIS standard "Terms
of Sale" (as the same may be amended by AMIS, at its sole discretion, from time to time). AMIS makes no warranty (express, statutory, implied
and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the
information set forth in the Materials pertaining to AMIS products, or regarding the freedom of any products described in the Materials from
patent and/or other infringement. AMIS reserves the right to discontinue production and change specifications and prices of its products at any
time and without notice. AMIS products are intended for use in commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are
specifically not recommended without additional mutually agreed upon processing by AMIS for such applications.
AMIS reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
A²SI™ is a trademark of AMI Semiconductor, Inc.
©Copyright 2000 AMI Semiconductor, Inc. 2300 Buckskin Road Pocatello, Idaho 83201, U.S.A. All rights reserved.
