For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1284/MAX1285 12-bit analog-to-digital con-
verters (ADCs) combine a high-bandwidth track/hold
(T/H), a serial interface with high conversion speed, an
internal +2.5V reference, and low power consumption.
The MAX1284 operates from a single +4.5V to +5.5V
supply. The MAX1285 operates from a single +2.7V to
+3.6V supply.
The 3-wire serial interface connects directly to
SPI™/QSPI™/ MICROWIRE™ devices without external
logic. The devices use an external serial-interface clock
to perform successive-approximation analog-to-digital
conversions.
Low power, ease of use, and small package size make
these converters ideal for remote-sensor and data-acqui-
sition applications or for other circuits with demanding
power consumption and space requirements. The
MAX1284/MAX1285 are available in 8-pin SO packages.
These devices are pin-compatible, higher-speed ver-
sions of the MAX1240/MAX1241. Refer to the respec-
tive data sheets for more information.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
____________________________Features
oSingle-Supply Operation
+4.5V to +5.5V (MAX1284)
+2.7V to +3.6V (MAX1285)
o±1LSB (max) DNL, ±1LSB (max) INL
o400ksps Sampling Rate (MAX1284)
oInternal Track/Hold
o+2.5V Internal Reference
oLow Power: 2.5mA (400ksps)
oSPI/QSPI/MICROWIRE 3-Wire Serial-Interface
oPin-Compatible, High-Speed Upgrades to
MAX1240/MAX1241
o8-Pin SO Package
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
________________________________________________________________
Maxim Integrated Products
1
19-1687; Rev 2; 12/10
TOP VIEW
1
2
3
4
8
7
6
5
SCLK
CS
DOUT
GND
REF
SHDN
AIN
VDD
SO
MAX1284
MAX1285
+
Pin Configuration
Ordering Information
Functional Diagram
7
AIN T/H
DOUT
6
1
OUTPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
12-BIT
SAR
8
2
3
5
REF 4
SHDN
+2.5V REFERENCE
GND
SCLK
CS
MAX1284
MAX1285
VDD
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX1284/MAX1285
+
Denotes a lead(Pb)-free/RoHS-compliant package.
PART
TEMP RANGE
PIN-
PACKAGE
SUPPLY
VOLTAGE (V)
MAX1284BCSA+
0°C to +70°C
8 SO 5
MAX1284BESA+
-40°C to +85°C
8 SO 5
MAX1285BCSA+
0°C to +70°C
8 SO 2.7 to 3.6
MAX1285BESA+
-40°C to +85°C
8 SO 2.7 to 3.6
EVALUATION KIT
AVAILABLE
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
2 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX1284
(VDD = +4.5V to +5.5V; fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
VDD to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C) ..............471mW
Operating Temperature Ranges
MAX1284BCSA/MAX1285BCSA .......................0°C to +70°C
MAX1284BESA/MAX1285BESA .....................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
Soldering Temperature (reflow)......................................+260°C
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
DC ACCURACY (Note 1)
Resolution 12
Relative Accuracy (Note 2) INL
±1.0
Differential Nonlinearity DNL No missing codes over temperature
±1.0
Offset Error
±6.0
Gain Error (Note 3)
±6.0
Gain-Error Temperature
Coefficient
±0.8
DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5VP-P, clock = 6.4MHz)
Signal-to-Noise Plus Distortion
Ratio
SINAD
70 dB
Total Harmonic Distortion THD Up to the 5th harmonic -80 dB
Spurious-Free Dynamic Range SFDR 80 dB
Intermodulation Distortion IMD fIN1 = 99Hz, fIN2 = 102Hz 76 dB
Full-Power Bandwidth -3dB point 6
Full-Linear Bandwidth SINAD > 68dB
350
CONVERSION RATE
Conversion Time (Note 4)
tCONV
2.5 µs
Track/Hold Acquisition Time tACQ
468
ns
Aperture Delay 10 ns
Aperture Jitter
< 50
ps
Serial Clock Frequency tSCLK 0.5 6.4
Duty Cycle 40 60 %
ANALOG INPUT (AIN)
Input Voltage Range VAIN 0 2.5 V
Input Capacitance 18 pF
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX1284 (continued)
(VDD = +4.5V to +5.5V; fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS—MAX1285
(VDD = +2.7V to +3.6V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE
REF Output Voltage VREF
2.48 2.50 2.52
V
REF Short-Circuit Current TA = +25°C 30 mA
REF Output Tempco
TC VREF ±15
ppm/°C
Load Regulation (Note 5) 0 to 1mA output load 0.1 2.0
mV/mA
Capacitive Bypass at REF 4.7 10 µF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage VINH 3.0 V
Input Low Voltage VINL 0.8 V
Input Hysteresis
VHYST
0.2 V
Input Leakage IIN VIN = 0V or VDD ±1 µA
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT)
Output Voltage Low VOL ISINK = 5mA 0.4 V
Output Voltage High VOH ISOURCE = 1mA 4 V
Three-State Leakage Current ILVCS = +5V
±10
µA
Three-State Output Capacitance
COUT VCS = +5V 15 pF
POWER SUPPLY
Positive Supply Voltage (Note 6)
VDD 4.5 5.5 V
Positive Supply Current (Note 7)
IDD VDD = +5.5V 2.5 4.0 mA
Shutdown Supply Current ISHDN SCLK = VDD, SHDN = GND 2 10 µA
Power-Supply Rejection PSR VDD = +5V ±10%, midscale input
±0.5 ±2.0
mV
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DC ACCURACY (Note 1)
Resolution 12
Bits
Relative Accuracy (Note 2) INL
±1.0
LSB
Differential Nonlinearity DNL No missing codes over temperature
±1.0
LSB
Offset Error
±6.0
LSB
Gain Error (Note 3)
±6.0
LSB
Gain-Error Temperature
Coefficient
±1.6
ppm/°C
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX1285 (continued)
(VDD = +2.7V to +3.6V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS (75kHz sine wave, 2.5VP-P, fSAMPLE = 300ksps, fSCLK = 4.8MHz)
Signal-to-Noise Plus Distortion
Ratio
SINAD
70 dB
Total Harmonic Distortion THD Up to the 5th harmonic -80 dB
Spurious-Free Dynamic Range SFDR 80 dB
Intermodulation Distortion IMD fIN1 = 73kHz, fIN2 = 77kHz 76 dB
Full-Power Bandwidth -3dB point 3
MHz
Full-Linear Bandwidth SINAD > 68dB
250 kHz
CONVERSION RATE
Conversion Time (Note 4)
tCONV
3.3 µs
Track/Hold Acquisition Time tACQ
625
ns
Aperture Delay 10 ns
Aperture Jitter
< 50
ps
Serial Clock Frequency tSCLK 0.5 4.8
MHz
Duty Cycle 40 60 %
ANALOG INPUT (AIN)
Input Voltage Range VAIN 0 2.5 V
Input Capacitance 18 pF
INTERNAL REFERENCE
REF Output Voltage VREF
2.48 2.50 2.52
V
REF Short-Circuit Current TA = +25°C 15 mA
REF Output Tempco
TC VREF ±15 ppm/°C
Load Regulation (Note 5) 0 to 0.75mA output load 0.1 2.0
mV/mA
Capacitive Bypass at REF 4.7 10 µF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage VINH 2.0 V
Input Low Voltage VINL 0.8 V
Input Hysteresis
VHYST
0.2 V
Input Leakage IIN VIN = 0V or VDD ±1 µA
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT)
Output Voltage Low VOL ISINK = 5mA 0.4 V
Output Voltage High VOH ISOURCE = 0.5mA
VDD - 0.5
V
Three-State Leakage Current ILVCS = +3V
±10
µA
Three-State Output Capacitance
COUT VCS = +3V 15 pF
POWER SUPPLY
Positive Supply Voltage (Note 6)
VDD 2.7 3.6 V
Positive Supply Current (Note 7)
IDD VDD = +3.6V 2.5 3.5 mA
Shutdown Supply Current ISHDN SCLK = VDD, SHDN = GND 2 10 µA
Power-Supply Rejection PSR VDD = +2.7V to 3.6V, midscale input
±0.5 ±2.0
mV
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 5
SCLK Rise to CS Fall Ignore tCSO 35 ns
SCLK Rise to CS Rise Hold tCSH 0ns
CS Fall to SCLK Rise Setup tCSS 35 ns
SCLK Pulse-Width Low tCL 62 ns
CS Rise to SCLK Rise Ignore tCS1 35 ns
SCLK Rise to DOUT Hold tDOH 10 ns
SCLK Rise to DOUT Valid tDOV 80 ns
CLOAD = 20pF
CLOAD = 20pF
SCLK Pulse-Width High tCH 62 ns
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
SCLK Period tCP 156 ns
TIMING CHARACTERISTICS—MAX1284 (Figures 1, 2, 8, 9)
(VDD = +4.5V to +5.5V, TA= TMIN to TMAX, unless otherwise noted.)
TIMING CHARACTERISTICS—MAX1285 (Figures 1, 2, 8, 9)
(VDD = +2.7V to +3.6V, TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at VDD = VDD(MIN).
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitations.
Note 6: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operations beyond this range, see
Typical
Operating Characteristics
.
Note 7: MAX1284 tested with 20pF on DOUT and fSCLK = 6.4MHz, 0 to 5V. MAX1285 tested with same loads, fSCLK = 4.8MHz,
0 to 3V. DOUT = full scale.
CS Rise to DOUT Disable tDOD 10 65 ns
CS Fall to DOUT Enable tDOE 65 ns
CS Pulse-Width High tCSW 100 ns
CLOAD = 20pF
CLOAD = 20pF
SCLK Rise to CS Fall Ignore tCSO 45 ns
SCLK Rise to CS Rise Hold tCSH 0ns
CS Fall to SCLK Rise Setup tCSS 45 ns
SCLK Pulse-Width Low tCL 83 ns
CS Rise to SCLK Rise Ignore tCS1 45 ns
SCLK Rise to DOUT Hold tDOH 13 ns
SCLK Rise to DOUT Valid tDOV 100 ns
CS Rise to DOUT Disable tDOD 13 85 ns
CLOAD = 20pF
CLOAD = 20pF
CS Fall to DOUT Enable tDOE 85 ns
CS Pulse-Width High tCSW 100 ns
CLOAD = 20pF
CLOAD = 20pF
SCLK Period tCP 208
SCLK Pulse-Width High tCH 83 ns
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
ns
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
6 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(MAX1284: VDD = +5.0V, fSCLK = 6.4MHz, MAX1285: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
01k2k3k 5k
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1284/5 toc01
DIGITAL OUTPUT CODE
INL (LSB)
4k
-0.4
-0.1
-0.2
-0.3
0
0.1
0.2
0.3
0.4
0.5
0.6
02k1k 3k 4k 5k
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1284/5 toc02
DIGITAL OUTPUT CODE
DNL (LSB)
-1.0
0
-0.5
1.0
0.5
1.5
2.0
2.5 4.0 4.53.0 3.5 5.0 5.5 6.0
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1284/5 toc03
VDD (V)
OFFSET ERROR (LSB)
0
0.4
0.2
1.0
0.8
0.6
1.6
1.4
1.2
1.8
-40 0 20-20 40 60 80 100
OFFSET ERROR vs. TEMPERATURE
MAX1284/5 toc04
TEMPERATURE (°C)
OFFSET ERROR (LSB)
2.490
2.496
2.494
2.492
2.498
2.500
2.502
2.504
2.506
2.508
2.510
2.5 3.53.0 4.0 4.5 5.0 5.5
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1284/5 toc07
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
2.5 3.53.0 4.0 4.5 5.0 5.5
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1284/5 toc05
VDD (V)
GAIN ERROR (LSB)
-2.5
-1.5
-2.0
-0.5
-1.0
0.5
0
1.0
-40 0 20-20 40 60 80 100
GAIN ERROR vs. TEMPERATURE
MAX1284/5 toc06
TEMPERATURE (°C)
GAIN ERROR (LSB)
2.490
2.496
2.494
2.492
2.500
2.498
2.508
2.506
2.504
2.502
2.510
-40 -20 0 20 40 60 80 100
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1284/5 toc08
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(MAX1284: VDD = +5.0V, fSCLK = 6.4MHz, MAX1285: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
1.5
1.8
2.4
2.1
2.7
3.0
-40 0-20 20 40 60 80 100
SUPPLY CURRENT vs. TEMPERATURE
MAX1284/5 toc10
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VDD = 5V, CONVERTING
VDD = 3V, CONVERTING
VDD = 5V, STATIC VDD = 3V, STATIC
Serial-Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz
(MAX1284) or 4.8MHz (MAX1285).
PIN
Positive Supply VoltageVDD
1
FUNCTIONNAME
Sampling Analog Input, 0 to VREF rangeAIN2
Analog and Digital GroundGND5
Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
CS
7
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with 4.7µF
capacitor.
REF4
Active-Low Shutdown Input. Pulling SHDN low shuts down the device and reduces the supply current
to 2µA (typ).
SHDN
3
SCLK8
Pin Description
1.50
2.00
1.75
2.50
2.25
2.75
3.00
2.5 3.5 4.03.0 4.5 5.0 5.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1284/5 toc09
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
CONVERTING
SCLK = 6.4MHz
CONVERTING
SCLK = 4.8MHz
STATIC
CODE = 1111 1111 1111
RL = ∞
CL = 10pF
Serial-Data Output. DOUT changes state at SCLK’s rising edge High impedance when CS is high.DOUT6
Detailed Description
Converter Operation
The MAX1284/MAX1285 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. Figure
3 shows the MAX1284/MAX1285 in its simplest configu-
ration. The internal reference is trimmed to +2.5V. The
serial interface requires only three digital lines (SCLK,
CS,
and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1284/MAX1285 have two modes: normal and
shutdown. Pulling
SHDN
low shuts the device down and
reduces supply current to below 2µA (typ), while pulling
SHDN
high puts the device into operational mode. Pulling
CS low initiates a conversion that is driven by SCLK. The
conversion result is available at DOUT in unipolar serial
format. The serial data stream consists of three zeros,
followed by the data bits (MSB first). All transitions on
DOUT occur 20ns after the rising edge of SCLK. Figures
8 and 9 show the interface timing information.
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s comparator. The full-scale input voltage is set by
the internal reference (VREF = +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing
CS
low, ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD rep-
resents a sample of the input, unbalancing node ZERO
at the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
8 _______________________________________________________________________________________
DOUT DOUT
6kΩ
DGND
CLOAD = 20pF CLOAD = 20pF
6kΩ
DGND
VDD
b) High-Z to VOL and VOH to VOL
a) High-Z to VOH and VOL to VOH
Figure 1. Load Circuits for DOUT Enable Time
DOUT DOUT
6kΩ
DGND
CLOAD = 20pF CLOAD = 20pF
6kΩ
DGND
VDD
b) VOL to High-Z
a) VOH to High-Z
Figure 2. Load Circuits for DOUT Disable Time
MAX1284/MAX1285
side of CHOLD switches back to AIN, and CHOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. Acquisition time is calculated by:
tACQ = 9(RS+ RIN) x 12pF,
where RIN = 800Ω, RS= the input signal’s source
impedance, and tACQ is never less than 468ns
(MAX1284) or 625ns (MAX1285). Source impedances
below 2kΩdo not significantly affect the ADCs AC per-
formance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADCs input signal
bandwidth.
Input Bandwidth
The ADCs’ input tracking circuitry has a 6MHz
(MAX1284) or 3MHz (MAX1285) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate, by using under-
sampling techniques. To avoid aliasing of unwanted
high-frequency signals into the frequency band of inter-
est, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow the input to swing from
(GND - 0.3V) to (VDD + 0.3V) without damage.
If the analog input exceeds 50mV beyond the sup-
plies, limit the input current to 2mA.
Internal Reference
The MAX1284/MAX1285 have an on-chip voltage refer-
ence trimmed to 2.5V. The internal reference output is
connected to REF and also drives the internal capaci-
tive DAC. The output can be used as a reference volt-
age source for other components and can source up to
800µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shut-
down (see the
Using SHDN to Reduce Supply Current
section). The internal reference is disabled in shutdown
(SHDN = 0).
Serial Interface
Initialization after Power-Up and
Starting a Conversion
When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7µF reference
bypass capacitor up to 2ms to provide adequate
charge for specified accuracy. No conversions should
be performed during this time.
CHOLD
12pF
RIN
800Ω
HOLD
CSWITCH*
6pF
*INCLUDES ALL INPUT PARASITICS
AIN
REF
GND
ZERO
AUTOZERO
RAIL
COMPARATOR
CAPACITIVE DAC
TRACK
SHUTDOWN
INPUT
ANALOG INPUT
0 TO VREF
+5V OR +3V
1
2
3
4
VDD
AIN
SHDN
REF
8
7
6
5
SCLK
CS
DOUT
GND
SERIAL
INTERFACE
4.7μF
10μF 0.1μF
MAX1284
MAX1285
Figure 3. Typical Operating Circuit
Figure 4. Equivalent Input Circuit
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 9
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
10 ______________________________________________________________________________________
Figure 5. Supply Current vs. Conversion Rate
To start a conversion, pull
CS
low. At
CS’s
falling edge,
the T/H enters its hold mode and a conversion is initiat-
ed. Data can then be shifted out serially with the exter-
nal clock.
Using
SHDN
to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX1284/MAX1285 between con-
versions. Figure 5 shows a plot of average supply cur-
rent versus conversion rate. The wake-up time (tWAKE)
is the time from when SHDN is deasserted to the time
when a conversion may be initiated (Figure 6). This
time depends on the time in shutdown (Figure 7)
because the external 4.7µF reference bypass capacitor
loses charge slowly during shutdown and can be as
long as 2ms.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the
CS
and SCLK digital inputs. The timing dia-
grams of Figures 8 and 9 outline serial-interface
operation.
A
CS
falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of conversion
is determined.
SCLK begins shifting out the data after the rising edge
of the third SCLK pulse. DOUT transitions 20ns after
each SCLK rising edge. The third rising clock edge
produces the MSB of the conversion at DOUT, followed
by the remaining bits. Since there are twelve data bits
and three leading zeros, at least fifteen rising clock
edges are needed to shift out these bits. Extra clock
pulses occurring after the conversion result has been
clocked out, and prior to a rising edge of
CS
, produce
trailing zeros at DOUT and have no effect on converter
operation.
Pull
CS
high after reading the conversion’s LSB. For
maximum throughout,
CS
can be pulled low again to
initiate the next conversion immediately after the speci-
fied minimum time (tCS).
Output Coding and Transfer Function
The data output from the MAX1284/MAX1285 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successive-
integer LSB value V
REF
= +2.5V, and 1LSB = 610µV or
2.5V/4096.
COMPLETE CONVERSION SEQUENCE
CONVERSION 0 CONVERSION 1
POWERED-UPPOWERED-UP POWERED-DOWN
tWAKE
DOUT
CS
SHDN
Figure 6. Shutdown Sequence
0.1
1
100
10
1k
10k
0.1 101 100 1000 10,000 100,000
CONVERSION RATE (ksps)
SUPPLY CURRENT (μA)
VDD = 3V
DOUT = FS
RL = ∞
CL = 10pF
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 11
Applications Information
Connection to Standard Interfaces
The MAX1284/MAX1285 serial interface is fully compat-
ible with SPI/QSPI and MICROWIRE (Figure 11).
If a serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 6.4MHz (MAX1284) or
4.8MHz (MAX1285).
1) Use a general-purpose I/O line on the CPU to pull
CS
low. Keep SCLK low.
2) Activate SCLK for a minimum of fifteen clock cycles.
The first two clocks produce zeros at DOUT. DOUT
output data transitions 20ns after the third SCLK rising
edge and is available in MSB-first format. Observe the
0
0.50
0.25
1.00
0.75
1.25
1.50
0.0001 0.010.001 0.1 1 10
TIME IN SHUTDOWN (s)
REFERENCE POWER-UP DELAY (ms)
CREF = 4.7μF
Figure 7. Reference Power-Up vs. Time in Shutdown
A/D STATE
DOUT HIGH-Z HIGH-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
143 8 12 15
ACQ
CS
HOLD/CONVERT ACQUISITION
Figure 8. Interface Timing Sequence
CS
SCLK
DOUT
tDOE
tDOH
tDOD
tDOV
tCSO tCSS tCSI
tCSO tCSH
tCH
tCL
tCP
tCSW
Figure 9. Detailed Serial-Interface Timing
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
12 ______________________________________________________________________________________
SCLK to DOUT valid timing characteristic. Data can be
clocked into the µP on SCLK rising edge.
3) Pull
CS
high at or after the 15th rising clock edge. If CS
remains low, trailing zeros are clocked out after the
LSB.
4) With CS = high, wait the minimum specified time, tCS,
before initiating a new conversion by pulling CS low. If
a conversion is aborted by pulling CS high before the
conversion completes, wait for the minimum acquisition
time, tACQ, before starting a new conversion.
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with three leading zeros and three
trailing zeros.
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a
CS
falling edge.
DOUT goes low, indicating a conversion in progress. Two
consecutive 1-byte reads are required to get the full
twelve bits from the ADC. DOUT output data transitions
on SCLK’s rising edge and is clocked into the following
µP on the rising edge.
The first byte contains three leading zeros, and five bits of
conversion result. The second byte contains the remaining
seven bits and one trailing zero. See Figure 11 for con-
nections and Figure 12 for timing.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1284/MAX1285 require 15 clock cycles
from the µP to clock out the 12 bits of data. Figure 13
shows a transfer using CPOL = 0 and CPHA = 1. The
conversion result contains two zeros followed by the 12
bits of data in MSB-first formatted.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap boards
are not recommended. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the ADC package.
11…111
11…110
11…101
00…011
00…010
00…001
00…000
012 FS
OUTPUT CODE
FS - 3/2LSBINPUT VOLTAGE (LSBs)
FS = VREF
1LSB = VREF
4096
FULL-SCALE
TRANSITION
3
Figure 10. Unipolar Transfer Function, Full Scale (FS) = V
REF
,
Zero Scale (ZS) = GND
CS
SCLK
DOUT
I/O
SCK
MISO
+3V TO +5V
SS
a) SPI
CS
SCLK
DOUT
CS
SCK
MISO
+3V TO +5V
SS
b) QSPI
MAX1284
MAX1285
MAX1284
MAX1285
MAX1284
MAX1285
CS
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1284/MAX1285
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 13
Figure 14 shows the recommended system ground con-
nections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1µF and 10µF
bypass capacitors. Minimize capacitor lead lengths for
best supply noise rejection. To reduce the effects of sup-
ply noise, a 10Ωresistor can be connected as a lowpass
filter to attenuate supply noise (Figure 14).
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1284/MAX1285 are mea-
sured using the endpoints method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A DNL
error specification of 1LSB or less guarantees no missing
codes and a monotonic transfer function.
CS
SCLK
DOUT
916
8
1
D0
D11 D10 D9 D8 D6 D5 D4 D3 D2 D1
D7
FIRST BYTE READ SECOND BYTE READ
HIGH-Z HIGH-Z
SCLK
DOUT
CS
14
13
D11 D10 D9 D8 D4D5D6 D3 D2 D1 D0
HIGH-Z
D7
HIGH-Z
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)
MAX1284/MAX1285
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CS and the instant when an actual sample
is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The theoretical minimum analog-to-digital
noise is caused by quantization error, and results directly
from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 x log (SignalRMS/NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the effective number of bits
as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd through 5th-order har-
monics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
THD x VVVV
V
=+++
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20 2
23
24
25
2
1
log
ENOB SINAD=−(.)
.
176
602
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
14 ______________________________________________________________________________________
SUPPLIES
GND
DGNDVDD
DIGITAL
CIRCUITRY
GNDVDD
MAX1284
MAX1285
*OPTIONAL
R* = 10Ω
4.7μF
0.1μF
VDD VDD
Figure 14. Power-Supply Grounding Condition
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 SO S8+5 21-0041 90-0096
MAX1284/MAX1285
2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/00 Initial release —
1 7/00 Release of MAX1284 1
2 12/10 Add lead-free, update Absolute Maximum Ratings, update Figure 10, style updates 1–5, 7, 9, 10,
12, 14, 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
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