DG408/409
Vishay Siliconix
Document Number: 70062
S-52433—Rev. E, 06-Sep-99 www.vishay.com
1
8-Ch/Dual 4-Ch High-Performance CMOS Analog Multiplexers
FEATURES BENEFITS APPLICATIONS
DLow On-Resistance—rDS(on): 100
DLow Charge Injection—Q: 20 pC
DFast Transition Time—tTRANS: 160 ns
DLow Power—ISUPPLY: 10 A
DSingle Supply Capability
D44-V Supply Max Rating
DTTL Compatible Logic
DReduced Switching Errors
DReduced Glitching
DImproved Data Throughput
DReduced Power Consumption
DIncreased Ruggedness
DWide Supply Ranges ("5 V to "20 V)
DData Acquisition Systems
DAudio Signal Routing
DATE Systems
DBattery Powered Systems
DHigh Rel Systems
DSingle Supply Systems
DMedical Instrumentation
DESCRIPTION
The DG408 is an 8-channel single-ended analog multiplexer
designed to connect one of eight inputs to a common output
as determined by a 3-bit binary address (A0, A1, A2). The
DG409 is a dual 4-channel differential analog multiplexer
designed t o connect one of four dif ferential inputs to a common
dual output as determined by its 2-bit binary address (A0, A1).
Break-before-make switching action protects against
momentary crosstalk between adjacent channels.
An on channel conducts current equally well in both directions.
In the off state each channel blocks voltages up to the power
supply rails. An enable (EN) function allows the user to reset
the multiplexer/demultiplexer to all switches off for stacking
several devices. All control inputs, address (Ax) and enable
(EN) are TTL compatible over the full specified operating
temperature range.
Applications for the DG408/409 include high speed data
acquisition, audio signal switching and routing, ATE systems,
and avionics. High performance and low power dissipation
make them ideal for battery operated and remote
instrumentation applications.
Designed in the 44-V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 V.
Additionally, single supply operation is also allowed. An
epitaxial layer prevents latchup.
For additional information please see Technical Article TA201
(FaxBack Number 70600).
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
S3
A0
S6
D
S4
A1
S8
S7
EN
Dual-In-Line
SOIC and TSSOP
A2
V– GND
S1V+
S2S5
Decoders/Drivers
1
2
3
4
5
6
7
16
15
14
13
12
11
10
Top View
89
A0
Da
A1
Db
EN GND
V– V+
S1a S1b
S2a S2b
S3a S3b
S4a S4b
Dual-In-Line
SOIC and TSSOP
Decoders/Drivers
1
2
3
4
5
6
7
16
15
14
13
12
11
10
Top View
89
DG408 DG409