CY62256V 32K x 8 Static RAM Features feature, reducing the power consumption by over 99% when deselected. The CY62256V family is available in the standard 450-mil-wide (300-mil body width) SOIC, TSOP, and reverse TSOP packages. * Low voltage range: -- CY62256V (2.7V-3.6V) * * * * * An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. -- CY62256V25 (2.3V-2.7V) Low active power and standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Functional Description The CY62256V family is composed of two high-performance CMOS static RAM's organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. These devices have an automatic power-down The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. Logic Block Diagram Pin Configurations SOIC Top View I/O0 INPUTBUFFER I/O1 I/O2 SENSE AMPS ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 512 x 512 ARRAY I/O3 I/O4 I/O5 CE WE COLUMN DECODER A12 A11 A1 A0 A13 A14 8 9 5 4 3 2 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O7 7 6 1 28 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I/O6 POWER DOWN OE A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP I Reverse Pinout Top View (not to scale) Cypress Semiconductor Corporation Document #: 38-05057 Rev. *B 19 20 21 * A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 3901 North First Street 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 * TSOP I Top View (not to scale) San Jose * 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 CA 95134 * 408-943-2600 Revised May 16, 2002 CY62256V DC Input Voltage[1].................................... -0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied................................................... 0C to +70C Operating Range Supply Voltage to Ground Potential (Pin 28 to Pin 14).................................................-0.5V to +4.6V Range Ambient Temperature 0C to +70C 2.3V to 3.6V -40C to +85C 2.3V to 3.6V Commercial DC Voltage Applied to Outputs in High-Z State[1] ....................................... -0.5V to VCC + 0.5V Industrial VCC Product Portfolio Power Dissipation VCC Range (V) Product Typ.[2] Min. Speed Max. (ns) Operating, ICC (mA) Standby, ISB2 (A) Typ.[2] Max. Typ.[2] Max. CY62256V 2.7 3.0 3.6 70 11 30 0.1 5 CY62256V25 2.3 2.5 2.7 100 9 15 0.1 4 Electrical Characteristics Over the Operating Range CY62256V-70 Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = -1.0 mA Vcc= 2.7V VOL Output LOW Voltage IOL = 2.1 mA Vcc= 2.7V VIH Input HIGH Voltage VIL Input Leakage Voltage IIX Input Leakage Current IOZ Output Leakage Current ICC VCC Operating Supply Current VCC = 3.6V, IOUT = 0 mA, f = fMAX = 1/tRC Com'l ISB1 Automatic CE Power-down Current-- TTL Inputs VCC = 3.6V, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-down Current-- CMOS Inputs Typ.[2] Max. 2.4 Unit V 0.4 V 2.2 VCC +0.3V V -0.5 0.8 V GND < VIN < VCC -1 +1 A GND < VIN < VCC, Output Disabled -1 +1 A 11 30 mA Com'l 100 300 A VCC = 3.6V, CE > VCC - 0.3V Com'l VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Ind'l 0.1 5 A 10 A Max. Unit Electrical Characteristics Over the Operating Range CY62256V25-100 Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = -0.1 mA Vcc= 2.3V VOL Output LOW Voltage IOL = 0.1 mA Vcc= 2.3V VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current GND < VIN < VCC Typ.[2] 2 V 0.4 V 1.7 Vcc + 0.3V V -0.3 0.7 V -1 +1 A Output Leakage Current GND < VIN < VCC, Output Disabled -1 +1 A Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25C, and tAA = 70 ns. IOZ Document #: 38-05057 Rev. *B Page 2 of 11 CY62256V Electrical Characteristics Over the Operating Range (continued) CY62256V25-100 Parameter Description Test Conditions Min. Typ.[2] Max. Unit ICC VCC Operating Supply Current VCC = 2.7V, IOUT = 0 mA, f = fMAX = 1/tRC Com'l 14 23 mA ISB1 Automatic CE Power-down Current-- TTL Inputs VCC = 2.7V, CE > VIH, Com'l VIN > VIH or VIN < VIL, f = fMAX 75 225 A ISB2 Automatic CE Power-down Current -- CMOS Inputs VCC = 2.7V, CE > VCC - 0.3V Com'l VIN > VCC - 0.3V or VIN < 0.3V, f Ind'l =0 0.1 4 A 8 A Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25C, f = 1 MHz, VCC = 3.0V AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC R2 50 pF GND < 5 ns < 5 ns INCLUDING JIG AND SCOPE Equivalent to: 90% 10% 90% 10% THEVENIN EQUIVALENT Rth OUTPUT Vth Parameter 3.3V 2.5V Units R1 1.100 16.60 K Ohms R2 1.500 15.40 K Ohms RTH 0.645 8.00 K Ohms VTH 1.750 1.20 Volts Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[3] Operation Recovery Time Conditions[4] Min. Typ.[2] Max. 1.4 VCC = 1.6V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Com'l V 0.1 Ind'l Unit 3 A 6 A 0 ns tRC ns Notes: 3. Tested initially and after any design or process changes that may affect these parameters. 4. No input may exceed VCC + 0.3V. Document #: 38-05057 Rev. *B Page 3 of 11 CY62256V Data Retention Waveform DATA RETENTION MODE 1.8V VCC 1.8V VDR > 1.4V tR tCDR CE Switching Characteristics Over the Operating Range[5] CY62256V-70 Parameter Description Min. Max. CY62256V25-100 Min. Max. Unit Read Cycle tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 100 ns tDOE OE LOW to Data Valid 35 75 ns [6] tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[6, 7] [6] tLZCE CE LOW to Low-Z tHZCE CE HIGH to High-Z[6, 7] tPU CE LOW to Power-up tPD CE HIGH to Power-down Write Cycle 100 70 10 ns 100 10 5 ns 5 25 10 ns 50 10 25 0 ns ns 50 0 70 ns ns ns 100 ns [8, 9] tWC Write Cycle Time 70 100 ns tSCE CE LOW to Write End 60 90 ns tAW Address Set-up to Write End 60 90 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 50 80 ns tSD Data Set-up to Write End 30 60 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High-Z[6, 7] tLZWE [6] WE HIGH to Low-Z 0 25 10 ns 50 10 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05057 Rev. *B Page 4 of 11 CY62256V Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT Read Cycle No. 2 tAA PREVIOUS DATA VALID DATA VALID [11, 12] t RC CE tACE OE t HZOE tHZCE tDOE DATA OUT t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT t PD t PU ICC 50% 50% Write Cycle No. 1 (WE Controlled) ISB [8, 13, 14] tWC ADDRESS CE tAW tSA WE tHA t PWE OE tSD DATA I/O NOTE 15 tHD DATAINVALID t HZOE Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. Document #: 38-05057 Rev. *B Page 5 of 11 CY62256V Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [8, 13, 14] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O t HD DATAINVALID Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14] tWC ADDRESS CE tAW t HA tSA WE tSD DATA I/O NOTE 15 t HZWE t HD DATA INVALID tLZWE Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05057 Rev. *B Page 6 of 11 CY62256V Typical DC and AC Characteristics 1.4 1.6 1.4 1.2 2.5 1.0 2.0 0.4 0.2 0.0 25 2.0 1.4 OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 NORMALIZED t AA VCC = 3.0V TA = 25C 0.0 1.65 VCC = 2.5V 1.2 1.0 0.8 0.5 2.1 2.6 3.1 3.6 0.6 -55 25 125 AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT (mA) SUPPLY VOLTAGE (V) 3V 3. 5V = 25 105 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) 2.5 ISB -0.5 -55 125 = 0.5 SUPPLY VOLTAGE (V) 1.0 1.0 0.4 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.5 1.5 2. 0.6 0.0 -55 3.6 3.2 2.8 2.4 2.0 1.8 1.6 VCC = 2.5V cc TA= 25C 0.6 0.8 cc 0.8 V 1.0 V 1.2 3.0 VCC = 3.0V ISB2 A NORMALIZED I CC NORMALIZED ICC 1.8 0.2 NORMALIZED t AA STANDBY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT SINK CURRENT 14 vs. OUTPUT VOLTAGE 12 10 8 6 VCC = 2.5 V 4 TA = 25C 2 0 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE -14 -12 -10 -8 VCC = 2.5V -6 TA = 25C -4 0 0.0 0.5 1.0 1.5 2 2.5 OUTPUT VOLTAGE (V) Document #: 38-05057 Rev. *B Page 7 of 11 CY62256V Typical DC and AC Characteristics (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING NORMALIZED I CC vs.CYCLE TIME 1.25 25.0 T = 25C A VCC = 3V 20.0 NORMALIZED ICC DELTA tAA (ns) 30.0 15.0 10.0 VCC = 3.0V 1.00 TA = 25C VIN = 0.5V 0.75 5.0 0.0 0 200 400 600 0.50 1 800 1000 10 20 30 CYCLE FREQUENCY (MHz) CAPACITANCE (pF) Truth Table Inputs/Outputs Mode Power CE WE OE H X X High-Z Deselect/Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High-Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) 70 Ordering Code CY62256VLL-70SNC CY62256VLL-70ZC Package Name Package Type SN28 28-lead (300-mil Narrow Body) SOIC Commercial Z28 28-lead Thin Small Outline Package Commercial CY62256VLL-70ZI 100 Industrial CY62256VLL -70SNI SN28 28-lead (300-mil Narrow Body) SOIC CY62256VLL-70ZRI ZR28 28-lead Reverse Thin Small Outline Package CY62256V25LL-100ZC Document #: 38-05057 Rev. *B Operating Range Z28 28-lead Thin Small Outline Package Industrial Commercial Page 8 of 11 CY62256V Package Diagrams 28-lead (300-mil) SNC (Narrow Body) SN28 51-85092-*B 28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28 51-85071-*G Document #: 38-05057 Rev. *B Page 9 of 11 CY62256V Package Diagrams (continued) 28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28 51-85074-*F All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05057 Rev. *B Page 10 of 11 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62256V Document Title: CY62256V 32K x 8 Static RAM Document Number: 38-05057 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107248 09/10/01 SZV Change from Spec number: 38-00519 to 38-05057. *A 111445 11/01/01 MGN Remove obsolete parts. Change to standard format. *B 115229 05/23/02 GBI Document #: 38-05057 Rev. *B Changed SN package diagram. Page 11 of 11