Product Folder Order Now Support & Community Tools & Software Technical Documents TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 TPS735 500-mA, Low Quiescent Current, Low Noise, High PSRR, Low-Dropout Linear Regulator 1 Features 3 Description * * * * The TPS735 low-dropout (LDO), low-power linear regulator offers excellent AC performance with very low ground current. High power-supply rejection ratio (PSRR), low noise, fast start-up, and excellent line and load transient responses are provided while consuming a very low 45-A (typical) ground current. 1 * * * * * * * * Input Voltage: 2.7 V to 6.5 V 500-mA Low-Dropout Regulator With EN Low IQ: 45 A Multiple Output Voltage Versions Available: - Fixed Outputs of 1.2 V to 4.3 V - Adjustable Outputs from 1.25 V to 6 V High PSRR: 68 dB at 1 kHz Low Noise: 13.2 VRMS Fast Start-Up Time: 45 s Stable With a Ceramic, 2.2-F, Low-ESR Output Capacitor Excellent Load and Line Transient Response 2% Overall Accuracy (Load, Line, and Temperature, VOUT > 2.2 V) Very Low Dropout: 280 mV at 500 mA 2-mm x 2-mm WSON-6 and 3-mm x 3-mm SON-8 Packages 2 Applications * * * * Post DC-DC Converter Ripple Filtering IP Network Cameras Macro Base Stations Thermostats The TPS735 device is stable with ceramic capacitors and uses an advanced BiCMOS fabrication process to yield a typical dropout voltage of 280 mV at 500mA output. The TPS735 device uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% (VOUT > 2.2 V) over all load, line, process, and temperature variations. This device is fully specified from TJ = -40C to +125C and is offered in a low-profile, 3 mm x 3 mm SON-8 package and a 2 mm x 2 mm WSON-6 package. Device Information(1) PART NUMBER PACKAGE TPS735 BODY SIZE (NOM) WSON (6) 2.00 mm x 2.00 mm SON (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Optional input capacitor, C , IN to improve source impedance, noise, and PSRR VIN IN OUT VOUT TPS735 EN VEN GND NR 2.2 F Ceramic Optional bypass capacitor, C , NR to reduce output noise and increase PSRR 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ 10 10 11 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Applications ................................................ 13 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 16 10.1 10.2 10.3 10.4 10.5 Layout Guidelines ................................................. Layout Example .................................................... Power Dissipation ................................................. Estimating Junction Temperature ......................... Package Mounting ................................................ 16 16 17 18 19 11 Device and Documentation Support ................. 20 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (January 2015) to Revision M Page * Updated data sheet text to latest data sheet and translation standards ............................................................................... 1 * Changed "Ultra-Low Noise" to "Low Noise" in document title ............................................................................................... 1 * Changed Low IQ from 46 A to 45 A in Features, Description, and Application Information sections. ................................ 1 * Changed "Standard" to "Ceramic" in Features list ................................................................................................................. 1 * Changed 6-pin package from "SON" to "WSON" in Features list ......................................................................................... 1 * Deleted printers, WiFi(R), WiMax Modules, cellular phones, smart phones and microprocessor power from Applications section ............................................................................................................................................................... 1 * Added post DC/DC ripple filtering, IP network cameras, macro base stations, and thermostats to Applications section ..... 1 * Changed TA to TJ in Description section ............................................................................................................................... 1 * Changed 6-pin package from "SON" to "WSON" in Description section .............................................................................. 1 * Changed package in Device Information table from VSON (6) to WSON (6)........................................................................ 1 * Changed 6-pin DRB package designator from "VSON" to "SON" in Pin Configurations and Functions section .................. 4 * Changed 6-pin DRV package designator from "VSON" to "WSON" in Pin Configurations and Functions section .............. 4 * Added "feedback resistor" parameter to Recommended Operating Conditions table ........................................................... 5 * Changed DRV package designator from "VSON" to "WSON" in Thermal Information table ................................................ 6 * Changed DRB package designator from "VSON" to "SON" in Thermal Information table ................................................... 6 * Changed TPS735 Ground Pin Current (Disable) vs Temperature in Typical Characteristics section ................................... 8 * Changed TPS735 Dropout Voltage vs Output Current in Typical Characteristics section..................................................... 8 * Updated Equation 1 ............................................................................................................................................................. 14 * Changed x-axis scale from "10 ms/div" to "10 s/div" in Figure 17 ..................................................................................... 15 * Changed x-axis scale from "10 ms/div" to "10 s/div" in Figure 18 ..................................................................................... 15 * Changed VOUT starting value to 0 V in Figure 19 ................................................................................................................ 15 * Updated Equation 2 ............................................................................................................................................................. 17 * Updated Equation 3 ............................................................................................................................................................. 17 * Changed DRV package designator from "SON" to "WSON" in Measuring Points for TT and TB......................................... 19 2 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 Revision History (continued) * Deleted references to thermal information documents in Related Documentation section ................................................ 20 Changes from Revision K (August, 2013) to Revision L Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sections ............................................................................................... 1 * Added first bullet item in Features list ................................................................................................................................... 1 * Changed fourth bullet item in Features list to "fixed outputs of 1.2 V" .................................................................................. 1 * Changed eighth bullet item in Features list ........................................................................................................................... 1 * Changed last bullet in Features list ....................................................................................................................................... 1 * Changed last Applications list item ........................................................................................................................................ 1 * Changed Pin Configuration and Functions section; updated table format and pin descriptions to meet new standards ..... 4 * Changed CNR value notation from 0.01 F to 10 nF throughout Electrical Characteristics.................................................... 7 * Changed feedback voltage parameter values and measured test conditions ....................................................................... 7 * Changed output current limit maximum specified value ........................................................................................................ 7 * Changed power-supply rejection ratio typical specified values for 100 Hz, 10 kHz, and 100 kHz frequency test conditions ............................................................................................................................................................................... 7 * Added note (1) to Figure 1 .................................................................................................................................................... 8 * Changed y-axis title for Figure 6 ............................................................................................................................................ 8 * Changed y-axis title for Figure 7 ............................................................................................................................................ 8 * Changed footnote for Figure 13............................................................................................................................................ 10 * Changed reference to noise-reduction capacitor (CNR) to feed-forward capacitor (CFF) in Transient Response................. 11 * Changed noise-reduction capacitor to feed-forward capacitor in Figure 16 ........................................................................ 13 * Changed references to "noise-reduction capacitor" (CNR) to "feed-forward capacitor" (CFF) and section title from "Feedback Capacitor Requirements" to "Feed-forward Capacitor Requirements" in Feed-Forward Capacitor Requirements section ........................................................................................................................................................... 14 * Changed CNR value notation from 0.01 F to 10 nF in Output Noise section...................................................................... 14 Changes from Revision J (May, 2011) to Revision K * Page Added last sentence to first paragraph of Startup and Noise Reduction Capacitor section ................................................ 11 Changes from Revision I (April, 2011) to Revision J Page * Replaced the Dissipation Ratings with Thermal Information.................................................................................................. 6 * Revised conditions for Typical Characteristics to include statement about TPS73525 device availability ............................ 8 * Added Estimating Junction Temperature section ................................................................................................................. 18 * Updated Power Dissipation section...................................................................................................................................... 19 Changes from Revision H (November, 2009) to Revision I * Page Corrected typo in Electrical Characteristics table for VOUT specification, DRV package test conditions, VOUT 2.2V........... 7 Changes from Revision G (March 2009) to Revision H Page * Revised bullet point in Features list to show very low dropout of 280 mV............................................................................. 1 * Changed dropout voltage typical specification from 250mV to 280mV.................................................................................. 7 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 3 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com 5 Pin Configuration and Functions DRB Package 8-Pin SON With Exposed Thermal Pad Top View OUT 1 NC 2 FB,NR 3 GND 4 Thermal Pad 8 IN 7 DRV Package 6-Pin WSON With Exposed Thermal Pad Top View OUT 1 6 IN NC FB,NR 2 Thermal 5 Pad NC 6 NC GND 3 4 EN 5 EN Not to scale NC - No internal connection Not to scale Pin Functions PIN NAME NO I/O DESCRIPTION DRV DRB IN 6 8 I GND 3 4 -- EN 4 5 I NR 2 3 -- FB 2 3 I This pin is only available for the adjustable version. The FB pin is the input to the control-loop error amplifier, and is used to set the output voltage of the device. This pin must not be left floating. OUT 1 1 O This pin is the output of the regulator. A small, 2.2-F ceramic capacitor is required from this pin to ground to assure stability. The minimum output capacitance required for stability is 2 F. NC 5 2, 6, 7 -- Not internally connected. Thermal pad 4 Input supply. A 0.1-F to 1-F, low ESR capacitor must be placed from this pin to ground near the device. Ground. The pad must be tied to GND. Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. The EN pin can be connected to the IN pin if not used. This pin is only available for the fixed voltage versions. Connecting an external capacitor to this pin bypasses noise that is generated by the internal band gap and allows the output noise to be reduced to very low levels. The maximum recommended capacitor is 0.01 F. -- Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 6 Specifications 6.1 Absolute Maximum Ratings at -40C TJ and TA +125C (unless otherwise noted). All voltages are with respect to GND. (1) VIN VEN Voltage VFB VOUT MIN MAX UNIT -0.3 7 V -0.3 VIN + 0.3 V -0.3 1.6 V -0.3 VIN + 0.3 V IOUT Current PD(tot) Continuous total power dissipation See Thermal Information TJ Operating junction temperature -40 150 C Tstg Storage temperature -55 150 C (1) Internally limited A Stresses beyond those listed as Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated as Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) VALUE UNIT 2000 V 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 2.7 VOUT Output voltage VFB 6 IOUT Output current (1) 0 500 mA TA Operating free-air temperature -40 125 C CIN Input capacitor 1 F COUT Output capacitor 2 F CNR Noise reduction capacitor 10 nF CFF Feed-forward capacitor R2 Feedback resistor (1) (2) (2) 3 (2) 6.5 22 110 V V 1000 pF k When operating at TJ near 125C, IOUT(min) is 500 A. Adjustable version only. Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 5 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com 6.4 Thermal Information TPS735 THERMAL METRIC RJA Junction-to-ambient thermal resistance (1) (3) (4) RJC(top) Junction-to-case (top) thermal resistance RJB Junction-to-board thermal resistance JT Junction-to-top characterization parameter (5) JB Junction-to-board characterization parameter (6) RJC(bot) Junction-to-case (bottom) thermal resistance (7) (1) (2) (3) (4) (5) (6) (7) 6 (2) DRB (SON) DRV (WSON) 8 PINS 6 PINS UNIT 52.2 65.1 C/W 59.4 85.6 C/W 19.3 34.7 C/W 2 1.6 C/W 19.3 35.1 C/W 11.8 5.8 C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2 x 2 thermal via array. ii. DRV: The exposed pad is connected to the PCB ground layer through a 2 x 2 thermal via array. Due to size limitation of thermal pad, 0.8-mm pitch array is used which is off the JEDEC standard. (b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. ii DRV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-in x 3-in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 6.5 Electrical Characteristics over operating temperature range (-40C TJ 125C), VIN = VOUT(nom) + 0.5 V or 2.7 V (whichever is greater), IOUT = 1 mA, VEN = VIN, COUT = 2.2 F, and CNR = 10 nF (unless otherwise noted). For the adjustable version (TPS73501), VOUT = 3 V. Typical values are at TA = 25C. PARAMETER TEST CONDITIONS (1) VIN Input voltage VFB Internal reference (adjustable version only) VOUT Output voltage range (adjustable version only) TJ = 25C 1.196 3% Dropout voltage (2) (VIN = VOUT(nom) - 0.1 V) IOUT = 500 mA ILIM Output current limit VOUT = 0.9 x VOUT(nom), VIN = VOUT(nom) + 0.9 V VIN 2.7 V IGND Ground pin current 10 mA IOUT 500 mA ISHDN Shutdown current VEN 0 V IFB Feedback pin current (adjustable version only) VOUT(nom) = 1.2 V Power-supply rejection ratio VIN = 3.85 V VOUT = 2.85 V CNR = 0.01 F IOUT = 100 mA 800 %/V 0.005 %/mA 280 500 mV 1170 1900 mA 45 65 A 0.15 1 A 0.5 A -0.5 f = 100 Hz 66 f = 1k Hz 68 f = 10 kHz 44 f = 100 kHz 11 x VOUT CNR = none 95 x VOUT 45 CNR = 1 nF 45 CNR = 10 nF 50 Enable low (shutdown) IEN(HI) Enable pin current, enabled Tsd Thermal shutdown temperature UVLO Undervoltage lockout VIN rising Vhys Hysteresis VIN falling dB 22 CNR = 10 nF CNR = 47 nF (1) (2) 0.02 CNR = none VEN(LO) V 2% VDO Enable high (enabled) 6 1% 500 A IOUT 500 mA VEN(HI) V 1% Load regulation Start-up time 1.220 -3% VOUT(IOUT) tSTR V -2% VOUT(nom) + 0.5 V VIN 6.5 V UNIT 6.5 VOUT 2.2 V Line regulation (1) BW = 10 Hz to 100 kHz, VOUT = 2.8 V MAX VOUT > 2.2 V VOUT(VIN) Output noise voltage 1.208 VFB 1 mA IOUT 500 mA, VOUT + 0.5 V VIN < 6.5 V Vn TYP 2.7 DC output accuracy (1) PSRR MIN VRMS s 50 1.2 V VEN = VIN = 6.5 V 0.03 Shutdown, temperature increasing 165 Reset, temperature decreasing 145 1.9 2.2 0.4 V 1 A C 2.65 70 V mV Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater. VDO is not measured for this family of devices with VOUT(nom) < 2.8 V because the minimum VIN = 2.7 V. Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 7 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com 6.6 Typical Characteristics 0.5 0.5 0.4 0.4 0.3 0.2 0.1 0 -0.1 TJ = 125C TJ = 85C TJ = 25C (1) TJ = 0C TJ = -40C -0.2 -0.3 -0.4 -0.5 3 3.5 4 4.5 5 5.5 6 Change in Output Voltage (%) Change in Output Voltage (%) over operating temperature range (TJ= -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN,COUT = 2.2 F, CNR = 10 nF. Typical values are at TJ = 25C, (unless otherwise noted). TJ = 125C TJ = 85C TJ = 25C TJ = 0C TJ = -40C 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 3 6.5 3.5 4 2.83 TJ = 85C 2.54 TJ = -40C 2.53 Output Voltage (V) Output Voltage (V) 2.55 TJ = 125C 2.84 5.5 2.82 2.81 2.8 2.79 2.78 2.77 TJ = 125C TJ = 85C TJ = 25C TJ = 0C TJ = -40C 2.52 2.51 2.5 2.49 2.48 2.46 2.75 2.45 2.74 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 Load (mA) Load (mA) The y-axis range is 2% of 2.8 V The y-axis range is 2% of 2.5 V Figure 3. TPS735 Load Regulation Figure 4. TPS735 Load Regulation 500 60 VIN = 6.5 V VIN = 5 V VIN = 3.3 V 50 40 30 TJ = 125C TJ = 85C TJ = 25C TJ = 0C TJ = -40C 20 10 0 0 50 100 150 200 250 300 350 400 450 500 Ground Pin Current (nA) 450 Current on the GND Pin (mA) 6.5 2.47 2.76 400 350 300 250 200 150 100 50 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (C) Output Current (mA) Figure 5. TPS735 Ground Pin Current vs Output Current 8 6 Figure 2. TPS735 Line Regulation Figure 1. TPS735 Line Regulation 2.85 5 IOUT = 100 mA IOUT = 100 mA 2.86 4.5 Input Voltage (V) Input Voltage (V) Figure 6. TPS735 Ground Pin Current (Disable) vs Temperature Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 Typical Characteristics (continued) over operating temperature range (TJ= -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN,COUT = 2.2 F, CNR = 10 nF. Typical values are at TJ = 25C, (unless otherwise noted). 90 400 TJ = +125C 80 TJ = +85C 300 70 TJ = +25C 250 200 TJ = 0C 150 PSRR (dB) Dropout Voltage (mV) 350 50 40 IOUT = 1 mA IOUT = 100 mA IOUT = 200 mA IOUT = 250 mA IOUT = 500 mA 30 TJ = -40C 100 60 20 50 10 0 0 0 50 10 100 150 200 250 300 350 400 450 500 100 80 80 70 70 60 60 50 40 IOUT = 1 mA IOUT = 100 mA IOUT = 200 mA IOUT = 250 mA IOUT = 500 mA 50 40 30 IOUT = 1 mA IOUT = 100 mA IOUT = 200 mA IOUT = 250 mA IOUT = 500 mA 20 10 0 0 10 100 10k 1k 100k 1M 10M 10 100 Frequency (Hz) 10k 1k 100k 1M 10M Frequency (Hz) (VIN - VOUT = 0.5 V) (VIN - VOUT = 0.3 V) Figure 9. Power-Supply Ripple Rejection vs Frequency Figure 10. Power-Supply Ripple Rejection vs Frequency 140 30 120 25 Total Noise (mVRMS) Total Noise (mVRMS) 10M Figure 8. Power-Supply Ripple Rejection vs Frequency 90 PSRR (dB) PSRR (dB) Figure 7. TPS735 Dropout Voltage vs Output Current 10 1M (VIN - VOUT = 1 V) 90 20 100k Frequency (Hz) VEN = 0.4 V 30 10k 1k Output Current (mA) 100 80 60 40 20 15 10 5 20 0 0 0.01 0.1 10 1 0 5 10 15 20 25 Output Capacitance (mF) Capacitance on the NR Pin (nF) CNR = 0.01 F, IOUT = 1 mA Figure 11. TPS73525 RMS Noise vs CNR Figure 12. TPS735 RMS Noise vs COUT Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 9 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com 7 Detailed Description 7.1 Overview The TPS735 of low dropout (LDO) regulator combines the high performance required by radio frequency (RF) and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain, high-bandwidth error loop with good supply rejection and very low headroom (VIN - VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise that is generated by the band-gap reference and to improve PSRR. A quick-start circuit fast-charges this capacitor at start-up. The combination of high performance and low ground current make the TPS735 device designed for portable applications. All versions have thermal and overcurrent protection and are specified from -40C TJ +125C. 7.2 Functional Block Diagrams IN OUT 400 W 2 mA Current Limit Overshoot Detect Thermal Shutdown EN UVLO Quickstart 1.208 V (1) Bandgap NR 500 kW GND (1) The 1.2-V fixed voltage version has a 1-V band gap instead of a 1.208-V circuit. Figure 13. Fixed Voltage Versions IN OUT 400 W 3.3 MW Current Limit Thermal Shutdown EN Overshoot Detect UVLO 1.208 V Bandgap FB 500 kW GND Figure 14. Adjustable Voltage Versions 10 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 7.3 Feature Description 7.3.1 Internal Current Limit The TPS735 internal current limit protects the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is independent of the output voltage. For reliable operation, do not operate the device in current limit for extended periods of time. The PMOS pass element in the TPS735 device contains a built-in body diode that conducts current when the voltage at the OUT pin exceeds the voltage at the IN pin. This current is not limited, so if extended reverse voltage operation is expected, external limiting is appropriate. 7.3.2 Shutdown The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When shutdown capability is not required, the EN pin can connect to the IN pin. 7.3.3 Dropout Voltage The TPS735 device uses a PMOS pass transistor to achieve low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance (R(IN/OUT)) of the PMOS pass element. VDO scales with the output current because the PMOS device operates like a resistor in dropout. As with any linear regulator, PSRR and transient response degrades as (VIN - VOUT) approaches dropout. Typical Characteristics shows this effect; (see Figure 8 through Figure 10). 7.3.4 Start-Up and Noise Reduction Capacitor Fixed voltage versions of the TPS735 use a quick-start circuit to charge the noise reduction (NR) capacitor (CNR) if present (see Functional Block Diagrams). This architecture allows the combination of low output noise and fast start-up times. The NR pin is high impedance so a low-leakage CNR capacitor must be used. Most ceramic capacitors are appropriate in this configuration. A high-quality, COG-type (NPO) dielectric ceramic capacitor is recommended for CNR when used in environments where abrupt changes in temperature can occur. For the fastest start-up, first apply VIN , then drive the enable (EN) pin high. If EN is tied to IN, start-up is slower. See Typical Applications . The quick-start switch closes for approximately 135 s. To ensure that CNR is charged during the quick-start time, use a capacitor with a value of no more than 0.01 F. 7.3.5 Transient Response As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases the transient response duration. In the adjustable version, adding CFF between the OUT and FB pins improves stability and transient response performance. The transient response of the TPS735 device is enhanced by an active pulldown that engages when the output overshoots by approximately 5% or more when the device is enabled. The pull-down device operates like a 400- resistor to ground when enabled. 7.3.6 Undervoltage Lockout The TPS735 device uses an undervoltage lockout circuit to disable the output until the internal circuitry is operates properly. The UVLO circuit contains a deglitch feature so that the UVLO ignores undershoot transients on the input if the transients are less than 50 s in duration. 7.3.7 Minimum Load The TPS735 device is stable with no output load. To meet the specified accuracy, a minimum load of 500 A is required. If the output is below 500 A and if the junction temperature is approximately 125C, the output can increase enough to turn on the output pulldown. The output pulldown limits voltage drift to 5% (typically) but ground current can increase by approximately 50 A. In most applications, the junction does not reach high temperatures at light loads because little power is dissipated. As a result, the specified ground current is valid at no load in most applications. Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 11 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com Feature Description (continued) 7.3.8 Thermal Protection Thermal protection disables the output when the junction temperature increases to approximately 165C, which allows the device to cool. When the junction temperature cools to approximately 145C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit cycles on and off. This cycling limits the dissipation of the regulator and protects the regulator from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, limit junction temperature to 125C (maximum). To estimate the thermal margin in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered. Use worst-case loads and signal conditions. For reliable operation, trigger thermal protection at least 40C above the maximum expected ambient condition of a particular application. This configuration produces a worst-case junction temperature of 125C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS735 protects against overload conditions. This protection circuitry is not intended to replace proper heat sinking. Continuously running the TPS735 into thermal shutdown degrades device reliability. 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: * The input voltage previously exceeded the UVLO voltage and did not decrease below the UVLO threshold minus Vhys. The input voltage is greater than the nominal output voltage that is added to the dropout voltage. The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold. The output current is less than the current limit. The device junction temperature is within the specified range. * * * * 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is equal to the input voltage minus the dropout voltage. The transient performance of the device degrades because the pass device is in a triode state and the LDO operates like a resistor. Line or load transients in dropout can result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: * The input voltage is less than the UVLO threshold minus Vhys, or has not yet exceeded the UVLO threshold. * The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. * The device junction temperature is greater than the thermal shutdown temperature. Table 1 lists the conditions that result in different modes of operation. Table 1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal mode VIN > VOUTnom + VDO and VIN > UVLO VEN > VEN(HI) IOUT < ILIM TJ < 125C Dropout mode UVLO < VIN < VOUTnom + VDO VEN > VEN(HI) -- TJ < 165C Disabled mode (any true condition disables the device) VIN < UVLO - Vhys VEN < VEN(LO) -- TJ > 165C 12 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS735 LDO regulator provides a design with an ultra-low noise, high PSRR, low-dropout linear regulation with a very small ground current (5 A, typical). The devices are stable with ceramic capacitors and have a dropout voltage of 280 mV at the full output rating of 500 mA. The features of the TPS735 device enables the LDO regulators to be used in a wide variety of applications with minimal design complexity. 8.2 Typical Applications Figure 15 shows the basic circuit connections for fixed-voltage models. Figure 16 shows the connections for the adjustable output version. R1 and R2 can be calculated for any output voltage using the formula in Figure 16. Optional input capacitor. May improve source impedance, noise, or PSRR. V IN IN V OUT OUT TPS735 EN V EN GND 2.2 F Ceramic NR Optional bypass capacitor to reduce output noise and increase PSRR. Figure 15. Typical Application Circuit for Fixed-Voltage Versions Optional input capacitor. May improve source impedance, noise, or PSRR. V IN IN V (R + R ) 1 2 R V OUT GND x 1.208 2 TPS735 EN = OUT OUT R 1 FB C FF 2.2 F Ceramic R 2 V EN Figure 16. Typical Application Circuit for Adjustable-Voltage Versions Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 13 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com Typical Applications (continued) 8.2.1 Design Requirements 8.2.1.1 Input and Output Capacitor Requirements Although an input capacitor is not required for stability, connecting a 0.1-F to 1-F low-equivalent seriesresistance (ESR) capacitor across the input supply near the regulator is good analog design practice. This capacitor counteracts reactive input sources and improves transient response and ripple rejection. A higher-value capacitor may be required if large, fast, rise-time load transients are expected, or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-F input capacitor may be required to ensure stability. TheTPS735 device is designed to be stable with standard ceramic output capacitors of values 2 F or larger. X5R- and X7R-type capacitors are best because these capacitors feature minimal variation in value and ESR over temperature. Maximum ESR of the output capacitor is < 1 and, therefore, the output capacitor type must be ceramic or conductive polymer electrolytic. 8.2.1.2 Feed-Forward Capacitor Requirements The feed-forward capacitor (CFF), shown in Figure 16, is required for stability. For a parallel combination of R1 and R2 equal to 250 k, any value between 3 pF to 1 nF can be used. Fixed-voltage versions have an internal 30-pF feed-forward capacitor that is quick-charged at start-up. Larger value capacitors improve noise slightly. The TPS735 device is stable in unity-gain configurations (the OUT pin is tied to the FB pin) without CFF. 8.2.2 Detailed Design Procedure 8.2.2.1 Output Noise In most LDO regulators, the band gap is the dominant noise source. If a noise-reduction capacitor (CNR) is used with the TPS735 device, the band gap does not contribute significantly to noise. Noise is dominated by the output resistor divider and the error-amplifier input. To minimize noise in a given application, use a 10-nF noise reduction capacitor. For the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that produces 2 A of divider current has the same noise performance as a fixed voltage version with a CNR. To further optimize noise, set the ESR of the output capacitor to approximately 0.2 . This configuration maximizes phase margin in the control loop, which reduces the total output noise up to 10%. TI recommends a maximum capacitor value of 10 nF. Equation 1 calculates the approximate integrated output noise from 10 Hz to 100 kHz with a CNR value of 10 nF. Vn (mVRMS ) = 11(mVRMS / V) VOUT (V) (1) The TPS735adjustable version does not have the noise-reduction pin available, so ultra-low noise operation is not possible. Noise is minimized according to the previously listed recommendations. 14 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 Typical Applications (continued) 8.2.3 Application Curves 3.5 3.5 3 3 2.5 2.5 2 2 Voltage (V) Voltage (V) at VIN = VOUT(nom) + 0.5 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN, COUT = 2.2 F, CNR = 10 nF, and TJ = 25C (unless otherwise noted) 1.5 1 0.5 1.5 1 0.5 VOUT, COUT = 10 mF VOUT, COUT = 2.2 mF VEN 0 VOUT, COUT = 10 mF VOUT, COUT = 2.2 mF VEN 0 -0.5 -0.5 10 s/div 10 s/div Figure 17. TPS735 Turnon Response (VIN = VEN) Figure 18. TPS735 Turnon Response Using EN 7 COUT = 470 mF OSCON VOUT 6 200 mV/div VIN = VEN COUT = 10 mF 200 mV/div Voltage (V) 5 4 COUT = 2.2 mF 200 mV/div 3 2 VOUT 1 500 mA 0 500 mA/div IOUT 1 mA -1 10 ms/div 10 ms/div VIN = 3 V RL = 5 Figure 20. TPS735 Load Transient Response Figure 19. TPS73525 Power-Up and Power-Down (VIN = VEN) COUT = 470 mF OSCON 50 mV/div COUT = 10VmOUT F 50 mV/div COUT = 2.2 mF 50 mV/div 4V VOUT VIN 0.5 V/div 3V 10 ms/div Figure 21. TPS735 Line Transient Response Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 15 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 2.7 V and 6.5 V. The input voltage range must provide adequate headroom for the device to have a regulated output. This input supply must be well-regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve output noise. 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near to the respective LDO pin connections as possible. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO component connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and as a result, reduces load-current transients, minimizes noise, and increases circuit stability. TI recommends using a ground reference plane, and is embedded in the printed circuit board (PCB) itself or located on the bottom side of the PCB opposite the components. This reference plane ensures accuracy of the output voltage, shields the LDO from noise, and operates similar to a thermal plane to spread (or sink) heat from the LDO device when connected to the exposed thermal pad. In most applications, this ground plane is required to meet thermal requirements. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance To improve AC performance (such as PSRR, output noise, and transient response), TI recommends designing the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the GND pin of the device. 10.2 Layout Example Input GND Plane VOUT CIN(1) COUT(1) OUT 1 NC 2 NR/FB 3 GND 4 CNR(1) Thermal Pad 8 IN 7 NC 6 NC 5 EN VIN Output GND Plane (1) CIN and COUT are 0603 capacitors and CNR is a 0402 capacitor. The footprint is shown to scale with package size. Figure 22. TPS735 Fixed Version Layout Reference Diagram 16 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 10.3 Power Dissipation The ability to remove heat from the die is different for each package type, which presents different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal Information section. Heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers improves the heat sink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation can be approximated by the product of the output current and the voltage drop across the output pass element, as Equation 2 shows. PD = (VIN - VOUT ) IOUT (2) NOTE When the device is used in a condition of high input and low output voltages, PD can exceed the junction temperature rating even when the ambient temperature is at room temperature. Equation 3 is an example calculation for the power dissipation (PD) of the DRB package. PD = (6.5 V - 1.2 V) 500 mA = 2.65 W (3) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output performance. On the DRB package, the primary conduction path for heat is through the exposed thermal pad to the PCB. The pad can be connected to ground or left floating. The pad must be attached to an appropriate amount of copper PCB area to ensure that the device does not overheat. The maximum allowable junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device. Equation 4 calculates the maximum junction-to-ambient thermal resistance. 125qC TA RTJA PD (4) Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 17 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com Power Dissipation (continued) Figure 23 estimates the maximum RJA and the minimum amount of PCB copper area required to heat sink. 160 DRV DRB 140 qJA (C/W) 120 100 80 60 40 20 0 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 JA value at board size of 9 in2 (that is, 3 in x 3 in) is a JEDEC standard. Figure 23. JA vs Board Size Figure 23 shows the variation of JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and must not be used to estimate actual thermal performance in real application environments. NOTE When the device is mounted on an application PCB, it is strongly recommended to use JT and JB, as explained in the Estimating Junction Temperature section. 10.4 Estimating Junction Temperature Using the thermal metrics JT and JB, as the table shows, the junction temperature can be estimated with corresponding formulas (Equation 5), which are more accurate than the value of TJ through calculation with JA. YJT: TJ = TT + YJT * PD YJB: TJ = TB + YJB * PD where: * * * PD is the power dissipation calculated with Equation 2, TT is the temperature at the center-top of the device package, and TB is the PCB temperature measured 1 mm away from the device package on the PCB surface (as shown in Figure 25). (5) NOTE Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see Using New Thermal Metrics, available for download at www.ti.com. 18 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 TPS735 www.ti.com SBVS087M - JUNE 2008 - REVISED JUNE 2018 Estimating Junction Temperature (continued) According to Figure 24, the new thermal metrics (JT and JB) do not depend on the copper area. Using JT or JB with Equation 5 can estimate TJ by measuring TT or TB on an application board. 35 YJT and YJB (C/W) 30 25 DRV Y JB DRB 20 15 10 DRV Y JT DRB 5 0 0 1 2 3 4 5 7 6 8 9 10 Board Copper Area (in2) Figure 24. JT and JB vs Board Size TT on top of device TB on PCB surface TT on top of device TB on PCB surface 1 mm 1 mm See note (1) (a) Example DRB (SON) Package Measurement (1) (b) Example DRV (WSON) Package Measurement Power dissipation may limit operating range. See Thermal Information . Figure 25. Measuring Points for TT and TB 10.5 Package Mounting Solder pad footprint recommendations for the TPS735 device is available from the TI website at www.ti.com. Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 19 TPS735 SBVS087M - JUNE 2008 - REVISED JUNE 2018 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Modules Two evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the TPS735. The TPS73501EVM-276 evaluation module and the TPS73525EVM-276 Evaluation Module (and related user guide) can be requested at the TI website through the product folders or purchased directly from the TI eStore. 11.1.2 Device Nomenclature Table 2. Device Nomenclature (1) PRODUCT TPS735xx(x)yyyz (1) VOUT xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 33 = 3.3 V; 125 = 1.25 V). yyy is the package designator. z is the tape and reel quantity (R = 3000, T = 250). 01 is the adjustable version. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: * Texas Instruments, TPS735EVM-276 User Guide 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright (c) 2008-2018, Texas Instruments Incorporated Product Folder Links: TPS735 PACKAGE OPTION ADDENDUM www.ti.com 13-Jun-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS73501DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBK TPS73501DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBK TPS73501DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDR TPS73501DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDR TPS73512DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTT TPS73512DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTT TPS73515DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWH TPS73515DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWH TPS73525DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM TPS73525DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM TPS73525DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM TPS73525DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NSW TPS73525DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NSW TPS73527DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAK TPS73527DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAK TPS735285DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAW TPS735285DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAW Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 13-Jun-2017 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS73533DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CVY TPS73533DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CVY TPS73533DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 CVY TPS73533DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 CVY TPS73534DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTU TPS73534DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTU (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 13-Jun-2017 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS735 : * Automotive: TPS735-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS73501DRBR Package Package Pins Type Drawing SON DRB 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 3.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.3 1.1 8.0 12.0 Q2 TPS73501DRBT SON DRB 8 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2 TPS73501DRVR WSON DRV 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2 TPS73501DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73501DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73501DRVT WSON DRV 6 250 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2 TPS73512DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS73512DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS73515DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS73515DRBT SON DRB 8 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2 TPS73525DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS73525DRBT SON DRB 8 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2 TPS73525DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73525DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73527DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73527DRVR WSON DRV 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2 TPS73527DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS735285DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS735285DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73533DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS73533DRBT SON DRB 8 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2 TPS73533DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73533DRVR WSON DRV 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2 TPS73533DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73533DRVT WSON DRV 6 250 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2 TPS73534DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS73534DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73501DRBR SON DRB 8 3000 338.0 355.0 50.0 TPS73501DRBT SON DRB 8 250 338.0 355.0 50.0 TPS73501DRVR WSON DRV 6 3000 205.0 200.0 33.0 TPS73501DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73501DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS73501DRVT WSON DRV 6 250 205.0 200.0 33.0 TPS73512DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS73512DRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73515DRBR SON DRB 8 3000 338.0 355.0 50.0 TPS73515DRBT SON DRB 8 250 338.0 355.0 50.0 TPS73525DRBR SON DRB 8 3000 338.0 355.0 50.0 TPS73525DRBT SON DRB 8 250 338.0 355.0 50.0 TPS73525DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73525DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS73527DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73527DRVR WSON DRV 6 3000 205.0 200.0 33.0 TPS73527DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS735285DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS735285DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS73533DRBR SON DRB 8 3000 338.0 355.0 50.0 TPS73533DRBT SON DRB 8 250 338.0 355.0 50.0 TPS73533DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS73533DRVR WSON DRV 6 3000 205.0 200.0 33.0 TPS73533DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS73533DRVT WSON DRV 6 250 205.0 200.0 33.0 TPS73534DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS73534DRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 3 GENERIC PACKAGE VIEW DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4206925/F PACKAGE OUTLINE DRV0006A WSON - 0.8 mm max height SCALE 5.500 PLASTIC SMALL OUTLINE - NO LEAD 2.1 1.9 B A PIN 1 INDEX AREA 2.1 1.9 0.8 0.7 C SEATING PLANE 0.08 C (0.2) TYP 0.05 0.00 1 0.1 EXPOSED THERMAL PAD 3 2X 1.3 4 7 1.6 0.1 6 1 4X 0.65 PIN 1 ID (OPTIONAL) 6X 6X 0.3 0.2 0.35 0.25 0.1 0.05 C A C B 4222173/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) (1) 1 7 6 6X (0.3) (1.6) SYMM (1.1) 4X (0.65) 4 3 SYMM (R0.05) TYP ( 0.2) VIA TYP (1.95) LAND PATTERN EXAMPLE SCALE:25X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4222173/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. www.ti.com EXAMPLE STENCIL DESIGN DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) 1 SYMM METAL 7 6 6X (0.3) (0.45) SYMM 4X (0.65) (0.7) 4 3 (R0.05) TYP (1) (1.95) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X 4222173/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OUTLINE DRB0008A VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 1.5 0.1 DIM A OPT 1 OPT 2 (0.1) (0.2) 4X (0.23) EXPOSED THERMAL PAD (DIM A) TYP 4 5 2X 1.95 1.75 0.1 8 1 6X 0.65 8X PIN 1 ID (OPTIONAL) (0.65) 8X 0.37 0.25 0.1 0.05 C A B C 0.5 0.3 4218875/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.5) (0.65) SYMM 8X (0.6) (0.825) 8 8X (0.31) 1 SYMM (1.75) (0.625) 6X (0.65) 4 5 (R0.05) TYP ( 0.2) VIA TYP (0.23) (0.5) (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4218875/A 01/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.65) 4X (0.23) SYMM METAL TYP 8X (0.6) 8X (0.31) 4X (0.725) 8 1 (2.674) SYMM (1.55) 6X (0.65) 4 5 (R0.05) TYP (1.34) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TPS73501DRBT TPS73525DRBTG4 TPS73525DRBRG4 TPS73512DRBR TPS73512DRBT TPS73515DRBR TPS73515DRBT TPS73527DRVR TPS73525DRBT TPS73525DRBR TPS73501DRBR TPS73501DRVR TPS73501DRVT TPS73525DRVR TPS73525DRVT TPS73533DRBR TPS73533DRBT TPS73533DRVR TPS73533DRVT TPS73534DRBR TPS73534DRBT TPS73527DRVT TPS735285DRVR TPS735285DRVT