This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Jul. 2008 1
512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O
Specification of
512Mb (16Mx32bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 4,194,304 x32
Rev 1.2 / Jul. 2008 2
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
Document Title
512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM
Revision History
Revision No. History Draft Date Remark
0.1 Initial Draft Sep.2007 Preliminary
0.2 Update: IDD values Mar. 2008 Preliminary
1.0 Final Version Apr. 2008
1.1
-. Corrected max tDQSCK/tAC at DDR333 from 5.5ns to 5.0ns
-. Corrected tDIPW, tIPW and tHZ at DDR400
(tDIPW: 1.8 to 1.4; tIPW: 2.7 to 2.2; tHZ: 5.5 to 5.0)
-. Added the 200MHz product in ordering information
-. Deleted the extended temperature products
May 2008
1.2 Insert the reduced page information Jul. 2008
Rev 1.2 / Jul. 2008 3
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
FEATURES SUMMARY
Mobile DDR SDRAM
- Double data rate architecture: two data transfer per
clock cycle
Mobile DDR SDRAM INTERFACE
- x32 bus width
- Multiplexed Address (Row address and Column ad-
dress)
SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V
MEMORY CELL ARRAY
- 512Mbit (x32 device) = 4M x 4Bank x 32 I/O
DATA STROBE
- x32 device: DQS0 ~ DQS3
- Bidirectional, data strobe (DQS) is transmitted and re-
ceived with data, to be used in capturing data at the
receiver
- Data and data mask referenced to both edges of DQS
LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature,
so please contact Hynix office for the DPD feature
INPUT CLOCK
- Differential clock inputs (CK, CK)
Data MASK
- DM0 ~ DM3: Input mask signals for write data
- DM masks write data-in at the both rising and
falling edges of the data strobe
MODE RERISTER SET, EXTENDED MODE REGIS-
TER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation
(Low Power DDR SDRAM)
CAS LATENCY
- Programmable CAS latency 2 or 3 supported
BURST LENGTH
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
AUTO PRECHARGE
- Option for each burst access
AUTO REFRESH AND SELF REFRESH MODE
CLOCK STOP MODE
- Clock stop mode is a feature supported by Mobile DDR
SDRAM.
- Keep to the JEDEC Standard regulation
INITIALIZING THE MOBILE DDR SDRAM
- Occurring at device power up or interruption of device
power
PACKAGE
- 90 Ball, 0.8mm pitch FBGA, 8x13[mm2], t=1.0mm max,
Lead & Halogen Free
Operating Temperature
- Mobile Temp.: -30oC ~ 85oC
ADDRESS TABLE
Part Number Page Size Row
Address
Column
Address
H5MS5122DFR 2KByte A0 ~ A12 A0 ~ A8
H5MS5132DFR 1KByte A0 ~ A13 A0 ~ A7
Rev 1.2 / Jul. 2008 4
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
DESCRIPTION
The Hynix H5MS5122DFR Series is 536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile
DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones
with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 4,194,304
x32.
The HYNIX H5MS5122DFR series uses a double-data-rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2
n
prefetch architecture with an interface designed to transfer two data per clock
cycle at the I/O pins.
The Hynix H5MS5122DFR Series offers fully synchronous operations referenced to both rising and falling edges of the
clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates
from a differential clock
: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK
),
data, data strobe and data mask inputs are sampled on both rising and falling edges of it (
Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK
). The data
paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible
with LVCMOS.
Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits reg-
istered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and the starting column location
for the burst access.
The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 loca-
tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end
of the burst access.
As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM)
allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation
times.
The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which
are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh.
A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on
any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disa-
bled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be
used for Read with Autoprecharge enabled and for Write bursts.
Rev 1.2 / Jul. 2008 5
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
The Hynix H5MS5122DFR series has the special Low Power function of Auto TCSR (Temperature Compensated Self
Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables
to automatically adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode
can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM
(Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of
a power switch and giving up mother-board power-line layout flexibility.
All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
The Hynix H5MS5122DFR series is available in the following package:
- 90Ball FBGA [size: 8mm x 13mm, t=1.0mm
max
]
512M Mobile DDR SDRAM ORDERING INFORMATION
Part Number Clock Frequency Page Size Organization Interface Package
H5MS5122DFR-E3M 200MHz(CL3) / 83MHz(CL2)
2KByte
(Normal)
4banks x 4Mb
x 32 LVCMOS
90 Ball FBGA
Lead & Halogen
Free
H5MS5122DFR-J3M 166MHz(CL3) / 83MHz(CL2)
H5MS5122DFR-K3M 133MHz(CL3) / 83MHz(CL2)
H5MS5122DFR-L3M 100MHz(CL3) / 66MHz(CL2)
H5MS5132DFR-E3M 200MHz(CL3) / 83MHz(CL2)
1KByte
(Reduced)
H5MS5132DFR-J3M 166MHz(CL3) / 83MHz(CL2)
H5MS5132DFR-K3M 133MHz(CL3) / 83MHz(CL2)
H5MS5132DFR-L3M 100MHz(CL3) / 66MHz(CL2)
Rev 1.2 / Jul. 2008 6
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
INFORMATION for Hynix KNOWN GOOD DIE
With the advent of Multi-Chip package (MCP), Package on Package (PoP) and System in a Package (SiP) applications,
customer demand for Known Good Die (KGD) has increased.
Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solu-
tions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies
such as systems-in-a-package (SIP) and multi-chip package (MCP) to reduce the board area required, making them
ideal for hand-held PCs, and many other portable digital applications.
Hynix Mobile SDRAM will be able to continue its constant effort of enabling the advanced package products of all appli-
cation customers.
- Please Contact Hynix Office for Hynix KGD product availability and informations.
Rev 1.2 / Jul. 2008 7
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
90Ball FBGA ASSIGNMENT
(A13 is used as 1KBytes Reduced page)
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CKE
A9
DQ31
DQ29
DQ27
DQ25
DQS3
DM3
CK
A11
B
C
D
E
F
G
H
A6 A7
J
A4 DM1
K
VSSQ
DQ30
DQ28
DQ26
DQ24
NC
/CK
A8
A5
VDDQ
DQ17
DQ19
DQ21
DQ23
A13
/WE
/CS
A10
A2
DQ16
DQ18
DQ20
DQ22
DQS2
DM2
/CAS
BA0
A0
DM0
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSS
/RAS
BA1
A1
A3
123456789
VSSQ
VDDQ
VSSQ
DQS1
DQ9
DQ11
L
M
N
VDDQ DQ13
P
VSS DQ15
R
DQ8
DQ10
DQ12
DQ14
VSSQ
DQ7
DQ5
DQ3
DQ1
VDDQ
DQS0
DQ6
DQ4
DQ2
DQ0
VDDQ
VSSQ
VDDQ
VSSQ
VDD
A
A12
Top view
Rev 1.2 / Jul. 2008 8
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
Mobile DDR SDRAM PIN DESCRIPTIONS
SYMBOL TYPE DESCRIPTION
CK, CK INPUT
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossings of CK and CK (both directions of crossing).
CKE INPUT
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in
any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is
achieved asynchronously.
CS INPUT
Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command
code.
RAS, CAS, WE INPUT Command Inputs: RAS, CAS and WE (along with CS) define the command being entered
BA0, BA1 INPUT
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA0 and BA1 also determine which mode register
is to be loaded during a MODE REGISTER SET command (MRS, EMRS or SRR).
A0 ~ A13 INPUT
Address inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. The address inputs also provide the op-code during
a MODE REGISTER SET command. A10 sampled during a PRECHARGE command deter-
mines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
For 512Mb (x32, Normal page) Row Address: A0 ~ A12, Column Address: A0 ~ A8
For 512Mb (x32, Reduced Page) Row Address: A0 ~ A13, Column Address: A0 ~ A7
Auto-precharge flag: A10
DQ0 ~ DQ31 I/O Data Bus: data input / output pin
DM0 ~ DM3 INPUT
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ
and DQS loading.
For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data
on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds to the
data on DQ24-DQ31.
DQS0 ~ DQS3 I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
center-aligned with write data. Used to capture write data. For x32 device, DQS0 corre-
sponds to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 cor-
responds to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31.
VDD SUPPLY Power supply
VSS SUPPLY Ground
VDDQ SUPPLY I/O Power supply
VSSQ SUPPLY I/O Ground
NC - No Connect: No internal electrical connection is present.
Rev 1.2 / Jul. 2008 9
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 32 I/O Mobile DDR SDRAM
(A13 is used as 1KBytes Reduced page)
32
Sense AMP & I/O Gate
Output Buffer & Logic
Address
Register
Mode Register
State Machine Address Buffers
Bank Select
Row Active
CAS
Latency
CLK
CKE
/CS
/RAS
/CAS
/WE
DM0
~DM3
A0
A1
BA1
BA0
A13
PASR
Refresh
DQ0
DQ31
Row decoders
Row decoders
Row decoders
Row decoders
Column decoders
4Mx32 Bank0
4Mx32 Bank1
4Mx32 Bank2
4Mx32 Bank3
Memory
Cell
Array
Data Out Control
Burst
Length
/CLK
Input Buffer & Logic
DS
64
32
64
Data Strobe
Transmitter
Data Strobe
Receiver
DS
DQS0
~
DQS3
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
Write Data Register
2-bit Prefetch Unit
Row
Pre
Decoder
Column
Pre
Decoder
Column Add
Counter
Burst
Counter
Column Active
Rev 1.2 / Jul. 2008 10
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
REGISTER DEFINITION I
Mode Register Set (MRS) for Mobile DDR SDRAM (A13 is used as 1KBytes Reduced page)
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 CAS Latency BT Burst Length
Burst Type
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0 Burst Length
A3 = 0 A3=1
0 0 0 Reserved Reserved
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
CAS Latency
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Rev 1.2 / Jul. 2008 11
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
REGISTER DEFINITION II
Extended Mode Register Set (EMRS) for Mobile DDR SDRAM (A13 is used as 1KBytes Reduced page)
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 DS 0 0 PASR
DS (Drive Strength)
A7 A6 A5 Drive
Strength
0 0 0 Full
0 0 1 Half (Default)
0 1 0 Quarter
0 1 1 Octant
1 0 0 Three-Quarters
PASR (Partial Array Self Refresh)
A2 A1 A0 Self Refresh Coverage
0 0 0 All Banks (Default)
0 0 1 Half of Total Bank (BA1=0)
0 1 0 Quarter of Total Bank (BA1=BA0=0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One Eighth of Total Bank
(BA1 = BA0 = Row Address MSB=0)
1 1 0 One Sixteenth of Total Bank
(BA1 = BA0 = Row Address 2 MSBs=0)
1 1 1 Reserved
Rev 1.2 / Jul. 2008 12
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
REGISTER DEFINITION III
Status Register (SR) for Mobile DDR SDRAM (A13 is used as 1KBytes Reduced page)
Note)
1. The revision number starts at ‘0000’ and increments by ‘0001’ each time a change in the manufacturer’s specification, IBIS, or
process occurs.
2. Low temperature out of range.
3. High temperature out of range - no refresh rate can guarantee functionality.
4. The refresh rate multiplier is based on the memory’s temperature sensor.
5. Required average periodic refresh interval = tREFI * multiplier.
6. Status Register is only for Read.
7. To read out Status Register values, BA[1:0] set to 01b and A[13:0] set to all 0 with MRS command followed by Read command
with that BA[1:0] and A[13:0] are don’t care. If the page size is 2KByte,A[12:0] set to all 0.
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Density - DW Refresh Rate Revision Identification Manufacturers Identification
0 1 0 0 1 X X X X1) X1) X1) X1) 0 1 1 0
Density
DQ15 DQ14 DQ13 Density
0 0 0 128
0 0 1 256
0 1 0 512
0 1 1 1024
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
DW (Device Width)
DQ11 Device Width
0 16 bits
1 32 bits
Refresh Rate
DQ10 DQ9 DQ8 Refresh Rate
0 0 x 42)
0 1 0 4
0 1 1 2
1 0 0 1
1 0 1 0.5
1 1 0 0.25
1 1 1 0.253)
Manufacturers Identification
DQ3 DQ2 DQ1 DQ0 Manufacturer
0 1 1 0 Hynix
xxxx Reserved or
other companies
Rev 1.2 / Jul. 2008 13
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
COMMAND TRUTH TABLE
DM TRUTH TABLE
Note:
1. All states and sequences not shown are illegal or reserved.
2. DESLECT and NOP are functionally interchangeable.
3. Autoprecharge is non-persistent. A10 High enables Autoprecharge, while A10 Low disables Autoprecharge
4. Burst Terminate applies to only Read bursts with auto precharge disabled. This command is undefined and should not be used for
Read with Autoprecharge enabled, and for Write bursts.
5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.
6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and BA0-BA1 are
don't care.
7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.
8. All address inputs and I/O are ''don't care'' except for CKE. Internal refresh counters control Bank and Row addressing.
9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.
10. BA0 and BA1 value select among MRS, EMRS and SRR.
11. Used to mask write data, provided coincident with the corresponding data.
12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
Function CS RAS CAS WE BA A10/AP ADDR Note
DESELECT (NOP) H X X X X X X 2
NO OPERATION (NOP) L H H H X X X 2
ACTIVE (Select Bank and activate Row) L L H H V Row Row
READ (Select bank and column and start read burst) L H L H V L Col
READ with AP (Read Burst with Autoprecharge) L H L H V H Col 3
WRITE (Select bank and column and start write
burst) L H L L V L Col
WRITE with AP (Write Burst with Autoprecharge) L H L L V H Col 3
BURST TERMINATE or enter DEEP POWER DOWN L H H L X X X 4, 5
PRECHARGE (Deactivate Row in selected bank) L L H L V L X 6
PRECHARGE ALL (Deactivate rows in all Banks) L L H L X H X 6
AUTO REFRESH or enter SELF REFRESH L L L H X X X 7,8,9
MODE REGISTER SET L L L L V Op code 10
Function DM DQ Note
Write Enable L Valid 11
Write Inhibit H X 11
Rev 1.2 / Jul. 2008 14
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
CKE TRUTH TABLE
Note:
1. CKEn is the logic state of CKE at clock edge
n
; CKE
n
-1 was the state of CKE at the previous clock edge.
2. Current state is the state of LP DDR immediately prior to clock edge
n
.
3. COMMAND
n
is the command registered at clock edge n, and ACTION
n
is the result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description.
9. The clock must toggle at least one time during the tXP period.
10. The clock must toggle at least once during the tXSR time.
CKEn-1 CKEnCurrent State COMMAND
n
ACTION
n
Note
L L Power Down X Maintain Power Down
L L Self Refresh X Maintain Self Refresh
L L Deep Power Down X Maintain Deep Power
Down
L H Power Down NOP or DESELECT Exit Power Down 5,6,9
L H Self Refresh NOP or DESELECT Exit Self Refresh 5,7,10
L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5,8
H L All Banks Idle NOP or DESELECT Precharge Power
Down Entry 5
H L Bank(s) Active NOP or DESELECT Active Power Down
Entry 5
H L All Banks Idle AUTO REFRESH Self Refresh entry
H L All Banks Idle BURST TERMINATE Enter Deep Power
Down
H H See the other Truth Tables
Rev 1.2 / Jul. 2008 15
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
CURRENT STATE BANK
n
TRUTH TABLE (COMMAND TO BANK
n
)
Note:
1. The table applies when both CKE
n
-1 and CKE
n
are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh
or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.
5. A command other than NOP should not be issued to the same bank while a READ or WRITE Burst with auto precharge is enabled.
6. The new Read or Write command could be auto precharge enabled or auto precharge disabled.
Current State
Command
Action Notes
CS RAS CAS WE Description
Any
H X X X DESELECT (NOP) Continue previous Operation
L H H H NOP Continue previous Operation
Idle
L L H H ACTIVE Select and activate row
L L L H AUTO REFRESH Auto refresh 10
L L L L MODE REGISTER SET Mode register set 10
L L H H PRECHARGE No action if bank is idle
Row Active
L H L H READ Select Column & start read burst
L H L L WRITE Select Column & start write burst
L L H L PRECHARGE Deactivate Row in bank (or banks) 4
Read
(without Auto
recharge)
L H L H READ Truncate Read &
start new Read burst 5,6
L H L L WRITE Truncate Read &
start new Write burst 5,6,13
L L H L PRECHARGE Truncate Read, start Precharge
L H H L BURST TERMINATE Burst terminate 11
Write
(without Auto
precharge)
L H L H READ Truncate Write &
start new Read burst 5,6,12
L H L L WRITE Truncate Write &
start new Write burst 5,6
L L H L PRECHARGE Truncate Write, start Precharge 12
Rev 1.2 / Jul. 2008 16
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
7. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
8. The following states must not be interrupted by a command issued to the same bank.
DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring
during these states. Allowable commands to the other bank are determined by its current state and Truth Table3,
and according to Truth Table 4.
Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the ''row active'' state.
Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends
when tRP has been met. Once tRP has been met, the bank will be in the idle state.
Write with AP Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
to each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met.
Once tRFC is met, the LP DDR will be in an ''all banks idle'' state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once tMRD is met, the LP DDR will be in an ''all banks idle'' state.
Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
10. Not bank-specific; requires that all banks are idle and no bursts are in progress.
11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank.
12. Requires appropriate DM masking.
13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end
the READ prior to asserting a WRITE command.
Rev 1.2 / Jul. 2008 17
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
CURRENT STATE BANK
n
TRUTH TABLE (COMMAND TO BANK
m
)
Current State
Command
Action Notes
CS RAS CAS WE Description
Any
H X X X DESELECT (NOP) Continue previous Operation
L H H H NOP Continue previous Operation
Idle X X X X ANY Any command allowed to bank m
Row Activating,
Active, or Pre-
charging
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8
L H L L WRITE Start WRITE burst 8
L L H L PRECHARGE Precharge
Read with Auto
Precharge dis-
abled
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8
L H L L WRITE Start WRITE burst 8,10
L L H L PRECHARGE Precharge
Write with Auto
precharge dis-
abled
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8,9
L H L L WRITE Start WRITE burst 8
L L H L PRECHARGE Precharge
Read with Auto
Precharge
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 5,8
L H L L WRITE Start WRITE burst 5,8,10
L L H L PRECHARGE Precharge
Write with Auto
precharge
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 5,8
L H L L WRITE Start WRITE burst 5,8
L L H L PRECHARGE Precharge
Rev 1.2 / Jul. 2008 18
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
Note:
1. The table applies when both CKE
n
-1 and CKE
n
are HIGH, and after tXSR or tXP has been met if the previous state was
Self Refresh or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
5. Read with AP enabled and Write with AP enabled: The read with Autoprecharge enabled or Write with Autoprecharge
enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the
precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the
earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the
precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts
with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period,
of the Read with Autoprecharge enabled or Write with Autoprecharge enabled states, ACTIVE, PRECHARGE, READ, and
WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands
to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data
and WRITE data must be avoided).
6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
7. A BURST TERMINATE command cannot be issued to another bank;
it applies to the bank represented by the current state only.
8. READs or WRITEs listed in the Command column include READs and WRITEs with AUTO PRECHARGE enabled and
READs and WRITEs with AUTO PRECHARGE disabled.
9. Requires appropriate DM masking.
10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command
must be issued to end the READ prior to asserting a WRITE command.
Rev 1.2 / Jul. 2008 19
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
ABSOLUTE MAXIMUM RATING
AC and DC OPERATING CONDITIONS
OPERATING CONDITION
CLOCK INPUTS (CK, CK)
Address And Command Inputs (A0~An, BA0, BA1, CKE, CS, RAS, CAS, WE)
Data Inputs (DQ, DM, DQS)
Data Outputs (DQ, DQS)
Parameter Symbol Rating Unit
Operating Case Temperature TC-30 ~ 85 oC
Storage Temperature TSTG -55 ~ 150 oC
Voltage on Any Pin relative to VSS VIN, VOUT -0.3 ~ VDDQ+0.3 V
Voltage on VDD relative to VSS VDD -0.3 ~ 2.7 V
Voltage on VDDQ relative to VSS VDDQ -0.3 ~ 2.7 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD0.7 W
Parameter Symbol Min Typ Max Unit Note
Supply Voltage VDD 1.7 1.8 1.95 V 1
I/O Supply Voltage VDDQ 1.7 1.8 1.95 V 1
Operating Case Temperature TC-30 85 oC
Parameter Symbol Min Max Unit Note
DC Input Voltage VIN -0.3 VDDQ+0.3 V
DC Input Differential Voltage VID(DC) 0.4*VDDQ VDDQ+0.6 V 2
AC Input Differential Voltage VID(AC) 0.6*VDDQ VDDQ+0.6 V 2
AC Differential Crosspoint Voltage VIX 0.4*VDDQ 0.6*VDDQ V 3
Parameter Symbol Min Max Unit Note
Input High Voltage VIH 0.8*VDDQ VDDQ+0.3 V
Input Low Voltage VIL -0.3 0.2*VDDQ V
Parameter Symbol Min Max Unit Note
DC Input High Voltage VIHD(DC) 0.7*VDDQ VDDQ+0.3 V
DC Input Low Voltage VILD(DC) -0.3 0.3*VDDQ V
AC Input High Voltage VIHD(AC) 0.8*VDDQ VDDQ+0.3 V
AC Input Low Voltage VILD(AC) -0.3 0.2*VDDQ V
Parameter Symbol Min Max Unit Note
DC Output High Voltage (IOH = -0.1mA) VOH 0.9*VDDQ - V
DC Output Low Voltage (IOL = 0.1mA) VOL - 0.1*VDDQ V
Rev 1.2 / Jul. 2008 20
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
Leakage Current
Note:
1. All voltages are referenced to VSS = 0V and VSSQ must be same potential and VDDQ must not exceed the level of VDD.
2. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on CK.
3. The value of VIX is expected to be 0.5*VDDQ and must track variations in the DC level of the same.
4. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V.
5. DOUT is disabled. VOUT= 0 to 1.95V.
AC OPERATING TEST CONDITION
Note: 1. The circuit shown on the right represents the timing
load used in defining the relevant timing parameters of
the part. It is not intended to be either a precise repre-
sentation of the typical system environment nor a depic-
tion of the actual load presented by a production tester.
System designers will use IBIS or other simulation tools
to correlate the timing reference load to system environ-
ment. Manufacturers will correlate to their production
(generally a coaxial transmission line terminated at the
tester electronics). For the half strength driver with a
nominal 10pF load parameters tAC and tQH are
expected to be in the same range. However, these
parameters are not subject to production test but are
estimated by design and characterization. Use of IBIS or other simulation tools for system design validation is suggested.
Input / Output Capacitance
Note:
1. These values are guaranteed by design and are tested on a sample base only.
2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.
3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD,
VDDQ are applied and all other pins (except the pin under test) floating. DQ's should be in high impedance state. This may be
achieved by pulling CKE to low level.
4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This
is required to match signal propagation times of DQ, DQS and DM in the system.
Parameter Symbol Min Max Unit Note
Input Leakage Current ILI -1 1 uA 4
Output Leakage Current ILO -1.5 1.5 uA 5
Parameter Symbol Value Unit Note
AC Input High/Low Level Voltage VIH / VIL 0.8*VDDQ/0.2*VDDQ V
Input Timing Measurement Reference Level Voltage Vtrip 0.5*VDDQ V
Input Rise/Fall Time tR / tF1 ns
Output Timing Measurement Reference Level Voltage Voutref 0.5*VDDQ V
Output Load Capacitance for Access Time Measurement CL pF 1
Parameter Symbol Speed Unit Note
Min Max
Input capacitance, CK, CK CCK 1.5 3.5 pF
Input capacitance delta, CK, CK CDCK - 0.25 pF
Input capacitance, all other input-only pins CI 1.5 3.0 pF
Input capacitance delta, all other input-only pins CDI - 0.5 pF
Input/output capacitance, DQ, DM, DQS CIO 2.0 4.5 pF 4
Input/output capacitance delta, DQ, DM, DQS CDIO - 0.5 pF 4
Test Load for Full Drive Strength Buffer
(20 pF)
Test Load for Half Drive Strength Buffer
(10 pF)
Output
Z
O
=50Ω
Rev 1.2 / Jul. 2008 21
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
Mobile DDR OUTPUT SLEW RATE CHARACTERRISTICS
Note:
1. Measured with a test load of 20pF connected to VSSQ
2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC)
3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process
variation.
Mobile DDR AC OVERSHOOT / UNDERSHOOT SPECIFICATION
Note:
1. This specification is intended for devices with no clamp protection and is guaranteed by design.
Parameter Min Max Unit Note
Pull-up and Pull-Down Slew Rate for Full Strength Driver 0.7 2.5 V/ns 1, 2
Pull-up and Pull-Down Slew Rate for Half Strength Driver 0.3 1.0 V/ns 1, 2
Output Slew Rate Matching ratio (Pull-up to Pull-down) 0.7 1.4 - 3
Parameter Specification
Maximum peak amplitude allowed for overshoot 0.5V
Maximum peak amplitude allowed for undershoot 0.5V
The area between overshoot signal and VDD must be less than or equal to 3V-ns
The area between undershoot signal and GND must be less than or equal to 3V-ns
2.5V
2.0V
1.5V
1.0V
0.5V
0.0V
-0.5V
Overshoot
Undershoot
VDD
VSS
Max. Amplitude = 0.5V Max. Area = 3V-ns
Time (ns)
Voltage (V)
Rev 1.2 / Jul. 2008 22
11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
DC CHARACTERISTICS
Parameter Symbol Test Condition
Max
Unit No
te
DDR
400
DDR
333
DDR
266
DDR
200
Operating one bank
active-precharge
current
2KBytes
Page Size IDD0
tRC = tRC(min); tCK = tCK(min); CKE is HIGH;
CS is HIGH between valid commands; address
inputs are SWITCHING; data bus inputs are
STABLE
60 50 45 45
mA 1,6
1KByates
Page Size 60 50 45 45
Precharge power-down stand-
by current IDD2P
all banks idle; CKE is LOW; CS is HIGH; tCK =
tCK(min); address and control inputs are
SWITCHING; data bus inputs are STABLE
0.3 mA
Precharge power-down
standby current with clock stop IDD2PS
all banks idle; CKE is LOW; CS is HIGH; CK =
LOW; CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
0.3 mA
Precharge non power-down
standby current IDD2N
all banks idle; CKE is HIGH; CS is HIGH, tCK =
tCK(min); address and control inputs are
SWITCHING; data bus inputs are STABLE
12
mA
Precharge non power-down
standby current with clock stop IDD2NS
all banks idle; CKE is HIGH; CS is HIGH; CK =
LOW; CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
8
Active power-down
standby current IDD3P
one bank active; CKE is LOW; CS is HIGH; tCK =
tCK(min); address and control inputs are
SWITCHING; data bus inputs are STABLE
5
mA
Active power-down
standby current with clock stop IDD3PS
one bank active; CKE is LOW; CS is HIGH; CK =
LOW; CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
3
Active non power-down
standby current IDD3N
one bank active; CKE is HIGH; CS is HIGH; tCK
= tCK
(min);
address and control inputs are
SWITCHING; data bus inputs are STABLE
15 mA
Active non power-down
standby current with clock stop IDD3NS
one bank active; CKE is HIGH; CS is HIGH; CK =
LOW; CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
10 mA
Operating burst read current IDD4R
one bank active; BL=4; CL=3; tCK = tCK
(min)
;
continuous read bursts; IOUT=0mA; address in-
puts are SWITCHING, 50% data change each
burst transfer
130 110 100 100 mA
1
Operating burst write current IDD4W
one bank active; BL=4; tCK=tCK
(min)
; continu-
ous write bursts; address inputs are SWITCH-
ING; 50% data change each burst transfer
120 110 100 100 mA
Auto Refresh Current IDD5
tRC=tRFC
(min)
; tCK=tCK
(min);
burst refresh;
CKE is HIGH; address and control inputs are
SWITCHING; data bus inputs are STABLE
100 mA
Self Refresh Current IDD6
CKE is LOW; CK=LOW; CK=HIGH;
Extended Mode Register set to all 0's; address
and control inputs are STABLE; data bus inputs
are STABLE
See Next Page uA 2
Deep Power Down Current IDD8 Address, control and data bus inputs are STA-
BLE 10 uA 4