SL74HCT126
System Logic
Semiconductor
SLS
Quad 3-State Noninverting Buffers
High-Performance Silicon-Gate CMOS
The SL74HCT126 is identical in pinout to the LS/ALS126. The
SL74HCT126 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The SL74HCT126 noninverting buffers are designed to be used
with 3-state memory address drivers, clock drivers, and other bus-
oriented systems. The devices have four separate output enables that
are active-high.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT126N Plastic
SL74HCT126D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =VCC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
A OE Y
H H H
L H L
X L Z
X = don’t care
Z = high impedance
SL74HCT126
System Logic
Semiconductor
SLS
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC).
Unused outputs must be left open.
SL74HCT126
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C ≤125
°C Unit
VIH Minimum High-Level
Input Voltage VOUT= VCC-0.1 V
IOUT≤ 20 µA 4.5
5.5 2.0
2.0 2.0
2.0 2.0
2.0 V
VIL Maximum Low -Level
Input Voltage VOUT=0.1 V
IOUT ≤ 20 µA 4.5
5.5 0.8
0.8 0.8
0.8 0.8
0.8 V
VOH Minimum High-Level
Output Voltage VIN=VIH
IOUT ≤ 20 µA 4.5
5.5 4.4
5.4 4.4
5.4 4.4
5.4 V
VIN=VIH
IOUT ≤ 6.0 mA
4.5
3.98
3.84
3.7
VOL Maximum Low-Level
Output Voltage VIN=VIL
IOUT ≤ 20 µA 4.5
5.5 0.1
0.1 0.1
0.1 0.1
0.1 V
VIN=VIL
IOUT ≤ 6.0 mA
4.5
0.26
0.33
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
IOZ Maximum Three-State
Leakage Current Output in High-Impedance
State
VIN=VIL or VIH
VOUT=VCC or GND
5.5 ±0.5 ±5.0 ±10 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA 5.5 8.0 80 160 µA
∆ICC Additional Quiescent
Supply Current VIN = 2.4 V, Any One Input
VIN=VCC or GND, Other
Inputs
≥-55°C 25°C to
125°C mA
IOUT=0µA 5.5 2.9 2.4
SL74HCT126
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol Parameter 25 °C to
-55°C ≤85°C ≤125°C Unit
tPLH, tPHL Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 3) 23 30 35 ns
tPLZ, tPHZ Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4) 32 38 48 ns
tPZL, tPZH Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4) 22 28 34 ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 3) 12 15 18 ns
CIN Maximum Input Capacitance 10 10 10 pF
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State) 15 15 15 pF
Power Dissipation Capacitance (Per Buffer) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
55 pF
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
SL74HCT126
System Logic
Semiconductor
SLS
Figure 3. Test Circuit Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
