TLV717xx Series
GND
EN
IN OUT
VIN VOUT
On
Off
CIN COUT
1 F
Ceramic
m
GND OUT
EN IN
TLV717xx
1-mm x 1-mm DQN
(Bottom View)
TLV717xx
TLV717xxP
www.ti.com
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
150-mA, Low-Dropout Regulator with Foldback Current Limit for Portable Devices
Check for Samples: TLV717xx,TLV717xxP
1FEATURES DESCRIPTION
The TLV717xx series of low-dropout (LDO) linear
2• Very Low Dropout: 215 mV at 150 mA regulators are low quiescent current LDOs with
• Accuracy: 0.5% (typical) excellent line and load transient performance and are
• Low IQ: 35 µA designed for power-sensitive applications. These
devices provide a typical accuracy of 0.5%.
• Available in Fixed-Output Voltages:
1.2 V to 5.0 V(1) The TLV717xx series offer current foldback that
throttles down the output current with a decrease in
• High PSRR: load resistance. The typical value at which current
– 70 dB at 1 kHz foldback initiates is 350 mA; the typical value of the
– 50 dB at 1 MHz output short current limit value is 40 mA.
• Stable with Effective Output Capacitance: Furthermore, these devices are stable with an
0.1 µF(2) effective output capacitance of only 0.1 µF. This
• Foldback Current Limit feature enables the use of cost-effective capacitors
that have higher bias voltages and temperature
• Package: 1-mm × 1-mm DQN derating. The devices regulate to specified accuracy
(1) See the Package Option Addendum at the end of this with no output load.
document for a complete list of available voltage options. The TLV717xx series is available in a 1-mm × 1-mm
(2) See the Input and Output Capacitor Requirements section in
the Application Information for more details. DQN package that makes them ideal for hand-held
applications. The TLV717xxP provides an active pull-
down circuit to quickly discharge output loads.
APPLICATIONS
• Wireless Handsets, Smart Phones, PDAs Typical Application Circuit
• MP3 Players
• Other Hand-Held Products
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV717xx
TLV717xxP
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT
TLV717xx(x)Pyyyz XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; otherwise, three digits are used (for example, 28 =
2.8 V; 475 = 4.75 V).
Pis optional; devices with P have an LDO regulator with an active output discharge.
YYY is the package designator.
Zis the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
At TJ= –25°C, unless otherwise noted. All voltages are with respect to GND. VALUE
MIN MAX UNIT
Input range, VIN –0.3 6.0 V
Voltage Enable range, VEN –0.3 VIN + 0.3 V
Output range, VOUT –0.3 6.0 V
Current Maximum output, IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation, PDISS See Thermal Information table
Junction range, TJ–55 +150 °C
Temperature Storage junction range, Tstg –55 +150 °C
Human body model (HBM) 2000 V
Electrostatic discharge (ESD) ratings Charged device model (CDM) 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION TLV717xx
TLV717xxP
THERMAL METRIC(1) UNITS
DQN
4 PINS
θJA Junction-to-ambient thermal resistance 393.3
θJC(top) Junction-to-case(top) thermal resistance 140.3
θJB Junction-to-board thermal resistance 330 °C/W
ψJT Junction-to-top characterization parameter 6.5
ψJB Junction-to-board characterization parameter 329
θJC(bottom) Junction-to-case(bottom) thermal resistance 147.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TLV717xx TLV717xxP
TLV717xx
TLV717xxP
www.ti.com
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS
At operating temperature range (TA= –40°C to +85°C), TA= +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, and COUT = 1 µF, unless otherwise noted.
TLV717
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 1.7 5.5 V
VOUT Output voltage range 1.2 5.0 V
IOUT Output current 150 mA
TA= +25°C 0.5 %
DC output accuracy VOUT ≥1.2 V, –40°C ≤TA≤+85°C –1.5 +1.5 %
VOUT ≤1.2 V 25 mV
ΔVO/VIN Line regulation VOUT(NOM) + 0.5 V ≤VIN ≤5.5 V 1 5 mV
ΔVO/IOUT Load regulation 0 mA ≤IOUT ≤150 mA 10 20 mV
1.2 V ≤VOUT < 1.5 V 330 500 mV
VIN = 0.98 × VOUT(NOM),
VDO Dropout voltage 1.5 V ≤VOUT < 1.8 V 330 450 mV
IOUT = 150 mA 1.8 V ≤VOUT ≤5.0 V 215 350 mV
IGND Ground pin current IOUT = 0 mA 35 55 µA
ISHDN Shutdown current VEN ≤0.4 V, 2.0 V ≤VIN ≤4.5 V 0.1 0.5 µA
f = 10 Hz 70 dB
f = 100 Hz 70 dB
Power-supply VIN = 3.3 V, VOUT = 2.8 V,
PSRR f = 1 kHz 65 dB
rejection ratio IOUT = 30 mA f = 10 kHz 60 dB
f = 100 kHz 43 dB
BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V,
VNOISE Output noise voltage 55 µVRMS
IOUT = 10 mA
tSTR Startup time COUT = 1.0 μF, IOUT = 150 mA 100 µs
ISC Short current limit VIN = min (VOUT(NOM) + 1 V, 5.5 V), VOUT = 0 V 40 mA
VHI Enable high (enabled) 0.9 VIN V
VLO Enable low (disabled) 0 0.4 V
IEN EN pin current EN = 5.5 V 0.01 µA
Pull-down resistor
RPULLDOWN 120 Ω
(TLV717xxP only)
UVLO Undervoltage lockout VIN rising 1.6 V
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLV717xx TLV717xxP
OUT GND
IN EN
1 2
4 3
GND OUT
EN IN
3 4
2 1
TLV717xx
TLV717xxP
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
www.ti.com
PIN CONFIGURATION
DQN PACKAGE DQN PACKAGE
1-mm × 1-mm TBD 1-mm × 1-mm TBD
(Top View) (Bottom View)
PIN DESCRIPTIONS
PIN
NAME NO. DESCRIPTION
Enable pin. Driving EN over 1.2 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown
EN 3 mode.
GND 2 Ground pin
Input pin. A small capacitor is recommended from this pin to ground to assure stability. See the Input and Output
IN 4 Capacitor Requirements section in the Application Information for more details.
Regulated output voltage pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure
OUT 1 stability. See the Input and Output Capacitor Requirements section in the Application Information for more details.
Thermal — It is recommended to connect this pin to GND for improved thermal performance.
pad
4Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TLV717xx TLV717xxP
Foldback Current
Limit
Bandgap
IN
EN
OUT
LOGIC
GND
TLV717xx
UVLO
Foldback Current
Limit
UVLO
Bandgap
IN
EN
OUT
LOGIC
GND
TLV717xxP
120 W
TLV717xx
TLV717xxP
www.ti.com
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. TLV717xx Block Diagram
Figure 2. TLV717xxP Block Diagram
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLV717xx TLV717xxP
I (mA)
OUT
0 200
2.9
2.88
2.86
2.84
2.82
2.8
2.78
2.76
2.74
2.72
2.7
V (V)
OUT
20 40 60 80 100
G001
120 140 160 180
+85 C°
+25 C°
- °40 C
InputVoltage(V)
3 5.5
2.9
2.88
2.86
2.84
2.82
2.8
2.78
2.76
2.74
2.72
2.7
OutputVoltage(V)
3.5 4 4.5 5
G002
+85 C°
+25 C°
- °40 C
I =10mA
OUT
InputVoltage(V)
3 5.5
2.9
2.88
2.86
2.84
2.82
2.8
2.78
2.76
2.74
2.72
2.7
OutputVoltage(V)
3.5 4 4.5 5
G003
+85 C°
+25 C°
- °40 C
I =150mA
OUT
Fixed Output Voltage Versions (V)
1.5 5
0.3
0.25
0.2
0.15
0.1
Dropout Voltage (V)
2 2.5 3 3.5
G004
+85 C°
+25 C°
- °40 C
4 4.5
Temperature( C)°
-40 85
2.838
2.828
2.818
2.808
2.798
2.788
2.778
2.768
2.758
OutputVoltage(V)
-27.5 -15 -2.5 10
G006
10mA
150mA
22.5 60 72.547.535
TLV717xx
TLV717xxP
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
www.ti.com
TYPICAL CHARACTERISTICS
At operating temperature range (TA= –40°C to +85°C), TA= +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater),
IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs
LINE REGULATION FIXED OUTPUT VOLTAGE VERSIONS
Figure 5. Figure 6.
DROPOUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs TEMPERATURE
Figure 7. Figure 8.
6Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TLV717xx TLV717xxP
Input Voltage (V)
3 5.5
45
40
35
30
25
20
15
10
5
0
Ground Pin Current ( A)m
3.5 4 4.5 5
G007
+85 C°
+25 C°
- °40 C
I = 0 mA
OUT
OutputCurrent(mA)
0 150
3000
2500
2000
1500
1000
500
0
GroundPinCurrent( A)m
25 50
G008
+85 C°
+25 C°
- °40 C
75 100 125
Temperature ( C)°
-40 85
45
40
35
30
25
20
15
10
5
0
Ground Pin Current ( A)m
-27.5 -15 -2.5 10
G009
22.5 60 72.547.535
I = 0 mA
OUT
OutputCurrent(mA)
0 350
3
2.5
2
1.5
1
0.5
0
OutputVoltage(V)
50 100 150 200
G010
250 300
+85 C°
+25 C°
- °40 C
Frequency(Hz)
10 10M
80
70
60
50
40
30
20
10
0
Power-SupplyRejectionRatio(dB)
100 1k 10k
G011
100k 1M
I =30mA
OUT
I =150mA
OUT
V V =0.5V-
IN OUT
Frequency(Hz)
10 10M
80
70
60
50
40
30
20
10
0
Power-SupplyRejectionRatio(dB)
100 1k 10k
G012
100k 1M
I =30mA
OUT
I =150mA
OUT
V V =1V-
IN OUT
TLV717xx
TLV717xxP
www.ti.com
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
TYPICAL CHARACTERISTICS (continued)
At operating temperature range (TA= –40°C to +85°C), TA= +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater),
IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs OUTPUT CURRENT
Figure 9. Figure 10.
GROUND PIN CURRENT vs TEMPERATURE OUTPUT VOLTAGE vs OUTPUT CURRENT
Figure 11. Figure 12.
TLV71728 TLV71728
PSRR vs FREQUENCY PSRR vs FREQUENCY
Figure 13. Figure 14.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TLV717xx TLV717xxP
InputVoltage(V)
3.6 4.3
90
80
70
60
50
40
30
20
10
0
Power-SupplyRejectionRatio(dB)
3.7 3.8 3.9
G013
4 4.1
1kHz
10kHz
100kHz
4.2
Frequency(Hz)
10 10M
10
1
0.1
0.01
0
NoiseSpectralDensity( V/ )m ÖHz
100 1k 10k
G014
100k 1M
1.2
2.8
5
TLV717xx
TLV717xxP
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At operating temperature range (TA= –40°C to +85°C), TA= +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater),
IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
PSRR vs INPUT VOLTAGE OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
Figure 15. Figure 16.
8Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TLV717xx TLV717xxP
TLV717xx
TLV717xxP
www.ti.com
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
APPLICATION INFORMATION
The TLV717xx belongs to a new family of next-generation value low-dropout (LDO) regulators. These devices
consume low quiescent current and deliver excellent line and load transient performance. These characteristics,
combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for
RF portable applications.
This family of regulators offers current foldback. Device operating junction temperature is –40°C to +125°C.
INPUT AND OUTPUT CAPACITOR REQUIREMENTS
X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in
value and equivalent series resistance (ESR) over temperature. The TLV717xx is designed to be stable with an
effective capacitance of 0.1 µF or larger at the output, though a 1-µF ceramic capacitor is recommended for
typical applications. Thus, the device is stable with capacitors of other dielectric types as well, as long as the
effective capacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective
capacitance refers to the capacitance that the LDO detects under operating bias voltage and temperature
conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In
addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-µF effective capacitance
also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained
applications. Note that using a 0.1-µF rated capacitor at the LDO output does not ensure stability because the
effective capacitance under the specified operating conditions would be less than 0.1 µF. Maximum ESR should
be less than 200 mΩ.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to
1.0-µF, low ESR capacitor across the IN and GND pins of the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast, rise-time load transients are anticipated, or if the device is not located close to the power
source. If source impedance is more than 2 Ω, a 0.1-µF input capacitor may be necessary to ensure stability.
BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE
Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance
(such as PSRR, output noise, and transient response), it is recommended that the board be designed with
separate ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In
addition, the output capacitor ground connection should be connected directly to the device GND pin. High ESR
capacitors may degrade PSRR performance.
INTERNAL CURRENT LIMIT
The TLV717xx has an internal foldback current limit that helps to protect the regulator during fault conditions. The
current supplied by the device is gradually throttled down as the output voltage decreases. When the output is
shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in
current limit, and is VOUT = ILIMIT × RLOAD. The advantage of foldback current limit is that the ILIMIT value is less
than the fixed current limit. Therefore, the power that the PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] is
much less.
The TLV717xx PMOS pass element has a built-in body diode that conducts current when the voltage at OUT
exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,
external limiting to 5% of the rated output current is recommended.
SHUTDOWN
The enable pin (EN) is active high. The device is enabled when the voltage at the EN pin goes above 0.9 V. This
relatively lower voltage value required to turn the LDO on can be exploited to power the LDO with a GPIO of
recent processors whose GPIO logic 1 voltage level is lower than traditional microcontrollers. The device is
turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be
connected to the IN pin.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TLV717xx TLV717xxP
TLV717xx
TLV717xxP
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
www.ti.com
DROPOUT VOLTAGE
The TLV717xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
UNDERVOLTAGE LOCKOUT (UVLO)
The TLV717xx uses an undervoltage lockout circuit (UVLO = 1.6 V) to keep the output shut off until the internal
circuitry operates properly.
POWER DISSIPATION
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC-low and high-K boards are given in the
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition, plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in Equation 1.
PD= (VIN – VOUT) × IOUT (1)
10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TLV717xx TLV717xxP
TLV717xx
TLV717xxP
www.ti.com
SBVS176A –OCTOBER 2011–REVISED APRIL 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2011) to Revision A Page
• Changed document status from Product Preview to Production Data ................................................................................. 1
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TLV717xx TLV717xxP
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TLV71712PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UX
TLV71712PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UX
TLV71712PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UX
TLV71713PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VC
TLV71713PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VC
TLV71715PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UY
TLV71715PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UY
TLV717185PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VN
TLV717185PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VN
TLV71718PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UZ
TLV71718PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UZ
TLV71721PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AR
TLV71721PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AR
TLV71725PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VA
TLV71725PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VA
TLV71727PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AS
TLV71727PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AS
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TLV717285PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VE
TLV717285PQNR PREVIEW X2SON DQN 5 3000 TBD Call TI Call TI -40 to 85
TLV71728PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VD
TLV71728PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VD
TLV71728PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VD
TLV71729PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VI
TLV71729PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VI
TLV71730PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VF
TLV71730PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VF
TLV71733PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VG
TLV71733PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VG
TLV71736PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VH
TLV71736PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV71712PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71712PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71712PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 2.0 8.0 Q3
TLV71712PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71712PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71713PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71713PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71713PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71713PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71715PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71715PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71715PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71715PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV717185PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV717185PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV717185PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV717185PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71718PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2013
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV71718PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71718PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71718PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71721PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71721PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71721PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71721PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71725PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71725PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71725PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71725PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71727PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71727PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71727PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71727PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV717285PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV717285PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71728PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71728PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71728PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 2.0 8.0 Q3
TLV71728PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71728PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71729PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71729PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71729PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71729PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71730PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71730PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71730PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71730PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71733PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71733PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71733PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71733PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71736PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71736PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
TLV71736PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV71736PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2013
Pack Materials-Page 2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV71712PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71712PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71712PDQNR3 X2SON DQN 4 3000 180.0 180.0 30.0
TLV71712PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71712PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71713PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71713PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71713PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71713PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71715PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71715PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71715PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71715PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV717185PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV717185PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV717185PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV717185PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71718PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71718PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71718PDQNT X2SON DQN 4 250 202.0 201.0 28.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2013
Pack Materials-Page 3
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV71718PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71721PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71721PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71721PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71721PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71725PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71725PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71725PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71725PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71727PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71727PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71727PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71727PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV717285PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV717285PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71728PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71728PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71728PDQNR3 X2SON DQN 4 3000 180.0 180.0 30.0
TLV71728PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71728PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71729PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71729PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71729PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71729PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71730PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71730PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71730PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71730PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71733PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71733PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71733PDQNT X2SON DQN 4 250 180.0 180.0 30.0
TLV71733PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71736PDQNR X2SON DQN 4 3000 202.0 201.0 28.0
TLV71736PDQNR X2SON DQN 4 3000 180.0 180.0 30.0
TLV71736PDQNT X2SON DQN 4 250 202.0 201.0 28.0
TLV71736PDQNT X2SON DQN 4 250 180.0 180.0 30.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2013
Pack Materials-Page 4
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated