SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Designed to be Used in Voltage-Limiting
Applications
D
6.5-Ω On-State Connection Between Ports
A and B
D
Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
D
Direct Interface With GTL+ Levels
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
The SN74TVC3010 provides 11 parallel NMOS
pass transistors with a common gate. The low
on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device can be used as a 10-bit switch with the gates cascaded together to a reference transistor. The
low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to
protect components with inputs that are sensitive to high-state voltage-level overshoots. (See Application
Information in this data sheet.)
All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can
be used as the reference transistor . Since, within the device, the characteristics from transistor to transistor are
equal, the maximum output high-state voltage (VOH) is approximately the reference voltage (VREF), with
minimal deviation from one output to another . This is a large benefit of the TVC solution over discrete devices.
Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the
low-voltage side, and the I/O signals are bidirectional through each FET.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
–40 C to 85 C
SOIC – DW
Tube SN74TVC3010DW
TVC3010
–40 C to 85 C
SOIC – DW
Tape and reel SN74TVC3010DWR
TVC3010
–40
°
C to 85
°
C
SSOP (QSOP) – DBQ Tape and reel SN74TVC3010DBQR TVC3010
TSSOP – PW Tape and reel SN74TVC3010PWR TT010
TVSOP – DGV Tape and reel SN74TVC3010DGVR TT010
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
GATE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
simplified schematic
24 23 22 21 20 13
12 3 4 5 12
GND A1 A2 A3 A4 A11
GATE B1 B2 B3 B4 B11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/output voltage range, VI/O (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DBQ package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are
observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN TYP MAX UNIT
VI/O Input/output voltage 0 5 V
VGATE GATE voltage 0 5 V
IPASS Pass-transistor current 20 64 mA
TAOperating free-air temperature –40 85 °C
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
application operating conditions (see Figure 3)
MIN TYP MAX UNIT
VBIAS BIAS voltage VREF + 0.6 2.1 5 V
VGATE GATE voltage VREF + 0.6 2.1 5 V
VREF Reference voltage 0 1.5 4.4 V
VDPU Drain pullup voltage 2.36 2.5 2.64 V
IPASS Pass-transistor current 14 mA
IREF Reference-transistor current 5µA
TAOperating free-air temperature –40 85 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VBIAS = 0, II = –18 mA –1.2 V
VOL IREF = 5
m
A,
VDPU = 2.625 V, VREF = 1.365 V,
RDPU = 150 Ω
VS = 0.175 V,
See Figure 1 350 mV
Ci(GATE) VI = 3 V or 0 24 pF
Cio(off) VO = 3 V or 0 4 12 pF
Cio(on) VO = 3 V or 0 12 30 pF
ron‡IREF = 5
m
A,
VDPU = 2.625 V, VREF = 1.365 V,
RDPU = 150 Ω
VS = 0.175 V,
See Figure 1 12.5 Ω
†All typical values are at TA = 25°C.
‡Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range,
VDPU = 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) MIN MAX UNIT
tPLH
A or B
B or A
0 4
ns
tPHL
A or B
B or A
0 4
ns
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPLHREF tPHLREF
2.5 V
0 V
2.5 V
VOL
Input
Tester
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Reference
TESTER CALIBRATION SETUP (see Note C)
VOL
Output
Device
Under Test
tPLHDUT
tPLH
(see Note D)
tPHLDUT
tPHL
(see Note E)
2.5 V
200 kΩ
3.3 V
RDPU =
150 Ω
Open-Drain
Test Interface
Motherboard
Interface
2
A1 (VREF)
1
GATE
24 B1 (VBIAS)
23
VDPU
TVC3010
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
B. The outputs are measured one at a time with one transition per measurement.
C. Test procedure: tPLHREF and tPHLREF are obtained by measuring the propagation delay of a reference measuring point.
tPLHDUT and tPHLDUT are obtained by measuring the propagation delay of the device under test.
D. tPLH = tPLHDUT – tPLHREF
E. tPHL = tPHLDUT – tPHLREF
B2
22
RDPU =
150 Ω
RDPU =
150 Ω
RDPU =
150 Ω
B3
21 B4
20 B11
13
3
A2 (VS)4
A3 (VS)5
A4 (VS)12
A11 (VS)
1.25 V 1.25 V
1.25 V 1.25 V
1.25 V 1.25 V
††† †
§§§ §
‡
Output tested
Output reference
Input tested
†
‡
§
DEFINITION SYMBOL
GATE
Figure 1. Tester Calibration Setup and Voltage Waveforms
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TVC background information
In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define,
among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host
bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate
with existing bus infrastructure. Providing an evolutionary upgrade path is important in the design of PC
architecture, but the existing bus standards must be preserved.
To achieve the ever-present need for smaller, faster, lighter devices that draw less power, yet have faster
performance, most new high-performance digital integrated circuits are being designed and produced with
advanced submicron semiconductor process technologies. These devices have thin gate-oxide or short
channel lengths and very low absolute-maximum voltages that can be tolerated at the inputs/outputs (I/Os)
without causing damage. In many cases, the I/Os of these devices are not tolerant of the high-state voltage
levels on the preexisting buses with which they must communicate. Therefore, it became necessary to protect
the I/Os of devices by limiting the I/O voltages.
The Texas Instruments (TI) translation voltage-clamp (TVC) family was designed specifically for protecting
sensitive I/Os (see Figure 2). The information in this data sheet describes the I/O-protection application of the
TVC family and should enable the design engineer to successfully implement an I/O-protection circuit utilizing
the TI TVC solution.
Low-Voltage
I/O Device
TVC Family
Voltage-Clamp
Device
Standard-Voltage
I/O Bus
Figure 2. Thin Gate-Oxide Protection Application
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TVC voltage-limiting application
For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any
one of the transistors (see Figure 3). This connection determines the VBIAS input of the reference transistor. The
VBIAS input is connected through a pullup resistor (typically, 200 kΩ ) to the VDD supply. A filter capacitor on VBIAS
is recommended. The opposite side of the reference transistor is used as the reference voltage (VREF)
connection. The VREF input must be less than VDDREF – 1 V to bias the reference transistor into conduction.
The reference transistor regulates the gate voltage (VGATE) of all the pass transistors. VGATE is determined by
the characteristic gate-to-source voltage difference (VGS) because VGATE = VREF + VGS. The low-voltage side
of the pass transistors has a high-level voltage limited to a maximum of VGATE – VGS, or VREF.
200 kΩ
V
DDREF
= 3.3 V
150 Ω150 Ω150 Ω150 Ω
Open-Drain
CPU Interface
Motherboard
Interface
3
A2 4
A3 5
A4 12
A11
1
V
DPU
TVC3010
GATE†
24 B1 (VBIAS)†
23
2
A1 (VREF)†
†V
REF
and V
BIAS
can be applied to any one of the pass transistors. GATE must be connected externally to V
BIAS
.
B2
22 B3
21 B4
20 B11
13
Figure 3. Typical Application Circuit
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
electrical characteristics
The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE
simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in
Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different
reference voltages. The plots of the dc characteristics clearly reveal that the device clamps at the desired
reference voltage for the varying device environments.
Figure 5 shows the V-I characteristics, with low reference voltages and a reference-transistor drain-supply
voltage of 3.3 V. To further investigate the spread of the V-I characteristic curves, VREF was held at 2.5 V and
IREF was increased by raising VDDREF (see Figure 6). The result was a tighter grouping of the V-I curves.
VDPASS
VREF
RDREF
GATE VBIAS
VDDREF
RDPASS
VDDPASS
VSPASS
Figure 4. TI SPICE Simulation Schematic and Voltage-Node Names
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
VSPASS – Low Reference Voltage – V
– Pass Current – mA
PASS
I– Pass Current – mA
PASS
I– Pass Current – mA
PASS
I
Weak
Nominal
Strong
VREF = 1 V
VDDREF = 3.3 V
RDREF = 200 kΩ
RDPASS = 150 Ω
VDDPASS = 3.3 V
Weak
Nominal
Strong
Weak
Nominal
Strong
VSPASS – Low Reference Voltage – V
VSPASS – Low Reference Voltage – V
VREF = 1.5 V
VDDREF = 3.3 V
RDREF = 200 kΩ
RDPASS = 150 Ω
VDDPASS = 3.3 V
VREF = 2 V
VDDREF = 3.3 V
RDREF = 200 kΩ
RDPASS = 150 Ω
VDDPASS = 3.3 V
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
Figure 5. Electrical Characteristics at Low VREF Voltages
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
– Pass Current – mA
PASS
I– Pass Current – mA
PASS
I– Pass Current – mA
PASS
I
VSPASS – Low Reference Voltage – V
VSPASS – Low Reference Voltage – V
VSPASS – Low Reference Voltage – V
Weak
Nominal
Strong
VREF = 2.5 V
VDDREF = 3.3 V
RDREF = 200 kΩ
RDPASS = 150 Ω
VDDPASS = 3.3 V
Weak
Nominal
Strong
VREF = 2.5 V
VDDREF = 4 V
RDREF = 200 kΩ
RDPASS = 150 Ω
VDDPASS = 3.3 V
Weak
Nominal
Strong
VREF = 2.5 V
VDDREF = 5 V
RDREF = 200 kΩ
RDPASS = 150 Ω
VDDPASS = 3.3 V
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
Figure 6. Electrical Characteristics at VREF = 2.5 V
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
features and benefits
The TVC family has several features that benefit a system designer when implementing a
sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits.
Table 1. Features and Benefits
FEATURES BENEFITS
Any FET can be used as the reference transistor. Ease of layout
All FETs on one die, tight process control Very low spread of VO relative to VREF
No active control logic (passive device) No logic power supply (VCC) required
Flow-through pinout Ease of trace routing
Devices offered in dif ferent bit-widths and packages Optimizes design and cost effectiveness
Designer flexibility with VREF input Allows migration to lower-voltage I/Os without board redesign
conclusion
The TI TVC family provides the designer with a solution for protection of circuits with I/Os that are sensitive to
high-state voltage-level overshoots. The flexibility of TVC enables a low-voltage migration path for advanced
designs to align with industry standards.
frequently asked questions (FAQ)
1. Q: Can any of the transistors in the array be used as the reference transistor?
A: Yes, any transistor can be used as long as its VBIAS pin is connected to the GATE pin.
2. Q: In the recommended operating conditions table of the data sheet, the typical VBIAS is 3.3 V.
Should VBIAS be equal to or greater than VREF on the reference transistor?
A: VBIAS is a variable that is determined by VREF. VBIAS is connected to VDD through a resistor to allow the
bias voltage to be controlled by VREF. VDD can be as high as 5.5 V. VREF needs to be at least 1 V less
than VDDREF on the reference transistor.
3. Q: Do both A and B ports have 5-V I/O tolerance or is 5-V I/O tolerance provided only on the low-voltage
side?
A: Both ports are 5-V tolerant.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74TVC3010DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74TVC3010DBQRE4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74TVC3010DBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74TVC3010DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DWE4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010PW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010PWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74TVC3010PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74TVC3010PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74TVC3010DBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74TVC3010DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74TVC3010DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74TVC3010PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74TVC3010DBQR SSOP DBQ 24 2500 367.0 367.0 38.0
SN74TVC3010DGVR TVSOP DGV 24 2000 367.0 367.0 35.0
SN74TVC3010DWR SOIC DW 24 2000 367.0 367.0 45.0
SN74TVC3010PWR TSSOP PW 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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