IRFP460B, SiHG460B
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S12-0812-Rev. B, 16-Apr-12 1Document Number: 91502
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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D Series Power MOSFET
FEATURES
•Optimal Design
- Low Area Specific On-Resistance
- Low Input Capacitance (Ciss)
- Reduced Capacitive Switching Losses
- High Body Diode Ruggedness
- Avalanche Energy Rated (UIS)
• Optimal Efficiency and Operation
- Low Cost
- Simple Gate Drive Circuitry
- Low Figure-of-Merit (FOM): Ron x Qg
- Fast Switching
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
Note
*Lead (Pb)-containing terminations are not RoHS-compliant.
Exemptions may apply.
APPLICATIONS
• Consumer Electronics
- Displays (LCD or Plasma TV)
• Server and Telecom Power Supplies
- SMPS
• Industrial
- Welding
- Induction Heating
- Motor Drives
• Battery Chargers
•SMPS
- Power Factor Correction (PFC)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 10 mH, Rg = 25 , IAS = 7.5 A.
c. 1.6 mm from case.
d. ISD ID, starting TJ = 25 °C.
PRODUCT SUMMARY
VDS (V) at TJ max. 550
RDS(on) max. at 25 °C ()V
GS = 10 V 0.25
Qg max. (nC) 170
Qgs (nC) 14
Qgd (nC) 28
Configuration Single
N-Channel MOSFET
G
D
S
TO-247AC
G
D
S
ORDERING INFORMATION
Package TO-247AC
Lead (Pb)-free IRFP460BPbF
Lead (Pb)-free and Halogen-free SiHG460B-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500
V Gate-Source Voltage VGS ± 20
Gate-Source Voltage AC (f > 1 Hz) 30
Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C ID
20
ATC = 100 °C 13
Pulsed Drain CurrentaIDM 62
Linear Derating Factor 2.2 W/°C
Single Pulse Avalanche EnergybEAS 281 mJ
Maximum Power Dissipation PD278 W
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Drain-Source Voltage Slope TJ = 125 °C dV/dt 24 V/ns
Reverse Diode dV/dtd0.36
Soldering Recommendations (Peak Temperature) for 10 s 300c°C
IRFP460B, SiHG460B
www.vishay.com Vishay Siliconix
S12-0812-Rev. B, 16-Apr-12 2Document Number: 91502
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -40
°C/W
Maximum Junction-to-Case (Drain) RthJC - 0.45
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 500 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 250 μA -0.56-
V/°C
Gate-Source Threshold Voltage (N) VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 500 V, VGS = 0 V - - 1 μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 10
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 10 A - 0.2 0.25
Forward Transconductance gfs VDS = 50 V, ID = 10 A - 12 - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 100 V,
f = 1 MHz
- 3094 -
pF
Output Capacitance Coss - 152 -
Reverse Transfer Capacitance Crss -13-
Effective output capacitance, energy
relatedaCo(er) VGS = 0 V,
VDS = 0 V to 400 V
- 131 -
Effective output capacitance, time
relatedbCo(tr) - 189 -
Total Gate Charge Qg
VGS = 10 V ID = 10 A, VDS = 400 V
- 85 170
nC Gate-Source Charge Qgs -14-
Gate-Drain Charge Qgd -28-
Turn-On Delay Time td(on)
VDD = 400 V, ID = 10 A,
VGS = 10 V, Rg = 9.1
-2450
ns
Rise Time tr -3162
Turn-Off Delay Time td(off) - 117 176
Fall Time tf - 56 112
Gate Input Resistance Rgf = 1 MHz, open drain - 1.8 -
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current IS
MOSFET symbol
showing the
integral reverse
p - n junction diode
--20
A
Pulsed Diode Forward Current ISM --80
Diode Forward Voltage VSD TJ = 25 °C, IS = 10 A, VGS = 0 V - - 1.2 V
Reverse Recovery Time trr TJ = 25 °C, IF = IS = 10 A,
dI/dt = 100 A/μs, VR = 20 V
- 437 - ns
Reverse Recovery Charge Qrr -5.9-μC
Reverse Recovery Current IRRM -25-A
S
D
G
IRFP460B, SiHG460B
www.vishay.com Vishay Siliconix
S12-0812-Rev. B, 16-Apr-12 3Document Number: 91502
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
11 V
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
0 5 10 15 20 25 30
TJ = 25 °C
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
BOTTOM 5 V
11 V
0
10
20
30
40
VDS, Drain-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
0 5 10 15 20 25 30
TJ = 150 °C
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
BOTTOM 5 V
V
GS
, Gate-to-Source Voltage (V)
I
D
, Drain-to-Source Current (A)
0 5 10 15 20 25
TJ = 25 °C
TJ = 150 °C
20
40
60
80
0
TJ, Junction Temperature (°C)
RDS(on), Drain-to-Source
- 60 - 40 - 20 020 40 60 80 100 120 140 160
On Resistance (Normalized)
0
0.5
1
1.5
2
2.5
3
VGS = 10 V
ID = 10 A
ġ
ġ
ġ
ġ
ġ
V
DS
, Drain-to-Source Voltage (V)
Capacitance (pF)
Ciss
Coss
Crss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
1
10
100
1000
0 100 200 300 400 500
10 000
Qg, Total Gate Charge (nC)
VGS, Gate-to-Source Voltage (V)
16
4
0
24
20
12
8
0306090
120 150 180
VDS = 400 V
VDS = 250 V
VDS = 100 V
IRFP460B, SiHG460B
www.vishay.com Vishay Siliconix
S12-0812-Rev. B, 16-Apr-12 4Document Number: 91502
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10 - Temperature vs. Drain-to-Source Voltage
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
0.1
1
10
100
V
SD
, Source-Drain Voltage (V)
I
SD
, Reverse Drain Current (A)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
ġ
ġ
ġ
VGS = 0 V
TJ = 25 °C
TJ = 150 °C
T
J
, Case Temperature (°C)
I
D
, Drain Current (A)
25 50 75 100 125 150
20
16
12
8
4
0
TJ, Junction Temperature (°C)
VDS, Drain-to-Source
- 60 0 160
Brakdown Voltage (V)
- 40 - 20 20 40 60 80 100 120 140
475
500
525
550
575
600
625
0.01
0.1
1
0.0001 0.001 0.01 0.1 1
Normalized Effective Transient
Thermal Impedance
Pulse Time (s)
Duty Cycle = 0.5
0.2
0.1
0.02
0.05
Single Pulse
IRFP460B, SiHG460B
www.vishay.com Vishay Siliconix
S12-0812-Rev. B, 16-Apr-12 5Document Number: 91502
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 12 - Switching Time Test Circuit
Fig. 13 - Switching Time Waveforms
Fig. 14 - Unclamped Inductive Test Circuit
Fig. 15 - Unclamped Inductive Waveforms
Fig. 16 - Basic Gate Charge Waveform
Fig. 17 - Gate Charge Test Circuit
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10 V
+
-
VDS
VDD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
R
G
I
AS
0.01 Ω
t
p
D.U.T
L
V
DS
+
-V
DD
10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
QGS QGD
QG
V
G
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
IRFP460B, SiHG460B
www.vishay.com Vishay Siliconix
S12-0812-Rev. B, 16-Apr-12 6Document Number: 91502
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91502.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Package Information
www.vishay.com Vishay Siliconix
Revision: 01-Jul-13 1Document Number: 91360
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TO-247AC (High Voltage)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -
b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144
c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224
D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216
D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
123
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP (Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
CC
View B
(b1, b3, b5) Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
4
4
4
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
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Revision: 08-Feb-17 1Document Number: 91000
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