TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
16-CHANNEL Fm+ I
2
C-BUS CONSTANT-CURRENT LED SINK DRIVER
Check for Samples: TLC59116
1FEATURES
2•16 LED Drivers (Each Output Programmable at •Open-Load/Overtemperature Detection Mode
Off, On, Programmable LED Brightness, or to Detect Individual LED Errors
Programmable Group Dimming/Blinking Mixed •Output State Change Programmable on
With Individual LED Brightness) Acknowledge or Stop Command to Update
•16 Constant-Current Output Channels Outputs Byte by Byte or All at Same Time
(Default to Change on Stop)
•256-Step (8-Bit) Linear Programmable
Brightness Per LED Output Varying From Fully •Output Current Adjusted Through an External
Off (Default) to Maximum Brightness Using a Resistor
97-kHz PWM Signal •Constant Output Current Range: 5 mA to
•256-Step Group Brightness Control Allows 120 mA
General Dimming [Using a 190-Hz PWM Signal •Maximum Output Voltage: 17 V
From Fully Off to Maximum Brightness •25-MHz Internal Oscillator Requires No
(Default)] External Components
•256-Step Group Blinking With Frequency •1-MHz Fast-mode Plus (FMT) Compatible I2C
Programmable From 24 Hz to 10.73 s and Duty Bus Interface With 30-mA High-Drive
Cycle From 0% to 99.6% Capability on SDA Output for Driving
•Four Hardware Address Pins Allow 14 High-Capacitive Buses
TLC59116 Devices to Be Connected to Same •Internal Power-On Reset
I2C Bus •Noise Filter on SCL/SDA Inputs
•Four Software-Programmable I2C Bus •No Glitch on Power Up
Addresses (One LED Group Call Address and •Active-Low Reset
Three LED Sub Call Addresses) Allow Groups
of Devices to Be Addressed at Same Time in •Supports Hot Insertion
Any Combination •Low Standby Current
•Software Reset Feature (SWRST Call) Allows •3.3-V or 5-V Supply Voltage
Device to Be Reset Through I2C Bus •5.5-V Tolerant Inputs
•Up to 14 Possible Hardware-Adjustable •Offered in 28-Pin Thin Shrink Small-Outline
Individual I2C Bus Addresses Per Device, So Package (TSSOP) (PW) and 32-Pin Quad
That Each Device Can Be Programmed Flatpack No Lead (QFN)
• –40°C to 85°C Operation
DESCRIPTION/ORDERING INFORMATION
The TLC59116 is an I2C bus controlled 16-channel LED driver that is optimized for red/green/blue/amber (RGBA)
color mixing and backlight application for amusement products. Each LED output has its own 8-bit resolution
(256 steps) fixed-frequency individual PWM controller that operates at 97 kHz, with a duty cycle that is adjustable
from 0% to 99.6%. The individual PWM controller allows each LED to be set to a specific brightness value. An
additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 190 Hz and an
adjustable frequency between 24 Hz to once every 10.73 seconds, with a duty cycle that is adjustable from 0%
to 99.6%. The group PWM controller dims or blinks all LEDs with the same value.
Each LED output can be off, on (no PWM control), or set at its individual PWM controller value at both individual
and group PWM controller values.
The TLC59116 operates with a supply voltage range of 3 V to 5.5 V and the outputs are 17 V tolerant. LEDs can
be directly connected to the TLC59116 device outputs.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
I C Bus Control
2
OUT0 OUT1 OUT14 OUT15
REXT
I/O Regulator
Output Driver and Error Detection
LED State
Select Register
97 kHz GRPFRQ
Register
24.3 kHz
190 kHz
PWM Register X
Brightness Control
25-MHz
Oscillator
Power-On
Reset Control
Input Filter
SCL
SDA
A0 A1 A2 A3
RESET
VCC
GND
0 = Permanently off
1 = Permanently on
GRPPWM
Register
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or defined groups of
TLC59116 devices to respond to a common I2C-bus address, allowing for example, all the same color LEDs to
be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands.
Four hardware address pins allow up to 14 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the TLC59116 through the I2C-bus,
identical to the Power-On Reset (POR) that initializes the registers to their default state causing the outputs to be
set high (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.
Table 1. ORDERING INFORMATION(1)
TAPACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING
TSSOP –PW TLC59116IPWR Y59116
–40°C to 85°C Reel of 2000
QFN –RHB TLC59116IRHBR Y59116
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
BLOCK DIAGRAM
2Copyright ©2008–2011, Texas Instruments Incorporated
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
15
16
17
18
23
24
25
26
27
28
REXT
A0
A1
A2
A3
OUT0
OUT1
OUT3
GND
VCC
SDA
SCL
RESET
GND
OUT15
OUT11
OUT10
OUT9
OUT8
11
12
13
14
OUT4
OUT5
OUT6
OUT7
19
20
21
22 OUT14
OUT13
OUT12
GND
OUT2
RHB PACKAGE
(TOP VIEW)
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 15 16
A2
A3
OUT0
OUT1
OUT2
OUT3
GND
OUT4
RESET
GND
OUT15
OUT14
OUT13
OUT12
GND
OUT11
14
1
2
3
4
5
6
7
8
A1
A0
REXT
NC
NC
VCC
SDA
SCL
OUT5
OUT6
OUT7
NC
NC
OUT8
OUT9
OUT10
Exposed
Thermal Pad
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
NC - No internal connection
If used, the exposed thermal pad must be connected as a secondary ground.
Copyright ©2008–2011, Texas Instruments Incorporated 3
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
TERMINAL FUNCTIONS
PIN NO.
PIN NAME I/O(1) DESCRIPTION
PW RHB
REXT 1 30 I Input terminal used to connect an external resistor for setting up all output currents
A0 2 31 I Address input 0
A1 3 32 I Address input 1
A2 4 1 I Address input 2
A3 5 2 I Address input 3
OUT0 6 3 O Constant current output 0
OUT1 7 4 O Constant current output 1
OUT2 8 5 O Constant current output 2
OUT3 9 6 O Constant current output 3
GND 10 7 Ground
OUT4 11 8 O Constant current output 4
OUT5 12 9 O Constant current output 5
OUT6 13 10 O Constant current output 6
OUT7 14 11 O Constant current output 7
OUT8 15 14 O Constant current output 8
OUT9 16 15 O Constant current output 9
OUT10 17 16 O Constant current output 10
OUT11 18 17 O Constant current output 11
GND 19 18 Ground
OUT12 20 19 O Constant current output 12
OUT13 21 20 O Constant current output 13
OUT14 22 21 O Constant current output 14
OUT15 23 22 O Constant current output 15
GND 24 23 Ground
RESET 25 24 I Active-low reset input
SCL 26 25 I Serial clock input
SDA 27 26 I/O Serial data input/output
VCC 28 27 Power supply
12, 13,
NC –No internal connection
28, 29
(1) I = input, O = output
4Copyright ©2008–2011, Texas Instruments Incorporated
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range 0 V to 7 V
VIInput voltage range –0.4 V to VCC + 0.4 V
VOOutput voltage range –0.5 V to 20 V
IOOutput current per channel 120 mA
PDPower dissipation See Dissipation Ratings
TJJunction temperature range –40°C to 150°C
Tstg Storage temperature range –55°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS POWER RATING DERATING FACTOR(1) POWER RATING
PACKAGE TA≤25°C TA>25°C TA= 85°C
PW (TSSOP) 1207 mW 9.6 mW/°C 628 mW
RHB (QFN) 3.08 W 30.8 mW/°C 1.23 W
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
VCC Supply voltage 3 5.5 V
VIH High-level input voltage SCL, SDA, RESET, A0, A1, A2, A3 0.7 ×VCC VCC V
VIL Low-level input voltage SCL, SDA, RESET, A0, A1, A2, A3 0 0.3 ×VCC V
VOSupply voltage to output pins OUT0 to OUT15 17 V
VCC = 3 V 20
IOL Low-level output current sink SDA mA
VCC = 3 V 30
IOOutput current per channel OUT0 to OUT15 5 120 mA
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
Copyright ©2008–2011, Texas Instruments Incorporated 5
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA=–40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SCL, SDA, A0,
Input/output leakage
IIA1, A2, A3, VI= VCC or GND ±0.3 μA
current RESET
Output leakage current OUT0 to OUT15 VO= 17 V, TJ= 25°C 0.5 μA
VPOR Power-on reset voltage 2.5 V
VCC = 3 V, VOL = 0.4 V 20
IOL Low-level output current SDA mA
VCC = 5 V, VOL = 0.4 V 30
IO(1) Output current 1 OUT0 to OUT15 VO= 0.6 V, Rext = 720 Ω, CG = 0.992(2) 26 mA
IO= 26 mA, VO= 0.6 V, Rext = 720 Ω,
Output current error OUT0 to OUT15 ±8 %
TJ= 25°C
Output channel to IO= 26 mA, VO= 0.6 V, Rext = 720 Ω,
OUT0 to OUT15 ±6 %
channel current error TJ= 25°C
IO(2) Output current 2 OUT0 to OUT15 VO= 0.8 V, Rext = 360 Ω, CG = 0.992(2) 52 mA
IO= 52 mA, VO= 0.8 V, Rext = 360 Ω,
Output current error OUT0 to OUT15 ±8 %
TJ= 25°C
Output channel to IO= 52 mA, VO= 0.8 V, Rext = 360 Ω,
OUT0 to OUT15 ±6 %
channel current error TJ= 25°C
VO= 1 V to 3 V, IO= 26 mA ±0.1
IOUT vs Output current vs output OUT0 to OUT15 %/V
VOUT voltage regulation VO= 3 V to 5.5 V, IO= 26 mA to 120 mA ±1
Threshold current 1 for 0.5 ×
IOUT,Th1 OUT0 to OUT15 IOUT,target = 26 mA %
error detection ITARGET
Threshold current 2 for 0.5 ×
IOUT,Th2 OUT0 to OUT15 IOUT,target = 52 mA %
error detection ITARGET
Threshold current 3 for 0.5 ×
IOUT,Th3 OUT0 to OUT15 IOUT,target = 104 mA %
error detection ITARGET
TSD Overtemperature shutdown(3) 150 175 200 °C
THYS Restart hysteresis 15 °C
SCL, A0, A1,
CiInput capacitance VI= VCC or GND 5 pF
A2, A3, RESET
Cio Input/output capacitance SDA VI= VCC or GND 8 pF
OUT0 to OUT15 = OFF, 25
Rext = Open
OUT0 to OUT15 = OFF, 29
Rext = 720 Ω
OUT0 to OUT15 = OFF, 32
Rext = 360 Ω
OUT0 to OUT15 = OFF,
ICC Supply current VCC = 5.5 V 37 mA
Rext = 180 Ω
OUT0 to OUT15 = ON, 29
Rext = 720 Ω
OUT0 to OUT15 = ON, 32
Rext = 360 Ω
OUT0 to OUT15 = ON, 37
Rext = 180 Ω
(1) All typical values are at TA= 25°C.
(2) CG is the Current Gain and is defined in Table 12.
(3) Specified by design
6Copyright ©2008–2011, Texas Instruments Incorporated
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
TIMING REQUIREMENTS
TA=–40°C to 85°CSTANDARD MODE FAST MODE FAST MODE PLUS
I2C BUS I2C BUS I2C BUS UNIT
MIN MAX MIN MAX MIN MAX
I2C Interface
fSCL SCL clock frequency(1) 0 100 0 400 0 1000 kHz
I2C bus free time between Stop and
tBUF 4.7 1.3 0.5 μs
Start conditions
tHD;STA Hold time (repeated) Start condition 4 0.6 0.26 μs
Setup time for a repeated Start
tSU;STA 4.7 0.6 0.26 μs
condition
tSU;STO Setup time for Stop condition 4 0.6 0.26 μs
tHD;DAT Data hold time 0 0 0 ns
tVD;ACK Data valid acknowledge time(2) 0.3 3.45 0.1 0.9 0.05 0.45 μs
tVD;DAT Data valid time(3) 0.3 3.45 0.1 0.9 0.05 0.45 μs
tSU;DAT Data setup time 250 100 50 ns
tLOW Low period of SCL clock 4.7 1.3 0.5 μs
tHIGH High period of SCL clock 4 0.6 0.26 μs
Fall time of both SDA and SCL
tf300 20+0.1Cb(6) 300 120 ns
signals(4) (5)
Rise time of both SDA and SCL
tr1000 20+0.1Cb(6) 300 120 ns
signals
Pulse width of spikes that must be
tSP 50 50 50 ns
suppressed by the input filter(7)
Reset
tWReset pulse width 10 10 10 ns
tREC Reset recovery time 0 0 0 ns
tRESET Time to reset(8) (9) 400 400 400 ns
(1) Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
low for a minimum of 25 ms. Disable bus time-out feature for dc operation.
(2) tVD;ACK = time for ACK signal from SCL low to SDA (out) low.
(3) tVD;DAT = minimum time for SDA data out to be valid following SCL low.
(4) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of the SCL falling edge.
(5) The maximum tffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
(6) Cb= Total capacitance of one bus line in pF
(7) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
(8) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.
(9) Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
Copyright ©2008–2011, Texas Instruments Incorporated 7
SDA
SCL
Start
ACK or Read Cycle
tW
tREC
RESET
30%
50%
tRESET
OUTn
50%
tRESET
SDA
SCL
tBUF
tLOW
tr
tHD;STA
tHD;DAT
tf
tHIGH tSU;DAT Sr
tSU;DAT
tHD;STA tSP
tSU;STO
PP S
SCL
SDA
Protocol
START
(S)
Condition
Bit 7
MSB
(A7)
Bit 6
(A6)
Bit 7
(D1)
Bit 8
(D0)
Acknowledge
(A)
STOP Condition
(P)
tBUF
tLOW 1/fSCL
tHD;STA TSU;STO
tSU;DAT
tSU;STA
tHD;DAT tVD;DAT tVD;ACK
tHIGH
tf
tr
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 1. Reset Timing
Figure 2. Definition of Timing
NOTE: Rise and fall times refer to VIL and VIH.
Figure 3. I2C Bus Timing
8Copyright ©2008–2011, Texas Instruments Incorporated
Pulse
Generator DUT
VCC
Open
GND
RL
CL
VO
VCC
VI
RT
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
PARAMETER MEASUREMENT INFORMATION (continued)
NOTE: RL= Load resistance for SDA and SCL; should be >1 kΩat 3-mA or lower current
CL= Load capacitance; includes jig and probe capacitance
RT= Termination resistance; should be equal to the output impedance (ZO) of the pulse generator
Figure 4. Test Circuit for Switching Characteristics
Copyright ©2008–2011, Texas Instruments Incorporated 9
1 1 0 A3 A1A2 A0
Slave Address
R/W
Fixed Hardware
Selectable
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
APPLICATION INFORMATION
Functional Description
Device Address
Following a Start condition, the bus master must output the address of the slave it is accessing.
Regular I2C Bus Slave Address
The I2C bus slave address of the TLC59116 is shown in Figure 5. To conserve power, no internal pullup resistors
are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For buffer
management purposes, a set of sector information data should be stored.
Figure 5. Slave Address
The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is
selected. When set to logic 0, a write operation is selected.
LED All Call I2C Bus Address
•Default power-up value (ALLCALLADR register): D0h or 1101 000
•Programmable through I2C bus (volatile programming)
•At power-up, LED All Call I2C bus address is enabled. TLC59116 sends an ACK when D0h (R/W = 0) or D1h
(R/W = 1) is sent by the master.
See LED All Call I2C Bus Address Register (ALLCALLADR) for more detail.
NOTE
The default LED All Call I2C bus address (D0h or 1101 000) must not be used as a regular
I2C bus slave address, since this address is enabled at power-up. All the TLC59116
devices on the I2C bus will acknowledge the address if it is sent by the I2C bus master.
LED Sub Call I2C Bus Address
•Three different I2C bus addresses can be used
•Default power-up values:
–SUBADR1 register: D2h or 1101 001
–SUBADR2 register: D4h or 1101 010
–SUBADR3 register: D8h or 1101 100
•Programmable through I2C bus (volatile programming)
•At power-up, Sub Call I2C bus address is disabled. TLC59116 does not send an ACK when D2h (R/W = 0) or
D3h (R/W = 1) or D4h (R/W = 0) or D5h (R/W = 1) or D8h (R/W = 0) or D9h (R/W = 1) is sent by the master.
See I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3) for more detail.
NOTE
The LED Sub Call I2C bus addresses may be used as regular I2C bus slave addresses if
their corresponding enable bits are set to 0 in the MODE1 Register.
10 Copyright ©2008–2011, Texas Instruments Incorporated
1 1 0 1 10 1 R/W
AI2 AI1 AI0 D4 D2D3 D1 D0
Auto-Increment
Options
Register Address
Auto-Increment
Flag
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
Software Reset I2C Bus Address
The address shown in Figure 6 is used when a reset of the TLC59116 is performed by the master. The software
reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59116 does not acknowledge the
SWRST. See Software Reset for more detail.
Figure 6. Software Reset Address
NOTE
The Software Reset I2C bus address is reserved address and cannot be use as regular
I2C bus slave address or as an LED All Call or LED Sub Call address.
Control Register
Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address,
the bus master sends a byte to the TLC59116, which is stored in the Control register. The lowest five bits are
used as a pointer to determine which register is accessed (D[4:0]). The highest three bits are used as
auto-increment flag and auto-increment options (AI[2:0]).
Figure 7. Control Register
When the auto-increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically
incremented after a read or write. This allows the user to program the registers sequentially. Four different types
of auto-increment are possible, depending on AI1 and AI0 values.
Table 2. Auto-Increment Options
AI2 AI1 AI0 DESCRIPTION
0 0 0 No auto-increment
1 0 0 Auto-increment for all registers. D[4:0] roll over to 0 0000 after the last register (1 1011) is accessed.
Auto-increment for individual brightness registers only. D[4:0] roll over to 0 0010 after the last register
101(1 0001) is accessed.
Auto-increment for global control registers only. D[4:0] roll over to 1 0010 after the last register (1 0011) is
110accessed.
Auto-increment for individual and global control registers only. D[4:0] roll over to 0 0010 after the last
111register (1 0011) is accessed.
NOTE
Other combinations are not shown in Table 2. (AI[2:0] = 001, 010, and 011) are reserved
and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C bus
communication, for example, changing the brightness of a single LED. Data is overwritten each time the register
is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the
same I2C bus communication, for example, changing a color setting to another color setting.
Copyright ©2008–2011, Texas Instruments Incorporated 11
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same
I2C bus communication, for example, global brightness or blinking change.
AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C bus
communication, for example, changing color and global brightness at the same time.
Only the five least significant bits D[4:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[4:0] is the first register that will be
addressed (read or write operation), and can be anywhere between 0 0000 and 1 1011 (as defined in Table 3).
When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register
increment stops and goes to the next one is determined by AI[2:0]. See Table 2 for rollover values. For example,
if the Control register = 1111 0100 (F4h), then the register addressing sequence will be (in hex):
14 →... →1B →00 →... →13 →02 →... →13 →02 →... as long as the master keeps sending or
reading data.
Driver Output
Constant Current Output
In LED display applications, TLC59116 provides nearly no current variations from channel to channel and from
device to device. While IOUT ≤52 mA, the maximum current skew between channels is less than ±6% and less
than ±8% between devices.
Adjusting Output Current
TLC59116 scales up the reference current (Iref) set by the external resistor (Rext) to sink the output current (Iout) at
each output port. Table 12 shows the Configuration Code and discusses bits CM, HC, and CC[5:0]. The following
formulas can be used to calculate the target output current IOUT,target in the saturation region:
VREXT = 1.26 V ×VG
Iref = VREXT/Rext, if another end of the external resistor Rext is connected to ground
IOUT,target = Iref ×15 ×3CM –1
Where Rext is the resistance of the external resistor connected to the REXT terminal, and VREXT is the voltage of
REXT, which is controlled by the programmable voltage gain (VG), which is defined by the Configuration Code.
The Current Multiplier bit (CM) sets the ratio IOUT,target/Iref to 15 or 5 (sets the exponent "CM –1" to either 0
or –1). After power on, the default value of VG is 127/128 = 0.992, and the default value of CM is 1, so that the
ratio IOUT,target/Iref = 15. Based on the default VG and CM:
VREXT = 1.26 V ×127/128 = 1.25 V
IOUT,target = (1.25 V/Rext)×15
Therefore, the default current is approximately 52 mA at 360 Ωand 26 mA at 720 Ω. The default relationship
after power on between IOUT,target and Rext is shown in Figure 8.
Figure 9 shows the output voltage versus the output current with several different resistor values on REXT. This
shows the minimum voltage required at the device to have full VF across the LED. The VLED voltage must be
higher than the VF plus the VOL of the driver. If the VLED is too high, more power will be dissipated in the driver.
If this is the case, a resistor can be inserted in series with the LED to dissipate the excess power and reduce the
thermal conditions on the driver.
If a single driver is used with LEDs that have different VF values, resistors can also be used in series with the
LED to remove the excess power from the driver. In cases where not all outputs are being used, the unused
outputs can be left floating without issue.
Figure 10 shows an example of a single TLC59116 being driven by an MSP430. By adding a simple LDO
(TPS7A4533), the MSP430 and TLC59116 can be driven from a 3.3V supply and the VLED will be driven by the
5V supply. A 468 ohm resistor tied from R-EXT to ground sets the output current to 40mA per channel. A0
through A3 are all tied to ground setting the I2C address to 00h.
12 Copyright ©2008–2011, Texas Instruments Incorporated
0
20
40
60
80
100
120
140
R ( )
ext W
01500 2500 3500
500
1000 2000 3000 4000
Output Current, I (A)
out
0
25
50
75
100
125
150
0 2.01.0 3.0
Output Current (mA)
Output Voltage (V)
I = 120 mA
O
I = 100 mA
O
I = 80 mA
O
I = 60 mA
O
I = 40 mA
O
I = 20 mA
O
I = 5 mA
O
...
...
REXT
468Ω
GND
OUT14
OUT1
OUT15
OUT0
TLC59116 OUT13A0-A3
R-EXT
VDD
RESET
SDA
SCL
RESET
SDA
SCL
MSP430
+5V
TPS7A4533
IN SHDN
GND
OUT
SENSE
+3.3V
+3.3V
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
Figure 8. IOUT,target vs Rext Figure 9. Output Current vs Output Voltage
Figure 10. TLC59116 40 mA Per Channel Typical Application
Copyright ©2008–2011, Texas Instruments Incorporated 13
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
Register Descriptions
Table 3 describes the registers in the TLC59116.
Table 3. Register Descriptions
REGISTER
NUMBER NAME ACCESS(1) DESCRIPTION
(HEX)
00 MODE1 R/W Mode 1
01 MODE2 R/W Mode 2
02 PWM0 R/W Brightness control LED0
03 PWM1 R/W Brightness control LED1
04 PWM2 R/W Brightness control LED2
05 PWM3 R/W Brightness control LED3
06 PWM4 R/W Brightness control LED4
07 PWM5 R/W Brightness control LED5
08 PWM6 R/W Brightness control LED6
09 PWM7 R/W Brightness control LED7
0A PWM8 R/W Brightness control LED8
0B PWM9 R/W Brightness control LED9
0C PWM10 R/W Brightness control LED10
0D PWM11 R/W Brightness control LED11
0E PWM12 R/W Brightness control LED12
0F PWM13 R/W Brightness control LED13
10 PWM14 R/W Brightness control LED14
11 PWM15 R/W Brightness control LED15
12 GRPPWM R/W Group duty cycle control
13 GRPFREQ R/W Group frequency
14 LEDOUT0 R/W LED output state 0
15 LEDOUT1 R/W LED output state 1
16 LEDOUT2 R/W LED output state 2
17 LEDOUT3 R/W LED output state 3
18 SUBADR1 R/W I2C bus subaddress 1
19 SUBADR2 R/W I2C bus subaddress 2
1A SUBADR3 R/W I2C bus subaddress 3
1B ALLCALLADR R/W LED All Call I2C bus address
1C IREF R/W IREF configuration
1D EFLAG1 R Error flags 1
1E EFLAG2 R Error flags 2
(1) R = read, W = write
14 Copyright ©2008–2011, Texas Instruments Incorporated
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
Mode Register 1 (MODE1)
Table 4 describes Mode Register 1.
Table 4. MODE1 –Mode Register 1 (Address 00h) Bit Description
BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
0(2) Register auto-increment disabled
7 AI2 R 1 Register auto-increment enabled
0(2) Auto-increment bit 1 = 0
6 AI1 R 1 Auto-increment bit 1 = 1
0(2) Auto-increment bit 0 = 0
5 AI0 R 1 Auto-increment bit 0 = 1
0 Normal mode(3)
4 OSC R/W 1(2) Oscillator off.
0(2) Device does not respond to I2C bus subaddress 1.
3 SUB1 R/W 1 Device responds to I2C bus subaddress 1.
0(2) Device does not respond to I2C bus subaddress 2.
2 SUB2 R/W 1 Device responds to I2C bus subaddress 2.
0(2) Device does not respond to I2C bus subaddress 3.
1 SUB3 R/W 1 Device responds to I2C bus subaddress 3.
0 Device does not respond to LED All Call I2C bus address.
0 ALLCALL R/W 1(2) Device responds to LED All Call I2C bus address.
(1) R = read, W = write
(2) Default value
(3) Requires 500 μs maximum for the oscillator to be up and running once OSC bit has been set to logic 1. Timings on LED outputs are not
ensured if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 500-μs window.
IMPORTANT NOTE: The OSC bit (Bit 4) must be set to 0 before any outputs will turn on. Proper operation
requires this bit to be 0. Setting the bit to a 1 will turn all channels off.
Mode Register 2 (MODE2)
Table 5 describes Mode Register 2.
Table 5. MODE2 –Mode Register 2 (Address 01h) Bit Description
BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
0(2) Enable error status flag
7 EFCLR R/W 1 Clear error status flag
6 R 0(2) Reserved
0(2) Group control = dimming
5 DMBLNK R/W 1 Group control = blinking
4 R 0(2) Reserved
0(2) Outputs change on Stop command(3)
3 OCH R/W 1 Outputs change on ACK
2:0 R 000(2) Reserved
(1) R = read, W = write
(2) Default value
(3) Change of the outputs at the Stop command allows synchronizing outputs of more than one TLC59116. Applicable to registers from 02h
(PWM0) to 17h (LEDOUT3) only.
Copyright ©2008–2011, Texas Instruments Incorporated 15
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
Brightness Control Registers 0 to 15 (PWM0 to PWM15)
Table 6 describes Brightness Control Registers 0 to 15.
Table 6. PWM0 to PWM15 –Brightness Control Registers 0 to 15 (Address 02h to 11h) Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000(2) PWM0 individual duty cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000(2) PWM1 individual duty cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000(2) PWM2 individual duty cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000(2) PWM3 individual duty cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000(2) PWM4 individual duty cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000(2) PWM5 individual duty cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000(2) PWM6 individual duty cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000(2) PWM7 individual duty cycle
0Ah PWM8 7:0 IDC8[7:0] R/W 0000 0000(2) PWM8 individual duty cycle
0Bh PWM9 7:0 IDC9[7:0] R/W 0000 0000(2) PWM9 individual duty cycle
0Ch PWM10 7:0 IDC10[7:0] R/W 0000 0000(2) PWM10 individual duty cycle
0Dh PWM11 7:0 IDC11[7:0] R/W 0000 0000(2) PWM11 individual duty cycle
0Eh PWM12 7:0 IDC12[7:0] R/W 0000 0000(2) PWM12 individual duty cycle
0Fh PWM13 7:0 IDC13[7:0] R/W 0000 0000(2) PWM13 individual duty cycle
10h PWM14 7:0 IDC14[7:0] R/W 0000 0000(2) PWM14 individual duty cycle
11h PWM15 7:0 IDC15[7:0] R/W 0000 0000(2) PWM15 individual duty cycle
(1) R = read, W = write
(2) Default value
A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
Duty cycle = IDCn[7:0] / 256
Group Duty Cycle Control Register (GRPPWM)
Table 7 describes the Group Duty Cycle Control Register.
Table 7. GRPPWM –Group Brightness Control Register (Address 12h) Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
12h GRPPWM 7:0 GDC0[7:0] R/W 1111 1111(2) GRPPWM register
(1) R = read, W = write
(2) Default value
When the DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed-frequency signal is
superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness
control, allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don't
care.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED
output off) to FFh (99.6% duty cycle = maximum brightness). This is applicable to LED outputs programmed with
LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
When DMBLNK bit is programmed with logic 1, the GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPFREQ defines the blinking period (from 24 Hz to 10.73 s) and GRPPWM defines the duty
cycle (ON/OFF ratio in %).
Duty cycle = GDC0[7:0] / 256
16 Copyright ©2008–2011, Texas Instruments Incorporated
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
Group Frequency Register (GRPFREQ)
Table 8 describes the Group Frequency Register.
Table 8. GRPFREQ –Group Frequency Register (Address 13h) Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
13h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000(2) GRPFREQ register
(1) R = read, W = write
(2) Default value
GRPFREQ is used to program the global blinking period when the DMBLNK bit (MODE2 register) is equal to 1.
Value in this register is a Don't care when DMBLNK = 0. This is applicable to LED output programmed with
LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
The blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).
Global blinking period (seconds) = (GFRQ[7:0] + 1) / 24
LED Driver Output State Registers 0 to 3 (LEDOUT0 to LEDOUT3)
Table 9 describes LED Driver Output State Registers 0 to 3.
Table 9. LEDOUT0 to LEDOUT3 –LED Driver Output State Registers 0 to 3 (Address 14h to 17h)
Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
7:6 LDR3[1:0] R/W 00(2) LED3 output state control
5:4 LDR2[1:0] R/W 00(2) LED2 output state control
14h LEDOUT0 3:2 LDR1[1:0] R/W 00(2) LED1 output state control
1:0 LDR0[1:0] R/W 00(2) LED0 output state control
7:6 LDR7[1:0] R/W 00(2) LED7 output state control
5:4 LDR6[1:0] R/W 00(2) LED6 output state control
15h LEDOUT1 3:2 LDR5[1:0] R/W 00(2) LED5 output state control
1:0 LDR4[1:0] R/W 00(2) LED4 output state control
7:6 LDR11[1:0] R/W 00(2) LED11 output state control
5:4 LDR10[1:0] R/W 00(2) LED10 output state control
16h LEDOUT2 3:2 LDR9[1:0] R/W 00(2) LED9 output state control
1:0 LDR8[1:0] R/W 00(2) LED8 output state control
7:6 LDR15[1:0] R/W 00(2) LED15 output state control
5:4 LDR14[1:0] R/W 00(2) LED14 output state control
17h LEDOUT3 3:2 LDR13[1:0] R/W 00(2) LED13 output state control
1:0 LDR12[1:0] R/W 00(2) LED12 output state control
(1) R = read, W = write
(2) Default value
LDRx = 00: LED driver x is off (default power-up state).
LDRx = 01: LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx = 10: LED driver x is individual brightness can be controlled through its PWMx register.
LDRx = 11: LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx
register and the GRPPWM registers.
Copyright ©2008–2011, Texas Instruments Incorporated 17
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3)
Table 10 describes I2C Bus Subaddress Registers 1 to 3.
Table 10. SUBADR1 to SUBADR3 –I2C Bus Subaddress Registers 1 to 3 (Address 18h to 1Ah)
Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
7:1 A1[7:1] R/W 1101 001(2) I2C bus subaddress 1
18h SUBADR1 0 A1[0] R 0(2) Reserved
7:1 A2[7:1] R/W 1101 010(2) I2C bus subaddress 2
19h SUBADR2 0 A2[0] R 0(2) Reserved
7:1 A3[7:1] R/W 1101 100(2) I2C bus subaddress 3
1Ah SUBADR3 0 A3[0] R 0(2) Reserved
(1) R = read, W = write
(2) Default value
Subaddresses are programmable through the I2C bus. Default power-up values are D2h, D4h, D8h. The
TLC59116 does not acknowledge these addresses immediately after power-up (the corresponding SUBx bit in
MODE1 register is equal to 0).
Once subaddresses have been programmed to valid values, the SUBx bits (MODE1 register) must be set to 1 to
allows the device to acknowledge these addresses.
Only the 7 MSBs representing the I2C bus subaddress are valid. The LSB in SUBADRx register is a read-only bit
(0).
When SUBx is set to 1, the corresponding I2C bus subaddress can be used during either an I2C bus read or write
sequence.
LED All Call I2C Bus Address Register (ALLCALLADR)
Table 11 describes the LED All Call I2C Bus Address Register.
Table 11. ALLCALLADR –LED All Call I2C Bus Address Register (Address 1Bh) Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
7:1 AC[7:1] R/W 1101 000(2) All Call I2C bus address
1Bh ALLCALLADR 0 AC[0] R 0(2) Reserved
(1) R = read, W = write
(2) Default value
The LED All Call I2C bus address allows all the TLC59116 devices in the bus to be programmed at the same
time (ALLCALL bit in register MODE1 must be equal to 1, which is the power-up default state). This address is
programmable through the I2C bus and can be used during either an I2C bus read or write sequence. The
register address can also be programmed as a Sub Call.
Only the seven MSBs representing the All Call I2C bus address are valid. The LSB in ALLCALLADR register is a
read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.
18 Copyright ©2008–2011, Texas Instruments Incorporated
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
Output Gain Control Register (IREF)
Table 12 describes the Output Gain Control Register.
Table 12. IREF –Output Gain Control Register (Address 1Ch) Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
7 CM R/W 1(2) High/low current multiplier
1Ch IREF 6 HC R/W 1(2) Subcurrent
5:0 CC[5:0] R/W 11 1111(2) Current multiplier
(1) R = read, W = write
(2) Default value
IREF determines the voltage gain (VG), which affects the voltage at the REXT terminal and indirectly the
reference current (Iref) flowing through the external resistor at terminal REXT. Bit 0 is the Current Multiplier (CM)
bit, which determines the ratio IOUT,target/Iref. Each combination of VG and CM sets a Current Gain (CG).
•VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown:
VG = (1 + HC) ×(1 + D/64) / 4
D = CC0 ×25+ CC1 ×24+ CC2 ×23+ CC3 ×22+ CC4 ×21+ CC5 ×20
Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point
number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage
gain (VG) into 128 steps and two sub-bands:
Low-voltage subband (HC = 0): VG = 1/4 to 127/256, linearly divided into 64 steps
High-voltage subband (HC = 1): VG = 1/2 to 127/128, linearly divided into 64 steps
•CM: In addition to determining the ratio IOUT,target/Iref, CM limits the output current range.
High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA.
Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA
•CG: The total Current Gain is defined as:
VREXT = 1.26 V ×VG
Iref = VREXT/Rext, if the external resistor (Rext) is connected to ground.
IOUT,target = Iref ×15 ×3CM –1= 1.26 V/Rext ×VG ×15 ×3CM –1= (1.26 V/Rext ×15) ×CG
CG = VG ×3CM –1
Therefore, CG = (1/12) to (127/128), divided into 256 steps.
Examples
•IREF Code {CM, HC, CC[0:5]} = {1,1,111111}
VG = 127/128 = 0.992 and CG = VG ×30= VG = 0.992
•IREF Code {CM, HC, CC[0:5]} = {1,1,000000}
VG = (1 + 1) ×(1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5
•IREF Code {CM, HC, CC[0:5]} = {0,0,000000}
VG = (1 + 0) ×(1 + 0/64)/4 = 1/4, and CG = (1/4) ×3–1= 1/12
After power on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore,
VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 11.
Copyright ©2008–2011, Texas Instruments Incorporated 19
1.00
0.00
0.50
0.25
0.75
Configuration Code (CM, HC, CC[0:5]) in Binary Format
Current Gain (CG)
{0,0,000000}
{0,0,010000}
{0,0,100000}
{0,0,110000}
{0,1,000000}
{0,1,010000}
{0,1,100000}
{0,1,110000}
{1,0,000000}
{1,0,010000}
{1,0,100000}
{1,0,110000}
{1,1,100000}
{1,1,110000}
{1,1,000000}
{1,1,010000}
CM = 0 (Low Current Multiplier)
HC = 1 (High
Voltage SubBand)
HC = 0 (Low
Voltage SubBand) HC = 1 (High
Voltage SubBand)
CM = 1 (High Current Multiplier)
HC = 0 (Low
Voltage SubBand)
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
Figure 11. Current Gain vs Configuration Code
Error Flags Registers (EFLAG1, EFLAG2)
Table 13 describes Error Flags Registers 1 and 2.
Table 13. EFLAG1, EFLAG2 –Error Flags Registers (Address 1Dh and 1Eh) Bit Description
ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE(2) DESCRIPTION(3)
0 EFLAG1[0] 0 A 1 indicates an error - Channel 0
1 EFLAG1[1] 0 A 1 indicates an error - Channel 1
2 EFLAG1[2] 0 A 1 indicates an error - Channel 2
3 EFLAG1[3] 0 A 1 indicates an error - Channel 3
1Dh EFLAG1 R
4 EFLAG1[4] 0 A 1 indicates an error - Channel 4
5 EFLAG1[5] 0 A 1 indicates an error - Channel 5
6 EFLAG1[6] 0 A 1 indicates an error - Channel 6
7 EFLAG1[7] 0 A 1 indicates an error - Channel 7
0 EFLAG1[0] 0 A 1 indicates an error - Channel 8
1 EFLAG1[1] 0 A 1 indicates an error - Channel 9
2 EFLAG1[2] 0 A 1 indicates an error - Channel 10
3 EFLAG1[3] 0 A 1 indicates an error - Channel 11
1Eh EFLAG2 R
4 EFLAG1[4] 0 A 1 indicates an error - Channel 12
5 EFLAG1[5] 0 A 1 indicates an error - Channel 13
6 EFLAG1[6] 0 A 1 indicates an error - Channel 14
7 EFLAG1[7] 0 A 1 indicates an error - Channel 15
(1) R = read, W = write
(2) Default value
(3) At power up, in order to initialize the Error Flags registers, the host must write 1 to bit 7 of the MODE2 register and then write 0 to bit 7
of the MODE2 register.
Open-Circuit Detection
The TLC59116 LED open-circuit detection compares the effective current level IOUT with the open load detection
threshold current IOUT,Th. If IOUT is below the threshold IOUT,Th the TLC59116 detects an open load condition. This
error status can be read out as an error flag through the registers EFLAG1 and EFLAG2.
20 Copyright ©2008–2011, Texas Instruments Incorporated
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
For open-circuit error detection, a channel must be on and the PWM must be off.
Table 14. Open-Circuit Detection
CONDITION OF OUTPUT
STATE OF OUTPUT PORT ERROR STATUS CODE MEANING
CURRENT
Off IOUT = 0 mA 0 Detection not possible
IOUT <IOUT,Th (1) 0 Open circuit
On IOUT ≥IOUT,Th (1) Channel n error status bit 1 Normal
(1) IOUT,Th = 0.5 ×IOUT,target (typical)
Overtemperature Detection and Shutdown
The TLC59116 LED is equipped with a global overtemperature sensor and 16 individual channel-selective
overtemperature sensors.
•When the global sensor reaches the trip temperature, all output channels are shut down, and the error status
is stored in the internal Error Status register of every channel. After shutdown, the channels automatically
restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset
after cooling down and can be read out as the error status code in registers EFLAG1 and EFLAG2.
•When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut
down, and the error status is stored only in the internal Error Status register of the affected channel. After
shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains
on. The stored error status is not reset after cooling down and can be read out as error status code in
registers EFLAG1 and EFLAG2.
For channel-specific overtemperature error detection, a channel must be on.
The error flags of open-circuit and overtemperature are ORed to set the EFLAG1 and EFLAG2 registers.
The error status code due to overtemperature is reset when the host writes 1 to bit 7 of the MODE2 register. The
host must write 0 to bit 7 of the MODE2 register to enable the overtemperature error flag.
Table 15. Overtemperature Detection(1)
STATE OF OUTPUT PORT CONDITION ERROR STATUS CODE MEANING
Tj<Tj,trip global 1 Normal
On
On →all channels Off Tj>Tj,trip global All error status bits = 0 Global overtemperature
Tj<Tj,trip channel n 1 Normal
On
On →Off Tj>Tj,trip channel n Channel n error status bit = 0 Channel n overtemperature
(1) The global shutdown threshold temperature is approximately 170°C.
Power-On Reset (POR)
When power is applied to VCC, an internal power-on reset holds the TLC59116 in a reset condition until VCC
reaches VPOR. At this point, the reset condition is released and the TLC59116 registers, and I2C bus state
machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter,
VCC must be lowered below 0.2 V to reset the device.
External Reset
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59116 registers and
I2C state machine are held in their default states until the RESET input is again high.
This input requires a pullup resistor to VCC if no active connection is used.
Copyright ©2008–2011, Texas Instruments Incorporated 21
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
Software Reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C bus to be reset to the power-up state
value through a specific I2C bus command.
The SWRST Call function is defined as the following:
1. A Start command is sent by the I2C bus master.
2. The reserved SWRST I2C bus address 1101 011 with the R/W bit set to 0 (write) is sent by the I2C bus
master.
3. The TLC59116 device(s) acknowledge(s) after seeing the SWRST Call address 1101 0110 (D6h) only. If the
R/W bit is set to 1 (read), no acknowledge is returned to the I2C bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two
specific values (SWRST data byte 1 and byte 2):
(a) Byte1 = A5h: the TLC59116 acknowledges this value only. If byte 1 is not equal to A5h, the TLC59116
does not acknowledge it.
(b) Byte 2 = 5Ah: the TLC59116 acknowledges this value only. If byte 2 is not equal to 5Ah, the TLC59116
does not acknowledge it.
If more than two bytes of data are sent, the TLC59116 does not acknowledge any more.
5. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly
acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59116 then resets to
the default value (power-up value) and is ready to be addressed again within the specified bus free time
(tBUF).
The I2C bus master may interpret a non-acknowledge from the TLC59116 (at any time) as a SWRST Call Abort.
The TLC59116 does not initiate a reset of its registers. This happens only when the format of the Start Call
sequence is not correct.
Individual Brightness Control With Group Dimming/Blinking
A 97-kHz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control the individual
brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be applied to the four
LED outputs):
•A lower 190-Hz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) provides a global
brightness control.
•A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) provides a global blinking
control.
22 Copyright ©2008–2011, Texas Instruments Incorporated
N × 40 ns
with N = 0 to 255
(PWM register)
256 × 40 ns = 10.24 µs
(97.6 kHz)
M × 256 × 2 × 40 ns
with M = 0 to 255
(GRPPWM register)
Group Dimming Signal
507
1
2
3
4
5
6
7
8
9
10
11
12
508
509
510
511
512
1
2
3
4
5
6
7
8
9
10
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
Resulting Brightness + Group Dimming Signal
1
2
3
4
5
6
7
8
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
NOTE: Minimum pulse width for LEDn brightness control is 40 ns.
Minimum pulse width for group dimming is 20.48 μs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has two
pulses of the LED Brightness Control signal (pulse width = n ×40 ns, with n defined in the PWMx register).
This resulting Brightness + Group Dimming signal shows a resulting control signal with M = 4 (8 pulses).
Figure 12. Brightness and Group Dimming Signals
Characteristics of the I2C Bus
The I2C bus is for two-way two-line communication between different devices or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a
pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see
Figure 13).
Figure 13. Bit Transfer
Copyright ©2008–2011, Texas Instruments Incorporated 23
SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Slave
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I C Bus
Multiplexer
2
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
Start and Stop Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the Stop condition (P) (see Figure 14).
Figure 14. Start and Stop Conditions
System Configuration
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master and the devices that are controlled by the master are the slaves (see Figure 15).
Figure 15. System Configuration
Acknowledge
The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on
the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver that is addressed must generate an acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable low during the high period of the acknowledge related clock pulse; setup time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable
the master to generate a Stop condition.
24 Copyright ©2008–2011, Texas Instruments Incorporated
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
Start Condition R/W
Auto-Increment Flag
ACK From Slave ACK From Slave
D0
A2
11
SA30 A1 A0 0AD1D2D3
D4
XX
XA A P
Control RegisterSlave Address
Stop Condition
ACK From Slave
Auto-Increment Options
Start Condition R/W
Auto-Increment On
ACK From Slave ACK From Slave
0
A2
11
SA30 A1 A0 0A000
0
00
1A A
MODE1 RegisterControl RegisterSlave Address
ACK From Slave
Auto-Increment On All Registers (see Note A)
ACK From Slave
A P
ALLCALLADR Register
Stop Condition
A
SUBADR3 Register
ACK From Slave
A
MODE2 Register
MODE1 Register Selection
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
Figure 16. Acknowledge/Not Acknowledge on I2C Bus
Figure 17. Write to a Specific Register
A. See Table 3 for register definitions.
Figure 18. Write to All Registers Using Auto-Increment
Copyright ©2008–2011, Texas Instruments Incorporated 25
Start Condition R/W
Auto-Increment On
ACK From Slave ACK From Slave
0
A2
A6 A5
SA3A4 A1 A0 0A100
0
1
0
1A A
PWM0 RegisterControl RegisterSlave Address
ACK From Slave
Auto-Increment On Brightness Registers Only
ACK From Slave
A P
PWM15 Register
Stop Condition
A
PWM14 Register
ACK From Slave
A
PWM1 Register
PWM0 Register Selection
ACK From Slave
A
PWM0 Register
ACK From Slave
A
PWMx Register
Start Condition R/W
Auto-Increment On
ACK From Slave ACK From Slave
0
A2
A6 A5
SA3
A4 A1 A0 0A000000
1A A
Slave AddressControl RegisterSlave Address
ACK From Slave
Auto-Increment On All Registers
ACK From Master
A
Data From PWM0 Register
A
Data From MODE2 Register
ACK From Master
A
Data From MODE1 Register
MODE1 Register Selection
ACK From Master
A
Data From ALLCALLADR Register
P
Stop Condition
NACK From Master
A
Data From Last Read Byte
A2
A6 A5 A3
A4 A1 A0
R/W
1
ACK From Master
A
Data From MODE1 Register
Sr
ACK From Master
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
Figure 19. Multiple Writes to Individual Brightness Registers Using Auto-Increment
Figure 20. Read All Registers Auto-Increment
26 Copyright ©2008–2011, Texas Instruments Incorporated
Start Condition R/W ACK From the
Four Slaves
ACK From the
Four Slaves
0
1
11
S10 010A010
1
XX
XA A P
Control RegisterLED All Call I C Address
2
Stop Condition
ACK From Slave
Start Condition R/W
Auto-Increment Flag
ACK From Slave ACK From Slave
1
A2
A6 A5
SA3
A4 A1 A0 0A1
0
11
XXX A A P
Control RegisterSlave Address
Stop Condition
ACK From Slave
Auto-Increment Options
Sequence A
Sequence B
ALLCALLADR Register Selection
New LED All Call I C Address
(see Note B)
2
X
1
0
11
0
11
LEDOUT0 Register Selection
0
0110 101
The 16 LEDs are on at ACK (see Note C)
LEDOUT0 Register (LED3 to 0 Fully On)
TLC59116
www.ti.com
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
A. In this example, several TLC59116 devices are used, and the same Sequence A is sent to each of them.
B. The ALLCALL bit in the MODE1 register is equal to 1 for this example.
C. The OCH bit in the MODE2 register is equal to 1 for this example.
Figure 21. LED All Call I2C Bus Address Programming and LED All Call Sequence
Copyright ©2008–2011, Texas Instruments Incorporated 27
TLC59116
SLDS157D –FEBRUARY 2008–REVISED JULY 2011
www.ti.com
REVISION HISTORY
Changes from Revision C (June 2010) to Revision D Page
•Added Output Current vs Output Voltage Figure. ............................................................................................................... 13
•Changed "SLEEP"to "OSC"in Mode Register 1 (MODE1) Table. .................................................................................... 15
•Added Bits 6 and 4 to the Mode Register 2 Bit Description Table. .................................................................................... 15
•Changed VALUES column in the Mode Register 2 Bit Description Table. ........................................................................ 15
28 Copyright ©2008–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 26-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC59116IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC59116IPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC59116IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC59116IPWR TSSOP PW 28 2000 330.0 16.4 7.1 10.4 1.6 12.0 16.0 Q1
TLC59116IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC59116IPWR TSSOP PW 28 2000 367.0 367.0 38.0
TLC59116IRHBR QFN RHB 32 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
