74AC74MTCX - Fairchild Semiconductor

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

74AC74, 74ACT74 Rev. 1.6.1

January 2008

74AC74, 74ACT74

Dual D-Type Positive Edge-Triggered Flip-Flop

Features

■

reduced by 50%

■

Output source/sink 24mA

■

ACT74 has TTL-compatible inputs

General Description

The AC/ACT74 is a dual D-type flip-flop with Asynchro-

nous Clear and Set inputs and complementary (Q, Q)

outputs. Information at the input is transferred to the out-

puts on the positive edge of the clock pulse. Clock trig-

gering occurs at a voltage level of the clock pulse and is

not directly related to the transition time of the positive-

going pulse. After the Clock Pulse input threshold volt-

age has been passed, the Data input is locked out and

information present will not be transferred to the outputs

until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:

■

LOW input to S

(Set) sets Q to HIGH level

■

LOW input to C

(Clear) sets Q to LOW level

■

Clear and Set are independent of clock

■

Simultaneous LOW on C

and S

makes both Q and

Q HIGH

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74AC74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74ACT74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74AC74, 74ACT74 Rev. 1.6.1 2

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

Connection Diagram

Pin Descriptions

Logic Symbols

IEEE/IEC

Truth Table

(Each Half)

HIGH Voltage Level

LOW Voltage Level

Immaterial

LOW-to-HIGH Clock Transition

)

Previous Q (Q) before LOW-to-HIGH Transition of Clock

Pin Names Description

, D

Data Inputs

, CP

Clock Pulse Inputs

, C

Direct Clear Inputs

, S

Direct Set Inputs

, Q

Outputs

Inputs Outputs

CP D Q Q

LHXXHL

HLXXLH

LLXXHH

HH HHL

HH LLH

HHLXQ

74AC74, 74ACT74 Rev. 1.6.1 3

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

74AC74, 74ACT74 Rev. 1.6.1 4

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

Supply Voltage –0.5V to +7.0V

DC Input Diode Current

–0.5V –20mA

+ 0.5 +20mA

DC Input Voltage –0.5V to V

+ 0.5V

DC Output Diode Current

–0.5V –20mA

+ 0.5V +20mA

DC Output Voltage –0.5V to V

+ 0.5V

DC Output Source or Sink Current ±50mA

or I

GND

DC V

or Ground Current per Output Pin ±50mA

STG

Storage Temperature –65°C to +150°C

Junction Temperature 140°C

Symbol Parameter Rating

Supply Voltage

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage 0V to V

Output Voltage 0V to V

Operating Temperature –40°C to +85°C

∆

t Minimum Input Edge Rate, AC Devices:

from 30% to 70% of V

@ 3.3V, 4.5V, 5.5V

125mV/ns

∆

t Minimum Input Edge Rate, ACT Devices:

from 0.8V to 2.0V, V

@ 4.5V, 5.5V

125mV/ns

74AC74, 74ACT74 Rev. 1.6.1 5

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

DC Electrical Characteristics for AC

Notes:

1. All outputs loaded; thresholds on input associated with output under test.

2. Maximum test duration 2.0ms, one output loaded at a time.

3. I

and I

@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V

Symbol Parameter

(V) Conditions

+25°C T

–40°C to +85°C

UnitsTyp. Guaranteed Limits

Minimum HIGH Level

Input Voltage

3.0 V

OUT

0.1V or

– 0.1V

1.5 2.1 2.1 V

4.5 2.25 3.15 3.15

5.5 2.75 3.85 3.85

Maximum LOW Level

Input Voltage

3.0 V

OUT

0.1V or

– 0.1V

1.5 0.9 0.9 V

4.5 2.25 1.35 1.35

5.5 2.75 1.65 1.65

Minimum HIGH Level

Output Voltage

3.0 I

OUT

–50µA 2.99 2.9 2.9 V

4.5 4.49 4.4 4.4

5.5 5.49 5.4 5.4

3.0 V

or V

–12mA

2.56 2.46

4.5 V

or V

–24mA

3.86 3.76

5.5 V

or V

IOH = –24mA(1)

4.86 4.76

VOL Maximum LOW Level

Output Voltage

3.0 IOUT = 50µA 0.002 0.1 0.1 V

4.5 0.001 0.1 0.1

5.5 0.001 0.1 0.1

3.0 VIN = VIL or VIH,

IOL = 12mA

0.36 0.44

4.5 VIN = VIL or VIH,

IOL = 24mA

0.36 0.44

5.5 VIN = VIL or VIH,

IOL = 24mA(1)

0.36 0.44

IIN(3) Maximum Input

Leakage Current

5.5 VI = VCC, GND ±0.1 ±1.0 µA

IOLD Minimum Dynamic

Output Current(2) 5.5 VOLD = 1.65V Max. 75 mA

IOHD 5.5 VOHD = 3.85V Min. –75 mA

ICC(3) Maximum Quiescent

Supply Current

5.5 VIN = VCC or GND 2.0 20.0 µA

74AC74, 74ACT74 Rev. 1.6.1 6

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

DC Electrical Characteristics for ACT

Notes:

4. All outputs loaded; thresholds on input associated with output under test.

Symbol Parameter

VCC

(V) Conditions

TA = +25°C TA = –40°C to +85°C

UnitsTyp. Guaranteed Limits

VIH Minimum HIGH Level

Input Voltage

4.5 VOUT = 0.1V or

VCC – 0.1V

1.5 2.0 2.0 V

5.5 1.5 2.0 2.0

VIL Maximum LOW Level

Input Voltage

4.5 VOUT = 0.1V or

VCC – 0.1V

1.5 0.8 0.8 V

5.5 1.5 0.8 0.8

VOH Minimum HIGH Level

Output Voltage

4.5 IOUT = –50µA 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4

4.5 VIN = VIL or VIH,

IOH = –24mA

3.86 3.76

5.5 VIN = VIL or VIH,

IOH = –24mA(4)

4.86 4.76

VOL Maximum LOW Level

Output Voltage

4.5 IOUT = 50µA 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1

4.5 VIN = VIL or VIH,

IOL = 24mA

0.36 0.44

5.5 VIN = VIL or VIH,

IOL= 24mA(4)

0.36 0.44

IIN Maximum Input

Leakage Current

5.5 VI = VCC, GND ±0.1 ±1.0 µA

ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V 0.6 1.5 mA

IOLD Minimum Dynamic

Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA

IOHD 5.5 VOHD = 3.85V Min. –75 mA

ICC Maximum Quiescent

Supply Current

5.5 VIN = VCC or GND 2.0 20.0 µA

74AC74, 74ACT74 Rev. 1.6.1 7

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

AC Electrical Characteristics for AC

Note:

5. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.

AC Operating Requirements for AC

Note:

6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.

Symbol Parameter VCC (V)(6)

TA = +25°C,

CL = 50pF

TA = –40°C to +85°C,

CL = 50pF

UnitsMin. Typ. Max. Min. Max.

fMAX Maximum Clock Frequency 3.3 100 125 95 MHz

5.0 140 160 125

tPLH Propagation Delay,

CDn or SDn to Qn or Qn

3.3 3.5 8.0 12.0 2.5 13.0 ns

5.0 2.5 6.0 9.0 2.0 10.0

tPHL Propagation Delay,

CDn or SDn to Qn or Qn

3.3 4.0 10.5 12.0 3.5 13.5 ns

5.0 3.0 8.0 9.5 2.5 10.5

tPLH Propagation Delay,

CPn to Qn or Qn

3.3 4.5 8.0 13.5 4.0 16.0 ns

5.0 3.5 6.0 10.0 3.0 10.5

tPHL Propagation Delay,

CPn to Qn or Qn

3.3 3.5 8.0 14.0 3.5 14.5 ns

5.0 2.5 6.0 10.0 2.5 10.5

Symbol Parameter VCC (V)(7)

TA = +25°C,

CL = 50pF

TA = –40°C to +85°C,

CL = 50 pF

UnitsTyp. Guaranteed Minimum

tSSet-up Time, HIGH or LOW,

Dn to CPn

3.3 1.5 4.0 4.5 ns

5.0 1.0 3.0 3.0

tHHold Time, HIGH or LOW,

Dn to CPn

3.3 –2.0 0.5 0.5 ns

5.0 –1.5 0.5 0.5

tWCPn or CDn or SDn Pulse Width 3.3 3.0 5.5 7.0 ns

5.0 2.5 4.5 5.0

trec Recovery Time, CDn or SDn to CP 3.3 –2.5 0 0 ns

5.0 –2.0 0 0

74AC74, 74ACT74 Rev. 1.6.1 8

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

AC Electrical Characteristics for ACT

Note:

7. Voltage range 5.0 is 5.0V ± 0.5V.

AC Operating Requirements for ACT

Note:

8. Voltage range 5.0 is 5.0V ± 0.5V.

Capacitance

Symbol Parameter VCC (V)(8)

TA = +25°C,

CL = 50pF

TA = –40°C to +85°C,

CL = 50pF

UnitsMin. Typ. Max. Min. Max.

fMAX Maximum Clock Frequency 5.0 145 210 125 MHz

tPLH Propagation Delay,

CDn or SDn to Qn or Qn

5.0 3.0 5.5 9.5 2.5 10.5 ns

tPHL Propagation Delay,

CDn or SDn to Qn or Qn

5.0 3.0 6.0 10.0 3.0 11.5 ns

tPLH Propagation Delay,

CPn to Qn or Qn

5.0 4.0 7.5 11.0 4.0 13.0. ns

tPHL Propagation Delay,

CPn to Qn or Qn

5.0 3.5 6.0 10.0 3.0 11.5 ns

Symbol Parameter VCC (V)(9)

TA = +25°C,

CL = 50pF

TA = –40°C to +85°C,

CL = 50pF

UnitsTyp. Guaranteed Minimum

tSSet-up Time, HIGH or LOW,

Dn to CPn

5.0 1.0 3.0 3.5 ns

tHHold Time, HIGH or LOW,

Dn to CPn

5.0 –0.5 1.0 1.0 ns

tWCPn or CDn or SDn Pulse Width 5.0 3.0 5.0 6.0 ns

trec Recovery Time, CDn or SDn to CP 5.0 –2.5 0 0 ns

Symbol Parameter Conditions Typ. Units

CIN Input Capacitance VCC = OPEN 4.5 pF

CPD Power Dissipation Capacitance VCC = 5.0V 35.0 pF

74AC74, 74ACT74 Rev. 1.6.1 9

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

Physical Dimensions

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X45°

0.10

BC A

14 B

SEE DETAIL A

5.60

0.65

1.70 1.27

8.75

8.50

7.62

6.00 4.00

3.80

(0.33)

1.27 0.51

0.35

1.75 MAX

1.50

1.25 0.25

0.10 0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

0.50

0.25

74AC74, 74ACT74 Rev. 1.6.1 10

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

Physical Dimensions (Continued)

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74AC74, 74ACT74 Rev. 1.6.1 11

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

Physical Dimensions (Continued)

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

F. DRAWING FILE NAME: MTC14REV6

R0.09 min

12.00°TOP & BOTTO

0.43 TYP

1.00

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

R0.09min

E. LANDPATTERN STANDARD: SOP65P640X110-14M

0.65

6.10

1.65

0.45

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS

74AC74, 74ACT74 Rev. 1.6.1 12

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop

Physical Dimensions (Continued)

Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

14 8

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANCES PER

ASME Y14.5-1994

E) DRAWING FILE NAME: MKT-N14AREV7

6.60

6.09

8.12

7.62

0.35

0.20

19.56

18.80

3.56

3.30 5.33 MAX

0.38 MIN

1.77

1.14

0.58

0.35 2.54

3.81

3.17 8.82

(1.74)

74AC74, 74ACT74 Rev. 1.6.1 13

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Thefollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx®

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK®

EZSWITCH™ *

™

Fairchild®

Fairchild Semiconductor®

FACT Quiet Series™

FACT®

FAST®

FastvCore™

FlashWriter®*

FPS™

FRFET®

Global Power ResourceSM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC®

OPTOPLANAR®

PDP-SPM™

Power220®

Power247®

POWEREDGE®

Power-SPM™

PowerTrench®

Programmable Active Droop™

QFET®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™®

The Power Franchise®

TinyBoost™

TinyBuck™

TinyLogic®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC®

Ultra FRFET™

UniFET™

VCX™

*EZSWITCH™ and FlashWriter®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

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WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Form

First Production

ative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

Obsolete Not In Production

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I32

74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop