74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Features General Description ICC reduced by 50% The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positivegoing pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Output source/sink 24mA ACT74 has TTL-compatible inputs Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Information Order Number 74AC74SC 74AC74SJ 74AC74MTC 74AC74PC Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT74MTC 74ACT74PC MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop January 2008 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names Description D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs Truth Table (Each Half) Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H X Q0 Q0 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 3 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop Logic Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Parameter Rating Supply Voltage -0.5V to +7.0V DC Input Diode Current VI = -0.5V -20mA VI = VCC + 0.5 +20mA VI DC Input Voltage -0.5V to VCC + 0.5V IOK DC Output Diode Current VO = -0.5V -20mA VO = VCC + 0.5V +20mA VO DC Output Voltage -0.5V to VCC + 0.5V IO DC Output Source or Sink Current 50mA ICC or IGND DC VCC or Ground Current per Output Pin TSTG Storage Temperature TJ 50mA -65C to +150C Junction Temperature 140C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Supply Voltage AC 2.0V to 6.0V ACT 4.5V to 5.5V VI Input Voltage VO Output Voltage TA Operating Temperature V / t Rating 0V to VCC 0V to VCC -40C to +85C Minimum Input Edge Rate, AC Devices: 125mV/ns VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V V / t 125mV/ns Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 4 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop Absolute Maximum Ratings Symbol VIH Parameter VCC (V) Minimum HIGH Level Input Voltage 3.0 Maximum LOW Level Input Voltage 3.0 Minimum HIGH Level Output Voltage 3.0 TA = +25C Conditions VOUT = 0.1V or VCC - 0.1V 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 2.56 2.46 3.86 3.76 4.86 4.76 4.5 4.5 VOUT = 0.1V or VCC - 0.1V 5.5 VOH Guaranteed Limits 1.5 5.5 VIL Typ. TA = -40C to +85C 3.0 IOUT = -50A VIN = VIL or VIH, Units V V V IOH = -12mA 4.5 VIN = VIL or VIH, IOH = -24mA 5.5 VIN = VIL or VIH, IOH = VOL Maximum LOW Level Output Voltage 3.0 -24mA(1) IOUT = 50A 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 0.36 0.44 0.36 0.44 0.36 0.44 0.1 1.0 A 3.0 VIN = VIL or VIH, V IOL = 12mA 4.5 VIN = VIL or VIH, IOL = 24mA 5.5 VIN = VIL or VIH, IOL = 24mA(1) IIN(3) Maximum Input Leakage Current 5.5 VI = VCC, GND IOLD Minimum Dynamic Output Current(2) 5.5 VOLD = 1.65V Max. 75 mA 5.5 VOHD = 3.85V Min. -75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 20.0 A IOHD ICC (3) 2.0 Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 5 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter VCC (V) Conditions Typ. TA = -40C to +85C Guaranteed Limits VOUT = 0.1V or VCC - 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC - 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = -50A 4.49 4.4 4.4 Minimum HIGH Level Input Voltage 5.5 Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage TA = +25C 4.5 4.5 5.5 4.5 5.49 VIN = VIL or VIH, 5.4 5.4 3.86 3.76 4.86 4.76 0.1 0.1 Units V V V IOH = -24mA 5.5 VIN = VIL or VIH, IOH = -24mA(4) VOL Maximum LOW Level Output Voltage 4.5 IOUT = 50A 0.001 5.5 4.5 0.001 VIN = VIL or VIH, 0.1 0.1 0.36 0.44 0.36 0.44 0.1 1.0 V IOL = 24mA 5.5 VIN = VIL or VIH, IOL= 24mA(4) IIN Maximum Input Leakage Current 5.5 VI = VCC, GND A ICCT Maximum ICC/Input 5.5 VI = VCC - 2.1V 1.5 mA IOLD Minimum Dynamic Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA 5.5 VOHD = 3.85V Min. -75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 20.0 A IOHD ICC 0.6 2.0 Notes: 4. All outputs loaded; thresholds on input associated with output under test. (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 6 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop DC Electrical Characteristics for ACT TA = +25C, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL TA = -40C to +85C, CL = 50pF VCC (V)(6) Min. Typ. 3.3 100 125 95 5.0 140 160 125 Propagation Delay, CDn or SDn to Qn or Qn 3.3 3.5 8.0 12.0 2.5 13.0 5.0 2.5 6.0 9.0 2.0 10.0 Propagation Delay, CDn or SDn to Qn or Qn 3.3 4.0 10.5 12.0 3.5 13.5 5.0 3.0 8.0 9.5 2.5 10.5 Propagation Delay, CPn to Qn or Qn 3.3 4.5 8.0 13.5 4.0 16.0 5.0 3.5 6.0 10.0 3.0 10.5 Propagation Delay, CPn to Qn or Qn 3.3 3.5 8.0 14.0 3.5 14.5 5.0 2.5 6.0 10.0 2.5 10.5 Parameter Maximum Clock Frequency Max. Min. Max. Units MHz ns ns ns ns Note: 5. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V. AC Operating Requirements for AC TA = +25C, CL = 50pF Symbol Parameter TA = -40C to +85C, CL = 50 pF VCC (V)(7) Typ. 1.5 4.0 4.5 Guaranteed Minimum tS Set-up Time, HIGH or LOW, Dn to CPn 3.3 5.0 1.0 3.0 3.0 tH Hold Time, HIGH or LOW, Dn to CPn 3.3 -2.0 0.5 0.5 5.0 -1.5 0.5 0.5 tW CPn or CDn or SDn Pulse Width 3.3 3.0 5.5 7.0 5.0 2.5 4.5 5.0 trec Recovery Time, CDn or SDn to CP 3.3 -2.5 0 0 5.0 -2.0 0 0 Units ns ns ns ns Note: 6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V. (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 7 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop AC Electrical Characteristics for AC TA = +25C, CL = 50pF Symbol Parameter VCC (V)(8) Min. Typ. TA = -40C to +85C, CL = 50pF Max. Min. Max. 125 Units fMAX Maximum Clock Frequency 5.0 145 210 MHz tPLH Propagation Delay, CDn or SDn to Qn or Qn 5.0 3.0 5.5 9.5 2.5 10.5 ns tPHL Propagation Delay, CDn or SDn to Qn or Qn 5.0 3.0 6.0 10.0 3.0 11.5 ns tPLH Propagation Delay, CPn to Qn or Qn 5.0 4.0 7.5 11.0 4.0 13.0. ns tPHL Propagation Delay, CPn to Qn or Qn 5.0 3.5 6.0 10.0 3.0 11.5 ns Note: 7. Voltage range 5.0 is 5.0V 0.5V. AC Operating Requirements for ACT TA = +25C, CL = 50pF Symbol Parameter VCC (V)(9) Typ. TA = -40C to +85C, CL = 50pF Guaranteed Minimum Units tS Set-up Time, HIGH or LOW, Dn to CPn 5.0 1.0 3.0 3.5 ns tH Hold Time, HIGH or LOW, Dn to CPn 5.0 -0.5 1.0 1.0 ns tW CPn or CDn or SDn Pulse Width 5.0 3.0 5.0 6.0 ns trec Recovery Time, CDn or SDn to CP 5.0 -2.5 0 0 ns Note: 8. Voltage range 5.0 is 5.0V 0.5V. Capacitance Symbol Parameter Conditions Typ. Units CIN Input Capacitance VCC = OPEN 4.5 pF CPD Power Dissipation Capacitance VCC = 5.0V 35.0 pF (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 8 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop AC Electrical Characteristics for ACT 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45 0.25 R0.10 R0.10 8 0 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 9 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 10 0.65 0.43 TYP 1.65 6.10 0.45 12.00 TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 11 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 12 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM PDP-SPMTM SyncFETTM (R) Power220(R) (R) Power247 The Power Franchise(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) TinyBoostTM Programmable Active DroopTM TinyBuckTM (R) QFET TinyLogic(R) QSTM TINYOPTOTM QT OptoelectronicsTM TinyPowerTM (R) Quiet SeriesTM TinyPWMTM RapidConfigureTM TinyWireTM Fairchild(R) SMART STARTTM Fairchild Semiconductor(R) SerDesTM (R) SPM FACT Quiet SeriesTM UHC(R) STEALTHTM FACT(R) Ultra FRFETTM SuperFETTM FAST(R) UniFETTM SuperSOTTM-3 FastvCoreTM VCXTM (R) (R)* SuperSOTTM-6 FlashWriter SuperSOTTM-8 * EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTM e-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 (c)1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Rev. 1.6.1 www.fairchildsemi.com 13 74AC74, 74ACT74 -- Dual D-Type Positive Edge-Triggered Flip-Flop TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.