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FEATURES DESCRIPTION
APPLICATIONS
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
14-Bit, 125Msps ANALOG-TO-DIGITAL CONVERTER
14-Bit Resolution
The ADS5500 is a high-performance, 14-bit, 125Msps analog-to-digital converter (ADC). To provide a125 Msps Sample Rate
complete converter solution, it includes aHigh SNR: 71.2 dBFS at 100-MHz f
IN
high-bandwidth linear sample-and-hold stage (S&H)High SFDR: 82 dBc at 100-MHz f
IN
and internal reference. Designed for applications2.3-V
PP
Differential Input Voltage demanding the highest speed and highest dynamicperformance in little space, the ADS5500 hasInternal Voltage Reference
excellent power consumption of 578 mW at 3.3-V3.3-V Single-Supply Voltage
single-supply voltage. This allows an even higherAnalog Power Dissipation: 578 mW
system integration density. The provided internalreference simplifies system design requirements.Serial Programming Interface
Parallel CMOS-compatible output ensures seamlessTQFP-64 PowerPAD™ Package
interfacing with common logic.Recommended Amplifiers:
The ADS5500 is available in a 64-pin TQFPOPA695, OPA847, THS3201, THS3202,
PowerPAD™ package and in both a commercial andTHS4503, THS4509, THS9001
industrial temperature grade device.
ADS5500 PRODUCT FAMILYWireless Communication
80 Msps 105 Msps 125 Msps Communication Receivers
12 Bit ADS5522 ADS5521 ADS5520 Base Station Infrastructure
14 Bit ADS5542 ADS5541 ADS5500Test and Measurement InstrumentationSingle and Multichannel Digital ReceiversCommunication Instrumentation Radar, InfraredVideo and ImagingMedical Equipment
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
PACKAGE/ORDERING INFORMATION
(1)
SPECIFIED TRANSPORT MEDIA,PACKAGE PACKAGE ORDERINGPRODUCT PACKAGE LEAD TEMPERATURE QUANTITYDESIGNATOR MARKING NUMBERRANGE
ADS5500IPAP Tray, 160–40 °C to 85 °C ADS5500I
ADS5500IPAPR Tape and Reel, 1000RHTQFP-64
(2)ADS5500 PAPPowerPAD
ADS5500CPAP Tray, 1600°C to 70 °C ADS5500C
ADS5500CPAPR Tape and Reel, 100
(1) For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.(2) Thermal pad size: 3,5 mm ×3,5 mm (min), 4 mm ×4 mm (max). θ
JA
= 21.47 °C/W and θ
JC
= 2.99 °C/W, when used with 2 oz. coppertrace and pad soldered directly to a JEDEC standard four layer 3 in ×3 in PCB.
over operating free-air temperature range (unless otherwise noted)
(1)
ADS5500 UNIT
AV
DD
to A
GND
, DRV
DD
to DR
GND
VSupply voltage
A
GND
to DR
GND
VAnalog input to A
GND
(2) (2)
–0.3 to Min (AV
DD
+ 0.3 V, 3.6 V) VLogic input to DR
GND
0.3 to DRV
DD
VDigital data output to DR
GND
–0.3 to DRV
DD
V0 to 70Operating temperature range °C–40 to 85Junction temperature 105 °CStorage temperature range –65 to 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.(2) If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 should be added in series with each of the analoginput pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycleof the overshoot should be limited to less than 5% for inputs up to 3.9 V.
MIN NOM MAX UNIT
SUPPLIES
AV
DD
Analog supply voltage 3 3.3 3.6 VDRV
DD
Output driver supply voltage 3 3.3 3.6 V
ANALOG INPUT
Differential input range 2.3 V
PP
V
CM
Input common-mode voltage
(1)
1.45 1.55 1.65 V
DIGITAL OUTPUT
Maximum output load 10 pF
CLOCK INPUT
ADCLK input sample rate (sine DLL ON 60 125
Mspswave) 1/t
C
DLL OFF 2 80Clock amplitude, sine wave, differential (see Figure 50 for more information) 1 3 V
PP
(1) Input common-mode should be connected to CM.
2
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ELECTRICAL CHARACTERISTICS
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
RECOMMENDED OPERATING CONDITIONS (continued)
MIN NOM MAX UNIT
Clock duty cycle (see Figure 49 for more information) 50%0 70Open free-air temperature range °C–40 85
Typ values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AVDD =DRV
DD
= 3.3 V, sampling rate = 125 Msps, 50% clock duty cycle, DLL On, 3-V
PP
differential clock, and –1-dBFS differentialinput, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bits
ANALOG INPUTS
Differential input range 2.3 V
PP
Differential input impedance See Figure 41 6.6 Differential input capacitance See Figure 41 4 pFAnalog input common-mode current (per
300 µAinput)
Analog input bandwidth Source impedance = 50 750 MHz
ClockVoltage overload recovery time 4
Cycles
INTERNAL REFERENCE VOLTAGES
V
REFM
Reference bottom voltage 0.97 VV
REFP
Reference top voltage 2.11 VReference error 4% ±0.9% 4%V
CM
Common-mode voltage output 1.55 ±0.05 V
DYNAMIC DC CHARACTERISTICS AND ACCURACY
No missing codes TestedDNL Differential linearity error f
IN
= 10 MHz –0.9 ±0.75 1.1 LSBINL Integral linearity error f
IN
= 10 MHz –5 ±2.5 5 LSBOffset error –11 ±1.5 11 mVOffset temperature coefficient 0.02 mV/ °Coffset error/ AV
DD
from AV
DD
= 3DC power supply rejection ratio, DC PSRR 0.25 mV/VV to AV
DD
= 3.6 VGain error
(1)
–2 ±0.45 2 %FSGain temperature coefficient 0.01 %/ °C
DYNAMIC AC CHARACTERISTICS
25 °C to T
MAX
71.5 73.2f
IN
= 10 MHz
Full temp range 70.5 72.8f
IN
= 30 MHz 72.7f
IN
= 55 MHz 71.9SNR Signal-to-noise ratio 25 °C to T
MAX
70.8 72.3 dBFSf
IN
= 70 MHz
Full temp range 69.8 72f
IN
= 100 MHz 71.2f
IN
= 150 MHz 70.1f
IN
= 225 MHz 69.1RMS output noise Input tied to common-mode 1.1 LSB
(1) Gain error is specified by design and characterization; it is not tested in production.
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)Typ values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AVDD =DRV
DD
= 3.3 V, sampling rate = 125 Msps, 50% clock duty cycle, DLL On, 3-V
PP
differential clock, and –1-dBFS differentialinput, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
25 °C 82 84f
IN
= 10 MHz
Full temp range 78 84f
IN
= 30 MHz 84f
IN
= 55 MHz 79SFDR Spurious-free dynamic range 25 °C 80 83 dBcf
IN
= 70 MHz
Full temp range 77 82f
IN
= 100 MHz 82f
IN
= 150 MHz 78f
IN
= 225 MHz 7425 °C 82 91f
IN
= 10 MHz
Full temp range 78 86f
IN
= 30 MHz 86f
IN
= 55 MHz 84HD2 Second-harmonic 25 °C 80 87 dBcf
IN
= 70 MHz
Full temp range 77 83f
IN
= 100 MHz 84f
IN
= 150 MHz 78f
IN
= 225 MHz 7425 °C 82 89f
IN
= 10 MHz
Full temp range 78 88f
IN
= 30 MHz 90f
IN
= 55 MHz 79HD3 Third-harmonic 25 °C 80 85 dBcf
IN
= 70 MHz
Full temp range 77 82f
IN
= 100 MHz 82f
IN
= 150 MHz 80f
IN
= 225 MHz 76f
IN
= 10 MHz 25 °C 88Worst-harmonic/spur
dBc(other than HD2 and HD3)
f
IN
= 70 MHz 25 °C 8625 °C to T
MAX
71 72.8f
IN
= 10 MHz
Full temp range 69.5 72.2f
IN
= 30 MHz 72.3f
IN
= 55 MHz 70.7SINAD Signal-to-noise + distortion 25 °C to T
MAX
70.3 71.6 dBFSf
IN
= 70 MHz
Full temp range 69 71.3f
IN
= 100 MHz 70.5f
IN
= 150 MHz 69.1f
IN
= 225 MHz 67.4
4
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DIGITAL CHARACTERISTICS
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)Typ values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AVDD =DRV
DD
= 3.3 V, sampling rate = 125 Msps, 50% clock duty cycle, DLL On, 3-V
PP
differential clock, and –1-dBFS differentialinput, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
25 °C 80 85f
IN
= 10 MHz
Full temp range 78 83f
IN
= 30 MHz 82f
IN
= 55 MHz 77THD Total harmonic distortion 25 °C 77.5 81 dBcf
IN
= 70 MHz
Full temp range 76 79.5f
IN
= 100 MHz 79f
IN
= 150 MHz 75f
IN
= 225 MHz 71.8ENOB Effective number of bits f
IN
= 70 MHz 11.3 Bitsf = 10.1 MHz, 15.1 MHz
95(–7 dBFS each tone)f = 30.1 MHz, 35.1 MHzIMD Two-tone intermodulation distortion 94 dBFS(–7 dBFS each tone)f = 50.1 MHz, 55.1 MHz
94(–7 dBFS each tone)ACPSRR AC power supply rejection ratio Supply noise frequency 100 MHz 35 dB
POWER SUPPLY
I
CC
Total supply current f
IN
= 70 MHz 236 265 mAI
AVDD
Analog supply current f
IN
= 70 MHz 175 190 mAf
IN
= 70 MHz, 10-pF load fromI
DRVDD
Output buffer supply current 61 75 mAdigital outputs to groundAnalog only 578 627 mWPower dissipation
Output buffer power with 10-pF
202 248 mWload on digital output to groundStandby power With clocks running 181 250 mW
Valid over the full recommended operating temperature range, AV
DD
= DRV
DD
= 3.3 V, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS
High-level input voltage 2.4 VLow-level input voltage 0.8 VHigh-level input current 10 µALow-level input current –10 µAInput current for RESET –20 µAInput capacitance 4 pF
DIGITAL OUTPUTS
Low-level output voltage C
LOAD
= 10 pF 0.3 VHigh-level output voltage C
LOAD
= 10 pF 2.8 3 VOutput capacitance 3 pF
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TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
(1) (2)
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the abovetiming matches closely with the specified values.
Figure 1. Timing Diagram
Typ values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, samplingrate = 125 Msps, 50% clock duty cycle, AV
DD
= DRV
DD
= 3.3 V, 3-V
PP
differential clock, and C
LOAD
= 10 pF, (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING SPECIFICATION
t
A
Aperture delay Input CLK falling edge to data sampling point 1 nsAperture jitter (uncertainty) Uncertainty in sampling instant 300 fst
su
Data setup time Data valid
(3)
to 50% of CLKOUT rising edge 2.1 2.5 nst
h
Data hold time 50% of CLKOUT rising edge to data becoming invalid
(3)
1.7 2.1 nst
START
Input clock to output data valid Input clock rising edge to Data valid start delay 2.2 2.9 nsstart
(4) (5)
t
END
Input clock to output data valid Input clock rising edge to Data valid end delay 5.8 6.9 nsend
(4)(5)
t
JIT
Output clock jitter Uncertainty in CLKOUT rising edge, peak-to-peak 150 210 pst
r
Output clock rise time Rise time of CLKOUT measured from 20% to 80% of 1.7 1.9 nsDRVDDt
f
Output clock fall time Fall time of CLKOUT measured from 80% to 20% of 1.5 1.7 nsDRVDDt
PDI
Input clock to output clock delay Input clock rising edge, zero crossing, to output clock 4.2 4.8 5.5 nsrising edge 50%t
r
Data rise time Data rise time measured from 20% to 80% of DRVDD 3.6 4.6 nst
f
Data fall time Data fall time measured from 80% to 20% of DRVDD 2.8 3.7 nsOutput enable (OE) to data output Time required for outputs to have stable timings w.r.t 1000 Clockdelay input clock( after OE is activated Cycles
(1) Timing parameters are ensured by design and characterization and not tested in production.(2) See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies.(3) Data valid refers to 2 V for LOGIC high and 0.8 V for LOGIC low.(4) See the Output Information section for details on using the input clock for data capture.(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3 ). Add ½ clock period for the validnumber for a falling edge CLKOUT polarity.
6
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RESET TIMING CHARACTERISTICS
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TIMING CHARACTERISTICS (continued)Typ values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, samplingrate = 125 Msps, 50% clock duty cycle, AV
DD
= DRV
DD
= 3.3 V, 3-V
PP
differential clock, and C
LOAD
= 10 pF, (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Time to valid data after coming out of software power 1000
ClockdownWake-up time
CyclesTime to valid data after stopping and restarting the clock 1000Latency Time for a sample to 17.5 Clockpropagate to the ADC outputs 17.5 CyclesClock Cycles
Typ values given at T
A
= 25 °C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, 3-V
PP
differential clock(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING SPECIFICATION
t
1
Power-on delay Delay from power on of AV
DD
and DRV
DD
to RESET pulse 10 mst
2
Reset pulse width Pulse width of active RESET signal 2 µst
3
Register write delay Delay from RESET disable to SEN active 2 µsPower-up time Delay from power-up of AV
DD
and DRV
DD
to output stable 40 ms
Figure 2. Reset Timing Diagram
The device has a three-wire serial interface. The device latches the serial data SDATA on the falling edge ofserial clock SCLK when SEN is active.Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at falling edge.Minimum width of data stream for a valid loading is 16 clocks.Data is loaded at every 16th SCLK falling edge while SEN is low.In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.Data can be loaded in multiple of 16-bit words within a single active SEN pulse.The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
Figure 3. DATA Communication is 2-Byte, MSB First
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
PARAMETER MIN
(1)
TYP
(1)
MAX
(1)
UNIT
t
SCLK
SCLK period 50 nst
WSCLK
SCLK duty cycle 25% 50% 75%t
SLOADS
SEN to SCLK setup time 8 nst
SLOADH
SCLK to SEN hold time 6 nst
DS
Data setup time 8 nst
DH
Data hold time 6 ns
(1) Min, typ, and max values are characterized, but not production tested.
Table 2. Serial Register Table
(1)
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
DLL
CTR
L Clock DLL
Internal DLL is on, recommended for 60–125 Msps clock1101000000000000
speed
Internal DLL is off, recommended for 2-80 Msps clock1101000000000010
speed
TP<1> TP<0> Test Mode
1 1 1 0 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation
1 1 1 0 0 0 1 0 0 0 0 0 0 0 X 0 All outputs forced to 0.
(2)
11100100000000X0
All outputs forced to 1.
(2)
11100110000000X0
Each output bit toggles between 0 and 1.
(2)
(3)
PDN Power Down
1 1 1 1 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation
1 1 1 1 1 0 0 0 0 0 0 0 0 0 X 0 Device is put in power down (low current) mode
(1) The register contents default to the appropriate setting for normal operation upon RESET.(2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test modeoutputs will be the two's complement equivalent of these patterns as described in the Output Information section.(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. Forexample, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
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VDFS t2
12 AVDD
4
12 AVDD tVDFS t5
12 AVDD
7
12 AVDD tVDFS t8
12 AVDD
VDFS u10
12 AVDD
PIN CONFIGURATION
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
Table 3. Data Format Select (DFS Table)
DFS-PIN VOLTAGE (V
DFS
) DATA FORMAT CLOCK OUTPUT POLARITY
Straight Binary Data valid on rising edge
Two's Complement Data valid on rising edge
Straight Binary Data valid on falling edge
Two's Complement Data valid on falling edge
PIN ASSIGNMENTS
TERMINAL
NO. OF
I/O DESCRIPTIONPINSNAME NO.
5, 7, 9, 15, 22, 24, 26,AV
DD
12 I Analog power supply28, 33, 34, 37, 396, 8, 12-14, 16, 18,A
GND
21, 23, 25, 27, 32, 36, 14 I Analog ground38DRV
DD
49, 58 2 I Output driver power supply
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DEFINITION OF SPECIFICATIONS
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
PIN CONFIGURATION (continued)PIN ASSIGNMENTS (continued)
TERMINAL
NO. OF
I/O DESCRIPTIONPINSNAME NO.
DR
GND
1, 42, 48, 50, 57, 59 6 I Output driver groundINP 19 1 I Differential analog input (positive)INM 20 1 I Differential analog input (negative)REFP 29 1 O Reference voltage (positive); 1- µF capacitor to GNDREFM 30 1 O Reference voltage (negative); 1- µF capacitor to GNDIREF 31 1 I Current set; 56.2-k resistor to GND; do not connect capacitorsCM 17 1 O Common-mode output voltageRESET 35 1 I Reset (active high), internal 200-k resistor to AVDD
(1)
OE 41 1 I Output enable (active high)DFS 40 1 I Data format and clock out polarity select
(2) (3)
CLKP 10 1 I Data converter differential input clock (positive)CLKM 11 1 I Data converter differential input clock (negative)SEN 4 1 I Serial interface chip select
(3)
SDATA 3 1 I Serial interface data
(3)
SCLK 2 1 I Serial interface clock
(3)
D0 (LSB)–D13(MSB) 44-47, 51-56, 60-63 14 O Parallel data outputOVR 64 1 O Over-range indicator bitCLKOUT 43 1 O CMOS clock out in sync with dataNOTE: PowerPAD must be connected to analog ground.
(1) If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details.(2) Table 3 defines the voltage levels for each mode selectable via the DFS pin.(3) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pinsmust also run off the same supply voltage as DRVDD.
Minimum Conversion RateAnalog Bandwidth
The minimum sampling rate at which the ADCThe analog input frequency at which the power of the
functions.fundamental is reduced by 3 dB with respect to thelow frequency value. Differential Nonlinearity (DNL)An ideal ADC exhibits code transitions at analogAperture Delay
input values spaced exactly 1 LSB apart. The DNL isThe delay in time between the falling edge of the
the deviation of any single step from this ideal value,input sampling clock and the actual time at which the
measured in units of LSBs.sampling occurs.
Integral Nonlinearity (INL)Aperture Uncertainty (Jitter)
The INL is the deviation of the ADC's transferThe sample-to-sample variation in aperture delay.
function from a best fit line determined by a leastsquares curve fit of that transfer function, measuredClock Pulse Width/Duty Cycle
in units of LSBs.The duty cycle of a clock signal is the ratio of thetime the clock signal remains at a logic high (clock
Gain Errorpulse width) to the period of the clock signal. Duty
The gain error is the deviation of the ADC's actualcycle is typically expressed as a percentage. A
input full-scale range from its ideal value. The gainperfect differential sine-wave clock results in a 50%
error is given as a percentage of the ideal inputduty cycle.
full-scale range. Gain error does not account forvariations in the internal reference voltages (see theMaximum Conversion Rate
Electrical Specifications section for limits on theThe maximum sampling rate at which certified
variation of V
REFP
and V
REFM
).operation is given. All parametric testing is performedat this sampling rate unless otherwise noted.
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ENOB +SINAD *1.76
6.02
(3)
THD +10Log10 PS
PD
(4)
SNR +10Log10 PS
PN
(1)
SINAD +10Log10 PS
PN)PD
(2)
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
Offset Error Effective Number of Bits (ENOB)The offset error is the difference, given in number of The ENOB is a measure of a converter'sLSBs, between the ADC's actual average idle performance as compared to the theoretical limitchannel output code and the ideal average idle based on quantization noise.channel output code. This quantity is often mappedinto mV.
Temperature Drift
Total Harmonic Distortion (THD)The temperature drift coefficient (with respect to gain
THD is the ratio of the power of the fundamental (P
S
)error and offset error) specifies the change per
to the power of the first eight harmonics (P
D
).degree Celsius of the parameter from T
MIN
to T
MAX
. Itis calculated by dividing the maximum deviation ofthe parameter across the T
MIN
to T
MAX
range by thedifference T
MAX
-T
MIN
.
THD is typically given in units of dBc (dB to carrier).Signal-to-Noise Ratio
Spurious-Free Dynamic Range (SFDR)SNR is the ratio of the power of the fundamental (P
S
)
The ratio of the power of the fundamental to theto the noise floor power (P
N
), excluding the power at
highest other spectral component (either spur orDC and the first eight harmonics.
harmonic). SFDR is typically given in units of dBc(dB to carrier).
Two-Tone Intermodulation DistortionIMD3 is the ratio of the power of the fundamental (atSNR is either given in units of dBc (dB to carrier)
frequencies f1 and f2) to the power of the worstwhen the absolute power of the fundamental is used
spectral component at either frequency 2f
1
–f
2
oras the reference, or dBFS (dB to full scale) when the
2f
2
–f
1
. IMD3 is either given in units of dBc (dB topower of the fundamental is extrapolated to the
carrier) when the absolute power of the fundamentalconverter's full-scale range.
is used as the reference, or dBFS (dB to full scale)Signal-to-Noise and Distortion (SINAD)
when the power of the fundamental is extrapolated toSINAD is the ratio of the power of the fundamental
the converter's full-scale range.(P
S
) to the power of all the other spectral
DC Power Supply Rejection Ratio (DC PSRR)components including noise (P
N
) and distortion (P
D
),
The DC PSSR is the ratio of the change in offsetbut excluding dc.
error to a change in analog supply voltage. The DCPSRR is typically given in units of mV/V.
Reference ErrorSINAD is either given in units of dBc (dB to carrier)
The reference error is the variation of the actualwhen the absolute power of the fundamental is used
reference voltage (V
REFP
V
REFM
) from its ideal value.as the reference, or dBFS (dB to full scale) when the
The reference error is typically given as apower of the fundamental is extrapolated to the
percentage.converter's full-scale range.
Voltage Overload Recovery TimeThe voltage overload recovery time is defined as thetime required for the ADC to recover to within 1% ofthe full-scale range in response to an input voltageoverload of 10% beyond the full-scale range.
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TYPICAL CHARACTERISTICS
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 2-MHz Input Signal) (FFT for 15-MHz Input Signal)
Figure 5. Figure 6.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 60-MHz Input Signal) (FFT for 70-MHz Input Signal)
Figure 7. Figure 8.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 80-MHz Input Signal) (FFT for 100-MHz Input Signal)
Figure 9. Figure 10.
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 150-MHz Input Signal) (FFT for 225-MHz Input Signal)
Figure 11. Figure 12.
SPECTRAL PERFORMANCE
(FFT for 300-MHz Input Signal) TWO-TONE INTERMODULATION
Figure 13. Figure 14.
TWO-TONE INTERMODULATION TWO-TONE INTERMODULATION
Figure 15. Figure 16.
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
DIFFERENTIAL NONLINEARITY (DNL) INTEGRAL NONLINEARITY (INL)
Figure 17. Figure 18.
SPURIOUS-FREE DYNAMIC RANGE vs SIGNAL-TO-NOISE RATIO vsINPUT FREQUENCY INPUT FREQUENCY
Figure 19. Figure 20.
14
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
AC PERFORMANCE vs AC PERFORMANCE vsANALOG SUPPLY VOLTAGE ANALOG SUPPLY VOLTAGE
Figure 21. Figure 22.
AC PERFORMANCE vs AC PERFORMANCE vsDIGITAL SUPPLY VOLTAGE DIGITAL SUPPLY VOLTAGE
Figure 23. Figure 24.
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
TOTAL POWER DISSIPATION vs SIGNAL-TO-NOISE RATIO ANDSAMPLING FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE
Figure 25. Figure 26.
AC PERFORMANCE vs AC PERFORMANCE vsINPUT AMPLITUDE INPUT AMPLITUDE
Figure 27. Figure 28.
16
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
AC PERFORMANCE vsINPUT AMPLITUDE OUTPUT NOISE HISTOGRAM
Figure 29. Figure 30.
AC PERFORMANCE vsCLOCK AMPLITUDE WCDMA CARRIER
Figure 31. Figure 32.
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
SIGNAL-TO-NOISE RATIO (SNR) WITH DLL ON
Figure 33.
SIGNAL-TO-NOISE RATIO (SNR) WITH DLL OFF
Figure 34.
18
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL ON
Figure 35.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL OFF
Figure 36.
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
SECOND HARMONIC (HD2) WITH DLL ON
Figure 37.
SECOND HARMONIC (HD2) WITH DLL OFF
Figure 38.
20
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ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)Typical values are at T
A
= 25 °C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 125 Msps,DLL On, and 3-V differential clock unless otherwise noted
THIRD HARMONIC (HD3) WITH DLL ON
Figure 39.
THIRD HARMONIC (HD3) WITH DLL OFF
Figure 40.
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APPLICATION INFORMATION
THEORY OF OPERATION
INPUT CONFIGURATION
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
clock cycle. This process results in a data latency of17.5 clock cycles, after which the output data isavailable as a 14-bit parallel word, coded in eitherThe ADS5500 is a low-power, 14-bit, 125 Msps,
straight offset binary or binary two's complementCMOS, switched capacitor, pipeline ADC that
format.e sample through the pipeline every half clockoperates from a single 3.3-V supply. The conversion
cycle. This process resultsprocess is initiated by a falling edge of the externalinput clock. Once the signal is captured by the inputS&H, the input sample is sequentially converted by aseries of small resolution stages, with the outputs The analog input for the ADS5500 consists of acombined in a digital correction logic block. Both the differential sample-and-hold architecturerising and the falling clock edges are used to implemented using a switched capacitor technique,propagate the sample through the pipeline every half shown in Figure 41 .
NOTE: All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 41. Analog Input Stage
This differential input topology produces a high level differential signal of 1.15 V
PP
for a total differentialof AC performance for high sampling rates. It also input signal swing of 2.3 V
PP
. The maximum swing isresults in a high usable input bandwidth, especially determined by the two reference voltages, the topimportant for high intermediate-frequency (IF) or reference (REFP, pin 29), and the bottom referenceundersampling applications. The ADS5500 requires (REFM, pin 30).each of the analog inputs (INP, INM) to be externally
The ADS5500 obtains optimum performance whenbiased around the common-mode level of the
the analog inputs are driven differentially. The circuitinternal circuitry (CM, pin 17). For a full-scale
shown in Figure 42 shows one possible configurationdifferential input, each of the differential lines of the
using an RF transformer.input signal (pins 19 and 20) swings symmetricallybetween CM + 0.575 V and CM 0.575 V. Thismeans that each input is driven with a signal of up toCM 0.575 V, so that each input has a maximum
22
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600 mA fs
125MSPS
(5)
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
can be selected depending on the application. An RFgain block amplifier, such as TI's THS9001, can alsobe used with an RF transformer for very high inputfrequency applications. The THS4503 is arecommended differential input/output amplifier.Table 4 lists the recommended amplifiers.
When using single-ended operational amplifiers(such as the THS3201, THS3202, OPA847, orOPA695) to provide gain, a three-amplifier circuit isrecommended with one amplifier driving the primaryof an RF transformer and one amplifier in each of thelegs of the secondary driving the two differentialinputs of the ADS5500. These three amplifier circuitsFigure 42. Transformer Input to Convert
minimize even-order harmonics. For very highSingle-Ended Signal to Differential Signal
frequency inputs, an RF gain block amplifier can beused to drive a transformer primary; in this case, thetransformer secondary connections can drive theThe single-ended signal is fed to the primary winding
input of the ADS5500 directly, as shown inof an RF transformer. Since the input signal must be
Figure 42 , or with the addition of the filter circuitbiased around the common-mode voltage of the
shown in Figure 43 .internal circuitry, the common-mode voltage (V
CM
)from the ADS5500 is connected to the center-tap of
Figure 43 illustrates how RIN and CIN can be placedthe secondary winding. To ensure a steady low-noise
to isolate the signal source from the switching inputsV
CM
reference, best performance is obtained when
of the ADC and to implement a low-pass RC filter tothe CM (pin 17) output is filtered to ground with 0.1
limit the input noise in the ADC. It is recommendedµF and 0.001- µF low-inductance capacitors.
that these components be included in the ADS5500circuit layout when any of the amplifier circuitsOutput V
CM
(pin 17) is designed to directly drive the
discussed previously are used. The componentsADC input. When providing a custom CM level, be
allow fine-tuning of the circuit performance. Anyaware that the input structure of the ADC sinks a
mismatch between the differential lines of thecommon-mode current in the order of 600 µA (300
ADS5500 input produces a degradation inµA per input) at 125 Msps. Equation 5 describes the
performance at high input frequencies, mainlydependency of the common-mode current and the
characterized by an increase in the even-ordersampling frequency:
harmonics. In this case, special care should be takento keep as much electrical symmetry as possiblebetween both inputs.Where:
Another possible configuration for lower-frequencyf
S
> 2 Msps.
signals is the use of differential input/outputamplifiers that can simplify the driver circuit forThis equation helps to design the output capability
applications requiring dc-coupling of the input.and impedance of the driving circuit accordingly.
Flexible in their configurations (see Figure 44 ), suchWhen it is necessary to buffer or apply a gain to the
amplifiers can be used for single-ended-incoming analog signal, it is possible to combine
to-differential conversion, signal amplification.single-ended operational amplifiers with an RFtransformer, or to use a differential input/outputamplifier without a transformer, to drive the input ofthe ADS5500. TI offers a wide selection ofsingle-ended operational amplifiers (including theTHS3201, THS3202, OPA847, and OPA695) that
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POWER SUPPLY SEQUENCING POWER DOWN
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
Table 4. Recommended Amplifiers to Drive the Input of the ADS5500
INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER USE WITH TRANSFORMER?
DC to 20 MHz THS4503 Differential In/Out Amp NoDC to 50 MHz OPA847 Operational Amp YesDC to 100 MHz THS4509 Differential In/Out Amp NOOPA695 Operational Amp Yes10 MHz to 120 MHz THS3201 Operational Amp YesTHS3202 Operational Amp YesOver 100 MHz THS90016 RF Gain Block Yes
Figure 43. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
Figure 44. Using the THS4503 With the ADS5500
The preferred power-up sequence is to ramp AV
DD
The device enters power-down in one of two ways:first, followed by DRV
DD
, including a simultaneous either by reducing the clock speed or by setting theramp of AV
DD
and DRV
DD
. In the case that DRV
DD
PDN bit through the serial programming interface.ramps up first in the system, care must be taken to Using the reduced clock speed, power-down may beensure that AV
DD
ramps up within 10 ms. initiated for clock frequencies below 2 Msps. Theexact frequency at which the power down occursvaries from device to device.
24
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REFERENCE CIRCUIT
CLOCK INPUT
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
Using the serial interface PDN bit to power down thedevice places the outputs in a high-impedance stateand only the internal reference remains on to reducethe power-up time. The power-down mode reducespower dissipation to approximately 180 mW.
The ADS5500 has built-in internal referencegeneration, requiring no external circuitry on theprinted circuit board (PCB). For optimumperformance, it is best to connect both REFP andREFM to ground with a 1- µF decoupling capacitor(the 1- series resistor shown in Figure 45 isoptional). In addition, an external 56.2-k resistorshould be connected from IREF (pin 31) to AGND toset the proper current for the operation of the ADC,as shown in Figure 45 . No capacitor should be
Figure 46. Clock Inputsconnected between pin 31 and ground; only the56.2-k resistor should be used.
When driven with a single-ended CMOS clock input,it is best to connect CLKM (pin 11) to ground with a0.01- µF capacitor, while CLKP is ac-coupled with a0.01- µF capacitor to the clock source, as shown inFigure 47 .
Figure 45. REFP, REFM, and IREF Connections
Figure 47. AC-Coupled, Single-Ended Clock Inputfor Optimum Performance
The ADS5500 clock input can also be drivendifferentially, reducing susceptibility tocommon-mode noise. In this case, it is best toThe ADS5500 clock input can be driven with either a
connect both clock inputs to the differential inputdifferential clock signal or a single-ended clock input,
clock signal with 0.01- µF capacitors, as shown inwith little or no difference in performance between
Figure 48 .both configurations. The common-mode voltage ofthe clock inputs is set internally to CM (pin 17) usinginternal 5-k resistors that connect CLKP (pin 10)and CLKM (pin 11) to CM (pin 17), as shown inFigure 46 .
Figure 48. AC-Coupled, Differential Clock Input
For high input frequency sampling, it isrecommended to use a clock source with very lowjitter. Additionally, the internal ADC core uses bothedges of the clock for the conversion process. Thismeans that, ideally, a 50% duty cycle should beprovided. Figure 49 shows the performance variationof the ADC versus clock duty cycle.
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OUTPUT INFORMATION
INTERNAL DLL
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
DLL OFF mode described in the Serial InterfaceProgramming section. The Typical PerformanceCurves show the performance obtained in bothmodes of operation: DLL ON (default) and DLL OFF.In either of the two modes, the device enterspower-down mode if no clock or slow clock isprovided. The limit of the clock frequency where thedevice functions properly with default settings isensured to be over 2 MHz.
The ADC provides 14 data outputs (D13 to D0, withD13 being the MSB and D0 the LSB), a data-readysignal (CLKOUT, pin 43), and an out-of-rangeindicator (OVR, pin 64) that equals one when theoutput reaches the full-scale limits.Figure 49. AC Performance vs Clock Duty Cycle
Two different output formats (straight offset binary orBandpass filtering of the clock source can help
two's complement) and two different output clockproduce a 50% duty cycle clock and reduce the
polarities (latching output data on rising or fallingeffect of jitter. When using a sinusoidal clock, the
edge of the output clock) can be selected by settingclock jitter further improves as the amplitude is
DFS (pin 40) to one of four different voltages.increased. In that sense, using a differential clock
Table 3 details the four modes. In addition, outputallows for the use of larger amplitudes without
enable control (OE, pin 41, active high) is provided toexceeding the supply rails and absolute maximum
put the outputs into a high-impedance state.ratings of the ADC clock input. Figure 50 shows the
In the event of an input voltage overdrive, the digitalperformance variation of the device versus input
outputs go to the appropriate full scale level. For aclock amplitude. For detailed clocking schemes
positive overdrive, the output code is 0x3FFF inbased on transformer or PECL-level clocks, see the
straight offset binary output format, and 0x1FFF inADS5500EVM user's guide (SLWU010 ), available for
2's complement output format. For a negative inputdownload from www.ti.com .
overdrive, the output code is 0x0000 in straight offsetbinary output format and 0x2000 in two'scomplement output format. These outputs to anoverdrive signal are ensured through design andcharacterization.
The output circuitry of the ADS5500, by design,minimizes the noise produced by the data switchingtransients and, in particular, its coupling to the ADCanalog circuitry. Output D4 (pin 51) senses the loadcapacitance and adjusts the drive capability of all theoutput pins of the ADC to maintain the same outputslew rate described in the timing diagram of Figure 1 .Care should be taken to ensure that all output lines(including CLKOUT) have nearly the same load asD4 (pin 51). This circuit also reduces the sensitivityof the output timing versus supply voltage ortemperature. Placing external resistors in series withFigure 50. AC Performance vs Clock Amplitudes
the outputs is not recommended.
The timing characteristics of the digital outputschange for sampling rates below the 125 Mspsmaximum sampling frequency. Table 5 throughIn order to obtain the fastest sampling rates
Table 7 show the values of various timingachievable with the ADS5500, the device uses an
parameters for lower sampling frequencies, both withinternal digital delay lock loop (DLL). Nevertheless,
DLL on and off.the limited frequency range of operation of DLLdegrades the performance at clock frequenciesbelow 60 Msps. In order to operate the device below60 Msps, the internal DLL must be shut off using the
26
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SERIAL PROGRAMMING INTERFACE
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
To use the input clock as the data capture clock, it is Desired setup time = t
d
t
STARTnecessary to delay the input clock by a delay (t
d
) that
Desired hold time = t
END
t
dresults in the desired setup or hold time. Use eitherof the following equations to calculate the value of t
d
.
Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON)t
su
(ns) t
h
(ns) t
START
(ns) t
END
(ns)
tr
(ns) t
f
(ns)F
S
(Msps)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
105 2.2 2.8 2.2 2.5 1.9 2.8 5.8 7.3 4.4 5.1 3.3 3.8
80 2.8 3.7 2.8 3.3 0.5 1.7 5.3 7.9 5.8 6.6 4.4 5.3
65 3.8 4.6 3.6 4.1 –0.5 0.8 5.3 8.5 6.7 7.2 5.5 6.4
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)t
su
(ns) t
h
(ns) t
START
(ns) t
END
(ns)
tr
(ns) t
f
(ns)F
S
(Msps)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80 3.2 4.2 1.8 3 3.8 5 8.4 11 5.8 6.6 4.4 5.3
65 4.3 5.7 2 3 2.8 4.5 8.3 11.8 6.6 7.2 5.5 6.4
40 8.5 11 2.6 3.5 –1 1.5 8.9 14.5 7.5 8 7.3 7.8
20 17 25.7 2.5 4.7 –9.8 2 9.5 21.6 7.5 8 7.6 8
10 27 51 4 6.5 –30 –3 11.5 31
2 284 370 8 19 185 320 515 576 50 82 75 150
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON)CLKOUT, Rise Time CLKOUT, Fall Time
CLKOUT Jitter, Peak-to-Peak t
JIT
(ps) Input-to-Output Clock Delay t
PDI
(ns)t
r
(ns) t
f
(ns)F
S
(Msps)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
105 2 2.2 1.7 1.8 175 250 4 4.7 5.5
80 2.5 2.8 2.1 2.3 210 315 3.7 4.3 5.1
65 3.1 3.5 2.6 2.9 260 380 3.5 4.1 4.8
Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)CLKOUT, Rise Time CLKOUT, Fall Time
CLKOUT Jitter, Peak-to-Peak t
JIT
(ps) Input-to-Output Clock Delay t
PDI
(ns)t
r
(ns) t
f
(ns)F
S
(Msps)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80 2.5 2.8 2.1 2.3 210 315 7.1 8 8.9
65 3.1 3.5 2.6 2.9 260 380 7.8 8.5 9.4
40 4.8 5.3 4 4.4 445 650 9.5 10.4 11.4
20 8.3 9.5 7.6 8.2 800 1200 13 15.5 18
10 16 20.7 25.5
2 31 52 36 65 2610 4400 537 551 567
Note that some of these modes may modify thestandard operation of the device and possibly varythe performance with respect to the typical dataThe ADS5500 has internal registers for the
shown in this data sheet.programming of some of the modes described in theprevious sections. The registers should be reset after
Applying a RESET signal is required to set thepower-up by applying a 2 µs (minimum) high pulse
internal registers to their default states for normalon RESET (pin 35); this also resets the entire ADC
operation. If the hardware RESET function is notand sets the data outputs to low. This pin has a
used in the system, the RESET pin must be tied to200-k internal pullup resistor to AV
DD
. The
ground and it is necessary to write the default valuesprogramming is done through a three-wire interface.
to the internal registers through the serialThe timing diagram and serial register setting in the
programming interface. The registers must be writtenSerial Programing Interface section describe the
in the following order.programming of this register.
Write 9000h (Address 9, Data 000)Table 2 shows the different modes and the bit values
Write A000h (Address A, Data 000)to be written on the register to enable them.
Write B000h (Address B, Data 000)Write C000h (Address C, Data 000)
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PowerPAD PACKAGE
Assembly Process
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
Write D000h (Address D, Data 000) Data section. The recommended thermal padWrite E000h (Address E, Data 804) dimension is 8 mm x 8 mm.Write 0000h (Address 0, Data 000)
2. Place a 5-by-5 array of thermal vias in theWrite 1000h (Address 1, Data 000)
thermal pad area. These holes should be 13Write F000h (Address F, Data 000).
mils in diameter. The small size preventswicking of the solder through the holes.NOTE: This procedure is only required if a RESETpulse is not provided to the device. 3. It is recommended to place a small number of25 mil diameter holes under the package, butoutside the thermal pad area to provide anadditional heat path.The PowerPAD package is a thermally enhanced
4. Connect all holes (both those inside andstandard size IC package designed to eliminate the
outside the thermal pad area) to an internaluse of bulky heat sinks and slugs traditionally used in
copper plane (such as a ground plane).thermal packages. This package can be easily
5. Do not use the typical web or spoke viamounted using standard printed circuit board (PCB)
connection pattern when connecting theassembly techniques and can be removed and
thermal vias to the ground plane. The spokereplaced using standard repair procedures. AVDD.
pattern increases the thermal resistance to theThe programming is done through a three-wire
ground plane.interface. The timing diagram and serial registersetting in the Serial Programing Interface section
6. The top-side solder mask should leavedescribe the programming of this register.
exposed the terminals of the package and thethermal pad area.The PowerPAD package is designed so that the lead
7. Cover the entire bottom side of the PowerPADframe die pad (or thermal pad) is exposed on the
vias to prevent solder wicking.bottom of the IC. This provides a low thermalresistance path between the die and the exterior of
8. Apply solder paste to the exposed thermalthe package. The thermal pad on the bottom of the
pad area and all of the package terminals.IC can then be soldered directly to the printed circuit
For more detailed information regarding theboard (PCB), using the PCB as a heatsink.
PowerPAD package and its thermal properties, seeProgramming is done through a three-wire interface.
either the SLMA004 B application brief PowerPADThe timing diagram and serial register setting in the
Made Easy or SLMA002 technical brief PowerPADSerial Programing Interface section describe the
Thermally Enhanced Package.programming of this register.
1. Prepare the PCB top-side etch patternincluding etch for the leads as well as thethermal pad as illustrated in the Mechanical
28
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REVISION HISTORY
ADS5500
SBAS303F DECEMBER 2003 REVISED FEBRUARY 2007
REVISION DATE DESCRIPTION
0.0 12/03 Preliminary data sheet released1.0 03/04 Data sheet updated to reflect RTM silicon2.0 09/05 Added information regarding thermal pad size and thermal characteristics of the package.Removed input current from Absolute Maximum Ratings table. Updated specifications to AGND andDRGND. Added notes regarding the input voltage overstress requirements.Changed minimum recommended sampling rate to 2 Msps.Clarified the Electrical Characteristics measurement conditions.Changed analog input common-mode current specification.Removed maximum sampling rate from specification table.Added Voltage Overload Recovery Time specification.Changed offset temperature coefficient to units of mV/ °C.Changed power dissipation reporting to separate analog and digital power dissipation.Changed two-tone intermodulation distortion units to dBFS and updated the specification values to reflectthis change.
Clarified the Digital Characteristics measurement conditions.Added min V
OH
and max V
OL
specifications.Added data valid with respect to the input clock, output clock jitter, wakeup time, and output clock rise andfall time parameters.
Clarified the Timing Characteristics measurement conditions.Updated the timing diagram in Figure 1 to include t
START
and t
END
timing parameters.Added minimum and maximum specifications for various timing parameters.Added section on Reset Timing.Clarified serial interface data word format.Clarified output capture test modes.Simplified the information given in Table 3 .Updated the definitions section.Clarified measurement conditions for the specifications plots.Corrected text annotations on the WCDMA signal plot.Added axis label to HD3 with DLL ON contour plot.Updated Figure 4 to correct parameter values and improve readability.Added 25- series resistors to ADC inputs in Figure 5 .Corrected text in Input Configuration section to accurately reflect the CM voltage decoupling depicted inFigure 5 .Updated Equation 5 to match the new definition of common-mode input current and minimum sample rate.Added 25- series resistors to ADC inputs in Figure 6 .Changed Power Supply Sequence section to reduce constraints on the power-up sequence.Updated the Power Down section to reflect the newly specified 2 Msps minimum sampling rate.Updated Output Information text to include information on the output data in over-range conditions, describedata capture using the input clock, and add tables to specify timing parameters at various sampling rates.3.0 10/05 Improved SNR performance parameters.Updated Reference Circuit section to reflect that the 1- series resistors to REFP and REFM are nowoptional.
Updated timing parameters in Table 5 through Table 8 to reflect revised silicon timing.
REV G 02/07 Added min/max specs for offset and gain errors
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5500IPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5500IPAPR HTQFP PAP 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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