STM32F722xx STM32F723xx ARM(R)-based Cortex(R)-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash/256+16+ 4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com itf Data brief Features * Core: ARM(R) 32-bit Cortex(R)-M7 CPU with FPU, adaptive real-time accelerator (ART AcceleratorTM) and L1-cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions. * Memories - Up to 512 Kbytes of Flash memory with protection mechanisms (read and write protections, propriety code readout protection (PCROP)) - 528 bytes of OTP memory - SRAM: 256 Kbytes (including 64 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM (available in the lowest power modes) - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories * Dual mode Quad-SPI * Clock, reset and supply management - 1.7 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - Dedicated USB power - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC (1% accuracy) - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration * Low-power - Sleep, Stop and Standby modes September 2016 &"'! LQFP64 (10 x 10 mm) LQFP100 (14 x 14 mm) UFBGA176 (10 x 10 mm) WLCSP100 (0.4 mm pitch) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) - VBAT supply for RTC, 32x32 bit backup registers + 4 Kbytes of backup SRAM * 3x12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode * 2x12-bit D/A converters * Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWMs or pulse counter and quadrature (incremental) encoder inputs. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer * General-purpose DMA: 16-stream DMA controller with FIFOs and burst support * Debug mode - SWD & JTAG interfaces - Cortex(R)-M7 Trace MacrocellTM * Up to 140 I/O ports with interrupt capability - Up to 136 fast I/Os up to 108 MHz - Up to 138 5 V-tolerant I/Os * Up to 21 communication interfaces - Up to 3x I2C interfaces (SMBus/PMBus) - Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) - Up to 5 SPIs (up to 50 Mbit/s), 3 with muxed simplex I2Ss for audio class accuracy via internal audio PLL or external clock - 2 x SAIs (serial audio interface) DocID028479 Rev 1 For further information contact your local STMicroelectronics sales office. UFBGA144 (7 x 7 mm) 1/121 www.st.com STM32F722xx STM32F723xx - 1 x CAN (2.0B active) - 2 x SDMMCs * * * * True random number generator CRC calculation unit RTC: subsecond accuracy, hardware calendar 96-bit unique ID * Advanced connectivity - USB 2.0 full-speed device/host/OTG controller with on-chip PHY - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and on-chip Hi-speed PHY or ULPI depending on the product Table 1. Device summary Reference Part number STM32F722xx STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC, STM32F722VC, STM32F722RC STM32F723xx STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC 2/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Contents Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 STM32F723xx versus STM32F722xx LQFP144/LQFP176 packages: . . 14 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 ARM(R) Cortex(R)-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 17 2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 21 2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.16 2.15.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.15.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 30 2.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 30 2.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID028479 Rev 1 3/121 5 Contents STM32F722xx STM32F723xx 2.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.22 Universal synchronous/asynchronous receiver transmitters (USART) . . 37 2.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 38 2.24 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.26 Audio PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.27 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 39 2.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 40 2.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 40 2.30.1 Universal Serial Bus controller on-the-go High-Speed PHY controller (USBPHYC) only on STM32F723xx devices. . . . . . . . . . . . . . . . . . . . . 41 2.31 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.32 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.33 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.34 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.35 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.36 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.37 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4/121 5.1 LQFP64 - 10 x 10 mm, low-profile quad flat package information . . . . . 101 5.2 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 103 5.3 LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 105 5.4 LQFP176 24 x 24 mm low-profile quad flat package information . . . . . . 107 5.5 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 DocID028479 Rev 1 STM32F722xx STM32F723xx 6 Contents 5.6 UFBGA 176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 5.7 WLCSP100 - 0.4 mm pitch wafer level chip scale package information .114 5.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 119 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 DocID028479 Rev 1 5/121 5 List of tables STM32F722xx STM32F723xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. 6/121 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F722xx and STM32F723xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 27 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32F722xx and STM32F723xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 55 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 STM32F722xx and STM32F723xx alternate function mapping. . . . . . . . . . . . . . . . . . . . . 85 STM32F722xx and STM32F723xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 101 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 103 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 111 UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 113 WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 116 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 119 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 DocID028479 Rev 1 STM32F722xx STM32F723xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Compatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM32F722xx and STM32F723xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . . 18 VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 29 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29 STM32F722xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F722xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F723xx WLCSP100 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F722xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32F723xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32F723xx UFBGA144 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM32F722xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32F723xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32F723xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM32F723xx UFBGA176 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP64 - 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 101 LQFP64 - 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 102 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 103 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 105 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 107 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale DocID028479 Rev 1 7/121 8 List of figures STM32F722xx STM32F723xx package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8/121 DocID028479 Rev 1 STM32F722xx STM32F723xx 1 Description Description The STM32F722xx and STM32F723xx devices are based on the high-performance ARM(R) Cortex(R)-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex(R)-M7 core features a single floating point unit (SFPU) precision which supports ARM(R) single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. The STM32F722xx and STM32F723xx devices incorporate high-speed embedded memories with a Flash memory up to 512 Kbytes, 256 Kbytes of SRAM (including 64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces. * * * * * * * Up to three I2Cs Five SPIs, three I2Ss in half duplex mode. To achieve the audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. Four USARTs plus four UARTs An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI in the STM32F722xx devices and with the integrated HS PHY in the STM32F723xx devices) One CAN Two SAI serial audio interfaces Two SDMMC host interfaces Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface. Refer to Table 2: STM32F722xx and STM32F723xx features and peripheral counts for the list of peripherals available on each part number. The STM32F722xx and STM32F723xx devices operate in the -40 to +105 C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 and LQFP64 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor (refer to Section 2.15.2: Internal reset OFF). A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F722xx and STM32F723xx devices offer devices in 7 packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. DocID028479 Rev 1 9/121 43 Description STM32F722xx STM32F723xx These features make the STM32F722xx and STM32F723xx microcontrollers suitable for a wide range of applications: * Motor drive and application control, * Medical equipment, * Industrial applications: PLC, inverters, circuit breakers, * Printers, and scanners, * Alarm systems, video intercom, and HVAC, * Home audio appliances, * Mobile applications, Internet of Things, * Wearable devices: smartwatches. Figure 5 shows the general block diagram of the device family Table 2. STM32F722xx and STM32F723xx features and peripheral counts Peripherals Flash memory in Kbytes SRAM in Kbytes STM32F72xRx STM32F72xVx STM32F72xZx 256 256 256 512 512 256(176+16+64) Instruction 16 Backup 4 General-purpose 10(2) Advanced-control 2 Basic 2 No 1 Random number generator Yes SPI / I2S 3/3 (simplex)(3) 4/3 (simplex)(3) 2 I C USART/UART 4/2 4/4 USB OTG FS Yes USB OTG HS(4) Yes USB OTG PHY HS controller (USBPHYC) Yes(10) No 1 SAI 2 SDMMC1 SDMMC2 Yes Yes(5)(6) No 82 in STM32F722xx 79 in STM32F723xx 50 12-bit ADC Number of channels 114 in STM32F722xx 112 in STM32F723xx 140 in STM32F722xx 138 in STM32F723xx 3 16 12-bit DAC Number of channels 24 Yes 2 216 MHz(7) Maximum CPU frequency 10/121 5/3 (simplex)(3) 3 CAN GPIOs 512 Yes Low-power Communication interfaces 256 Yes(1) No Quad-SPI Timers 512 System FMC memory controller STM32F72xIx DocID028479 Rev 1 STM32F722xx STM32F723xx Description Table 2. STM32F722xx and STM32F723xx features and peripheral counts (continued) Peripherals STM32F72xRx STM32F72xVx STM32F72xIx 1.7 to 3.6 V(8) Operating voltage Ambient temperatures: -40 to +85 C /-40 to +105 C Operating temperatures Package STM32F72xZx Junction temperature: -40 to + 125 C LQFP64(9) LQFP100(9) WLCSP100(10) LQFP144 UFBGA144(10) UFBGA176 LQFP176 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 2. On the STM32F723xx device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 generalpurpose timers. 3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 4. USB OTG HS with the ULPI on the STM32F722xx devices and with integrated HS PHY on the STM32F723xx devices. 5. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 6. The SDMMC2 is not available on the STM32F723Vx devices. 7. 216 MHz maximum frequency for - 40C to + 85C ambient temperature range (200 MHz maximum frequency for - 40C to + 105C ambient temperature range). 8. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.15.2: Internal reset OFF). 9. Available only on the STM32F722xx devices. 10. Available only on the STM32F723xx devices. DocID028479 Rev 1 11/121 43 Description 1.1 STM32F722xx STM32F723xx Full compatibility throughout the family The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F7x5xx, STM32F7x6xx, STM32F7x7xx devices. The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 and Figure 2 give compatible board designs between the STM32F722xx and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package 3& 9'' 966$ 95() 9''$ 3$:.83 3$ 3$ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 9'' 3% 9&$3 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3& 3% 3& 3$ 3$ 3$ 3$ 9'' 3$ 3& 966$ 95() 9''$ 3$:.83 3$ 3$ 3$ 966 670)[[[ 3LQVWRDUHQRWFRPSDWLEOH 9'' 966 9&$3 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3% 3& 3& 3$ 3$ 3$ 3$ 9'' 966 06Y9 12/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Description 3& 3& 3& 3$ 3$ 3& 3& 3& 3$ 3$ Figure 2. Compatible board design for LQFP64 package 9'' 9&$3B 3$ 3$ 3$ 3$ 3$ 966 3$ 3& 3& 3& 3& 3% 3% 3% 3% 670)[ 3%QRWDYDLODEOHDQ\PRUH 5HSODFHGE\9 &$3B 9'' 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% 3% 9&$3B 966 9'' 3% 3% 3% 9&$3B 9'' 670) 670)OLQH 9LQFUHDVHGWRI &$3 (65RKPRUEHORZRKP 9'' 966 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 966 9&$3B 3% 3% 3% 3% 3% 3& 3$ 3$ 3$ 3$ 966 9'' 3$ 3&QRWDYDLODEOHDQ\PRUH 5HSODFHGE\9&$3B 9'' 966 9'' 670)[[ 9'' 3$ 3& 3& 3$ 3& 3% 3' 3% 3% 966 9LQFUHDVHGWRI &$3 (65EHWZHHQRKPDQGRKP 966 9'' 06Y9 The STM32F722xx LQFP144, UFBGA176 and LQFP176 packages are fully pin to pin compatible with the STM32F4xx devices. DocID028479 Rev 1 13/121 43 Description 1.2 STM32F722xx STM32F723xx STM32F723xx versus STM32F722xx LQFP144/LQFP176 packages: Figure 3. Compatible board design for LQFP144 package 670)[[ 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 670)[[ 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 9''27*+6 27*B+6B5(;7 3% 3% 9'' 9'' 3*3*UHPRYHGRQWKH670)[[ 06Y9 Figure 4. Compatible board design for LQFP176 package 670)[[ 3+ 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 9'' 966 3+ 3+ 670)[[ 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 9''27*+6 27*B+6B5(;7 3% 3% 9'' 966 3+ 3*3*UHPRYHGRQWKH670)[[ 06Y9 14/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Description Figure 5. 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The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DocID028479 Rev 1 15/121 43 Functional overview STM32F722xx STM32F723xx 2. Available only on the STM32F723xx devices. 2 Functional overview 2.1 ARM(R) Cortex(R)-M7 with FPU The ARM(R) Cortex(R)-M7 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex(R)-M7 processor is a highly efficient high-performance featuring: - Six-stage dual-issue pipeline - Dynamic branch prediction - Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache) - 64-bit AXI4 interface - 64-bit ITCM interface - 2x32-bit DTCM interfaces The processor supports the following memory interfaces: * Tightly Coupled Memory (TCM) interface. * Harvard instruction and data caches and AXI master (AXIM) interface. * Dedicated low-latency AHB-Lite peripheral (AHBP) interface. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It supports single precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 5 shows the general block diagram of the STM32F722xx and STM32F723xx family. Note: Cortex(R)-M7 with FPU core is binary compatible with the Cortex(R)-M4 core. 2.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 16/121 DocID028479 Rev 1 STM32F722xx STM32F723xx 2.3 Functional overview Embedded Flash memory The STM32F722xx and STM32F723xx devices embed a Flash memory of up to 512 Kbytes available for storing programs and data. The flexible protections can be configured thanks to option bytes: * 2.4 Readout protection (RDP) to protect the whole memory. Three levels are available: - Level 0: no readout protection - Level 1: No access (read, erase, program) to the Flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader - Level 2: debug/chip read protection disabled. * Write protection (WRP): the protected area is protected against erasing and programming. * Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can be protected against D-bus read accesses by using the proprietary readout protection (PCROP). The protected area is execute-only. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.5 Embedded SRAM All the devices feature: * * System SRAM up to 256 Kbytes: - SRAM1 on AHB bus Matrix: 176 Kbytes - SRAM2 on AHB bus Matrix: 16 Kbytes - DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for critical real-time data. Instruction RAM (ITCM-RAM) 16 Kbytes: - It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines. The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states. * 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. DocID028479 Rev 1 17/121 43 Functional overview 2.6 STM32F722xx STM32F723xx AXI-AHB bus matrix The STM32F722xx and STM32F723xx system architecture is based on 2 sub-systems: * * An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol: - 3x AXI to 32-bit AHB bridges connected to AHB bus matrix - 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory A multi-AHB Bus-Matrix - The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. ,^ h^,^D h^Kd' ,^ DW 'W D DDD ,W .% ,'&DFKH y/D 'W D DW/ ZDZD DDD /dD dD Figure 6. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1) dDZD < /dDZD < y/Z , Zd /dD , &>^, < ^D ^ZD < ^ZD < , W , &D D W W Y^W/ D^ 06Y9 1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus. 18/121 DocID028479 Rev 1 STM32F722xx STM32F723xx 2.7 Functional overview DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: * SPI and I2S * I2C * USART * General-purpose, basic and advanced-control timers TIMx * DAC * SDMMC * ADC * SAI * Quad-SPI DocID028479 Rev 1 19/121 43 Functional overview 2.8 STM32F722xx STM32F723xx Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: * The NOR/PSRAM memory controller * The NAND/memory controller * The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: * Interface with static-memory mapped devices including: - Static random access memory (SRAM) - NOR Flash memory/OneNAND Flash memory - PSRAM (4 memory banks) - NAND Flash memory with ECC hardware to check up to 8 Kbytes of data * Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories * 8-, 16-, 32-bit data bus width * Independent Chip Select control for each memory bank * Independent configuration for each memory bank * Write FIFO * Read FIFO for SDRAM controller * The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.9 Quad-SPI memory interface (QUADSPI) All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in: * Direct mode through registers * External Flash status register polling mode * Memory mapped mode. Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit access. The code execution is supported. The opcode and the frame format are fully programmable. Communication can be either in Single Data Rate or Dual Data Rate. 20/121 DocID028479 Rev 1 STM32F722xx STM32F723xx 2.10 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)M7 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the STM32F722xx devices (138 GPIOs in the STM32F723xx devices) can be connected to the 16 external interrupt lines. 2.12 Clocks and startup On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz. Similarly, a full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. The STM32F723xx devices embed two PLLs inside the PHY HS controller: PHYPLL1 and PHYPLL2. The PHYPLL1 allows to output 60 MHz used as an input for PHYPLL2 which itself allows to generate the 480 Mbps in the USB OTG High Speed mode. The PHYPLL1 has as input HSE clock. DocID028479 Rev 1 21/121 43 Functional overview 2.13 STM32F722xx STM32F723xx Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: * All Flash address space mapped on ITCM or AXIM interface * All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface * The System memory bootloader The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. 2.14 Note: Power supply schemes * VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. * VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. * * 22/121 The VDDSDMMC can be connected either to VDD or an external independent power supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For example, when the device is powered at 1.8V, an independent power supply 2.7V can be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDSDMMC must be respected: - During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - The VDDSDMMC rising and falling time rate specifications must be respected (see Table 20 and Table 21) - In the operating mode phase, VDDSDMMC could be lower or higher than VDD: All associated GPIOs powered by VDDSDMMC are operating between VDDSDMMC_MIN and VDDSDMMC_MAX. The VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer to Figure 7 and Figure 8). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to the VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDUSB must be respected: - During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower DocID028479 Rev 1 STM32F722xx STM32F723xx Functional overview than VDD - The VDDUSB rising and falling time rate specifications must be respected - In the operating mode phase, VDDUSB could be lower or higher than VDD: - If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB. - If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 7. VDDUSB connected to VDD power supply 9'' 9''B0$; 9'' 9''$ 9''86% 9''B0,1 3RZHURQ 2SHUDWLQJPRGH 3RZHUGRZQ WLPH 069 Figure 8. VDDUSB connected to external power supply 9''86%B0$; 86% IXQFWLRQDODUHD 9''86% 9''86%B0,1 86%QRQ IXQFWLRQDO DUHD 9'' 9''$ 86%QRQ IXQFWLRQDO DUHD 2SHUDWLQJPRGH 3RZHUGRZQ 9''B0,1 3RZHURQ WLPH 069 DocID028479 Rev 1 23/121 43 Functional overview STM32F722xx STM32F723xx On the STM32F7x3xx devices, the USB OTG HS sub-system uses an additional power supply pin: * The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor of 2.2 F must be connected on the VDD12OTGHS pin. 2.15 Power supply supervisor 2.15.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 2.15.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to VSS. Refer to Figure 9: Power supply supervisor interconnection with internal reset OFF. 24/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Functional overview Figure 9. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 1567 9'' $SSOLFDWLRQUHVHW VLJQDO 3'5B21 966 069 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 10). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled * The brownout reset (BOR) circuitry must be disabled * The embedded programmable voltage detector (PVD) is disabled * VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. Figure 10. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHWE\RWKHUVRXUFHWKDQ SRZHUVXSSO\VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 069 DocID028479 Rev 1 25/121 43 Functional overview 2.16 STM32F722xx STM32F723xx Voltage regulator The regulator has four operating modes: * * 2.16.1 Regulator ON - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: * MR mode used in Run/sleep modes or in Stop modes - In Run/Sleep modes The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. - In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). * LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: * - LPR operates in normal mode (default mode when LPR is ON) - LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. The VCAP_1 and VCAP_2 pins must be connected to 2*2.2 F, ESR < 2 (or 1*4.7 F, ESR between 0.1 and 0.2 if only the VCAP_1 pin is provided (on LQFP64 package)). All the packages have the regulator ON feature. 26/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Functional overview Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. `-' means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 2.16.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. The PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: * PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. * As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. * The over-drive and under-drive modes are not available. * The Standby mode is not available. DocID028479 Rev 1 27/121 43 Functional overview STM32F722xx STM32F723xx Figure 11. Regulator OFF 9 ([WHUQDO9&$3BSRZHU $SSOLFDWLRQUHVHW VXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYH VLJQDO RSWLRQDO ZKHQ9&$3B0LQ9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL9 The following conditions must be respected: * VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. * If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 12). * Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 13). * If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application. Note: On the LQFP64 pin package, the VCAP_2 is not available. 28/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Functional overview Figure 12. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9RU9 9 0LQ9 9&$3B9&$3B WLPH 1567 WLPH DLI 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 13. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9RU9 9&$3B9&$3B 9 0LQ9 1567 WLPH 3$DVVHUWHGH[WHUQDOO\ WLPH DLH 1. This figure is valid whatever the internal reset mode (ON or OFF). DocID028479 Rev 1 29/121 43 Functional overview 2.16.3 STM32F722xx STM32F723xx Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package LQFP64, LQFP100 Regulator ON Regulator OFF Yes Internal reset ON Internal reset OFF Yes No No LQFP144 LQFP176, UFBGA144, UFBGA176 2.17 Yes Yes Yes Yes PDR_ON set to VDD PDR_ON set to VSS BYPASS_REG set BYPASS_REG set to VDD to VSS Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. * Two programmable alarms. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. * 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC clock sources can be: * A 32.768 kHz external crystal (LSE) * An external resonator or oscillator(LSE) * The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) * The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. 30/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Functional overview All the RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 2.18 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. * Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): - Normal mode (default mode when MR or LPR is enabled) - Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup and the LPTIM1 asynchronous interrupt). Table 5. Voltage regulator modes in stop mode * Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs. The Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. DocID028479 Rev 1 31/121 43 Functional overview 2.19 STM32F722xx STM32F723xx VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 2.20 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. 32/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Functional overview Table 6. Timer feature comparison Max Max DMA Capture/ Complem interface timer request compare entary clock clock generation channels output (MHz) (MHz)(1) Timer type Timer Counter Counter Prescaler resolution type factor Advanced -control TIM1, TIM8 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 108 216 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Up Any integer between 1 and 65536 No 2 No 108 216 Up Any integer between 1 and 65536 No 1 No 108 216 Up Any integer between 1 and 65536 No 2 No 54 108/216 Up Any integer between 1 and 65536 No 1 No 54 108/216 Up Any integer between 1 and 65536 Yes 0 No 54 108/216 TIM2, TIM5 TIM3, TIM4 TIM9 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic TIM6, TIM7 16-bit 16-bit 16-bit 16-bit 1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DocID028479 Rev 1 33/121 43 Functional overview 2.20.1 STM32F722xx STM32F723xx Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. The TIM1 and TIM8 support independent DMA request generation. 2.20.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F722xx and STM32F723xx devices (see Table 6 for differences). * TIM2, TIM3, TIM4, TIM5 The STM32F722xx and STM32F723xx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit autoreload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 2.20.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. The TIM6 and TIM7 support independent DMA request generation. 34/121 DocID028479 Rev 1 STM32F722xx STM32F723xx 2.20.4 Functional overview Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 2.20.5 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / one-shot mode * Selectable software / hardware input trigger * Selectable clock source: * Internal clock source: LSE, LSI, HSI or APB clock * External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) * Programmable digital glitch filter * Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 2.20.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 2.20.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source DocID028479 Rev 1 35/121 43 Functional overview 2.21 STM32F722xx STM32F723xx Inter-integrated circuit interface (I2C) The device embeds 3 I2Cs. Refer to Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * * I2C-bus specification and user manual rev. 5 compatibility: - Slave and master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (Packet Error Checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert * Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility * Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. * Programmable analog and digital noise filters * 1-byte buffer with DMA capability Table 7. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X 1. X: supported. 36/121 DocID028479 Rev 1 STM32F722xx STM32F723xx 2.22 Functional overview Universal synchronous/asynchronous receiver transmitters (USART) The device embeds USARTs. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART peripheral supports: * Full-duplex asynchronous communications * Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance * Dual clock domain allowing convenient baud rate programming independent from the PCLK reprogramming * A common programmable transmit and receive baud rate of up to 27 Mbit/s when USART clock source is system clock frequency (max is 216 MHz) and oversampling by 8 is used. * Auto baud rate detection * Programmable data word length (7 or 8 or 9 bits) word length * Programmable data order with MSB-first or LSB-first shifting * Progarmmable parity (odd, even, no parity) * Configurable stop bits (1 or 1.5 or 2 stop bits) * Synchronous mode and clock output for synchronous communications * Single-wire half-duplex communications * Separate signal polarity control for transmission and reception * Swappable Tx/Rx pin configuration * Hardware flow control for modem and RS-485 transceiver * Multiprocessor communications * LIN master synchronous break send capability and LIN slave break detection capability * IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode * Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in the ISO/IEC 7816-3 standard) * Support for Modbus communication Table 8 summarizes the implementation of all U(S)ARTs instances Table 8. USART implementation features(1) USART1/2/3/6 Data Length UART4/5/7/8 7, 8 and 9 bits Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X - DocID028479 Rev 1 37/121 43 Functional overview STM32F722xx STM32F723xx Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 2.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, and SPI5 can communicate at up to 50 Mbit/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by the DMA controller. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.24 Serial audio interface (SAI) The devices embed two serial audio interfaces. The serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC'97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. 38/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Functional overview SAI1 and SAI2 can be served by the DMA controller 2.25 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve an error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU and USB interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 2.26 Audio PLL (PLLSAI) An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. 2.27 SD/SDIO/MMC card host interface (SDMMC) SDMMC host interfaces are available, that support MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDMMC Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a stack of MMC4.1 or previous. The SDMMC can be served by the DMA controller 2.28 Controller area network (bxCAN) The CAN is compliant with the 2.0A and B (active) specifications with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive FIFOs with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated to the CAN. DocID028479 Rev 1 39/121 43 Functional overview 2.29 STM32F722xx STM32F723xx Universal serial bus on-the-go full-speed (OTG_FS) The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: * Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints * 12 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Internal FS OTG PHY support * HNP/SNP/IP inside (no need for any external resistor) * BCD support For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected 2.30 Universal serial bus on-the-go high-speed (OTG_HS) The device embeds an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s). The STM32F722xx devices feature a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The STM32F723xx devices feature an integrated PHY HS. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 40/121 * Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 8 bidirectional endpoints * 16 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * For the STM32F722xx devices: External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. * For the STM32F723xx devices: Internal HS OTG PHY support. DocID028479 Rev 1 STM32F722xx STM32F723xx 2.30.1 Functional overview * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal Serial Bus controller on-the-go High-Speed PHY controller (USBPHYC) only on STM32F723xx devices. The USB HS PHY controller: - 2.31 Sets the PHYPLL1/2 values for the PHY HS - Sets the other controls on the PHY HS - Controls and monitors the USB PHY's LDO Random number generator (RNG) All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.32 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 108 MHz. 2.33 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In the scan mode, an automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. DocID028479 Rev 1 41/121 43 Functional overview 2.34 STM32F722xx STM32F723xx Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.35 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: * Two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Dual DAC channel independent or simultaneous conversions * DMA capability for each channel * External triggers for conversion * Input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.36 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 42/121 DocID028479 Rev 1 STM32F722xx STM32F723xx 2.37 Functional overview Embedded Trace MacrocellTM The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F722xx and STM32F723xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using the USB or any other high-speed channel. The real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. The TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DocID028479 Rev 1 43/121 43 Pinouts and pin description 3 STM32F722xx STM32F723xx Pinouts and pin description 9'' 3$ 3$ 3$ 3$ 3& 3% 3% 3% 3% 3% 9&$3B 966 9'' /4)3 3$ 966 9%$7 3& 3&26&B,1 3&26&B287 3+26&B,1 3)26&B287 1567 3& 3& 3& 3& 966$ 95() 3$:.83 3$ 3$ %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ 9'' 966 3% 3% Figure 14. STM32F722xx LQFP64 pinout 1. The above figure shows the package top view. 44/121 DocID028479 Rev 1 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 069 STM32F722xx STM32F723xx Pinouts and pin description s s^^ W W W W KKd W W W W W W W W W W W W W W W W W W Figure 15. STM32F722xx LQFP100 pinout /4)3 s s^^ sW W W W W W W W W W W W W W W W W W W W W W W s^^ s W W W W W W W W W W W W W W W W W W W W sW s^^ s W W W W W sd W WK^/E WK^Khd s^^ s W,K^/E W,K^Khd EZ^d W W W W s^^ sZ& s Wt<hW W W W 06Y9 1. The above figure shows the package top view. DocID028479 Rev 1 45/121 95 Pinouts and pin description STM32F722xx STM32F723xx Figure 16. STM32F723xx WLCSP100 ballout (with OTG PHY HS) 3& 3' 3' 3% 9&$3B 3$ 3' 3' 966 9'' 3( 3% 3% 3( 3( $ 9'' 966 % 3$ 3$ & 3$ 3$ 3$ 3$ 3& 3' 3% 3% 3( 9%$7 ' 3& 3& 3$ 3& 3& 3% 3( 3% 3( 3& ( 3& 3' 3' 3( 3' 3' 3( 3( 3& 3& ) 3' 3' 3' 3( 3% 3& 3& 3& 966 * 9'' 27*+6 27*B+6 B5(;7 3% 3( 3% 3$ 3$ 3$ 1567 3+ + 3% 3% 3% 3( 3( 3% 3$ 3$ 3& 3+ - 3% 3% 9&$3B 3( 3( 3& 9'' 3$ 95() 3& . 9'' 86% 9'' 966 3( 3( 3% 3$ 966 9''$ 966$ %227 9'' 06Y9 1. The above figure shows the package top view. 46/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Pinouts and pin description 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 17. STM32F722xx LQFP144 pinout /4)3 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$53" 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$ 0% 0% 0% 0% 0% 6"!4 0# 0# 0# 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 069 1. The above figure shows the package top view. DocID028479 Rev 1 47/121 95 Pinouts and pin description STM32F722xx STM32F723xx 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 18. STM32F723xx LQFP144 pinout /4)3 ZLWK+63+< 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$53" 633 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 6$$/4'(3 /4'?(3?2%84 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$ 0% 0% 0% 0% 0% 6"!4 0# 0# 0# 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 069 1. The above figure shows the package top view. 48/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Pinouts and pin description Figure 19. STM32F723xx UFBGA144 ballout (with OTG PHY HS) $ 3& 3( 3( 3( 3( 3% 3% 3' 3' 3$ 3$ 3$ % 3& 26&B,1 3( 3( 3( 3% 3% 3* 3* 3' 3& 3& 3$ & 3& 26&B287 9%$7 3) 3) 3% 3% 3* 3* 3' 3& 9''86% 3$ ' 3+ 26&B,1 966 9'' 3) %227 3% 3* 3* 3' 3' 3$ 3$ ( 3+ 26&B287 3) 3) 3) 3'5B21 966 966 3* 3' 3' 3& 3$ ) 1567 3) 3) 9'' 9'' 9'' 9'' 9'' 9'' 9'' 3& 3& * 3) 3) 3) 966 9'' 9'' 9'' 966 9&$3B 966 3* 3& + 3& 3& 3& 3& %<3$66B 5(* 966 9&$3B 3( 3' 9''27* +6 27*B+6 B5(;7 3* - 966$ 3$ 3$ 3& 3% 3* 3( 3( 3' 3* 3* 3* . 95() 3$ 3$ 3& 3) 3* 3( 3( 3' 3' 3' 3' / 95() 3$ 3$ 3% 3) 3) 3( 3( 3' 3' 3% 3% 0 9''$ 3$ 3$ 3% 3) 3) 3( 3( 3% 3% 3% 3% 06Y9 1. The above figure shows the package top view. DocID028479 Rev 1 49/121 95 Pinouts and pin description STM32F722xx STM32F723xx 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 20. 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STM32F723xx LQFP176 pinout /4)3 ZLWK+63+< 0) 0) 0( 0( 0( 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$53" 633 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 6$$/4'(3 /4'?(3?2%84 0" 0" 6$$ 633 0( 6#!0? 6$$ 0( 0( 0( 0( 0( 0( 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 0( 0( 0! "90!33?2%' 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0% 0% 0% 0% 0% 6"!4 0) 0# 0# 0# 0) 0) 0) 633 6$$ 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 0( 0( 069 1. The above figure shows the package top view. DocID028479 Rev 1 51/121 95 Pinouts and pin description STM32F722xx STM32F723xx Figure 22. STM32F723xx UFBGA176 ballout ! 0% 0% " 0% # 0% 0% 0" 0" 0' 0' 0" 0% 0% 0" 0" 0" 0' 0' 6"!4 0) 0) 0) 6$$ 0" 0$ 0# 0! 0! 0! 0' 0' 0$ 0$ 0# 0# 0! 6$$ 3$--# 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0! & 0# 633 6$$ 0( 633 633 633 633 633 633 6#!0 0# 0! ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$53" 0' 0# * .234 0& 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0' + 0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' , 0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' - 633! 0# 0# 0# 0# 0" 0' 633 633 0( 0( 0( 0$ 0$ . 62%& 0! 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 0 62%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 0$2?/. 6$$ "//4 633 633 6#!0? -36 1. The above figure shows the package top view. 52/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Pinouts and pin description Figure 23. STM32F723xx UFBGA176 ballout (with OTG PHY HS) ! 0% 0% " 0% # 0% 0% 0" 0" 0' 0' 0" 0% 0% 0" 0" 0" 0' 0' 6"!4 0) 0) 0) 6$$ 0" 0$ 0# 0! 0! 0! 0' 0' 0$ 0$ 0# 0# 0! 6$$ 3$--# 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0! & 0# 633 6$$ 0( 633 633 633 633 633 633 6#!0 0# 0! ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$53" 0' 0# * .234 0& 0& 0( 633 633 633 633 633 6$$ 6$$ 6$$ /4'?(3 /4'(3 ?2%84 + 0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' , 0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' - 633! 0# 0# 0# 0# 0" 0' 633 633 0( 0( 0( 0$ 0$ . 62%& 0! 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 0 62%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 0$2?/. 6$$ "//4 633 633 6#!0? -36 1. The above figure shows the package top view. DocID028479 Rev 1 53/121 95 Pinouts and pin description STM32F722xx STM32F723xx Table 9. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT pin RST Bidirectional reset pin with weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 54/121 DocID028479 Rev 1 Pin Number 1 PE2 I/O FT - - 2 2 A1 2 A10 A1 A2 2 2 PE3 I/O FT - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT - - 3 3 B1 3 D9 B1 B2 3 3 PE4 I/O FT - TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, EVENTOUT - - 4 4 B2 4 E8 B2 B3 4 4 PE5 I/O FT - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, EVENTOUT - - TRACED3, TIM1_BKIN2, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCK_B, FMC_A22, EVENTOUT - DocID028479 Rev 1 - 5 5 B3 5 B10 B3 B4 5 LQFP176 1 LQFP144 A3 UFBGA144 A2 UFBGA176 C9 WLCSP100 1 LQFP176 A2 UFBGA176 1 LQFP144 1 LQFP100 - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT LQFP64 Alternate functions 5 PE6 I/O FT Additional functions - 55/121 Pinouts and pin description Notes Pin name (function after reset)(1) I/O structure STM32F723xx Pin type STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition Pin Number LQFP144 UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Alternate functions 1 6 6 C1 6 C10 C1 C2 6 6 VBAT S - - - - - - D2 7 - D2 - - 7 PI8 I/O FT Pin name (function after reset)(1) Additional functions - EVENTOUT RTC_TAMP2/ RTC_TS, WKUP5 EVENTOUT RTC_TAMP1/ RTC_TS/ RTC_OUT, WKUP4 EVENTOUT OSC32_IN (2) (3) (2) 2 7 7 D1 8 D10 D1 A1 7 8 PC13 I/O FT 3 8 8 E1 9 E9 E1 B1 8 9 PC14OSC32_IN(PC1 4) I/O FT 4 9 9 F1 10 E10 F1 C1 9 10 PC15OSC32_OUT(P C15) I/O FT (3) EVENTOUT OSC32_OUT - - - D3 11 - D3 - - 11 PI9 I/O FT - UART4_RX, CAN1_RX, FMC_D30, EVENTOUT - - - - E3 12 - E3 - - 12 PI10 I/O FT - FMC_D31, EVENTOUT - - - - E4 13 - E4 - - 13 PI11 I/O FT (4) OTG_HS_ULPI_DIR, EVENTOUT WKUP6 (3) Pinouts and pin description 56/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) (2) (3) STM32F722xx STM32F723xx (2) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - - F2 14 - F2 - - 14 VSS S - - - - - - - F3 15 - F3 - - 15 VDD S - - - - - - 10 E2 16 - E2 C3 10 16 PF0 I/O FT - I2C2_SDA, FMC_A0, EVENTOUT - - - 11 H3 17 - H3 C4 11 17 PF1 I/O FT - I2C2_SCL, FMC_A1, EVENTOUT - - - 12 H2 18 - H2 D4 12 18 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - 13 J2 19 - J2 E2 13 19 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9 - - 14 J3 20 - J3 E3 14 20 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14 - - 15 K3 21 - K3 E4 15 21 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15 - 10 16 G2 22 F9 G2 D2 16 22 VSS S - - - - - 11 17 G3 23 F10 G3 D3 17 23 VDD S - - - - - TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, QUADSPI_BK1_IO3, EVENTOUT ADC3_IN4 - - 18 K2 24 - K2 F3 18 24 Pin name (function after reset)(1) PF6 I/O FT Additional functions 57/121 Pinouts and pin description LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number - - - 20 K1 L3 25 26 - - K1 L3 F2 G3 19 20 25 26 PF7 PF8 I/O I/O I/O structure Pin name (function after reset)(1) Pin type LQFP176 LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 19 STM32F723xx FT FT Alternate functions Additional functions - TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, QUADSPI_BK1_IO2, EVENTOUT ADC3_IN5 - SPI5_MISO, SAI1_SCK_B, UART7_RTS, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_IN6 ADC3_IN7 - - 21 L2 27 - L2 G2 21 27 PF9 I/O FT - SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT - - 22 L1 28 - L1 G1 22 28 PF10 I/O FT - EVENTOUT ADC3_IN8 5 12 23 G1 29 G10 G1 D1 23 29 PH0-OSC_IN I/O FT - EVENTOUT OSC_IN(5) 6 13 24 H1 30 H10 H1 E1 24 30 PH1-OSC_OUT I/O FT - EVENTOUT OSC_OUT(5) 7 14 25 J1 31 G9 J1 F1 25 31 NRST I/O RS T - - - STM32F722xx STM32F723xx Notes DocID028479 Rev 1 - LQFP100 LQFP64 STM32F722xx Pinouts and pin description 58/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 26 M2 32 F8 M2 H1 26 32 PC0 I/O FT Notes UFBGA176 15 I/O structure LQFP144 8 Pin name (function after reset)(1) Pin type LQFP100 STM32F723xx LQFP64 STM32F722xx DocID028479 Rev 1 Additional functions (5) SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT ADC1_IN10, ADC2_IN10, ADC3_IN10 (5) TRACED0, SPI2_MOSI/I2S2_SD, SAI1_SD_A, EVENTOUT ADC1_IN11, ADC2_IN11, ADC3_IN11, RTC_TAMP3, WKUP3 SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT ADC1_IN12, ADC2_IN12, ADC3_IN12 (5) SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT ADC1_IN13, ADC2_IN13, ADC3_IN13 (4) 59/121 9 16 27 M3 33 H9 M3 H2 27 33 PC1 I/O FT 10 17 28 M4 34 J10 M4 H3 28 34 PC2 I/O FT 11 18 29 M5 35 F7 M5 H4 29 35 PC3 I/O FT - - 30 - 36 J7 - F10 30 36 VDD S - - - - 12 19 31 M1 37 K10 M1 J1 31 37 VSSA S - - - - - - - N1 - - N1 K1 - - VREF- S - - - - 13 20 32 P1 38 J9 P1 L1 32 38 VREF+ S - - - - (4) (5) (4) Pinouts and pin description Alternate functions STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 33 R1 39 K9 R1 M1 33 39 DocID028479 Rev 1 14 15 - 23 24 - 34 35 36 - N3 N2 P2 F4 40 41 42 43 G8 J8 H8 - N3 N2 P2 F4 J2 K2 L2 - 34 35 36 - 40 41 42 43 S - PA0-WKUP PA1 PA2 PH2 I/O I/O I/O I/O Alternate functions Additional functions - - - (6) TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI2_SD_B, EVENTOUT ADC1_IN0, ADC2_IN0, ADC3_IN0, WKUP1 FT (5) TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCK_B, EVENTOUT ADC1_IN1, ADC2_IN1, ADC3_IN1 FT (5) TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, SAI2_SCK_B, EVENTOUT ADC1_IN2, ADC2_IN2, ADC3_IN2, WKUP2 LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, FMC_SDCKE0, EVENTOUT - FT FT (5) STM32F722xx STM32F723xx 16 22 VDDA Notes UFBGA176 21 I/O structure LQFP144 - Pin name (function after reset)(1) Pin type LQFP100 STM32F723xx LQFP64 STM32F722xx Pinouts and pin description 60/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - - G4 44 - G4 - - 44 PH3 I/O FT - QUADSPI_BK2_IO1, SAI2_MCK_B, FMC_SDNE0, EVENTOUT - - - - H4 45 - H4 - - 45 PH4 I/O FT (4) I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT - - - - J4 46 - J4 - - 46 PH5 I/O FT - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT - 17 25 37 R2 47 H7 R2 M2 37 47 PA3 I/O FT (5) TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, OTG_HS_ULPI_D0, EVENTOUT ADC1_IN3, ADC2_IN3, ADC3_IN3 18 26 38 - - K8 - G4 38 - VSS S - - - - - - - L4 48 - L4 H5 - 48 BYPASS_REG I FT - - - 19 27 39 K4 49 - K4 F4 39 49 VDD S - - - - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, EVENTOUT ADC1_IN4, ADC2_IN4, DAC_OUT1 20 21 28 29 40 41 N4 P4 50 51 G7 F6 N4 P4 J3 K3 40 41 50 51 Pin name (function after reset)(1) PA4 PA5 (4) 61/121 I/O TTa (5) I/O TIM2_CH1/TIM2_ETR, TIM8_CH1N, TTa (5) SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT (4) Additional functions ADC1_IN5, ADC2_IN5, DAC_OUT2 Pinouts and pin description LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 42 P3 52 G6 P3 L3 42 52 PA6 I/O DocID028479 Rev 1 Notes UFBGA176 30 I/O structure LQFP144 22 Pin name (function after reset)(1) Pin type LQFP100 STM32F723xx LQFP64 STM32F722xx Alternate functions Additional functions FT (5) TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM13_CH1, EVENTOUT ADC1_IN6, ADC2_IN6 ADC1_IN7, ADC2_IN7 31 43 R3 53 K7 R3 M3 43 53 PA7 I/O FT (5) 24 32 44 N5 54 H6 N5 J4 44 54 PC4 I/O FT (5) I2S1_MCK, FMC_SDNE0, EVENTOUT ADC1_IN14, ADC2_IN14 - 33 45 P5 55 J6 P5 K4 45 55 PC5 I/O FT (5) FMC_SDCKE0, EVENTOUT ADC1_IN15, ADC2_IN15 25 34 46 R5 56 F5 R5 L4 46 56 PB0 I/O FT (4) TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS, OTG_HS_ULPI_D1, EVENTOUT ADC1_IN8, ADC2_IN8 26 35 47 R4 57 G5 R4 M4 47 57 PB1 I/O FT TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, EVENTOUT ADC1_IN9, ADC2_IN9 (5) (4) (5) STM32F722xx STM32F723xx 23 TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1, FMC_SDNWE, EVENTOUT Pinouts and pin description 62/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions 27 36 48 M6 58 K6 M6 J5 48 58 PB2 I/O FT - SAI1_SD_A, SPI3_MOSI/I2S3_SD, QUADSPI_CLK, EVENTOUT - - - 49 R6 59 - R6 M5 49 59 PF11 I/O FT - SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, EVENTOUT - - - 50 P6 60 - P6 L5 50 60 PF12 I/O FT - FMC_A6, EVENTOUT - - - 51 M8 61 - M8 - 51 61 VSS S - - - - - - 52 N8 62 - N8 G5 52 62 VDD S - - - - - - 53 N6 63 - N6 K5 53 63 PF13 I/O FT - FMC_A7, EVENTOUT - - - 54 R7 64 - R7 M6 54 64 PF14 I/O FT - FMC_A8, EVENTOUT - - - 55 P7 65 - P7 L6 55 65 PF15 I/O FT - FMC_A9, EVENTOUT - - - 56 N7 66 - N7 K6 56 66 PG0 I/O FT - FMC_A10, EVENTOUT - - - 57 M7 67 - M7 J6 57 67 PG1 I/O FT - FMC_A11, EVENTOUT - - 37 58 R8 68 J5 R8 M7 58 68 PE7 I/O FT - TIM1_ETR, UART7_Rx, QUADSPI_BK2_IO0, FMC_D4, EVENTOUT - - 38 59 P8 69 H5 P8 L7 59 69 PE8 I/O FT - TIM1_CH1N, UART7_Tx, QUADSPI_BK2_IO1, FMC_D5, EVENTOUT - Pin name (function after reset)(1) Additional functions Pinouts and pin description 63/121 LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - 39 60 P9 70 K5 P9 K7 60 70 PE9 I/O FT - TIM1_CH1, UART7_RTS, QUADSPI_BK2_IO2, FMC_D6, EVENTOUT - - - 61 M9 71 - M9 H6 61 71 VSS S - - - - - - 62 N9 72 - N9 G6 62 72 VDD S - - - - - 40 63 R9 73 E4 R9 J7 63 73 PE10 I/O FT - TIM1_CH2N, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7, EVENTOUT - - 41 64 P10 74 G4 P10 H8 64 74 PE11 I/O FT - TIM1_CH2, SPI4_NSS, SAI2_SD_B, FMC_D8, EVENTOUT - - 42 65 R10 75 H4 R10 J8 65 75 PE12 I/O FT - TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9, EVENTOUT - - 43 66 N11 76 J4 N11 K8 66 76 PE13 I/O FT - TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10, EVENTOUT - - 44 67 P11 77 K4 P11 L8 67 77 PE14 I/O FT - TIM1_CH4, SPI4_MOSI, SAI2_MCK_B, FMC_D11,, EVENTOUT - - 45 68 R11 78 F4 R11 M8 68 78 PE15 I/O FT - TIM1_BKIN, FMC_D12, EVENTOUT - Pin name (function after reset)(1) Additional functions STM32F722xx STM32F723xx LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Pinouts and pin description 64/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number PB10 I/O FT 29 47 70 R13 80 H3 R13 M10 70 80 PB11 I/O FT (4) TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, EVENTOUT - 30 48 71 M10 81 J3 M10 H7 71 81 VCAP_1 S - - - - 31 49 - - - K3 - - - - VSS S - - - - 32 50 72 N10 82 K2 N10 G7 72 82 VDD S - - - - - - - M11 83 - M11 - - 83 PH6 I/O FT - I2C2_SMBA, SPI5_SCK, TIM12_CH1, FMC_SDNE1, EVENTOUT - - - - N12 84 - N12 - - 84 PH7 I/O FT - I2C3_SCL, SPI5_MISO, FMC_SDCKE1, EVENTOUT - - - - M12 85 - M12 - - 85 PH8 I/O FT - I2C3_SDA, FMC_D16, EVENTOUT - - - - M13 86 - M13 - - 86 PH9 I/O FT - I2C3_SMBA, TIM12_CH2, FMC_D17, EVENTOUT - Pin type 79 LQFP176 69 LQFP144 M9 UFBGA144 R12 UFBGA176 G3 WLCSP100 79 LQFP176 R12 UFBGA176 69 LQFP144 46 TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT LQFP100 28 (4) LQFP64 Alternate functions Pin name (function after reset)(1) DocID028479 Rev 1 Additional functions - 65/121 Pinouts and pin description Notes STM32F723xx I/O structure STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - - L13 87 - L13 - - 87 PH10 I/O FT - TIM5_CH1, FMC_D18, EVENTOUT - - - - L12 88 - L12 - - 88 PH11 I/O FT - TIM5_CH2, FMC_D19, EVENTOUT - - - - K12 89 - K12 - - 89 PH12 I/O FT - TIM5_CH3, FMC_D20, EVENTOUT - - - - H12 90 - H12 - - 90 VSS S - - - - - - - J12 91 K2 J12 - - 91 VDD S - - - - FT (4) TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT - TIM1_CH1N, SPI2_SCK/I2S2_CK, OTG_HS_VBUS USART3_CTS, OTG_HS_ULPI_D6, EVENTOUT USB HS OTG PHY calibration resistor 33 51 73 P12 92 J2 P12 M11 73 92 Pin name (function after reset)(1) PB12 I/O 34 52 74 P13 93 H2 P13 M12 74 93 PB13 I/O FT (4) - - - - - G2 J15 H11 75 94 OTG_HS_REXT - - - - - - - - G1 J14 H10 76 95 VDD12OTGHS - - - - Additional functions - STM32F722xx STM32F723xx LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Pinouts and pin description 66/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number - - PB14 I/O FT - - - - - - J1 R14 L11 77 96 PB14 I/O FT - OTG_HS_DM - - LQFP176 - LQFP144 - UFBGA144 - UFBGA176 94 WLCSP100 R14 LQFP176 75 UFBGA176 53 LQFP144 35 TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, SDMMC2_D0, OTG_HS_DM, EVENTOUT LQFP100 Alternate functions LQFP64 Notes Pin name (function after reset)(1) I/O structure STM32F723xx Pin type STM32F722xx DocID028479 Rev 1 Additional functions - 54 76 R15 95 - - - - - PB15 I/O FT - - - - - - H1 R15 L12 78 97 PB15 I/O FT - OTG_HS_DP - - 55 77 P15 96 - P15 L9 79 98 PD8 I/O FT - USART3_TX, FMC_D13, EVENTOUT - - 56 78 P14 97 - P14 K9 80 99 PD9 I/O FT - USART3_RX, FMC_D14, EVENTOUT - - 57 79 N15 98 - N15 J9 81 100 PD10 I/O FT - USART3_CK, FMC_D15, EVENTOUT - Pinouts and pin description 67/121 36 RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, SDMMC2_D1, OTG_HS_DP, EVENTOUT STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number - 58 59 81 N14 99 N13 100 F3 F2 N14 N13 H9 L10 82 83 101 102 PD11 PD12 I/O I/O I/O structure Pin name (function after reset)(1) Pin type LQFP176 LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 80 STM32F723xx FT FT Alternate functions Additional functions - USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT - - TIM4_CH1, LPTIM1_IN1, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, EVENTOUT - - 84 103 PD13 I/O FT - TIM4_CH2, LPTIM1_OUT, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT G8 85 104 VSS S - - - - F8 86 105 VDD S - - - - F1 M14 K11 87 106 PD14 I/O FT - TIM4_CH3, UART8_CTS, FMC_D0, EVENTOUT - 105 E2 L14 K12 88 107 PD15 I/O FT - TIM4_CH4, UART8_RTS, FMC_D1, EVENTOUT - 106 - L15 J12 89 108 PG2 I/O FT - FMC_A12, EVENTOUT - - 60 82 M15 101 E3 M15 K10 - - 83 - 102 - - - - 84 J13 103 - J13 - 61 85 M14 104 - 62 86 L14 - - 87 L15 STM32F722xx STM32F723xx Notes DocID028479 Rev 1 - LQFP100 LQFP64 STM32F722xx Pinouts and pin description 68/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - 88 K15 107 - K15 J11 90 109 PG3 I/O FT - FMC_A13, EVENTOUT - - - 89 K14 108 - K14 J10 91 110 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT - - - 90 K13 109 - K13 H12 92 111 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT - - - 91 J15 110 - - - - - PG6 I/O FT - EVENTOUT - - - 92 J14 111 - - - - - PG7 I/O FT - USART6_CK, FMC_INT, EVENTOUT - - - 93 H14 112 - H14 G11 93 112 PG8 I/O FT - USART6_RTS, FMC_SDCLK, EVENTOUT - - - 94 G12 113 - G12 - 94 113 VSS S - - - - - - F10 - - VDD 95 114 VDDUSB S - - - - - TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDMMC2_D6, SDMMC1_D6, EVENTOUT - - 37 - 63 95 96 H13 H15 114 115 K1 E1 H13 C11 H15 G12 96 115 Pin name (function after reset)(1) PC6 I/O FT Additional functions 69/121 Pinouts and pin description LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number 39 64 65 98 G15 116 G14 117 D4 D2 G15 F12 G14 F11 97 98 116 117 PC7 PC8 I/O I/O I/O structure Pin name (function after reset)(1) Pin type LQFP176 LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 97 STM32F723xx FT FT Notes DocID028479 Rev 1 38 LQFP100 LQFP64 STM32F722xx Alternate functions Additional functions - TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC2_D7, SDMMC1_D7, EVENTOUT - - TRACED1, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDMMC1_D0, EVENTOUT - - 66 99 F14 118 D1 F14 E11 99 118 PC9 I/O FT - 41 67 100 F15 119 D3 F15 E12 100 119 PA8 I/O FT - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT - 42 68 101 E15 120 C3 E15 D12 101 120 PA9 I/O FT - TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, EVENTOUT OTG_FS_VBUS 43 69 102 D15 121 C2 D15 D11 102 121 PA10 I/O FT - TIM1_CH3, USART1_RX, OTG_FS_ID, EVENTOUT - STM32F722xx STM32F723xx 40 MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDMMC1_D1, EVENTOUT Pinouts and pin description 70/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP144 LQFP176 Pin type I/O structure Notes 103 C15 122 C1 C15 C12 103 122 PA11 I/O FT - TIM1_CH4, USART1_CTS, CAN1_RX, OTG_FS_DM, EVENTOUT - 45 71 104 B15 123 B2 B15 B12 104 123 PA12 I/O FT - TIM1_ETR, USART1_RTS, SAI2_FS_B, CAN1_TX, OTG_FS_DP, EVENTOUT - 46 72 105 A15 124 B1 A15 A12 105 124 PA13(JTMSSWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - - 73 106 F13 125 B3 F13 G9 106 125 VCAP_2 S - - - - 47 74 107 F12 126 A2 F12 G10 107 126 VSS S - - - - 48 75 108 G13 127 A1 G13 F9 108 127 VDD S - - - - - - - E12 128 - E12 - - 128 PH13 I/O FT - TIM8_CH1N, UART4_TX, CAN1_TX, FMC_D21, EVENTOUT - - - - E13 129 - E13 - - 129 PH14 I/O FT - TIM8_CH2N, UART4_RX, CAN1_RX, FMC_D22, EVENTOUT - - - - D13 130 - D13 - - 130 PH15 I/O FT - TIM8_CH3N, FMC_D23, EVENTOUT - UFBGA144 WLCSP100 70 LQFP176 44 UFBGA176 Alternate functions Pin name (function after reset)(1) Additional functions 71/121 Pinouts and pin description LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - - E14 131 - E14 - - 131 PI0 I/O FT - TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, EVENTOUT - - - - D14 132 - D14 - - 132 PI1 I/O FT - TIM8_BKIN2, SPI2_SCK/I2S2_CK, FMC_D25, EVENTOUT - - - - C14 133 - C14 - - 133 PI2 I/O FT - TIM8_CH4, SPI2_MISO, FMC_D26, EVENTOUT - - - - C13 134 - C13 - - 134 PI3 I/O FT - TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, EVENTOUT - - - - D9 135 - D9 - - 135 VSS S - - - - - - - C9 136 - C9 - - 136 VDD S - - - - 49 76 109 A14 137 C4 A14 A11 109 137 PA14(JTCKSWCLK) I/O FT - JTCK-SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT - 50 77 110 A13 138 B4 A13 A10 110 138 Pin name (function after reset)(1) PA15(JTDI) I/O FT Additional functions STM32F722xx STM32F723xx LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Pinouts and pin description 72/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number 52 78 79 112 B14 B13 139 140 A3 C5 B14 B13 B11 B10 111 112 139 140 PC10 PC11 I/O I/O I/O structure Pin name (function after reset)(1) Pin type LQFP176 LQFP144 UFBGA144 UFBGA176 WLCSP100 LQFP176 UFBGA176 LQFP144 111 STM32F723xx FT FT Notes DocID028479 Rev 1 51 LQFP100 LQFP64 STM32F722xx Alternate functions Additional functions - SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, EVENTOUT - - SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, EVENTOUT - - 80 113 A12 141 D5 A12 C10 113 141 PC12 I/O FT - - 81 114 B12 142 B5 B12 E10 114 142 PD0 I/O FT - CAN1_RX, FMC_D2, EVENTOUT - - 82 115 C12 143 A4 C12 D10 115 143 PD1 I/O FT - CAN1_TX, FMC_D3, EVENTOUT - 54 83 116 D12 144 E5 D12 E9 116 144 PD2 I/O FT - TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD, EVENTOUT - - 84 117 C6 D11 D9 117 145 PD3 I/O FT - SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, EVENTOUT - D11 145 Pinouts and pin description 73/121 53 TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDMMC1_CK, EVENTOUT STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes - 85 118 D10 146 B6 D10 C9 118 146 PD4 I/O FT - USART2_RTS, FMC_NOE, EVENTOUT - - 86 119 C11 147 A5 C11 B9 119 147 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - - 120 D8 148 - D8 E7 120 148 VSS S - - - - - - 121 C8 149 - C8 F7 121 149 VDDSDMMC S - - - - - LQFP176 Alternate functions UFBGA176 LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Pin name (function after reset)(1) Additional functions 87 122 B11 150 D6 B11 A8 122 150 PD6 I/O FT - - 88 123 A11 151 E6 A11 A9 123 151 PD7 I/O FT - USART2_CK SDMMC2_CMD, FMC_NE1, EVENTOUT - - - - - 124 C10 152 - C10 E8 124 152 PG9 I/O FT - USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, EVENTOUT - - 125 B10 - B10 D8 125 153 PG10 I/O FT - SAI2_SD_B, SDMMC2_D1, FMC_NE3, EVENTOUT 153 STM32F722xx STM32F723xx - SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, SDMMC2_CK, FMC_NWAIT, EVENTOUT Pinouts and pin description 74/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - 126 B9 154 - B9 C8 126 154 PG11 I/O FT - SDMMC2_D2, FMC_INT, EVENTOUT - - - 127 B8 155 - B8 B8 127 155 PG12 I/O FT - LPTIM1_IN1, USART6_RTS, SDMMC2_D3, FMC_NE4, EVENTOUT - - - 128 A8 156 - A8 D7 128 156 PG13 I/O FT - TRACED0, LPTIM1_OUT, USART6_CTS, FMC_A24, EVENTOUT - - - Pin name (function after reset)(1) - - 129 A7 157 - A7 C7 129 157 PG14 I/O FT - TRACED1, LPTIM1_ETR, USART6_TX, QUADSPI_BK2_IO3, FMC_A25, EVENTOUT - - 130 D7 158 - D7 - 130 158 VSS S - - - Additional functions Pinouts and pin description 75/121 LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - 131 C7 159 - C7 F6 131 159 VDD S - - - - - - 132 B7 160 - B7 B7 132 160 PG15 I/O FT - USART6_CTS, FMC_SDNCAS, EVENTOUT - 161 PB3(JTDO/TRA CESWO) - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SDMMC2_D2, EVENTOUT - - NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, SDMMC2_D3, EVENTOUT - (4) TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, OTG_HS_ULPI_D7, FMC_SDCKE1, EVENTOUT - 55 56 57 89 90 91 133 A10 134 135 A9 A6 161 162 163 A6 B7 C7 A10 A9 A6 A7 A6 B6 133 134 135 162 163 Pin name (function after reset)(1) PB4(NJTRST) PB5 I/O I/O I/O FT FT FT Additional functions STM32F722xx STM32F723xx LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Pinouts and pin description 76/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number 164 PB6 I/O FT - 59 93 137 B5 165 B8 B5 D6 137 165 PB7 I/O FT - TIM4_CH2, I2C1_SDA, USART1_RX, FMC_NL, EVENTOUT - 60 94 138 D6 166 A7 D6 D5 138 166 BOOT I B - - VPP - TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDMMC2_D4, SDMMC1_D4, EVENTOUT - - TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDMMC2_D5, SDMMC1_D5, EVENTOUT - DocID028479 Rev 1 61 62 95 96 139 140 A5 B4 167 168 C8 D8 A5 B4 C5 B5 139 140 LQFP176 136 LQFP144 C6 UFBGA144 B6 UFBGA176 D7 WLCSP100 164 LQFP176 B6 UFBGA176 136 LQFP144 92 LQFP100 58 TIM4_CH1, I2C1_SCL, USART1_TX, QUAD SPI_BK1_NCS, FMC_SDNE1, EVENTOUT LQFP64 Alternate functions 167 168 PB8 PB9 I/O I/O FT FT Additional functions - 77/121 Pinouts and pin description Notes Pin name (function after reset)(1) I/O structure STM32F723xx Pin type STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number LQFP144 UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Alternate functions - 97 141 A4 169 E7 A4 A5 141 169 PE0 I/O FT - TIM4_ETR, LPTIM1_ETR, UART8_Rx, SAI2_MCK_A, FMC_NBL0, EVENTOUT - - 98 142 A3 170 B9 A3 A4 142 170 PE1 I/O FT - LPTIM1_IN2, UART8_Tx, FMC_NBL1, EVENTOUT - 63 99 - D5 - A8 D5 E6 - - VSS S - - - - - - 143 C6 171 - C6 E5 143 171 PDR_ON S - - - - 100 144 C5 172 A9 C5 F5 144 172 VDD S - - - - 64 Pin name (function after reset)(1) Additional functions - - D4 173 - D4 - - 173 PI4 I/O FT - TIM8_BKIN, SAI2_MCK_A, FMC_NBL2, EVENTOUT - - - - C4 174 - C4 - - 174 PI5 I/O FT - TIM8_CH1, SAI2_SCK_A, FMC_NBL3, EVENTOUT - STM32F722xx STM32F723xx - Pinouts and pin description 78/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - - C3 175 - C3 - - 175 PI6 I/O FT - TIM8_CH2, SAI2_SD_A, FMC_D28, EVENTOUT - - - - C2 176 - C2 - - 176 PI7 I/O FT - TIM8_CH3, SAI2_FS_A, FMC_D29, EVENTOUT - - - - F6 - - F6 - - - VSS S - - - - - - - F7 - - F7 - - - VSS S - - - - - - - F8 - - F8 - - - VSS S - - - - - - - F9 - - F9 - - - VSS S - - - - - - - F10 - - F10 - - - VSS S - - - - - - - G6 - - G6 - - - VSS S - - - - - - - G7 - - G7 - - - VSS S - - - - - - - G8 - - G8 - - - VSS S - - - - - - - G9 - - G9 - - - VSS S - - - - - - - G10 - - G10 - - - VSS S - - - - - - - H6 - - H6 - - - VSS S - - - - Pin name (function after reset)(1) Additional functions Pinouts and pin description 79/121 LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx STM32F722xx STM32F723xx Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) Pin Number UFBGA176 LQFP176 WLCSP100 UFBGA176 UFBGA144 LQFP144 LQFP176 Pin type I/O structure Notes Alternate functions - - - H7 - - H7 - - - VSS S - - - - - - - H8 - - H8 - - - VSS S - - - - - - - H9 - - H9 - - - VSS S - - - - - - - H10 - - H10 - - - VSS S - - - - - - - J6 - - J6 - - - VSS S - - - - - - - J7 - - J7 - - - VSS S - - - - - - - J8 - - J8 - - - VSS S - - - - - - - J9 - - J9 - - - VSS S - - - - - - - J10 - - J10 - - - VSS S - - - - - - - K6 - - K6 - - - VSS S - - - - - - - K7 - - K7 - - - VSS S - - - - - - - K8 - - K8 - - - VSS S - - - - - - - K9 - - K9 - - - VSS S - - - - - - - K10 - - K10 - - - VSS S - - - - 1. Function availability depends on the chosen device. Pin name (function after reset)(1) Additional functions STM32F722xx STM32F723xx LQFP144 DocID028479 Rev 1 LQFP100 STM32F723xx LQFP64 STM32F722xx Pinouts and pin description 80/121 Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued) - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). 4. ULPI signals not available on the STM32F723xx devices. 5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 6. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low). STM32F722xx STM32F723xx 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: DocID028479 Rev 1 Pinouts and pin description 81/121 Pinouts and pin description STM32F722xx STM32F723xx Table 11. FMC pin definition 82/121 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PF0 A0 - - A0 PF1 A1 - - A1 PF2 A2 - - A2 PF3 A3 - - A3 PF4 A4 - - A4 PF5 A5 - - A5 PF12 A6 - - A6 PF13 A7 - - A7 PF14 A8 - - A8 PF15 A9 - - A9 PG0 A10 - - A10 PG1 A11 - - A11 PG2 A12 - - A12 PG3 A13 - - - PG4 A14 - - BA0 PG5 A15 - - BA1 PD11 A16 A16 CLE - PD12 A17 A17 ALE - PD13 A18 A18 - - PE3 A19 A19 - - PE4 A20 A20 - - PE5 A21 A21 - - PE6 A22 A22 - - PE2 A23 A23 - - PG13 A24 A24 - - PG14 A25 A25 - - PD14 D0 DA0 D0 D0 PD15 D1 DA1 D1 D1 PD0 D2 DA2 D2 D2 PD1 D3 DA3 D3 D3 PE7 D4 DA4 D4 D4 PE8 D5 DA5 D5 D5 PE9 D6 DA6 D6 D6 DocID028479 Rev 1 STM32F722xx STM32F723xx Pinouts and pin description Table 11. FMC pin definition (continued) Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PE10 D7 DA7 D7 D7 PE11 D8 DA8 D8 D8 PE12 D9 DA9 D9 D9 PE13 D10 DA10 D10 D10 PE14 D11 DA11 D11 D11 PE15 D12 DA12 D12 D12 PD8 D13 DA13 D13 D13 PD9 D14 DA14 D14 D14 PD10 D15 DA15 D15 D15 PH8 D16 - - D16 PH9 D17 - - D17 PH10 D18 - - D18 PH11 D19 - - D19 PH12 D20 - - D20 PH13 D21 - - D21 PH14 D22 - - D22 PH15 D23 - - D23 PI0 D24 - - D24 PI1 D25 - - D25 PI2 D26 - - D26 PI3 D27 - - D27 PI6 D28 - - D28 PI7 D29 - - D29 PI9 D30 - - D30 PI10 D31 - - D31 PD7 NE1 NE1 - - PG9 NE2 NE2 NCE - PG10 NE3 NE3 - - PG11 - - - - PG12 NE4 NE4 - - PD3 CLK CLK - - PD4 NOE NOE NOE - PD5 NWE NWE NWE - PD6 NWAIT NWAIT NWAIT - DocID028479 Rev 1 83/121 95 Pinouts and pin description STM32F722xx STM32F723xx Table 11. FMC pin definition (continued) 84/121 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PB7 NADV NADV - - PF6 - - - - PF7 - - - - PF8 - - - - PF9 - - - - PF10 - - - - PG6 - - - - PG7 - - INT - PE0 NBL0 NBL0 - NBL0 PE1 NBL1 NBL1 - NBL1 PI4 NBL2 - - NBL2 PI5 NBL3 - - NBL3 PG8 - - - SDCLK PC0 - - - SDNWE PF11 - - - SDNRAS PG15 - - - SDNCAS PH2 - - - SDCKE0 PH3 - - - SDNE0 PH6 - - - SDNE1 PH7 - - - SDCKE1 PH5 - - - SDNWE PC2 - - - SDNE0 PC3 - - - SDCKE0 PB5 - - - SDCKE1 PB6 - - - SDNE1 DocID028479 Rev 1 AF0 AF1 AF2 AF3 AF4 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 I2C1/2/3/U SART1 Port SYS DocID028479 Rev 1 Port A TIM1/2 AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ 6/UART4/5/7/ ADSPI/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS - TIM2_CH1 /TIM2_ET TIM5_CH1 R TIM8_ETR - - - USART2_CT S UART4_ TX - SAI2_SD_B - - EVEN TOUT PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RT S UART4_RX QUADSPI_ BK1_IO3 SAI2_MCK _B - - EVEN TOUT PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX SAI2_SCK_B - - - - EVEN TOUT PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - OTG_HS_U LPI_D0 - - EVEN TOUT PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK /I2S1_WS /I2S3_WS - - - - OTG_HS_ SOF EVEN TOUT PA5 - TIM2_CH1 /TIM2_ET R - TIM8_CH1 N - SPI1_SCK /I2S1_CK - - - - OTG_HS_U LPI_CK - - EVEN TOUT PA6 - TIM1_BKI N TIM3_CH1 TIM8_BKIN - SPI1_MIS O - - - TIM13_CH1 - - - EVEN TOUT PA7 - TIM1_CH1 TIM3_CH2 N TIM8_CH1 N - SPI1_MO SI/I2S1_S D - - - TIM14_CH1 - - FMC_SDN WE EVEN TOUT PA8 MCO1 TIM1_CH1 - TIM8_BKIN 2 I2C3_SCL - - USART1_CK - - OTG_FS_S OF - - EVEN TOUT PA9 - TIM1_CH2 - - I2C3_SMB A SPI2_SCK /I2S2_CK - USART1_TX - - - - - EVEN TOUT PA10 - TIM1_CH3 - - - - - USART1_RX - - OTG_FS_I D - - EVEN TOUT PA11 - TIM1_CH4 - - - - - USART1_CT S - CAN1_RX OTG_FS_D M - - EVEN TOUT 85/121 Pinouts and pin description PA0 STM32F722xx STM32F723xx Table 12. STM32F722xx and STM32F723xx alternate function mapping AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PA12 - TIM1_ETR - - - - - USART1_RT S SAI2_FS_B CAN1_TX OTG_FS_D P - - EVEN TOUT PA13 JTMSSWDIO - - - - - - - - - - - - EVEN TOUT PA14 JTCKSWCLK - - - - - - - - - - - - EVEN TOUT PA15 JTDI TIM2_CH1 /TIM2_ET R - - - - UART4_RTS - - - - EVEN TOUT PB0 - TIM1_CH2 TIM3_CH3 N TIM8_CH2 N - - - - UART4_CTS OTG_HS_U LPI_D1 - - EVEN TOUT PB1 - TIM1_CH3 TIM3_CH4 N TIM8_CH3 N - - - - - OTG_HS_U LPI_D2 - - EVEN TOUT PB2 - - - - - - SAI1_SD_ A SPI3_MOSI/I 2S3_SD QUADSPI_ CLK - - - EVEN TOUT PB3 JTDO/TR ACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK /I2S1_CK /I2S3_CK PB4 NJTRST - TIM3_CH1 - - SPI1_MIS O PB5 - - TIM3_CH2 - I2C1_SMB A PB6 - - TIM4_CH1 - PB7 - - TIM4_CH2 PB8 - - TIM4_CH3 SPI1_NSS SPI3_NSS /I2S1_WS /I2S3_WS DocID028479 Rev 1 - - - SDMMC2_ D2 - - EVEN TOUT SPI3_MIS O SPI2_NSS/I2 S2_WS - - SDMMC2_ D3 - - EVEN TOUT SPI1_MO SI/I2S1_S D SPI3_MO SI/I2S3_S D - - - OTG_HS_U LPI_D7 - FMC_SDC KE1 EVEN TOUT I2C1_SCL - - USART1_TX - - QUADSPI_ BK1_NCS - FMC_SDN E1 EVEN TOUT - I2C1_SDA - - USART1_RX - - - - FMC_NL EVEN TOUT TIM10_CH 1 I2C1_SCL - - - - CAN1_RX SDMMC2_ D4 - SDMMC1 _D4 EVEN TOUT STM32F722xx STM32F723xx SYS TIM8/9/10/1 1/LPTIM1 Port A Port B AF5 Pinouts and pin description 86/121 Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 I2C1/2/3/U SART1 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS /I2S2_WS - - - CAN1_TX Port Port B AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS SDMMC2_ D5 - SDMMC1 _D5 EVEN TOUT DocID028479 Rev 1 SYS TIM1/2 PB9 - - PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK /I2S2_CK - USART3_TX - - OTG_HS_U LPI_D3 - - EVEN TOUT PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - OTG_HS_U LPI_D4 - - EVEN TOUT PB12 - TIM1_BKI N - - I2C2_SMB A SPI2_NSS /I2S2_WS - USART3_CK - - OTG_HS_U LPI_D5 - OTG_HS_ ID EVEN TOUT PB13 - TIM1_CH1 N - - - SPI2_SCK /I2S2_CK - USART3_CT S - - OTG_HS_U LPI_D6 - - EVEN TOUT PB14 - TIM1_CH2 N - TIM8_CH2 N - SPI2_MIS O - USART3_RT S - TIM12_CH1 SDMMC2_ D0 - OTG_HS_ DM EVEN TOUT RTC_REF TIM1_CH3 IN N - TIM8_CH3 N - SPI2_MO SI/I2S2_S D - - - TIM12_CH2 SDMMC2_ D1 - OTG_HS_ DP EVEN TOUT PB15 - - - - - - - - SAI2_FS_B - OTG_HS_U LPI_STP - FMC_SDN WE EVEN TOUT PC1 TRACED0 - - - - SPI2_MO SI/I2S2_S D SAI1_SD_ A - - - - - - EVEN TOUT PC2 - - - - - SPI2_MIS O - - - - OTG_HS_U LPI_DIR - FMC_SDN E0 EVEN TOUT PC3 - - - - - SPI2_MO SI/I2S2_S D - - - - OTG_HS_U LPI_NXT - FMC_SDC KE0 EVEN TOUT Port C 87/121 Pinouts and pin description PC0 STM32F722xx STM32F723xx Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DocID028479 Rev 1 TIM1/2 TIM3/4/5 PC4 - - - - - I2S1_MCK - - - - - - FMC_SDN E0 EVEN TOUT PC5 - - - - - - - - - - - - FMC_SDC KE0 EVEN TOUT PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - - USART6_TX - SDMMC2_ D6 - SDMMC1 _D6 EVEN TOUT PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - USART6_RX - SDMMC2_ D7 - SDMMC1 _D7 EVEN TOUT PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - UART5_RTS USART6_CK - - - SDMMC1 _D0 EVEN TOUT PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - UART5_CTS - QUADSPI_ BK1_IO0 - - SDMMC1 _D1 EVEN TOUT PC10 - - - - - - SPI3_SCK /I2S3_CK USART3_TX UART4_TX QUADSPI_ BK1_IO1 - - SDMMC1 _D2 EVEN TOUT PC11 - - - - - - SPI3_MIS O USART3_RX UART4_RX QUADSPI_ BK2_NCS - - SDMMC1 _D3 EVEN TOUT PC12 TRACED3 - - - - - SPI3_MO SI/I2S3_S D USART3_CK UART5_TX - - - SDMMC1 _CK EVEN TOUT PC13 - - - - - - - - - - - - - EVEN TOUT PC14 - - - - - - - - - - - - - EVEN TOUT PC15 - - - - - - - - - - - - - EVEN TOUT Port C STM32F722xx STM32F723xx SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 88/121 Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DocID028479 Rev 1 TIM1/2 TIM3/4/5 PD0 - - - - - - - - - CAN1_RX - - FMC_D2 EVEN TOUT PD1 - - - - - - - - - CAN1_TX - - FMC_D3 EVEN TOUT PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - - SDMMC1 _CMD EVEN TOUT PD3 - - - - - SPI2_SCK /I2S2_CK - USART2_CT S - - - - FMC_CLK EVEN TOUT PD4 - - - - - - - USART2_RT S - - - - FMC_NO E EVEN TOUT PD5 - - - - - - - USART2_TX - - - - FMC_NW E EVEN TOUT PD6 - - - - - SPI3_MO SI/I2S3_S D SAI1_SD_ A USART2_RX - - - SDMMC2 _CK FMC_NW AIT EVEN TOUT PD7 - - - - - - - USART2_CK - - - SDMMC2 _CMD FMC_NE1 EVEN TOUT PD8 - - - - - - - USART3_TX - - - - FMC_D13 EVEN TOUT PD9 - - - - - - - USART3_RX - - - - FMC_D14 EVEN TOUT PD10 - - - - - - - USART3_CK - - - - FMC_D15 EVEN TOUT PD11 - - - - - - - USART3_CT S - QUADSPI_ BK1_IO0 SAI2_SD_A - FMC_A16/ FMC_CLE EVEN TOUT PD12 - - TIM4_CH1 LPTIM1_IN 1 - - - USART3_RT S - QUADSPI_ BK1_IO1 SAI2_FS_A - FMC_A17/ FMC_ALE EVEN TOUT PD13 - - TIM4_CH2 LPTIM1_O UT - - - - - QUADSPI_ BK1_IO3 SAI2_SCK_ A - FMC_A18 EVEN TOUT PD14 - - TIM4_CH3 - - - - - UART8_CTS - - - FMC_D0 EVEN TOUT PD15 - - TIM4_CH4 - - - - - UART8_RTS - - - FMC_D1 EVEN TOUT Port D Port D Pinouts and pin description 89/121 SYS TIM8/9/10/1 1/LPTIM1 STM32F722xx STM32F723xx Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DocID028479 Rev 1 TIM1/2 TIM3/4/5 PE0 - - TIM4_ETR LPTIM1_ET R - - - - UART8_Rx - SAI2_MCK _A - FMC_NBL 0 EVEN TOUT PE1 - - - LPTIM1_IN 2 - - - - UART8_Tx - - - FMC_NBL 1 EVEN TOUT PE2 TRACECL K - - - - SPI4_SCK SAI1_MCL K_A - - QUADSPI_ BK1_IO2 - - FMC_A23 EVEN TOUT PE3 TRACED0 - - - - - SAI1_SD_ B - - - - - FMC_A19 EVEN TOUT PE4 TRACED1 - - - - SPI4_NSS SAI1_FS_ A - - - - - FMC_A20 EVEN TOUT PE5 TRACED2 - - TIM9_CH1 - SPI4_MIS O SAI1_SCK _A - - - - - FMC_A21 EVEN TOUT PE6 TRACED3 TIM1_BKI N2 - TIM9_CH2 - SPI4_MO SI SAI1_SD_ A - - - SAI2_MCK _B - FMC_A22 EVEN TOUT PE7 - TIM1_ETR - - - - - - UART7_Rx - QUADSPI_ BK2_IO0 - FMC_D4 EVEN TOUT PE8 - TIM1_CH1 N - - - - - - UART7_Tx - QUADSPI_ BK2_IO1 - FMC_D5 EVEN TOUT PE9 - TIM1_CH1 - - - - - - UART7_RTS - QUADSPI_ BK2_IO2 - FMC_D6 EVEN TOUT PE10 - TIM1_CH2 N - - - - - - UART7_CTS - QUADSPI_ BK2_IO3 - FMC_D7 EVEN TOUT PE11 - TIM1_CH2 - - - SPI4_NSS - - - - SAI2_SD_B - FMC_D8 EVEN TOUT PE12 - TIM1_CH3 N - - - SPI4_SCK - - - - SAI2_SCK_ B - FMC_D9 EVEN TOUT PE13 - TIM1_CH3 - - - SPI4_MIS O - - - - SAI2_FS_B - FMC_D10 EVEN TOUT PE14 - TIM1_CH4 - - - SPI4_MO SI - - - - SAI2_MCK _B - FMC_D11 EVEN TOUT PE15 - TIM1_BKI N - - - - - - - - - - FMC_D12 EVEN TOUT Port E Port E STM32F722xx STM32F723xx SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 90/121 Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port DocID028479 Rev 1 Port F AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS 91/121 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 EVEN TOUT PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 EVEN TOUT PF2 - - - - I2C2_SMB A - - - - - - - FMC_A2 EVEN TOUT PF3 - - - - - - - - - - - - FMC_A3 EVEN TOUT PF4 - - - - - - - - - - - - FMC_A4 EVEN TOUT PF5 - - - - - - - - - - - - FMC_A5 EVEN TOUT PF6 - - - TIM10_CH 1 - SPI5_NSS SAI1_SD_ B - UART7_Rx QUADSPI_ BK1_IO3 - - - EVEN TOUT PF7 - - - TIM11_CH1 - SPI5_SCK SAI1_MCL K_B - UART7_Tx QUADSPI_ BK1_IO2 - - - EVEN TOUT PF8 - - - - - SPI5_MIS O SAI1_SCK _B - UART7_RTS TIM13_CH1 QUADSPI_ BK1_IO0 - - EVEN TOUT PF9 - - - - - SPI5_MO SI SAI1_FS_ B - UART7_CTS TIM14_CH1 QUADSPI_ BK1_IO1 - - EVEN TOUT PF10 - - - - - - - - - - - - - EVEN TOUT PF11 - - - - - SPI5_MO SI - - - - SAI2_SD_B - FMC_SDN RAS EVEN TOUT PF12 - - - - - - - - - - - - FMC_A6 EVEN TOUT PF13 - - - - - - - - - - - - FMC_A7 EVEN TOUT PF14 - - - - - - - - - - - - FMC_A8 EVEN TOUT PF15 - - - - - - - - - - - - FMC_A9 EVEN TOUT Pinouts and pin description Port F AF5 STM32F722xx STM32F723xx Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port DocID028479 Rev 1 Port G AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PG0 - - - - - - - - - - - - FMC_A10 EVEN TOUT PG1 - - - - - - - - - - - - FMC_A11 EVEN TOUT PG2 - - - - - - - - - - - - FMC_A12 EVEN TOUT PG3 - - - - - - - - - - - - FMC_A13 EVEN TOUT PG4 - - - - - - - - - - - - FMC_A14/ FMC_BA0 EVEN TOUT PG5 - - - - - - - - - - - - FMC_A15/ FMC_BA1 EVEN TOUT PG6 - - - - - - - - - - - - - EVEN TOUT PG7 - - - - - - - - USART6_CK - - - FMC_INT EVEN TOUT PG8 - - - - - - - - USART6_RT S - - - FMC_SDC LK EVEN TOUT PG9 - - - - - - - - USART6_RX QUADSPI_ BK2_IO2 SAI2_FS_B SDMMC2 _D0 FMC_NE2 /FMC_NC E EVEN TOUT PG10 - - - - - - - - - - SAI2_SD_B SDMMC2 _D1 FMC_NE3 EVEN TOUT STM32F722xx STM32F723xx SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 92/121 Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port Port G AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DocID028479 Rev 1 TIM1/2 TIM3/4/5 PG11 - - - - - - - - - - SDMMC2_ D2 - - EVEN TOUT PG12 - - - LPTIM1_IN 1 - - - - USART6_RT S - - SDMMC2 _D3 FMC_NE4 EVEN TOUT PG13 TRACED0 - - LPTIM1_O UT - - - - USART6_CT S - - - FMC_A24 EVEN TOUT PG14 TRACED1 - - LPTIM1_ET R - - - - USART6_TX QUADSPI_ BK2_IO3 - - FMC_A25 EVEN TOUT PG15 - - - - - - - - USART6_CT S - - - FMC_SDN CAS EVEN TOUT PH0 - - - - - - - - - - - - - EVEN TOUT PH1 - - - - - - - - - - - - - EVEN TOUT PH2 - - - LPTIM1_IN 2 - - - - - QUADSPI_ BK2_IO0 SAI2_SCK_ B - FMC_SDC KE0 EVEN TOUT PH3 - - - - - - - - - QUADSPI_ BK2_IO1 SAI2_MCK _B - FMC_SDN E0 EVEN TOUT PH4 - - - - I2C2_SCL - - - - - OTG_HS_U LPI_NXT - - EVEN TOUT PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_SDN WE EVEN TOUT PH6 - - - - I2C2_SMB A SPI5_SCK - - - TIM12_CH1 - - FMC_SDN E1 EVEN TOUT PH7 - - - - I2C3_SCL SPI5_MIS O - - - - - - FMC_SDC KE1 EVEN TOUT Port H 93/121 Pinouts and pin description SYS TIM8/9/10/1 1/LPTIM1 STM32F722xx STM32F723xx Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PH8 - - - - I2C3_SDA - - - - - - - FMC_D16 EVEN TOUT PH9 - - - - I2C3_SMB A - - - - TIM12_CH2 - - FMC_D17 EVEN TOUT PH10 - - TIM5_CH1 - - - - - - - - - FMC_D18 EVEN TOUT PH11 - - TIM5_CH2 - - - - - - - - - FMC_D19 EVEN TOUT PH12 - - TIM5_CH3 - - - - - - - - - FMC_D20 EVEN TOUT PH13 - - - TIM8_CH1 N - - - - UART4_TX CAN1_TX - - FMC_D21 EVEN TOUT PH14 - - - TIM8_CH2 N - - - - UART4_RX CAN1_RX - - FMC_D22 EVEN TOUT PH15 - - - TIM8_CH3 N - - - - - - - - FMC_D23 EVEN TOUT PI0 - - TIM5_CH4 - - SPI2_NSS /I2S2_WS - - - - - - FMC_D24 EVEN TOUT PI1 - - - TIM8_BKIN 2 - SPI2_SCK /I2S2_CK - - - - - - FMC_D25 EVEN TOUT PI2 - - - TIM8_CH4 - SPI2_MIS O - - - - - - FMC_D26 EVEN TOUT PI3 - - - TIM8_ETR - SPI2_MO SI/I2S2_S D - - - - - - FMC_D27 EVEN TOUT PI4 - - - TIM8_BKIN - - - - - - SAI2_MCK _A - FMC_NBL 2 EVEN TOUT PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_ A - FMC_NBL 3 EVEN TOUT PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 EVEN TOUT Port H DocID028479 Rev 1 Port I STM32F722xx STM32F723xx SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 94/121 Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port Port I AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DocID028479 Rev 1 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 EVEN TOUT PI8 - - - - - - - - - - - - - EVEN TOUT PI9 - - - - - - - - UART4_RX CAN1_RX - - FMC_D30 EVEN TOUT PI10 - - - - - - - - - - - - FMC_D31 EVEN TOUT PI11 - - - - - - - - - - OTG_HS_U LPI_DIR - - EVEN TOUT PI12 - - - - - - - - - - - - - EVEN TOUT PI13 - - - - - - - - - - - - - EVEN TOUT PI14 - - - - - - - - - - - - - EVEN TOUT PI15 - - - - - - - - - - - - - EVEN TOUT STM32F722xx STM32F723xx Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued) Pinouts and pin description 95/121 Memory mapping 4 STM32F722xx STM32F723xx Memory mapping The memory map is shown in Figure 24. Figure 24. Memory map [)))))))) [( ['))))))) 5HVHUYHG [([)))))))) &RUWH[0LQWHUQDO SHULSKHUDOV [([())))) $+% [['))))))) 5HVHUYHG [&[))))))) [%)) $+% 0E\WH %ORFN &RUWH[0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [[))))))) [)))) 0E\WH %ORFN )0& [' [&))))))) $+% 0E\WH %ORFN )0& [& [))))))) [ [))))))) [ [))))))) 0E\WH %ORFN 4XDG63,DQG )0&EDQN 5HVHUYHG [ [&[)))) [%)) 0E\WH %ORFN )0&EDQNWR EDQN $3% [ [))))))) 0E\WH %ORFN 3HULSKHUDOV 0E\WH %ORFN 65$0 [ [))))))) 0E\WH %ORFN [ 5HVHUYHG [[))))))) 65$0 .% [&[)))) 65$0 .% [[%))) '7&0 .% [[)))) 5HVHUYHG [)))[))))))) 2SWLRQ%\WHV [)))[)))) 5HVHUYHG [[))()))) )ODVKPHPRU\RQ$;,0 LQWHUIDFH 5HVHUYHG [ [[)))) [))) $3% [[)))) [[)))))) )ODVKPHPRU\RQ,7&0 LQWHUIDFH [[)))) 5HVHUYHG [[))))) 6\VWHPPHPRU\ 5HVHUYHG [[('%) 5HVHUYHG [[))))) ,7&05$0 [[))) [ 06Y9 96/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Memory mapping Table 13. STM32F722xx and STM32F723xx register boundary addresses(1) Bus Cortex-M7 AHB3 AHB2 Boundary address Peripheral 0xE00F FFFF - 0xFFFF FFFF Reserved 0xE000 0000 - 0xE00F FFFF Cortex-M7 internal peripherals 0xD000 0000 - 0xDFFF FFFF FMC bank 6 0xC000 0000 - 0xCFFF FFFF FMC bank 5 0xA000 2000 - 0xBFFF FFFF Reserved 0xA000 1000 - 0xA000 1FFF Quad-SPI control register 0xA000 0000- 0xA000 0FFF FMC control register 0x9000 0000 - 0x9FFF FFFF Quad-SPI 0x8000 0000 - 0x8FFF FFFF FMC bank 3 0x7000 0000 - 0x7FFF FFFF FMC bank 2 0x6000 0000 - 0x6FFF FFFF FMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved 0x5006 0800 - 0x5006 0BFF RNG 0x5004 0000 - 0x5006 07FF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS DocID028479 Rev 1 97/121 100 Memory mapping STM32F722xx STM32F723xx Table 13. STM32F722xx and STM32F723xx register boundary addresses(1) (continued) Bus AHB1 98/121 Boundary address Peripheral 0x4008 0000- 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 6800- 0x4003 FFFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0X4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0X4002 3400 - 0X4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0X4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA DocID028479 Rev 1 STM32F722xx STM32F723xx Memory mapping Table 13. STM32F722xx and STM32F723xx register boundary addresses(1) (continued) Bus APB2 Boundary address Peripheral 0x4001 8000- 0x4001 FFFF Reserved 0x4001 7C00 - 0x4001 7FFF OTG PHY HS Controller(2) 0x4001 6000- 0x4001 7BFF Reserved 0x4001 5C00 - 0x4001 5FFF SAI2 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF SPI5 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF SPI4 0x4001 3000 - 0x4001 33FF SPI1/I2S1 0x4001 2C00 - 0x4001 2FFF SDMMC1 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1C00- 0x4001 1FFF SDMMC2 0x4001 1800 - 0x4001 1BFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 DocID028479 Rev 1 99/121 100 Memory mapping STM32F722xx STM32F723xx Table 13. STM32F722xx and STM32F723xx register boundary addresses(1) (continued) Bus APB1 Boundary address 0x4000 8000- 0x4000 FFFF Reserved 0x4000 7C00 - 0x4000 7FFF UART8 0x4000 7800 - 0x4000 7BFF UART7 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6800 - 0x4000 6FFF Reserved 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF LPTIM1 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 1. The gray color is used for reserved Flash memory addresses. 2. Only for the STM32F723xx devices. 100/121 Peripheral DocID028479 Rev 1 STM32F722xx STM32F723xx 5 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. LQFP64 - 10 x 10 mm, low-profile quad flat package information Figure 25. LQFP64 - 10 x 10 mm, low-profile quad flat package outline PP *$8*(3/$1( F $ $ 6($7,1*3/$1( & $ $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( E ( 5.1 H :B0(B9 1. Drawing is not to scale. Table 14. LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1 0.05 - 0.15 0.0020 - 0.0059 DocID028479 Rev 1 101/121 117 Package information STM32F722xx STM32F723xx Table 14. LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 1.350 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 D - 12.00 - - 0.4724 - D1 - 10.00 - - 0.3937 - D3 - 7.50 - - 0.2953 - E - 12.00 - - 0.4724 - E1 - 10.00 - - 0.3937 - E3 - 7.50 - - 0.2953 - e - 0.50 - - 0.0197 - K 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - ccc - - 0.08 - - 0.0031 0.0079 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 26. LQFP64 - 10 x 10 mm, low-profile quad flat package recommended footprint AIC 1. Dimensions are in millimeters. 102/121 DocID028479 Rev 1 STM32F722xx STM32F723xx LQFP100, 14 x 14 mm low-profile quad flat package information Figure 27. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 3%!4).' 0,!.% # MM C ! ! ! '!5'% 0,!.% $ , $ ! + CCC # , $ % % % B 5.2 Package information 0). )$%.4)&)#!4)/. E ,?-%?6 1. Drawing is not to scale. Table 15. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 DocID028479 Rev 1 103/121 117 Package information STM32F722xx STM32F723xx Table 15. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 28. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint AIC 1. Dimensions are expressed in millimeters. 104/121 DocID028479 Rev 1 STM32F722xx STM32F723xx LQFP144, 20 x 20 mm low-profile quad flat package information Figure 29. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline C ! ! 3%!4).' 0,!.% # ! MM CCC # $ , $ + ! '!5'% 0,!.% , $ % % % B 5.3 Package information 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. Table 16. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 DocID028479 Rev 1 105/121 117 Package information STM32F722xx STM32F723xx Table 16. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 30. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. 106/121 DocID028479 Rev 1 STM32F722xx STM32F723xx LQFP176 24 x 24 mm low-profile quad flat package information Figure 31. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline # 3EATING PLANE C ! ! ! 5.4 Package information MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 17. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0060 b 0.170 - 0.270 0.0067 - 0.0106 C 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 DocID028479 Rev 1 107/121 117 Package information STM32F722xx STM32F723xx Table 17. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - HD 25.900 - 26.100 1.0200 - 1.0276 HE 25.900 - 26.100 1.0200 - 1.0276 L 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - ZD - 1.250 - - 0.0492 - ZE - 1.250 - - 0.0492 - ccc - - 0.080 - - 0.0031 k 0 - 7 0 - 7 1. Values in inches are converted from mm and rounded to 4 decimal digits. 108/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Package information Figure 32. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. DocID028479 Rev 1 109/121 117 Package information 5.5 STM32F722xx STM32F723xx UFBGA144 package information Figure 33. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < 0 %277209,(: E EDOOV HHH 0 = < ; III 0 = 7239,(: $$6B0(B9 1. Drawing is not to scale. Table 18. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol 110/121 Min. Typ. Max. Min. Typ. Max. A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 - 0.130 - - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.320 0.0091 0.0110 0.0126 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DocID028479 Rev 1 STM32F722xx STM32F723xx Package information Table 18. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 34. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint 'SDG 'VP ^&Ws Table 19. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) Dimension Recommended values Pitch 0.50 mm Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm DocID028479 Rev 1 111/121 117 Package information 5.6 STM32F722xx STM32F723xx UFBGA 176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid array package information Figure 35. UFBGA 176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline & ^ $EDOO LGHQWLILHU $EDOO LQGH[ DUHD $ & & Z KddKDs/t E EDOOV dKWs/t HHH 0 & $ III 0 & Ds 1. Drawing is not to scale. Table 20. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3917 0.3937 0.3957 E 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - F 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 112/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Package information Figure 36. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint 'SDG 'VP &Ws Table 21. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID028479 Rev 1 113/121 117 Package information 5.7 STM32F722xx STM32F723xx WLCSP100 - 0.4 mm pitch wafer level chip scale package information Figure 37.WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package outline $%$///2&$7,21 $ '(7$,/$ . %277209,(: 6,'(9,(: )52179,(: '(7$,/$ 527$7(' $25,(17$7,21 5()(5(1&( DDD ; 7239,(: :$)(5%$&.6,'( 1. Drawing is not to scale. 114/121 DocID028479 Rev 1 :/&63/B$4B0(B9 STM32F722xx STM32F723xx Package information Table 22. WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Typ Min Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.17 - - 0.0067 - A2 - 0.38 - - 0.0150 - (2) - 0.025 - - 0.0010 - (3) Ob 0.22 0.25 0.28 - 0.0098 0.0110 D 4.166 4.201 4.236 - 0.1654 0.1668 E 4.628 4.663 4.698 - 0.1836 0.1850 e - 0.4 - - 0.0157 - e1 - 3.6 - - 0.1417 - e2 - 3.6 - - 0.1417 - F - 0.3005 - - 0.0118 - G - 0.5315 - - 0.0209 - N - 100 - - 3.9370 - aaa - 0.1 - - 0.0039 - bbb - 0.1 - - 0.0039 - ccc - 0.1 - - 0.0039 - ddd - 0.05 - - 0.0020 - eee - 0.05 - - 0.0020 - A3 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. DocID028479 Rev 1 115/121 117 Package information STM32F722xx STM32F723xx Figure 38. WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP :/&63/B$4B)3B9 Table 23. WLCSP100 recommended PCB design rules (0.4 mm pitch) Dimension 116/121 Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm Stencil thickness 0.1 mm DocID028479 Rev 1 STM32F722xx STM32F723xx 5.8 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DocID028479 Rev 1 117/121 117 Ordering information 6 STM32F722xx STM32F723xx Ordering information Table 24. Ordering information scheme Example: STM32 F 722 V C T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 722 = STM32F722xx, no OTG PHY HS 723 = STM32F723xx, with OTG PHY HS Pin count R = 64 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size C = 256 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package T = LQFP K = UFBGA (10 x 10 mm) I = UFBGA (7 x 7 mm) Y = WLCSP Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 118/121 DocID028479 Rev 1 STM32F722xx STM32F723xx Appendix A Recommendations when using internal reset OFF Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. * The brownout reset (BOR) circuitry must be disabled. * The embedded programmable voltage detector (PVD) is disabled. * VBAT functionality is no more available and VBAT pin should be connected to VDD. * The over-drive mode is not supported. Operating conditions Table 25. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency with no wait states (fFlashmax) VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz Maximum Flash memory access frequency with wait states (1)(2) 180 MHz with 8 wait states and over-drive OFF I/O operation Possible Flash memory operations 8-bit erase and - No I/O program compensation operations only 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here does not impact the execution speed from the Flash memory since the ART accelerator or L1cache allows to achieve a performance equivalent to 0-wait state program execution. 3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 2.15.1: Internal reset ON). DocID028479 Rev 1 119/121 120 Revision history STM32F722xx STM32F723xx Revision history Table 26. Document revision history 120/121 Date Revision 21-Sep-2016 1 Changes Initial release. DocID028479 Rev 1 STM32F722xx STM32F723xx IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved DocID028479 Rev 1 121/121 121